drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #undef  DEBUG
  25 #undef  VERBOSE
  26
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/ioport.h>
  30 #include <linux/types.h>
  31 #include <linux/errno.h>
  32 #include <linux/delay.h>
  33 #include <linux/slab.h>
  34 #include <linux/init.h>
  35 #include <linux/timer.h>
  36 #include <linux/list.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/proc_fs.h>
  39 #include <linux/mm.h>
  40 #include <linux/moduleparam.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/usb/ch9.h>
  43 #include <linux/usb/gadget.h>
  44 #include <linux/usb/otg.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/clk.h>
  47
  48 #include <asm/byteorder.h>
  49 #include <asm/io.h>
  50 #include <asm/irq.h>
  51 #include <asm/system.h>
  52 #include <asm/unaligned.h>
  53 #include <asm/mach-types.h>
  54
  55 #include <asm/arch/dma.h>
  56 #include <asm/arch/usb.h>
  57 #include <asm/arch/control.h>
  58
  59 #include "omap_udc.h"
  60
  61 #undef  USB_TRACE
  62
  63 /* bulk DMA seems to be behaving for both IN and OUT */
  64 #define USE_DMA
  65
  66 /* ISO too */
  67 #define USE_ISO
  68
  69 #define DRIVER_DESC     "OMAP UDC driver"
  70 #define DRIVER_VERSION  "4 October 2004"
  71
  72 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  73
  74 #define OMAP2_DMA_CH(ch)        (((ch) - 1) << 1)
  75 #define OMAP24XX_DMA(name, ch)  (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
  76
  77 /*
  78  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  79  * D+ pullup to allow enumeration.  That's too early for the gadget
  80  * framework to use from usb_endpoint_enable(), which happens after
  81  * enumeration as part of activating an interface.  (But if we add an
  82  * optional new "UDC not yet running" state to the gadget driver model,
  83  * even just during driver binding, the endpoint autoconfig logic is the
  84  * natural spot to manufacture new endpoints.)
  85  *
  86  * So instead of using endpoint enable calls to control the hardware setup,
  87  * this driver defines a "fifo mode" parameter.  It's used during driver
  88  * initialization to choose among a set of pre-defined endpoint configs.
  89  * See omap_udc_setup() for available modes, or to add others.  That code
  90  * lives in an init section, so use this driver as a module if you need
  91  * to change the fifo mode after the kernel boots.
  92  *
  93  * Gadget drivers normally ignore endpoints they don't care about, and
  94  * won't include them in configuration descriptors.  That means only
  95  * misbehaving hosts would even notice they exist.
  96  */
  97 #ifdef  USE_ISO
  98 static unsigned fifo_mode = 3;
  99 #else
 100 static unsigned fifo_mode = 0;
 101 #endif
 102
 103 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 104  * boot parameter "omap_udc:fifo_mode=42"
 105  */
 106 module_param (fifo_mode, uint, 0);
 107 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
 108
 109 #ifdef  USE_DMA
 110 static unsigned use_dma = 1;
 111
 112 /* "modprobe omap_udc use_dma=y", or else as a kernel
 113  * boot parameter "omap_udc:use_dma=y"
 114  */
 115 module_param (use_dma, bool, 0);
 116 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 117 #else   /* !USE_DMA */
 118
 119 /* save a bit of code */
 120 #define use_dma         0
 121 #endif  /* !USE_DMA */
 122
 123
 124 static const char driver_name [] = "omap_udc";
 125 static const char driver_desc [] = DRIVER_DESC;
 126
 127 /*-------------------------------------------------------------------------*/
 128
 129 /* there's a notion of "current endpoint" for modifying endpoint
 130  * state, and PIO access to its FIFO.
 131  */
 132
 133 static void use_ep(struct omap_ep *ep, u16 select)
 134 {
 135         u16     num = ep->bEndpointAddress & 0x0f;
 136
 137         if (ep->bEndpointAddress & USB_DIR_IN)
 138                 num |= UDC_EP_DIR;
 139         UDC_EP_NUM_REG = num | select;
 140         /* when select, MUST deselect later !! */
 141 }
 142
 143 static inline void deselect_ep(void)
 144 {
 145         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
 146         /* 6 wait states before TX will happen */
 147 }
 148
 149 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 150
 151 /*-------------------------------------------------------------------------*/
 152
 153 static int omap_ep_enable(struct usb_ep *_ep,
 154                 const struct usb_endpoint_descriptor *desc)
 155 {
 156         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 157         struct omap_udc *udc;
 158         unsigned long   flags;
 159         u16             maxp;
 160
 161         /* catch various bogus parameters */
 162         if (!_ep || !desc || ep->desc
 163                         || desc->bDescriptorType != USB_DT_ENDPOINT
 164                         || ep->bEndpointAddress != desc->bEndpointAddress
 165                         || ep->maxpacket < le16_to_cpu
 166                                                 (desc->wMaxPacketSize)) {
 167                 DBG("%s, bad ep or descriptor\n", __func__);
 168                 return -EINVAL;
 169         }
 170         maxp = le16_to_cpu (desc->wMaxPacketSize);
 171         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 172                                 && maxp != ep->maxpacket)
 173                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 174                         || !desc->wMaxPacketSize) {
 175                 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
 176                 return -ERANGE;
 177         }
 178
 179 #ifdef  USE_ISO
 180         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 181                                 && desc->bInterval != 1)) {
 182                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 183                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 184                                 1 << (desc->bInterval - 1));
 185                 return -EDOM;
 186         }
 187 #else
 188         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 189                 DBG("%s, ISO nyet\n", _ep->name);
 190                 return -EDOM;
 191         }
 192 #endif
 193
 194         /* xfer types must match, except that interrupt ~= bulk */
 195         if (ep->bmAttributes != desc->bmAttributes
 196                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 197                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 198                 DBG("%s, %s type mismatch\n", __func__, _ep->name);
 199                 return -EINVAL;
 200         }
 201
 202         udc = ep->udc;
 203         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 204                 DBG("%s, bogus device state\n", __func__);
 205                 return -ESHUTDOWN;
 206         }
 207
 208         spin_lock_irqsave(&udc->lock, flags);
 209
 210         ep->desc = desc;
 211         ep->irqs = 0;
 212         ep->stopped = 0;
 213         ep->ep.maxpacket = maxp;
 214
 215         /* set endpoint to initial state */
 216         ep->dma_channel = 0;
 217         ep->has_dma = 0;
 218         ep->lch = -1;
 219         use_ep(ep, UDC_EP_SEL);
 220         UDC_CTRL_REG = udc->clr_halt;
 221         ep->ackwait = 0;
 222         deselect_ep();
 223
 224         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 225                 list_add(&ep->iso, &udc->iso);
 226
 227         /* maybe assign a DMA channel to this endpoint */
 228         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 229                 /* FIXME ISO can dma, but prefers first channel */
 230                 dma_channel_claim(ep, 0);
 231
 232         /* PIO OUT may RX packets */
 233         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 234                         && !ep->has_dma
 235                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 236                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 237                 ep->ackwait = 1 + ep->double_buf;
 238         }
 239
 240         spin_unlock_irqrestore(&udc->lock, flags);
 241         VDBG("%s enabled\n", _ep->name);
 242         return 0;
 243 }
 244
 245 static void nuke(struct omap_ep *, int status);
 246
 247 static int omap_ep_disable(struct usb_ep *_ep)
 248 {
 249         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 250         unsigned long   flags;
 251
 252         if (!_ep || !ep->desc) {
 253                 DBG("%s, %s not enabled\n", __func__,
 254                         _ep ? ep->ep.name : NULL);
 255                 return -EINVAL;
 256         }
 257
 258         spin_lock_irqsave(&ep->udc->lock, flags);
 259         ep->desc = NULL;
 260         nuke (ep, -ESHUTDOWN);
 261         ep->ep.maxpacket = ep->maxpacket;
 262         ep->has_dma = 0;
 263         UDC_CTRL_REG = UDC_SET_HALT;
 264         list_del_init(&ep->iso);
 265         del_timer(&ep->timer);
 266
 267         spin_unlock_irqrestore(&ep->udc->lock, flags);
 268
 269         VDBG("%s disabled\n", _ep->name);
 270         return 0;
 271 }
 272
 273 /*-------------------------------------------------------------------------*/
 274
 275 static struct usb_request *
 276 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 277 {
 278         struct omap_req *req;
 279
 280         req = kzalloc(sizeof(*req), gfp_flags);
 281         if (req) {
 282                 req->req.dma = DMA_ADDR_INVALID;
 283                 INIT_LIST_HEAD (&req->queue);
 284         }
 285         return &req->req;
 286 }
 287
 288 static void
 289 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 290 {
 291         struct omap_req *req = container_of(_req, struct omap_req, req);
 292
 293         if (_req)
 294                 kfree (req);
 295 }
 296
 297 /*-------------------------------------------------------------------------*/
 298
 299 static void
 300 done(struct omap_ep *ep, struct omap_req *req, int status)
 301 {
 302         unsigned                stopped = ep->stopped;
 303
 304         list_del_init(&req->queue);
 305
 306         if (req->req.status == -EINPROGRESS)
 307                 req->req.status = status;
 308         else
 309                 status = req->req.status;
 310
 311         if (use_dma && ep->has_dma) {
 312                 if (req->mapped) {
 313                         dma_unmap_single(ep->udc->gadget.dev.parent,
 314                                 req->req.dma, req->req.length,
 315                                 (ep->bEndpointAddress & USB_DIR_IN)
 316                                         ? DMA_TO_DEVICE
 317                                         : DMA_FROM_DEVICE);
 318                         req->req.dma = DMA_ADDR_INVALID;
 319                         req->mapped = 0;
 320                 } else
 321                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 322                                 req->req.dma, req->req.length,
 323                                 (ep->bEndpointAddress & USB_DIR_IN)
 324                                         ? DMA_TO_DEVICE
 325                                         : DMA_FROM_DEVICE);
 326         }
 327
 328 #ifndef USB_TRACE
 329         if (status && status != -ESHUTDOWN)
 330 #endif
 331                 VDBG("complete %s req %p stat %d len %u/%u\n",
 332                         ep->ep.name, &req->req, status,
 333                         req->req.actual, req->req.length);
 334
 335         /* don't modify queue heads during completion callback */
 336         ep->stopped = 1;
 337         spin_unlock(&ep->udc->lock);
 338         req->req.complete(&ep->ep, &req->req);
 339         spin_lock(&ep->udc->lock);
 340         ep->stopped = stopped;
 341 }
 342
 343 /*-------------------------------------------------------------------------*/
 344
 345 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 346 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 347
 348 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 349 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 350
 351 static inline int
 352 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 353 {
 354         unsigned        len;
 355         u16             *wp;
 356
 357         len = min(req->req.length - req->req.actual, max);
 358         req->req.actual += len;
 359
 360         max = len;
 361         if (likely((((int)buf) & 1) == 0)) {
 362                 wp = (u16 *)buf;
 363                 while (max >= 2) {
 364                         UDC_DATA_REG = *wp++;
 365                         max -= 2;
 366                 }
 367                 buf = (u8 *)wp;
 368         }
 369         while (max--)
 370                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
 371         return len;
 372 }
 373
 374 // FIXME change r/w fifo calling convention
 375
 376
 377 // return:  0 = still running, 1 = completed, negative = errno
 378 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 379 {
 380         u8              *buf;
 381         unsigned        count;
 382         int             is_last;
 383         u16             ep_stat;
 384
 385         buf = req->req.buf + req->req.actual;
 386         prefetch(buf);
 387
 388         /* PIO-IN isn't double buffered except for iso */
 389         ep_stat = UDC_STAT_FLG_REG;
 390         if (ep_stat & UDC_FIFO_UNWRITABLE)
 391                 return 0;
 392
 393         count = ep->ep.maxpacket;
 394         count = write_packet(buf, req, count);
 395         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 396         ep->ackwait = 1;
 397
 398         /* last packet is often short (sometimes a zlp) */
 399         if (count != ep->ep.maxpacket)
 400                 is_last = 1;
 401         else if (req->req.length == req->req.actual
 402                         && !req->req.zero)
 403                 is_last = 1;
 404         else
 405                 is_last = 0;
 406
 407         /* NOTE:  requests complete when all IN data is in a
 408          * FIFO (or sometimes later, if a zlp was needed).
 409          * Use usb_ep_fifo_status() where needed.
 410          */
 411         if (is_last)
 412                 done(ep, req, 0);
 413         return is_last;
 414 }
 415
 416 static inline int
 417 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 418 {
 419         unsigned        len;
 420         u16             *wp;
 421
 422         len = min(req->req.length - req->req.actual, avail);
 423         req->req.actual += len;
 424         avail = len;
 425
 426         if (likely((((int)buf) & 1) == 0)) {
 427                 wp = (u16 *)buf;
 428                 while (avail >= 2) {
 429                         *wp++ = UDC_DATA_REG;
 430                         avail -= 2;
 431                 }
 432                 buf = (u8 *)wp;
 433         }
 434         while (avail--)
 435                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
 436         return len;
 437 }
 438
 439 // return:  0 = still running, 1 = queue empty, negative = errno
 440 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 441 {
 442         u8              *buf;
 443         unsigned        count, avail;
 444         int             is_last;
 445
 446         buf = req->req.buf + req->req.actual;
 447         prefetchw(buf);
 448
 449         for (;;) {
 450                 u16     ep_stat = UDC_STAT_FLG_REG;
 451
 452                 is_last = 0;
 453                 if (ep_stat & FIFO_EMPTY) {
 454                         if (!ep->double_buf)
 455                                 break;
 456                         ep->fnf = 1;
 457                 }
 458                 if (ep_stat & UDC_EP_HALTED)
 459                         break;
 460
 461                 if (ep_stat & UDC_FIFO_FULL)
 462                         avail = ep->ep.maxpacket;
 463                 else  {
 464                         avail = UDC_RXFSTAT_REG;
 465                         ep->fnf = ep->double_buf;
 466                 }
 467                 count = read_packet(buf, req, avail);
 468
 469                 /* partial packet reads may not be errors */
 470                 if (count < ep->ep.maxpacket) {
 471                         is_last = 1;
 472                         /* overflowed this request?  flush extra data */
 473                         if (count != avail) {
 474                                 req->req.status = -EOVERFLOW;
 475                                 avail -= count;
 476                                 while (avail--)
 477                                         (void) *(volatile u8 *)&UDC_DATA_REG;
 478                         }
 479                 } else if (req->req.length == req->req.actual)
 480                         is_last = 1;
 481                 else
 482                         is_last = 0;
 483
 484                 if (!ep->bEndpointAddress)
 485                         break;
 486                 if (is_last)
 487                         done(ep, req, 0);
 488                 break;
 489         }
 490         return is_last;
 491 }
 492
 493 /*-------------------------------------------------------------------------*/
 494
 495 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 496 {
 497         dma_addr_t      end;
 498
 499         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 500          * the last transfer's bytecount by more than a FIFO's worth.
 501          */
 502         if (cpu_is_omap15xx())
 503                 return 0;
 504
 505         end = omap_get_dma_src_pos(ep->lch);
 506         if (end == ep->dma_counter)
 507                 return 0;
 508
 509         end |= start & (0xffff << 16);
 510         if (end < start)
 511                 end += 0x10000;
 512         return end - start;
 513 }
 514
 515 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 516 {
 517         dma_addr_t      end;
 518
 519         end = omap_get_dma_dst_pos(ep->lch);
 520         if (end == ep->dma_counter)
 521                 return 0;
 522
 523         end |= start & (0xffff << 16);
 524         if (cpu_is_omap15xx())
 525                 end++;
 526         if (end < start)
 527                 end += 0x10000;
 528         return end - start;
 529 }
 530
 531
 532 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 533  * When DMA completion isn't request completion, the UDC continues with
 534  * the next DMA transfer for that USB transfer.
 535  */
 536
 537 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 538 {
 539         u16             txdma_ctrl;
 540         unsigned        length = req->req.length - req->req.actual;
 541         const int       sync_mode = cpu_is_omap15xx()
 542                                 ? OMAP_DMA_SYNC_FRAME
 543                                 : OMAP_DMA_SYNC_ELEMENT;
 544         int             dma_trigger = 0;
 545
 546         if (cpu_is_omap24xx())
 547                 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
 548
 549         /* measure length in either bytes or packets */
 550         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 551                         || (cpu_is_omap24xx() && length < ep->maxpacket)
 552                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 553                 txdma_ctrl = UDC_TXN_EOT | length;
 554                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 555                                 length, 1, sync_mode, dma_trigger, 0);
 556         } else {
 557                 length = min(length / ep->maxpacket,
 558                                 (unsigned) UDC_TXN_TSC + 1);
 559                 txdma_ctrl = length;
 560                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 561                                 ep->ep.maxpacket >> 1, length, sync_mode,
 562                                 dma_trigger, 0);
 563                 length *= ep->maxpacket;
 564         }
 565         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 566                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 567                 0, 0);
 568
 569         omap_start_dma(ep->lch);
 570         ep->dma_counter = omap_get_dma_src_pos(ep->lch);
 571         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
 572         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
 573         req->dma_bytes = length;
 574 }
 575
 576 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 577 {
 578         if (status == 0) {
 579                 req->req.actual += req->dma_bytes;
 580
 581                 /* return if this request needs to send data or zlp */
 582                 if (req->req.actual < req->req.length)
 583                         return;
 584                 if (req->req.zero
 585                                 && req->dma_bytes != 0
 586                                 && (req->req.actual % ep->maxpacket) == 0)
 587                         return;
 588         } else
 589                 req->req.actual += dma_src_len(ep, req->req.dma
 590                                                         + req->req.actual);
 591
 592         /* tx completion */
 593         omap_stop_dma(ep->lch);
 594         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
 595         done(ep, req, status);
 596 }
 597
 598 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 599 {
 600         unsigned packets = req->req.length - req->req.actual;
 601         int dma_trigger = 0;
 602
 603         if (cpu_is_omap24xx())
 604                 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
 605
 606         /* NOTE:  we filtered out "short reads" before, so we know
 607          * the buffer has only whole numbers of packets.
 608          * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
 609          */
 610         if (cpu_is_omap24xx() && packets < ep->maxpacket) {
 611                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 612                                 packets, 1, OMAP_DMA_SYNC_ELEMENT,
 613                                 dma_trigger, 0);
 614                 req->dma_bytes = packets;
 615         } else {
 616                 /* set up this DMA transfer, enable the fifo, start */
 617                 packets /= ep->ep.maxpacket;
 618                 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 619                 req->dma_bytes = packets * ep->ep.maxpacket;
 620                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 621                                 ep->ep.maxpacket >> 1, packets,
 622                                 OMAP_DMA_SYNC_ELEMENT,
 623                                 dma_trigger, 0);
 624         }
 625         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 626                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 627                 0, 0);
 628         ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
 629
 630         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
 631         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
 632         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
 633         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 634
 635         omap_start_dma(ep->lch);
 636 }
 637
 638 static void
 639 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 640 {
 641         u16     count;
 642
 643         if (status == 0)
 644                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 645         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 646         count += req->req.actual;
 647         if (one)
 648                 count--;
 649         if (count <= req->req.length)
 650                 req->req.actual = count;
 651
 652         if (count != req->dma_bytes || status)
 653                 omap_stop_dma(ep->lch);
 654
 655         /* if this wasn't short, request may need another transfer */
 656         else if (req->req.actual < req->req.length)
 657                 return;
 658
 659         /* rx completion */
 660         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
 661         done(ep, req, status);
 662 }
 663
 664 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 665 {
 666         u16             dman_stat = UDC_DMAN_STAT_REG;
 667         struct omap_ep  *ep;
 668         struct omap_req *req;
 669
 670         /* IN dma: tx to host */
 671         if (irq_src & UDC_TXN_DONE) {
 672                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 673                 ep->irqs++;
 674                 /* can see TXN_DONE after dma abort */
 675                 if (!list_empty(&ep->queue)) {
 676                         req = container_of(ep->queue.next,
 677                                                 struct omap_req, queue);
 678                         finish_in_dma(ep, req, 0);
 679                 }
 680                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
 681
 682                 if (!list_empty (&ep->queue)) {
 683                         req = container_of(ep->queue.next,
 684                                         struct omap_req, queue);
 685                         next_in_dma(ep, req);
 686                 }
 687         }
 688
 689         /* OUT dma: rx from host */
 690         if (irq_src & UDC_RXN_EOT) {
 691                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 692                 ep->irqs++;
 693                 /* can see RXN_EOT after dma abort */
 694                 if (!list_empty(&ep->queue)) {
 695                         req = container_of(ep->queue.next,
 696                                         struct omap_req, queue);
 697                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 698                 }
 699                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
 700
 701                 if (!list_empty (&ep->queue)) {
 702                         req = container_of(ep->queue.next,
 703                                         struct omap_req, queue);
 704                         next_out_dma(ep, req);
 705                 }
 706         }
 707
 708         if (irq_src & UDC_RXN_CNT) {
 709                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 710                 ep->irqs++;
 711                 /* omap15xx does this unasked... */
 712                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 713                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
 714         }
 715 }
 716
 717 static void dma_error(int lch, u16 ch_status, void *data)
 718 {
 719         struct omap_ep  *ep = data;
 720
 721         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 722         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 723         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 724
 725         /* complete current transfer ... */
 726 }
 727
 728 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 729 {
 730         u16     reg;
 731         int     status, restart, is_in;
 732         int     dma_channel;
 733
 734         is_in = ep->bEndpointAddress & USB_DIR_IN;
 735         if (is_in)
 736                 reg = UDC_TXDMA_CFG_REG;
 737         else
 738                 reg = UDC_RXDMA_CFG_REG;
 739         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 740
 741         ep->dma_channel = 0;
 742         ep->lch = -1;
 743         if (channel == 0 || channel > 3) {
 744                 if ((reg & 0x0f00) == 0)
 745                         channel = 3;
 746                 else if ((reg & 0x00f0) == 0)
 747                         channel = 2;
 748                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 749                         channel = 1;
 750                 else {
 751                         status = -EMLINK;
 752                         goto just_restart;
 753                 }
 754         }
 755         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 756         ep->dma_channel = channel;
 757
 758         if (is_in) {
 759                 if (cpu_is_omap24xx())
 760                         dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
 761                 else
 762                         dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
 763                 status = omap_request_dma(dma_channel,
 764                         ep->ep.name, dma_error, ep, &ep->lch);
 765                 if (status == 0) {
 766                         UDC_TXDMA_CFG_REG = reg;
 767                         /* EMIFF or SDRC */
 768                         omap_set_dma_src_burst_mode(ep->lch,
 769                                                 OMAP_DMA_DATA_BURST_4);
 770                         omap_set_dma_src_data_pack(ep->lch, 1);
 771                         /* TIPB */
 772                         omap_set_dma_dest_params(ep->lch,
 773                                 OMAP_DMA_PORT_TIPB,
 774                                 OMAP_DMA_AMODE_CONSTANT,
 775                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 776                                 0, 0);
 777                 }
 778         } else {
 779                 if (cpu_is_omap24xx())
 780                         dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
 781                 else
 782                         dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
 783
 784                 status = omap_request_dma(dma_channel,
 785                         ep->ep.name, dma_error, ep, &ep->lch);
 786                 if (status == 0) {
 787                         UDC_RXDMA_CFG_REG = reg;
 788                         /* TIPB */
 789                         omap_set_dma_src_params(ep->lch,
 790                                 OMAP_DMA_PORT_TIPB,
 791                                 OMAP_DMA_AMODE_CONSTANT,
 792                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 793                                 0, 0);
 794                         /* EMIFF or SDRC */
 795                         omap_set_dma_dest_burst_mode(ep->lch,
 796                                                 OMAP_DMA_DATA_BURST_4);
 797                         omap_set_dma_dest_data_pack(ep->lch, 1);
 798                 }
 799         }
 800         if (status)
 801                 ep->dma_channel = 0;
 802         else {
 803                 ep->has_dma = 1;
 804                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 805
 806                 /* channel type P: hw synch (fifo) */
 807                 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
 808                         omap_set_dma_color_mode(ep->lch,
 809                                         OMAP_DMA_TRANSPARENT_COPY, 0);
 810         }
 811
 812 just_restart:
 813         /* restart any queue, even if the claim failed  */
 814         restart = !ep->stopped && !list_empty(&ep->queue);
 815
 816         if (status)
 817                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 818                         restart ? " (restart)" : "");
 819         else
 820                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 821                         is_in ? 't' : 'r',
 822                         ep->dma_channel - 1, ep->lch,
 823                         restart ? " (restart)" : "");
 824
 825         if (restart) {
 826                 struct omap_req *req;
 827                 req = container_of(ep->queue.next, struct omap_req, queue);
 828                 if (ep->has_dma)
 829                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 830                 else {
 831                         use_ep(ep, UDC_EP_SEL);
 832                         (is_in ? write_fifo : read_fifo)(ep, req);
 833                         deselect_ep();
 834                         if (!is_in) {
 835                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 836                                 ep->ackwait = 1 + ep->double_buf;
 837                         }
 838                         /* IN: 6 wait states before it'll tx */
 839                 }
 840         }
 841 }
 842
 843 static void dma_channel_release(struct omap_ep *ep)
 844 {
 845         int             shift = 4 * (ep->dma_channel - 1);
 846         u16             mask = 0x0f << shift;
 847         struct omap_req *req;
 848         int             active;
 849
 850         /* abort any active usb transfer request */
 851         if (!list_empty(&ep->queue))
 852                 req = container_of(ep->queue.next, struct omap_req, queue);
 853         else
 854                 req = NULL;
 855
 856         active = omap_get_dma_active_status(ep->lch);
 857
 858         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 859                         active ? "active" : "idle",
 860                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 861                         ep->dma_channel - 1, req);
 862
 863         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 864          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 865          */
 866
 867         /* wait till current packet DMA finishes, and fifo empties */
 868         if (ep->bEndpointAddress & USB_DIR_IN) {
 869                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 870
 871                 if (req) {
 872                         finish_in_dma(ep, req, -ECONNRESET);
 873
 874                         /* clear FIFO; hosts probably won't empty it */
 875                         use_ep(ep, UDC_EP_SEL);
 876                         UDC_CTRL_REG = UDC_CLR_EP;
 877                         deselect_ep();
 878                 }
 879                 while (UDC_TXDMA_CFG_REG & mask)
 880                         udelay(10);
 881         } else {
 882                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 883
 884                 /* dma empties the fifo */
 885                 while (UDC_RXDMA_CFG_REG & mask)
 886                         udelay(10);
 887                 if (req)
 888                         finish_out_dma(ep, req, -ECONNRESET, 0);
 889         }
 890         omap_free_dma(ep->lch);
 891         ep->dma_channel = 0;
 892         ep->lch = -1;
 893         /* has_dma still set, till endpoint is fully quiesced */
 894 }
 895
 896
 897 /*-------------------------------------------------------------------------*/
 898
 899 static int
 900 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 901 {
 902         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 903         struct omap_req *req = container_of(_req, struct omap_req, req);
 904         struct omap_udc *udc;
 905         unsigned long   flags;
 906         int             is_iso = 0;
 907
 908         /* catch various bogus parameters */
 909         if (!_req || !req->req.complete || !req->req.buf
 910                         || !list_empty(&req->queue)) {
 911                 DBG("%s, bad params\n", __func__);
 912                 return -EINVAL;
 913         }
 914         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 915                 DBG("%s, bad ep\n", __func__);
 916                 return -EINVAL;
 917         }
 918         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 919                 if (req->req.length > ep->ep.maxpacket)
 920                         return -EMSGSIZE;
 921                 is_iso = 1;
 922         }
 923
 924         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 925          * have a hard time with partial packet reads...  reject it.
 926          * Except OMAP2 can handle the small packets.
 927          */
 928         if (use_dma
 929                         && ep->has_dma
 930                         && ep->bEndpointAddress != 0
 931                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 932                         && !cpu_class_is_omap2()
 933                         && (req->req.length % ep->ep.maxpacket) != 0) {
 934                 DBG("%s, no partial packet OUT reads\n", __func__);
 935                 return -EMSGSIZE;
 936         }
 937
 938         udc = ep->udc;
 939         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 940                 return -ESHUTDOWN;
 941
 942         if (use_dma && ep->has_dma) {
 943                 if (req->req.dma == DMA_ADDR_INVALID) {
 944                         req->req.dma = dma_map_single(
 945                                 ep->udc->gadget.dev.parent,
 946                                 req->req.buf,
 947                                 req->req.length,
 948                                 (ep->bEndpointAddress & USB_DIR_IN)
 949                                         ? DMA_TO_DEVICE
 950                                         : DMA_FROM_DEVICE);
 951                         req->mapped = 1;
 952                 } else {
 953                         dma_sync_single_for_device(
 954                                 ep->udc->gadget.dev.parent,
 955                                 req->req.dma, req->req.length,
 956                                 (ep->bEndpointAddress & USB_DIR_IN)
 957                                         ? DMA_TO_DEVICE
 958                                         : DMA_FROM_DEVICE);
 959                         req->mapped = 0;
 960                 }
 961         }
 962
 963         VDBG("%s queue req %p, len %d buf %p\n",
 964                 ep->ep.name, _req, _req->length, _req->buf);
 965
 966         spin_lock_irqsave(&udc->lock, flags);
 967
 968         req->req.status = -EINPROGRESS;
 969         req->req.actual = 0;
 970
 971         /* maybe kickstart non-iso i/o queues */
 972         if (is_iso)
 973                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
 974         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
 975                 int     is_in;
 976
 977                 if (ep->bEndpointAddress == 0) {
 978                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
 979                                 spin_unlock_irqrestore(&udc->lock, flags);
 980                                 return -EL2HLT;
 981                         }
 982
 983                         /* empty DATA stage? */
 984                         is_in = udc->ep0_in;
 985                         if (!req->req.length) {
 986
 987                                 /* chip became CONFIGURED or ADDRESSED
 988                                  * earlier; drivers may already have queued
 989                                  * requests to non-control endpoints
 990                                  */
 991                                 if (udc->ep0_set_config) {
 992                                         u16     irq_en = UDC_IRQ_EN_REG;
 993
 994                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
 995                                         if (!udc->ep0_reset_config)
 996                                                 irq_en |= UDC_EPN_RX_IE
 997                                                         | UDC_EPN_TX_IE;
 998                                         UDC_IRQ_EN_REG = irq_en;
 999                                 }
1000
1001                                 /* STATUS for zero length DATA stages is
1002                                  * always an IN ... even for IN transfers,
1003                                  * a weird case which seem to stall OMAP.
1004                                  */
1005                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1006                                 UDC_CTRL_REG = UDC_CLR_EP;
1007                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1008                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1009
1010                                 /* cleanup */
1011                                 udc->ep0_pending = 0;
1012                                 done(ep, req, 0);
1013                                 req = NULL;
1014
1015                         /* non-empty DATA stage */
1016                         } else if (is_in) {
1017                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1018                         } else {
1019                                 if (udc->ep0_setup)
1020                                         goto irq_wait;
1021                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1022                         }
1023                 } else {
1024                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1025                         if (!ep->has_dma)
1026                                 use_ep(ep, UDC_EP_SEL);
1027                         /* if ISO: SOF IRQs must be enabled/disabled! */
1028                 }
1029
1030                 if (ep->has_dma)
1031                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1032                 else if (req) {
1033                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1034                                 req = NULL;
1035                         deselect_ep();
1036                         if (!is_in) {
1037                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1038                                 ep->ackwait = 1 + ep->double_buf;
1039                         }
1040                         /* IN: 6 wait states before it'll tx */
1041                 }
1042         }
1043
1044 irq_wait:
1045         /* irq handler advances the queue */
1046         if (req != NULL)
1047                 list_add_tail(&req->queue, &ep->queue);
1048         spin_unlock_irqrestore(&udc->lock, flags);
1049
1050         return 0;
1051 }
1052
1053 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1054 {
1055         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1056         struct omap_req *req;
1057         unsigned long   flags;
1058
1059         if (!_ep || !_req)
1060                 return -EINVAL;
1061
1062         spin_lock_irqsave(&ep->udc->lock, flags);
1063
1064         /* make sure it's actually queued on this endpoint */
1065         list_for_each_entry (req, &ep->queue, queue) {
1066                 if (&req->req == _req)
1067                         break;
1068         }
1069         if (&req->req != _req) {
1070                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1071                 return -EINVAL;
1072         }
1073
1074         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1075                 int channel = ep->dma_channel;
1076
1077                 /* releasing the channel cancels the request,
1078                  * reclaiming the channel restarts the queue
1079                  */
1080                 dma_channel_release(ep);
1081                 dma_channel_claim(ep, channel);
1082         } else
1083                 done(ep, req, -ECONNRESET);
1084         spin_unlock_irqrestore(&ep->udc->lock, flags);
1085         return 0;
1086 }
1087
1088 /*-------------------------------------------------------------------------*/
1089
1090 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1091 {
1092         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1093         unsigned long   flags;
1094         int             status = -EOPNOTSUPP;
1095
1096         spin_lock_irqsave(&ep->udc->lock, flags);
1097
1098         /* just use protocol stalls for ep0; real halts are annoying */
1099         if (ep->bEndpointAddress == 0) {
1100                 if (!ep->udc->ep0_pending)
1101                         status = -EINVAL;
1102                 else if (value) {
1103                         if (ep->udc->ep0_set_config) {
1104                                 WARN("error changing config?\n");
1105                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1106                         }
1107                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1108                         ep->udc->ep0_pending = 0;
1109                         status = 0;
1110                 } else /* NOP */
1111                         status = 0;
1112
1113         /* otherwise, all active non-ISO endpoints can halt */
1114         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1115
1116                 /* IN endpoints must already be idle */
1117                 if ((ep->bEndpointAddress & USB_DIR_IN)
1118                                 && !list_empty(&ep->queue)) {
1119                         status = -EAGAIN;
1120                         goto done;
1121                 }
1122
1123                 if (value) {
1124                         int     channel;
1125
1126                         if (use_dma && ep->dma_channel
1127                                         && !list_empty(&ep->queue)) {
1128                                 channel = ep->dma_channel;
1129                                 dma_channel_release(ep);
1130                         } else
1131                                 channel = 0;
1132
1133                         use_ep(ep, UDC_EP_SEL);
1134                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1135                                 UDC_CTRL_REG = UDC_SET_HALT;
1136                                 status = 0;
1137                         } else
1138                                 status = -EAGAIN;
1139                         deselect_ep();
1140
1141                         if (channel)
1142                                 dma_channel_claim(ep, channel);
1143                 } else {
1144                         use_ep(ep, 0);
1145                         UDC_CTRL_REG = ep->udc->clr_halt;
1146                         ep->ackwait = 0;
1147                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1148                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1149                                 ep->ackwait = 1 + ep->double_buf;
1150                         }
1151                 }
1152         }
1153 done:
1154         VDBG("%s %s halt stat %d\n", ep->ep.name,
1155                 value ? "set" : "clear", status);
1156
1157         spin_unlock_irqrestore(&ep->udc->lock, flags);
1158         return status;
1159 }
1160
1161 static struct usb_ep_ops omap_ep_ops = {
1162         .enable         = omap_ep_enable,
1163         .disable        = omap_ep_disable,
1164
1165         .alloc_request  = omap_alloc_request,
1166         .free_request   = omap_free_request,
1167
1168         .queue          = omap_ep_queue,
1169         .dequeue        = omap_ep_dequeue,
1170
1171         .set_halt       = omap_ep_set_halt,
1172         // fifo_status ... report bytes in fifo
1173         // fifo_flush ... flush fifo
1174 };
1175
1176 /*-------------------------------------------------------------------------*/
1177
1178 static int omap_get_frame(struct usb_gadget *gadget)
1179 {
1180         u16     sof = UDC_SOF_REG;
1181         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1182 }
1183
1184 static int omap_wakeup(struct usb_gadget *gadget)
1185 {
1186         struct omap_udc *udc;
1187         unsigned long   flags;
1188         int             retval = -EHOSTUNREACH;
1189
1190         udc = container_of(gadget, struct omap_udc, gadget);
1191
1192         spin_lock_irqsave(&udc->lock, flags);
1193         if (udc->devstat & UDC_SUS) {
1194                 /* NOTE:  OTG spec erratum says that OTG devices may
1195                  * issue wakeups without host enable.
1196                  */
1197                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1198                         DBG("remote wakeup...\n");
1199                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1200                         retval = 0;
1201                 }
1202
1203         /* NOTE:  non-OTG systems may use SRP TOO... */
1204         } else if (!(udc->devstat & UDC_ATT)) {
1205                 if (udc->transceiver)
1206                         retval = otg_start_srp(udc->transceiver);
1207         }
1208         spin_unlock_irqrestore(&udc->lock, flags);
1209
1210         return retval;
1211 }
1212
1213 static int
1214 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1215 {
1216         struct omap_udc *udc;
1217         unsigned long   flags;
1218         u16             syscon1;
1219
1220         udc = container_of(gadget, struct omap_udc, gadget);
1221         spin_lock_irqsave(&udc->lock, flags);
1222         syscon1 = UDC_SYSCON1_REG;
1223         if (is_selfpowered)
1224                 syscon1 |= UDC_SELF_PWR;
1225         else
1226                 syscon1 &= ~UDC_SELF_PWR;
1227         UDC_SYSCON1_REG = syscon1;
1228         spin_unlock_irqrestore(&udc->lock, flags);
1229
1230         return 0;
1231 }
1232
1233 static int can_pullup(struct omap_udc *udc)
1234 {
1235         return udc->driver && udc->softconnect && udc->vbus_active;
1236 }
1237
1238 static void pullup_enable(struct omap_udc *udc)
1239 {
1240         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1241         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1242                 OTG_CTRL_REG |= OTG_BSESSVLD;
1243         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1244 }
1245
1246 static void pullup_disable(struct omap_udc *udc)
1247 {
1248         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1249                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1250         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1251         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1252 }
1253
1254 static struct omap_udc *udc;
1255
1256 static void omap_udc_enable_clock(int enable)
1257 {
1258         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1259                 return;
1260
1261         if (enable) {
1262                 clk_enable(udc->dc_clk);
1263                 clk_enable(udc->hhc_clk);
1264                 udelay(100);
1265         } else {
1266                 clk_disable(udc->hhc_clk);
1267                 clk_disable(udc->dc_clk);
1268         }
1269 }
1270
1271 /*
1272  * Called by whatever detects VBUS sessions:  external transceiver
1273  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1274  */
1275 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1276 {
1277         struct omap_udc *udc;
1278         unsigned long   flags;
1279
1280         udc = container_of(gadget, struct omap_udc, gadget);
1281         spin_lock_irqsave(&udc->lock, flags);
1282         VDBG("VBUS %s\n", is_active ? "on" : "off");
1283         udc->vbus_active = (is_active != 0);
1284         if (cpu_is_omap15xx()) {
1285                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1286                 if (is_active)
1287                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1288                 else
1289                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1290         }
1291         if (udc->dc_clk != NULL && is_active) {
1292                 if (!udc->clk_requested) {
1293                         omap_udc_enable_clock(1);
1294                         udc->clk_requested = 1;
1295                 }
1296         }
1297         if (can_pullup(udc))
1298                 pullup_enable(udc);
1299         else
1300                 pullup_disable(udc);
1301         if (udc->dc_clk != NULL && !is_active) {
1302                 if (udc->clk_requested) {
1303                         omap_udc_enable_clock(0);
1304                         udc->clk_requested = 0;
1305                 }
1306         }
1307         spin_unlock_irqrestore(&udc->lock, flags);
1308         return 0;
1309 }
1310
1311 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1312 {
1313         struct omap_udc *udc;
1314
1315         udc = container_of(gadget, struct omap_udc, gadget);
1316         if (udc->transceiver)
1317                 return otg_set_power(udc->transceiver, mA);
1318         return -EOPNOTSUPP;
1319 }
1320
1321 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1322 {
1323         struct omap_udc *udc;
1324         unsigned long   flags;
1325
1326         udc = container_of(gadget, struct omap_udc, gadget);
1327         spin_lock_irqsave(&udc->lock, flags);
1328         udc->softconnect = (is_on != 0);
1329         if (can_pullup(udc))
1330                 pullup_enable(udc);
1331         else
1332                 pullup_disable(udc);
1333         spin_unlock_irqrestore(&udc->lock, flags);
1334         return 0;
1335 }
1336
1337 static struct usb_gadget_ops omap_gadget_ops = {
1338         .get_frame              = omap_get_frame,
1339         .wakeup                 = omap_wakeup,
1340         .set_selfpowered        = omap_set_selfpowered,
1341         .vbus_session           = omap_vbus_session,
1342         .vbus_draw              = omap_vbus_draw,
1343         .pullup                 = omap_pullup,
1344 };
1345
1346 /*-------------------------------------------------------------------------*/
1347
1348 /* dequeue ALL requests; caller holds udc->lock */
1349 static void nuke(struct omap_ep *ep, int status)
1350 {
1351         struct omap_req *req;
1352
1353         ep->stopped = 1;
1354
1355         if (use_dma && ep->dma_channel)
1356                 dma_channel_release(ep);
1357
1358         use_ep(ep, 0);
1359         UDC_CTRL_REG = UDC_CLR_EP;
1360         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1361                 UDC_CTRL_REG = UDC_SET_HALT;
1362
1363         while (!list_empty(&ep->queue)) {
1364                 req = list_entry(ep->queue.next, struct omap_req, queue);
1365                 done(ep, req, status);
1366         }
1367 }
1368
1369 /* caller holds udc->lock */
1370 static void udc_quiesce(struct omap_udc *udc)
1371 {
1372         struct omap_ep  *ep;
1373
1374         udc->gadget.speed = USB_SPEED_UNKNOWN;
1375         nuke(&udc->ep[0], -ESHUTDOWN);
1376         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1377                 nuke(ep, -ESHUTDOWN);
1378 }
1379
1380 /*-------------------------------------------------------------------------*/
1381
1382 static void update_otg(struct omap_udc *udc)
1383 {
1384         u16     devstat;
1385
1386         if (!gadget_is_otg(&udc->gadget))
1387                 return;
1388
1389         if (OTG_CTRL_REG & OTG_ID)
1390                 devstat = UDC_DEVSTAT_REG;
1391         else
1392                 devstat = 0;
1393
1394         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1395         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1396         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1397
1398         /* Enable HNP early, avoiding races on suspend irq path.
1399          * ASSUMES OTG state machine B_BUS_REQ input is true.
1400          */
1401         if (udc->gadget.b_hnp_enable)
1402                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1403                                 & ~OTG_PULLUP;
1404 }
1405
1406 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1407 {
1408         struct omap_ep  *ep0 = &udc->ep[0];
1409         struct omap_req *req = NULL;
1410
1411         ep0->irqs++;
1412
1413         /* Clear any pending requests and then scrub any rx/tx state
1414          * before starting to handle the SETUP request.
1415          */
1416         if (irq_src & UDC_SETUP) {
1417                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1418
1419                 nuke(ep0, 0);
1420                 if (ack) {
1421                         UDC_IRQ_SRC_REG = ack;
1422                         irq_src = UDC_SETUP;
1423                 }
1424         }
1425
1426         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1427          * This driver uses only uses protocol stalls (ep0 never halts),
1428          * and if we got this far the gadget driver already had a
1429          * chance to stall.  Tries to be forgiving of host oddities.
1430          *
1431          * NOTE:  the last chance gadget drivers have to stall control
1432          * requests is during their request completion callback.
1433          */
1434         if (!list_empty(&ep0->queue))
1435                 req = container_of(ep0->queue.next, struct omap_req, queue);
1436
1437         /* IN == TX to host */
1438         if (irq_src & UDC_EP0_TX) {
1439                 int     stat;
1440
1441                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1442                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1443                 stat = UDC_STAT_FLG_REG;
1444                 if (stat & UDC_ACK) {
1445                         if (udc->ep0_in) {
1446                                 /* write next IN packet from response,
1447                                  * or set up the status stage.
1448                                  */
1449                                 if (req)
1450                                         stat = write_fifo(ep0, req);
1451                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1452                                 if (!req && udc->ep0_pending) {
1453                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1454                                         UDC_CTRL_REG = UDC_CLR_EP;
1455                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1456                                         UDC_EP_NUM_REG = 0;
1457                                         udc->ep0_pending = 0;
1458                                 } /* else:  6 wait states before it'll tx */
1459                         } else {
1460                                 /* ack status stage of OUT transfer */
1461                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1462                                 if (req)
1463                                         done(ep0, req, 0);
1464                         }
1465                         req = NULL;
1466                 } else if (stat & UDC_STALL) {
1467                         UDC_CTRL_REG = UDC_CLR_HALT;
1468                         UDC_EP_NUM_REG = UDC_EP_DIR;
1469                 } else {
1470                         UDC_EP_NUM_REG = UDC_EP_DIR;
1471                 }
1472         }
1473
1474         /* OUT == RX from host */
1475         if (irq_src & UDC_EP0_RX) {
1476                 int     stat;
1477
1478                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1479                 UDC_EP_NUM_REG = UDC_EP_SEL;
1480                 stat = UDC_STAT_FLG_REG;
1481                 if (stat & UDC_ACK) {
1482                         if (!udc->ep0_in) {
1483                                 stat = 0;
1484                                 /* read next OUT packet of request, maybe
1485                                  * reactiviting the fifo; stall on errors.
1486                                  */
1487                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1488                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1489                                         udc->ep0_pending = 0;
1490                                         stat = 0;
1491                                 } else if (stat == 0)
1492                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1493                                 UDC_EP_NUM_REG = 0;
1494
1495                                 /* activate status stage */
1496                                 if (stat == 1) {
1497                                         done(ep0, req, 0);
1498                                         /* that may have STALLed ep0... */
1499                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1500                                         UDC_CTRL_REG = UDC_CLR_EP;
1501                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1502                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1503                                         udc->ep0_pending = 0;
1504                                 }
1505                         } else {
1506                                 /* ack status stage of IN transfer */
1507                                 UDC_EP_NUM_REG = 0;
1508                                 if (req)
1509                                         done(ep0, req, 0);
1510                         }
1511                 } else if (stat & UDC_STALL) {
1512                         UDC_CTRL_REG = UDC_CLR_HALT;
1513                         UDC_EP_NUM_REG = 0;
1514                 } else {
1515                         UDC_EP_NUM_REG = 0;
1516                 }
1517         }
1518
1519         /* SETUP starts all control transfers */
1520         if (irq_src & UDC_SETUP) {
1521                 union u {
1522                         u16                     word[4];
1523                         struct usb_ctrlrequest  r;
1524                 } u;
1525                 int                     status = -EINVAL;
1526                 struct omap_ep          *ep;
1527
1528                 /* read the (latest) SETUP message */
1529                 do {
1530                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1531                         /* two bytes at a time */
1532                         u.word[0] = UDC_DATA_REG;
1533                         u.word[1] = UDC_DATA_REG;
1534                         u.word[2] = UDC_DATA_REG;
1535                         u.word[3] = UDC_DATA_REG;
1536                         UDC_EP_NUM_REG = 0;
1537                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1538
1539 #define w_value         le16_to_cpu(u.r.wValue)
1540 #define w_index         le16_to_cpu(u.r.wIndex)
1541 #define w_length        le16_to_cpu(u.r.wLength)
1542
1543                 /* Delegate almost all control requests to the gadget driver,
1544                  * except for a handful of ch9 status/feature requests that
1545                  * hardware doesn't autodecode _and_ the gadget API hides.
1546                  */
1547                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1548                 udc->ep0_set_config = 0;
1549                 udc->ep0_pending = 1;
1550                 ep0->stopped = 0;
1551                 ep0->ackwait = 0;
1552                 switch (u.r.bRequest) {
1553                 case USB_REQ_SET_CONFIGURATION:
1554                         /* udc needs to know when ep != 0 is valid */
1555                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1556                                 goto delegate;
1557                         if (w_length != 0)
1558                                 goto do_stall;
1559                         udc->ep0_set_config = 1;
1560                         udc->ep0_reset_config = (w_value == 0);
1561                         VDBG("set config %d\n", w_value);
1562
1563                         /* update udc NOW since gadget driver may start
1564                          * queueing requests immediately; clear config
1565                          * later if it fails the request.
1566                          */
1567                         if (udc->ep0_reset_config)
1568                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1569                         else
1570                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1571                         update_otg(udc);
1572                         goto delegate;
1573                 case USB_REQ_CLEAR_FEATURE:
1574                         /* clear endpoint halt */
1575                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1576                                 goto delegate;
1577                         if (w_value != USB_ENDPOINT_HALT
1578                                         || w_length != 0)
1579                                 goto do_stall;
1580                         ep = &udc->ep[w_index & 0xf];
1581                         if (ep != ep0) {
1582                                 if (w_index & USB_DIR_IN)
1583                                         ep += 16;
1584                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1585                                                 || !ep->desc)
1586                                         goto do_stall;
1587                                 use_ep(ep, 0);
1588                                 UDC_CTRL_REG = udc->clr_halt;
1589                                 ep->ackwait = 0;
1590                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1591                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1592                                         ep->ackwait = 1 + ep->double_buf;
1593                                 }
1594                                 /* NOTE:  assumes the host behaves sanely,
1595                                  * only clearing real halts.  Else we may
1596                                  * need to kill pending transfers and then
1597                                  * restart the queue... very messy for DMA!
1598                                  */
1599                         }
1600                         VDBG("%s halt cleared by host\n", ep->name);
1601                         goto ep0out_status_stage;
1602                 case USB_REQ_SET_FEATURE:
1603                         /* set endpoint halt */
1604                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1605                                 goto delegate;
1606                         if (w_value != USB_ENDPOINT_HALT
1607                                         || w_length != 0)
1608                                 goto do_stall;
1609                         ep = &udc->ep[w_index & 0xf];
1610                         if (w_index & USB_DIR_IN)
1611                                 ep += 16;
1612                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1613                                         || ep == ep0 || !ep->desc)
1614                                 goto do_stall;
1615                         if (use_dma && ep->has_dma) {
1616                                 /* this has rude side-effects (aborts) and
1617                                  * can't really work if DMA-IN is active
1618                                  */
1619                                 DBG("%s host set_halt, NYET \n", ep->name);
1620                                 goto do_stall;
1621                         }
1622                         use_ep(ep, 0);
1623                         /* can't halt if fifo isn't empty... */
1624                         UDC_CTRL_REG = UDC_CLR_EP;
1625                         UDC_CTRL_REG = UDC_SET_HALT;
1626                         VDBG("%s halted by host\n", ep->name);
1627 ep0out_status_stage:
1628                         status = 0;
1629                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1630                         UDC_CTRL_REG = UDC_CLR_EP;
1631                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1632                         UDC_EP_NUM_REG = UDC_EP_DIR;
1633                         udc->ep0_pending = 0;
1634                         break;
1635                 case USB_REQ_GET_STATUS:
1636                         /* USB_ENDPOINT_HALT status? */
1637                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1638                                 goto intf_status;
1639
1640                         /* ep0 never stalls */
1641                         if (!(w_index & 0xf))
1642                                 goto zero_status;
1643
1644                         /* only active endpoints count */
1645                         ep = &udc->ep[w_index & 0xf];
1646                         if (w_index & USB_DIR_IN)
1647                                 ep += 16;
1648                         if (!ep->desc)
1649                                 goto do_stall;
1650
1651                         /* iso never stalls */
1652                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1653                                 goto zero_status;
1654
1655                         /* FIXME don't assume non-halted endpoints!! */
1656                         ERR("%s status, can't report\n", ep->ep.name);
1657                         goto do_stall;
1658
1659 intf_status:
1660                         /* return interface status.  if we were pedantic,
1661                          * we'd detect non-existent interfaces, and stall.
1662                          */
1663                         if (u.r.bRequestType
1664                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1665                                 goto delegate;
1666
1667 zero_status:
1668                         /* return two zero bytes */
1669                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1670                         UDC_DATA_REG = 0;
1671                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1672                         UDC_EP_NUM_REG = UDC_EP_DIR;
1673                         status = 0;
1674                         VDBG("GET_STATUS, interface %d\n", w_index);
1675                         /* next, status stage */
1676                         break;
1677                 default:
1678 delegate:
1679                         /* activate the ep0out fifo right away */
1680                         if (!udc->ep0_in && w_length) {
1681                                 UDC_EP_NUM_REG = 0;
1682                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1683                         }
1684
1685                         /* gadget drivers see class/vendor specific requests,
1686                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1687                          * and more
1688                          */
1689                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1690                                 u.r.bRequestType, u.r.bRequest,
1691                                 w_value, w_index, w_length);
1692
1693 #undef  w_value
1694 #undef  w_index
1695 #undef  w_length
1696
1697                         /* The gadget driver may return an error here,
1698                          * causing an immediate protocol stall.
1699                          *
1700                          * Else it must issue a response, either queueing a
1701                          * response buffer for the DATA stage, or halting ep0
1702                          * (causing a protocol stall, not a real halt).  A
1703                          * zero length buffer means no DATA stage.
1704                          *
1705                          * It's fine to issue that response after the setup()
1706                          * call returns, and this IRQ was handled.
1707                          */
1708                         udc->ep0_setup = 1;
1709                         spin_unlock(&udc->lock);
1710                         status = udc->driver->setup (&udc->gadget, &u.r);
1711                         spin_lock(&udc->lock);
1712                         udc->ep0_setup = 0;
1713                 }
1714
1715                 if (status < 0) {
1716 do_stall:
1717                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1718                                         u.r.bRequestType, u.r.bRequest, status);
1719                         if (udc->ep0_set_config) {
1720                                 if (udc->ep0_reset_config)
1721                                         WARN("error resetting config?\n");
1722                                 else
1723                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1724                         }
1725                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1726                         udc->ep0_pending = 0;
1727                 }
1728         }
1729 }
1730
1731 /*-------------------------------------------------------------------------*/
1732
1733 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1734
1735 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1736 {
1737         u16     devstat, change;
1738
1739         devstat = UDC_DEVSTAT_REG;
1740         change = devstat ^ udc->devstat;
1741         udc->devstat = devstat;
1742
1743         if (change & (UDC_USB_RESET|UDC_ATT)) {
1744                 udc_quiesce(udc);
1745
1746                 if (change & UDC_ATT) {
1747                         /* driver for any external transceiver will
1748                          * have called omap_vbus_session() already
1749                          */
1750                         if (devstat & UDC_ATT) {
1751                                 udc->gadget.speed = USB_SPEED_FULL;
1752                                 VDBG("connect\n");
1753                                 if (!udc->transceiver)
1754                                         pullup_enable(udc);
1755                                 // if (driver->connect) call it
1756                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1757                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1758                                 if (!udc->transceiver)
1759                                         pullup_disable(udc);
1760                                 DBG("disconnect, gadget %s\n",
1761                                         udc->driver->driver.name);
1762                                 if (udc->driver->disconnect) {
1763                                         spin_unlock(&udc->lock);
1764                                         udc->driver->disconnect(&udc->gadget);
1765                                         spin_lock(&udc->lock);
1766                                 }
1767                         }
1768                         change &= ~UDC_ATT;
1769                 }
1770
1771                 if (change & UDC_USB_RESET) {
1772                         if (devstat & UDC_USB_RESET) {
1773                                 VDBG("RESET=1\n");
1774                         } else {
1775                                 udc->gadget.speed = USB_SPEED_FULL;
1776                                 INFO("USB reset done, gadget %s\n",
1777                                         udc->driver->driver.name);
1778                                 /* ep0 traffic is legal from now on */
1779                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1780                         }
1781                         change &= ~UDC_USB_RESET;
1782                 }
1783         }
1784         if (change & UDC_SUS) {
1785                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1786                         // FIXME tell isp1301 to suspend/resume (?)
1787                         if (devstat & UDC_SUS) {
1788                                 VDBG("suspend\n");
1789                                 update_otg(udc);
1790                                 /* HNP could be under way already */
1791                                 if (udc->gadget.speed == USB_SPEED_FULL
1792                                                 && udc->driver->suspend) {
1793                                         spin_unlock(&udc->lock);
1794                                         udc->driver->suspend(&udc->gadget);
1795                                         spin_lock(&udc->lock);
1796                                 }
1797                                 if (udc->transceiver)
1798                                         otg_set_suspend(udc->transceiver, 1);
1799                         } else {
1800                                 VDBG("resume\n");
1801                                 if (udc->transceiver)
1802                                         otg_set_suspend(udc->transceiver, 0);
1803                                 if (udc->gadget.speed == USB_SPEED_FULL
1804                                                 && udc->driver->resume) {
1805                                         spin_unlock(&udc->lock);
1806                                         udc->driver->resume(&udc->gadget);
1807                                         spin_lock(&udc->lock);
1808                                 }
1809                         }
1810                 }
1811                 change &= ~UDC_SUS;
1812         }
1813         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1814                 update_otg(udc);
1815                 change &= ~OTG_FLAGS;
1816         }
1817
1818         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1819         if (change)
1820                 VDBG("devstat %03x, ignore change %03x\n",
1821                         devstat,  change);
1822
1823         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1824 }
1825
1826 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1827 {
1828         struct omap_udc *udc = _udc;
1829         u16             irq_src;
1830         irqreturn_t     status = IRQ_NONE;
1831         unsigned long   flags;
1832
1833         spin_lock_irqsave(&udc->lock, flags);
1834         irq_src = UDC_IRQ_SRC_REG;
1835
1836         /* Device state change (usb ch9 stuff) */
1837         if (irq_src & UDC_DS_CHG) {
1838                 devstate_irq(_udc, irq_src);
1839                 status = IRQ_HANDLED;
1840                 irq_src &= ~UDC_DS_CHG;
1841         }
1842
1843         /* EP0 control transfers */
1844         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1845                 ep0_irq(_udc, irq_src);
1846                 status = IRQ_HANDLED;
1847                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1848         }
1849
1850         /* DMA transfer completion */
1851         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1852                 dma_irq(_udc, irq_src);
1853                 status = IRQ_HANDLED;
1854                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1855         }
1856
1857         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1858         if (irq_src)
1859                 DBG("udc_irq, unhandled %03x\n", irq_src);
1860         spin_unlock_irqrestore(&udc->lock, flags);
1861
1862         return status;
1863 }
1864
1865 /* workaround for seemingly-lost IRQs for RX ACKs... */
1866 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1867 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1868
1869 static void pio_out_timer(unsigned long _ep)
1870 {
1871         struct omap_ep  *ep = (void *) _ep;
1872         unsigned long   flags;
1873         u16             stat_flg;
1874
1875         spin_lock_irqsave(&ep->udc->lock, flags);
1876         if (!list_empty(&ep->queue) && ep->ackwait) {
1877                 use_ep(ep, UDC_EP_SEL);
1878                 stat_flg = UDC_STAT_FLG_REG;
1879
1880                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1881                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1882                         struct omap_req *req;
1883
1884                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1885                         req = container_of(ep->queue.next,
1886                                         struct omap_req, queue);
1887                         (void) read_fifo(ep, req);
1888                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1889                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1890                         ep->ackwait = 1 + ep->double_buf;
1891                 } else
1892                         deselect_ep();
1893         }
1894         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1895         spin_unlock_irqrestore(&ep->udc->lock, flags);
1896 }
1897
1898 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1899 {
1900         u16             epn_stat, irq_src;
1901         irqreturn_t     status = IRQ_NONE;
1902         struct omap_ep  *ep;
1903         int             epnum;
1904         struct omap_udc *udc = _dev;
1905         struct omap_req *req;
1906         unsigned long   flags;
1907
1908         spin_lock_irqsave(&udc->lock, flags);
1909         epn_stat = UDC_EPN_STAT_REG;
1910         irq_src = UDC_IRQ_SRC_REG;
1911
1912         /* handle OUT first, to avoid some wasteful NAKs */
1913         if (irq_src & UDC_EPN_RX) {
1914                 epnum = (epn_stat >> 8) & 0x0f;
1915                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1916                 status = IRQ_HANDLED;
1917                 ep = &udc->ep[epnum];
1918                 ep->irqs++;
1919
1920                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1921                 ep->fnf = 0;
1922                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1923                         ep->ackwait--;
1924                         if (!list_empty(&ep->queue)) {
1925                                 int stat;
1926                                 req = container_of(ep->queue.next,
1927                                                 struct omap_req, queue);
1928                                 stat = read_fifo(ep, req);
1929                                 if (!ep->double_buf)
1930                                         ep->fnf = 1;
1931                         }
1932                 }
1933                 /* min 6 clock delay before clearing EP_SEL ... */
1934                 epn_stat = UDC_EPN_STAT_REG;
1935                 epn_stat = UDC_EPN_STAT_REG;
1936                 UDC_EP_NUM_REG = epnum;
1937
1938                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1939                  * reduces lossage; timer still needed though (sigh).
1940                  */
1941                 if (ep->fnf) {
1942                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1943                         ep->ackwait = 1 + ep->double_buf;
1944                 }
1945                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1946         }
1947
1948         /* then IN transfers */
1949         else if (irq_src & UDC_EPN_TX) {
1950                 epnum = epn_stat & 0x0f;
1951                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1952                 status = IRQ_HANDLED;
1953                 ep = &udc->ep[16 + epnum];
1954                 ep->irqs++;
1955
1956                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1957                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1958                         ep->ackwait = 0;
1959                         if (!list_empty(&ep->queue)) {
1960                                 req = container_of(ep->queue.next,
1961                                                 struct omap_req, queue);
1962                                 (void) write_fifo(ep, req);
1963                         }
1964                 }
1965                 /* min 6 clock delay before clearing EP_SEL ... */
1966                 epn_stat = UDC_EPN_STAT_REG;
1967                 epn_stat = UDC_EPN_STAT_REG;
1968                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
1969                 /* then 6 clocks before it'd tx */
1970         }
1971
1972         spin_unlock_irqrestore(&udc->lock, flags);
1973         return status;
1974 }
1975
1976 #ifdef  USE_ISO
1977 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1978 {
1979         struct omap_udc *udc = _dev;
1980         struct omap_ep  *ep;
1981         int             pending = 0;
1982         unsigned long   flags;
1983
1984         spin_lock_irqsave(&udc->lock, flags);
1985
1986         /* handle all non-DMA ISO transfers */
1987         list_for_each_entry (ep, &udc->iso, iso) {
1988                 u16             stat;
1989                 struct omap_req *req;
1990
1991                 if (ep->has_dma || list_empty(&ep->queue))
1992                         continue;
1993                 req = list_entry(ep->queue.next, struct omap_req, queue);
1994
1995                 use_ep(ep, UDC_EP_SEL);
1996                 stat = UDC_STAT_FLG_REG;
1997
1998                 /* NOTE: like the other controller drivers, this isn't
1999                  * currently reporting lost or damaged frames.
2000                  */
2001                 if (ep->bEndpointAddress & USB_DIR_IN) {
2002                         if (stat & UDC_MISS_IN)
2003                                 /* done(ep, req, -EPROTO) */;
2004                         else
2005                                 write_fifo(ep, req);
2006                 } else {
2007                         int     status = 0;
2008
2009                         if (stat & UDC_NO_RXPACKET)
2010                                 status = -EREMOTEIO;
2011                         else if (stat & UDC_ISO_ERR)
2012                                 status = -EILSEQ;
2013                         else if (stat & UDC_DATA_FLUSH)
2014                                 status = -ENOSR;
2015
2016                         if (status)
2017                                 /* done(ep, req, status) */;
2018                         else
2019                                 read_fifo(ep, req);
2020                 }
2021                 deselect_ep();
2022                 /* 6 wait states before next EP */
2023
2024                 ep->irqs++;
2025                 if (!list_empty(&ep->queue))
2026                         pending = 1;
2027         }
2028         if (!pending)
2029                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2030         UDC_IRQ_SRC_REG = UDC_SOF;
2031
2032         spin_unlock_irqrestore(&udc->lock, flags);
2033         return IRQ_HANDLED;
2034 }
2035 #endif
2036
2037 /*-------------------------------------------------------------------------*/
2038
2039 static inline int machine_without_vbus_sense(void)
2040 {
2041         return (machine_is_omap_innovator()
2042                 || machine_is_omap_osk()
2043                 || machine_is_omap_apollon()
2044 #ifndef CONFIG_MACH_OMAP_H4_OTG
2045                 || machine_is_omap_h4()
2046 #endif
2047                 || machine_is_sx1()
2048                 );
2049 }
2050
2051 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2052 {
2053         int             status = -ENODEV;
2054         struct omap_ep  *ep;
2055         unsigned long   flags;
2056
2057         /* basic sanity tests */
2058         if (!udc)
2059                 return -ENODEV;
2060         if (!driver
2061                         // FIXME if otg, check:  driver->is_otg
2062                         || driver->speed < USB_SPEED_FULL
2063                         || !driver->bind
2064                         || !driver->setup)
2065                 return -EINVAL;
2066
2067         spin_lock_irqsave(&udc->lock, flags);
2068         if (udc->driver) {
2069                 spin_unlock_irqrestore(&udc->lock, flags);
2070                 return -EBUSY;
2071         }
2072
2073         /* reset state */
2074         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2075                 ep->irqs = 0;
2076                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2077                         continue;
2078                 use_ep(ep, 0);
2079                 UDC_CTRL_REG = UDC_SET_HALT;
2080         }
2081         udc->ep0_pending = 0;
2082         udc->ep[0].irqs = 0;
2083         udc->softconnect = 1;
2084
2085         /* hook up the driver */
2086         driver->driver.bus = NULL;
2087         udc->driver = driver;
2088         udc->gadget.dev.driver = &driver->driver;
2089         spin_unlock_irqrestore(&udc->lock, flags);
2090
2091         if (udc->dc_clk != NULL)
2092                 omap_udc_enable_clock(1);
2093
2094         status = driver->bind (&udc->gadget);
2095         if (status) {
2096                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2097                 udc->gadget.dev.driver = NULL;
2098                 udc->driver = NULL;
2099                 goto done;
2100         }
2101         DBG("bound to driver %s\n", driver->driver.name);
2102
2103         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2104
2105         /* connect to bus through transceiver */
2106         if (udc->transceiver) {
2107                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2108                 if (status < 0) {
2109                         ERR("can't bind to transceiver\n");
2110                         if (driver->unbind) {
2111                                 driver->unbind (&udc->gadget);
2112                                 udc->gadget.dev.driver = NULL;
2113                                 udc->driver = NULL;
2114                         }
2115                         goto done;
2116                 }
2117         } else {
2118                 if (can_pullup(udc))
2119                         pullup_enable (udc);
2120                 else
2121                         pullup_disable (udc);
2122         }
2123
2124         /* boards that don't have VBUS sensing can't autogate 48MHz;
2125          * can't enter deep sleep while a gadget driver is active.
2126          */
2127         if (machine_without_vbus_sense())
2128                 omap_vbus_session(&udc->gadget, 1);
2129
2130 done:
2131         if (udc->dc_clk != NULL)
2132                 omap_udc_enable_clock(0);
2133         return status;
2134 }
2135 EXPORT_SYMBOL(usb_gadget_register_driver);
2136
2137 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2138 {
2139         unsigned long   flags;
2140         int             status = -ENODEV;
2141
2142         if (!udc)
2143                 return -ENODEV;
2144         if (!driver || driver != udc->driver || !driver->unbind)
2145                 return -EINVAL;
2146
2147         if (udc->dc_clk != NULL)
2148                 omap_udc_enable_clock(1);
2149
2150         if (machine_without_vbus_sense())
2151                 omap_vbus_session(&udc->gadget, 0);
2152
2153         if (udc->transceiver)
2154                 (void) otg_set_peripheral(udc->transceiver, NULL);
2155         else
2156                 pullup_disable(udc);
2157
2158         spin_lock_irqsave(&udc->lock, flags);
2159         udc_quiesce(udc);
2160         spin_unlock_irqrestore(&udc->lock, flags);
2161
2162         driver->unbind(&udc->gadget);
2163         udc->gadget.dev.driver = NULL;
2164         udc->driver = NULL;
2165
2166         if (udc->dc_clk != NULL)
2167                 omap_udc_enable_clock(0);
2168         DBG("unregistered driver '%s'\n", driver->driver.name);
2169         return status;
2170 }
2171 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2172
2173
2174 /*-------------------------------------------------------------------------*/
2175
2176 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2177
2178 #include <linux/seq_file.h>
2179
2180 static const char proc_filename[] = "driver/udc";
2181
2182 #define FOURBITS "%s%s%s%s"
2183 #define EIGHTBITS FOURBITS FOURBITS
2184
2185 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2186 {
2187         u16             stat_flg;
2188         struct omap_req *req;
2189         char            buf[20];
2190
2191         use_ep(ep, 0);
2192
2193         if (use_dma && ep->has_dma)
2194                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2195                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2196                         ep->dma_channel - 1, ep->lch);
2197         else
2198                 buf[0] = 0;
2199
2200         stat_flg = UDC_STAT_FLG_REG;
2201         seq_printf(s,
2202                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2203                 ep->name, buf,
2204                 ep->double_buf ? "dbuf " : "",
2205                 ({char *s; switch(ep->ackwait){
2206                 case 0: s = ""; break;
2207                 case 1: s = "(ackw) "; break;
2208                 case 2: s = "(ackw2) "; break;
2209                 default: s = "(?) "; break;
2210                 } s;}),
2211                 ep->irqs, stat_flg,
2212                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2213                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2214                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2215                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2216                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2217                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2218                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2219                 (stat_flg & UDC_STALL) ? "STALL " : "",
2220                 (stat_flg & UDC_NAK) ? "NAK " : "",
2221                 (stat_flg & UDC_ACK) ? "ACK " : "",
2222                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2223                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2224                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2225
2226         if (list_empty (&ep->queue))
2227                 seq_printf(s, "\t(queue empty)\n");
2228         else
2229                 list_for_each_entry (req, &ep->queue, queue) {
2230                         unsigned        length = req->req.actual;
2231
2232                         if (use_dma && buf[0]) {
2233                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2234                                                 ? dma_src_len : dma_dest_len)
2235                                         (ep, req->req.dma + length);
2236                                 buf[0] = 0;
2237                         }
2238                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2239                                         &req->req, length,
2240                                         req->req.length, req->req.buf);
2241                 }
2242 }
2243
2244 static char *trx_mode(unsigned m, int enabled)
2245 {
2246         switch (m) {
2247         case 0:         return enabled ? "*6wire" : "unused";
2248         case 1:         return "4wire";
2249         case 2:         return "3wire";
2250         case 3:         return "6wire";
2251         default:        return "unknown";
2252         }
2253 }
2254
2255 static int proc_otg_show(struct seq_file *s)
2256 {
2257         u32             tmp;
2258         u32             trans;
2259         char            *ctrl_name;
2260
2261         tmp = OTG_REV_REG;
2262         if (cpu_is_omap24xx()) {
2263                 /*
2264                  * REVISIT: Not clear how this works on OMAP2.  trans
2265                  * is ANDed to produce bits 7 and 8, which might make
2266                  * sense for USB_TRANSCEIVER_CTRL_REG on OMAP1,
2267                  * but with CONTROL_DEVCONF, these bits have something to
2268                  * do with the frame adjustment counter and McBSP2.
2269                  */
2270                 ctrl_name = "control_devconf";
2271                 trans = omap_ctrl_readb(OMAP2_CONTROL_DEVCONF0);
2272         } else {
2273                 ctrl_name = "tranceiver_ctrl";
2274                 trans = USB_TRANSCEIVER_CTRL_REG;
2275         }
2276         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2277                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2278         tmp = OTG_SYSCON_1_REG;
2279         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2280                         FOURBITS "\n", tmp,
2281                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2282                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2283                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2284                         ? "internal"
2285                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2286                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2287                 (tmp & HST_IDLE_EN) ? " !host" : "",
2288                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2289                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2290         tmp = OTG_SYSCON_2_REG;
2291         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2292                         " b_ase_brst=%d hmc=%d\n", tmp,
2293                 (tmp & OTG_EN) ? " otg_en" : "",
2294                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2295                 // much more SRP stuff
2296                 (tmp & SRP_DATA) ? " srp_data" : "",
2297                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2298                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2299                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2300                 (tmp & UHOST_EN) ? " uhost_en" : "",
2301                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2302                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2303                 B_ASE_BRST(tmp),
2304                 OTG_HMC(tmp));
2305         tmp = OTG_CTRL_REG;
2306         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2307                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2308                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2309                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2310                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2311                 (tmp & OTG_ID) ? " id" : "",
2312                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2313                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2314                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2315                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2316                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2317                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2318                 (tmp & OTG_PULLDOWN) ? " down" : "",
2319                 (tmp & OTG_PULLUP) ? " up" : "",
2320                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2321                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2322                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2323                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2324                 );
2325         tmp = OTG_IRQ_EN_REG;
2326         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2327         tmp = OTG_IRQ_SRC_REG;
2328         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2329         tmp = OTG_OUTCTRL_REG;
2330         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2331         tmp = OTG_TEST_REG;
2332         seq_printf(s, "otg_test    %04x" "\n", tmp);
2333         return 0;
2334 }
2335
2336 static int proc_udc_show(struct seq_file *s, void *_)
2337 {
2338         u32             tmp;
2339         struct omap_ep  *ep;
2340         unsigned long   flags;
2341
2342         spin_lock_irqsave(&udc->lock, flags);
2343
2344         seq_printf(s, "%s, version: " DRIVER_VERSION
2345 #ifdef  USE_ISO
2346                 " (iso)"
2347 #endif
2348                 "%s\n",
2349                 driver_desc,
2350                 use_dma ?  " (dma)" : "");
2351
2352         tmp = UDC_REV_REG & 0xff;
2353         seq_printf(s,
2354                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2355                 "hmc %d, transceiver %s\n",
2356                 tmp >> 4, tmp & 0xf,
2357                 fifo_mode,
2358                 udc->driver ? udc->driver->driver.name : "(none)",
2359                 HMC,
2360                 udc->transceiver
2361                         ? udc->transceiver->label
2362                         : ((cpu_is_omap1710() || cpu_is_omap24xx())
2363                                 ? "external" : "(none)"));
2364         if (cpu_class_is_omap1()) {
2365                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2366                         __REG16(ULPD_CLOCK_CTRL),
2367                         __REG16(ULPD_SOFT_REQ),
2368                         __REG16(ULPD_STATUS_REQ));
2369         }
2370
2371         /* OTG controller registers */
2372         if (!cpu_is_omap15xx())
2373                 proc_otg_show(s);
2374
2375         tmp = UDC_SYSCON1_REG;
2376         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2377                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2378                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2379                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2380                 (tmp & UDC_NAK_EN) ? " nak" : "",
2381                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2382                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2383                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2384                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2385         // syscon2 is write-only
2386
2387         /* UDC controller registers */
2388         if (!(tmp & UDC_PULLUP_EN)) {
2389                 seq_printf(s, "(suspended)\n");
2390                 spin_unlock_irqrestore(&udc->lock, flags);
2391                 return 0;
2392         }
2393
2394         tmp = UDC_DEVSTAT_REG;
2395         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2396                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2397                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2398                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2399                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2400                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2401                 (tmp & UDC_SUS) ? " SUS" : "",
2402                 (tmp & UDC_CFG) ? " CFG" : "",
2403                 (tmp & UDC_ADD) ? " ADD" : "",
2404                 (tmp & UDC_DEF) ? " DEF" : "",
2405                 (tmp & UDC_ATT) ? " ATT" : "");
2406         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2407         tmp = UDC_IRQ_EN_REG;
2408         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2409                 (tmp & UDC_SOF_IE) ? " sof" : "",
2410                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2411                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2412                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2413                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2414         tmp = UDC_IRQ_SRC_REG;
2415         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2416                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2417                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2418                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2419                 (tmp & UDC_SOF) ? " sof" : "",
2420                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2421                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2422                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2423                 (tmp & UDC_SETUP) ? " setup" : "",
2424                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2425                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2426         if (use_dma) {
2427                 unsigned i;
2428
2429                 tmp = UDC_DMA_IRQ_EN_REG;
2430                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2431                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2432                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2433                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2434
2435                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2436                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2437                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2438
2439                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2440                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2441                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2442
2443                 tmp = UDC_RXDMA_CFG_REG;
2444                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2445                 if (tmp) {
2446                         for (i = 0; i < 3; i++) {
2447                                 if ((tmp & (0x0f << (i * 4))) == 0)
2448                                         continue;
2449                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2450                                                 UDC_RXDMA_REG(i + 1));
2451                         }
2452                 }
2453                 tmp = UDC_TXDMA_CFG_REG;
2454                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2455                 if (tmp) {
2456                         for (i = 0; i < 3; i++) {
2457                                 if (!(tmp & (0x0f << (i * 4))))
2458                                         continue;
2459                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2460                                                 UDC_TXDMA_REG(i + 1));
2461                         }
2462                 }
2463         }
2464
2465         tmp = UDC_DEVSTAT_REG;
2466         if (tmp & UDC_ATT) {
2467                 proc_ep_show(s, &udc->ep[0]);
2468                 if (tmp & UDC_ADD) {
2469                         list_for_each_entry (ep, &udc->gadget.ep_list,
2470                                         ep.ep_list) {
2471                                 if (ep->desc)
2472                                         proc_ep_show(s, ep);
2473                         }
2474                 }
2475         }
2476         spin_unlock_irqrestore(&udc->lock, flags);
2477         return 0;
2478 }
2479
2480 static int proc_udc_open(struct inode *inode, struct file *file)
2481 {
2482         return single_open(file, proc_udc_show, NULL);
2483 }
2484
2485 static const struct file_operations proc_ops = {
2486         .owner          = THIS_MODULE,
2487         .open           = proc_udc_open,
2488         .read           = seq_read,
2489         .llseek         = seq_lseek,
2490         .release        = single_release,
2491 };
2492
2493 static void create_proc_file(void)
2494 {
2495         proc_create(proc_filename, 0, NULL, &proc_ops);
2496 }
2497
2498 static void remove_proc_file(void)
2499 {
2500         remove_proc_entry(proc_filename, NULL);
2501 }
2502
2503 #else
2504
2505 static inline void create_proc_file(void) {}
2506 static inline void remove_proc_file(void) {}
2507
2508 #endif
2509
2510 /*-------------------------------------------------------------------------*/
2511
2512 /* Before this controller can enumerate, we need to pick an endpoint
2513  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2514  * buffer space among the endpoints we'll be operating.
2515  *
2516  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2517  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2518  * capability yet though.
2519  */
2520 static unsigned __init
2521 omap_ep_setup(char *name, u8 addr, u8 type,
2522                 unsigned buf, unsigned maxp, int dbuf)
2523 {
2524         struct omap_ep  *ep;
2525         u16             epn_rxtx = 0;
2526
2527         /* OUT endpoints first, then IN */
2528         ep = &udc->ep[addr & 0xf];
2529         if (addr & USB_DIR_IN)
2530                 ep += 16;
2531
2532         /* in case of ep init table bugs */
2533         BUG_ON(ep->name[0]);
2534
2535         /* chip setup ... bit values are same for IN, OUT */
2536         if (type == USB_ENDPOINT_XFER_ISOC) {
2537                 switch (maxp) {
2538                 case 8:         epn_rxtx = 0 << 12; break;
2539                 case 16:        epn_rxtx = 1 << 12; break;
2540                 case 32:        epn_rxtx = 2 << 12; break;
2541                 case 64:        epn_rxtx = 3 << 12; break;
2542                 case 128:       epn_rxtx = 4 << 12; break;
2543                 case 256:       epn_rxtx = 5 << 12; break;
2544                 case 512:       epn_rxtx = 6 << 12; break;
2545                 default:        BUG();
2546                 }
2547                 epn_rxtx |= UDC_EPN_RX_ISO;
2548                 dbuf = 1;
2549         } else {
2550                 /* double-buffering "not supported" on 15xx,
2551                  * and ignored for PIO-IN on newer chips
2552                  * (for more reliable behavior)
2553                  */
2554                 if ((!use_dma && (addr & USB_DIR_IN))
2555                                 || machine_is_omap_apollon()
2556                                 || cpu_is_omap15xx())
2557                         dbuf = 0;
2558
2559                 switch (maxp) {
2560                 case 8:         epn_rxtx = 0 << 12; break;
2561                 case 16:        epn_rxtx = 1 << 12; break;
2562                 case 32:        epn_rxtx = 2 << 12; break;
2563                 case 64:        epn_rxtx = 3 << 12; break;
2564                 default:        BUG();
2565                 }
2566                 if (dbuf && addr)
2567                         epn_rxtx |= UDC_EPN_RX_DB;
2568                 init_timer(&ep->timer);
2569                 ep->timer.function = pio_out_timer;
2570                 ep->timer.data = (unsigned long) ep;
2571         }
2572         if (addr)
2573                 epn_rxtx |= UDC_EPN_RX_VALID;
2574         BUG_ON(buf & 0x07);
2575         epn_rxtx |= buf >> 3;
2576
2577         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2578                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2579
2580         if (addr & USB_DIR_IN)
2581                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2582         else
2583                 UDC_EP_RX_REG(addr) = epn_rxtx;
2584
2585         /* next endpoint's buffer starts after this one's */
2586         buf += maxp;
2587         if (dbuf)
2588                 buf += maxp;
2589         BUG_ON(buf > 2048);
2590
2591         /* set up driver data structures */
2592         BUG_ON(strlen(name) >= sizeof ep->name);
2593         strlcpy(ep->name, name, sizeof ep->name);
2594         INIT_LIST_HEAD(&ep->queue);
2595         INIT_LIST_HEAD(&ep->iso);
2596         ep->bEndpointAddress = addr;
2597         ep->bmAttributes = type;
2598         ep->double_buf = dbuf;
2599         ep->udc = udc;
2600
2601         ep->ep.name = ep->name;
2602         ep->ep.ops = &omap_ep_ops;
2603         ep->ep.maxpacket = ep->maxpacket = maxp;
2604         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2605
2606         return buf;
2607 }
2608
2609 static void omap_udc_release(struct device *dev)
2610 {
2611         complete(udc->done);
2612         kfree (udc);
2613         udc = NULL;
2614 }
2615
2616 static int __init
2617 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2618 {
2619         unsigned        tmp, buf;
2620
2621         /* abolish any previous hardware state */
2622         UDC_SYSCON1_REG = 0;
2623         UDC_IRQ_EN_REG = 0;
2624         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2625         UDC_DMA_IRQ_EN_REG = 0;
2626         UDC_RXDMA_CFG_REG = 0;
2627         UDC_TXDMA_CFG_REG = 0;
2628
2629         /* UDC_PULLUP_EN gates the chip clock */
2630         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2631
2632         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2633         if (!udc)
2634                 return -ENOMEM;
2635
2636         spin_lock_init (&udc->lock);
2637
2638         udc->gadget.ops = &omap_gadget_ops;
2639         udc->gadget.ep0 = &udc->ep[0].ep;
2640         INIT_LIST_HEAD(&udc->gadget.ep_list);
2641         INIT_LIST_HEAD(&udc->iso);
2642         udc->gadget.speed = USB_SPEED_UNKNOWN;
2643         udc->gadget.name = driver_name;
2644
2645         device_initialize(&udc->gadget.dev);
2646         strcpy (udc->gadget.dev.bus_id, "gadget");
2647         udc->gadget.dev.release = omap_udc_release;
2648         udc->gadget.dev.parent = &odev->dev;
2649         if (use_dma)
2650                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2651
2652         udc->transceiver = xceiv;
2653
2654         /* ep0 is special; put it right after the SETUP buffer */
2655         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2656                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2657         list_del_init(&udc->ep[0].ep.ep_list);
2658
2659         /* initially disable all non-ep0 endpoints */
2660         for (tmp = 1; tmp < 15; tmp++) {
2661                 UDC_EP_RX_REG(tmp) = 0;
2662                 UDC_EP_TX_REG(tmp) = 0;
2663         }
2664
2665 #define OMAP_BULK_EP(name,addr) \
2666         buf = omap_ep_setup(name "-bulk", addr, \
2667                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2668 #define OMAP_INT_EP(name,addr, maxp) \
2669         buf = omap_ep_setup(name "-int", addr, \
2670                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2671 #define OMAP_ISO_EP(name,addr, maxp) \
2672         buf = omap_ep_setup(name "-iso", addr, \
2673                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2674
2675         switch (fifo_mode) {
2676         case 0:
2677                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2678                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2679                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2680                 break;
2681         case 1:
2682                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2683                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2684                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2685
2686                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2687                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2688                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2689
2690                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2691                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2692                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2693
2694                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2695                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2696                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2697
2698                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2699                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2700                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2701                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2702
2703                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2704                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2705                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2706                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2707
2708                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2709                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2710
2711                 break;
2712
2713 #ifdef  USE_ISO
2714         case 2:                 /* mixed iso/bulk */
2715                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2716                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2717                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2718                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2719
2720                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2721
2722                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2723                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2724                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2725                 break;
2726         case 3:                 /* mixed bulk/iso */
2727                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2728                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2729                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2730
2731                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2732                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2733                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2734
2735                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2736                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2737                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2738                 break;
2739 #endif
2740
2741         /* add more modes as needed */
2742
2743         default:
2744                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2745                 return -ENODEV;
2746         }
2747         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2748         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2749         return 0;
2750 }
2751
2752 static int __init omap_udc_probe(struct platform_device *pdev)
2753 {
2754         int                     status = -ENODEV;
2755         int                     hmc;
2756         struct otg_transceiver  *xceiv = NULL;
2757         const char              *type = NULL;
2758         struct omap_usb_config  *config = pdev->dev.platform_data;
2759         struct clk              *dc_clk;
2760         struct clk              *hhc_clk;
2761
2762         /* NOTE:  "knows" the order of the resources! */
2763         if (!request_mem_region(pdev->resource[0].start,
2764                         pdev->resource[0].end - pdev->resource[0].start + 1,
2765                         driver_name)) {
2766                 DBG("request_mem_region failed\n");
2767                 return -EBUSY;
2768         }
2769
2770         if (cpu_is_omap16xx()) {
2771                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2772                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2773                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2774                 /* can't use omap_udc_enable_clock yet */
2775                 clk_enable(dc_clk);
2776                 clk_enable(hhc_clk);
2777                 udelay(100);
2778         }
2779
2780         if (cpu_is_omap24xx()) {
2781                 dc_clk = clk_get(&pdev->dev, "usb_fck");
2782                 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2783                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2784                 /* can't use omap_udc_enable_clock yet */
2785                 clk_enable(dc_clk);
2786                 clk_enable(hhc_clk);
2787                 udelay(100);
2788         }
2789
2790         INFO("OMAP UDC rev %d.%d%s\n",
2791                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2792                 config->otg ? ", Mini-AB" : "");
2793
2794         /* use the mode given to us by board init code */
2795         if (cpu_is_omap15xx()) {
2796                 hmc = HMC_1510;
2797                 type = "(unknown)";
2798
2799                 if (machine_without_vbus_sense()) {
2800                         /* just set up software VBUS detect, and then
2801                          * later rig it so we always report VBUS.
2802                          * FIXME without really sensing VBUS, we can't
2803                          * know when to turn PULLUP_EN on/off; and that
2804                          * means we always "need" the 48MHz clock.
2805                          */
2806                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2807
2808                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2809                         tmp |= VBUS_MODE_1510;
2810                         tmp &= ~VBUS_CTRL_1510;
2811                         FUNC_MUX_CTRL_0_REG = tmp;
2812                 }
2813         } else {
2814                 /* The transceiver may package some GPIO logic or handle
2815                  * loopback and/or transceiverless setup; if we find one,
2816                  * use it.  Except for OTG, we don't _need_ to talk to one;
2817                  * but not having one probably means no VBUS detection.
2818                  */
2819                 xceiv = otg_get_transceiver();
2820                 if (xceiv)
2821                         type = xceiv->label;
2822                 else if (config->otg) {
2823                         DBG("OTG requires external transceiver!\n");
2824                         goto cleanup0;
2825                 }
2826
2827                 hmc = HMC_1610;
2828
2829                 if (cpu_is_omap24xx()) {
2830                         /* this could be transceiverless in one of the
2831                          * "we don't need to know" modes.
2832                          */
2833                         type = "external";
2834                         goto known;
2835                 }
2836
2837                 switch (hmc) {
2838                 case 0:                 /* POWERUP DEFAULT == 0 */
2839                 case 4:
2840                 case 12:
2841                 case 20:
2842                         if (!cpu_is_omap1710()) {
2843                                 type = "integrated";
2844                                 break;
2845                         }
2846                         /* FALL THROUGH */
2847                 case 3:
2848                 case 11:
2849                 case 16:
2850                 case 19:
2851                 case 25:
2852                         if (!xceiv) {
2853                                 DBG("external transceiver not registered!\n");
2854                                 type = "unknown";
2855                         }
2856                         break;
2857                 case 21:                        /* internal loopback */
2858                         type = "loopback";
2859                         break;
2860                 case 14:                        /* transceiverless */
2861                         if (cpu_is_omap1710())
2862                                 goto bad_on_1710;
2863                         /* FALL THROUGH */
2864                 case 13:
2865                 case 15:
2866                         type = "no";
2867                         break;
2868
2869                 default:
2870 bad_on_1710:
2871                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2872                         goto cleanup0;
2873                 }
2874         }
2875 known:
2876         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2877
2878         /* a "gadget" abstracts/virtualizes the controller */
2879         status = omap_udc_setup(pdev, xceiv);
2880         if (status) {
2881                 goto cleanup0;
2882         }
2883         xceiv = NULL;
2884         // "udc" is now valid
2885         pullup_disable(udc);
2886 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2887         udc->gadget.is_otg = (config->otg != 0);
2888 #endif
2889
2890         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2891         if (UDC_REV_REG >= 0x61)
2892                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2893         else
2894                 udc->clr_halt = UDC_RESET_EP;
2895
2896         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2897         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2898                         IRQF_SAMPLE_RANDOM, driver_name, udc);
2899         if (status != 0) {
2900                 ERR("can't get irq %d, err %d\n",
2901                         (int) pdev->resource[1].start, status);
2902                 goto cleanup1;
2903         }
2904
2905         /* USB "non-iso" IRQ (PIO for all but ep0) */
2906         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2907                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2908         if (status != 0) {
2909                 ERR("can't get irq %d, err %d\n",
2910                         (int) pdev->resource[2].start, status);
2911                 goto cleanup2;
2912         }
2913 #ifdef  USE_ISO
2914         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2915                         IRQF_DISABLED, "omap_udc iso", udc);
2916         if (status != 0) {
2917                 ERR("can't get irq %d, err %d\n",
2918                         (int) pdev->resource[3].start, status);
2919                 goto cleanup3;
2920         }
2921 #endif
2922         if (cpu_is_omap16xx()) {
2923                 udc->dc_clk = dc_clk;
2924                 udc->hhc_clk = hhc_clk;
2925                 clk_disable(hhc_clk);
2926                 clk_disable(dc_clk);
2927         }
2928
2929         if (cpu_is_omap24xx()) {
2930                 udc->dc_clk = dc_clk;
2931                 udc->hhc_clk = hhc_clk;
2932                 /* FIXME OMAP2 don't release hhc & dc clock */
2933 #if 0
2934                 clk_disable(hhc_clk);
2935                 clk_disable(dc_clk);
2936 #endif
2937         }
2938
2939         create_proc_file();
2940         status = device_add(&udc->gadget.dev);
2941         if (!status)
2942                 return status;
2943         /* If fail, fall through */
2944 #ifdef  USE_ISO
2945 cleanup3:
2946         free_irq(pdev->resource[2].start, udc);
2947 #endif
2948
2949 cleanup2:
2950         free_irq(pdev->resource[1].start, udc);
2951
2952 cleanup1:
2953         kfree (udc);
2954         udc = NULL;
2955
2956 cleanup0:
2957         if (xceiv)
2958                 put_device(xceiv->dev);
2959
2960         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
2961                 clk_disable(hhc_clk);
2962                 clk_disable(dc_clk);
2963                 clk_put(hhc_clk);
2964                 clk_put(dc_clk);
2965         }
2966
2967         release_mem_region(pdev->resource[0].start,
2968                         pdev->resource[0].end - pdev->resource[0].start + 1);
2969
2970         return status;
2971 }
2972
2973 static int __exit omap_udc_remove(struct platform_device *pdev)
2974 {
2975         DECLARE_COMPLETION_ONSTACK(done);
2976
2977         if (!udc)
2978                 return -ENODEV;
2979         if (udc->driver)
2980                 return -EBUSY;
2981
2982         udc->done = &done;
2983
2984         pullup_disable(udc);
2985         if (udc->transceiver) {
2986                 put_device(udc->transceiver->dev);
2987                 udc->transceiver = NULL;
2988         }
2989         UDC_SYSCON1_REG = 0;
2990
2991         remove_proc_file();
2992
2993 #ifdef  USE_ISO
2994         free_irq(pdev->resource[3].start, udc);
2995 #endif
2996         free_irq(pdev->resource[2].start, udc);
2997         free_irq(pdev->resource[1].start, udc);
2998
2999         if (udc->dc_clk) {
3000                 if (udc->clk_requested)
3001                         omap_udc_enable_clock(0);
3002                 clk_put(udc->hhc_clk);
3003                 clk_put(udc->dc_clk);
3004         }
3005
3006         release_mem_region(pdev->resource[0].start,
3007                         pdev->resource[0].end - pdev->resource[0].start + 1);
3008
3009         device_unregister(&udc->gadget.dev);
3010         wait_for_completion(&done);
3011
3012         return 0;
3013 }
3014
3015 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3016  * system is forced into deep sleep
3017  *
3018  * REVISIT we should probably reject suspend requests when there's a host
3019  * session active, rather than disconnecting, at least on boards that can
3020  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
3021  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3022  * may involve talking to an external transceiver (e.g. isp1301).
3023  */
3024
3025 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3026 {
3027         u32     devstat;
3028
3029         devstat = UDC_DEVSTAT_REG;
3030
3031         /* we're requesting 48 MHz clock if the pullup is enabled
3032          * (== we're attached to the host) and we're not suspended,
3033          * which would prevent entry to deep sleep...
3034          */
3035         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3036                 WARN("session active; suspend requires disconnect\n");
3037                 omap_pullup(&udc->gadget, 0);
3038         }
3039
3040         return 0;
3041 }
3042
3043 static int omap_udc_resume(struct platform_device *dev)
3044 {
3045         DBG("resume + wakeup/SRP\n");
3046         omap_pullup(&udc->gadget, 1);
3047
3048         /* maybe the host would enumerate us if we nudged it */
3049         msleep(100);
3050         return omap_wakeup(&udc->gadget);
3051 }
3052
3053 /*-------------------------------------------------------------------------*/
3054
3055 static struct platform_driver udc_driver = {
3056         .probe          = omap_udc_probe,
3057         .remove         = __exit_p(omap_udc_remove),
3058         .suspend        = omap_udc_suspend,
3059         .resume         = omap_udc_resume,
3060         .driver         = {
3061                 .owner  = THIS_MODULE,
3062                 .name   = (char *) driver_name,
3063         },
3064 };
3065
3066 static int __init udc_init(void)
3067 {
3068         INFO("%s, version: " DRIVER_VERSION
3069 #ifdef  USE_ISO
3070                 " (iso)"
3071 #endif
3072                 "%s\n", driver_desc,
3073                 use_dma ?  " (dma)" : "");
3074         return platform_driver_register(&udc_driver);
3075 }
3076 module_init(udc_init);
3077
3078 static void __exit udc_exit(void)
3079 {
3080         platform_driver_unregister(&udc_driver);
3081 }
3082 module_exit(udc_exit);
3083
3084 MODULE_DESCRIPTION(DRIVER_DESC);
3085 MODULE_LICENSE("GPL");
3086 MODULE_ALIAS("platform:omap_udc");