drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #undef  DEBUG
  25 #undef  VERBOSE
  26
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/ioport.h>
  30 #include <linux/types.h>
  31 #include <linux/errno.h>
  32 #include <linux/delay.h>
  33 #include <linux/slab.h>
  34 #include <linux/init.h>
  35 #include <linux/timer.h>
  36 #include <linux/list.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/proc_fs.h>
  39 #include <linux/mm.h>
  40 #include <linux/moduleparam.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/usb/ch9.h>
  43 #include <linux/usb/gadget.h>
  44 #include <linux/usb/otg.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/clk.h>
  47
  48 #include <asm/byteorder.h>
  49 #include <asm/io.h>
  50 #include <asm/irq.h>
  51 #include <asm/system.h>
  52 #include <asm/unaligned.h>
  53 #include <asm/mach-types.h>
  54
  55 #include <asm/arch/dma.h>
  56 #include <asm/arch/usb.h>
  57
  58 #include "omap_udc.h"
  59
  60 #undef  USB_TRACE
  61
  62 /* bulk DMA seems to be behaving for both IN and OUT */
  63 #define USE_DMA
  64
  65 /* ISO too */
  66 #define USE_ISO
  67
  68 #define DRIVER_DESC     "OMAP UDC driver"
  69 #define DRIVER_VERSION  "4 October 2004"
  70
  71 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  72
  73 #define OMAP2_DMA_CH(ch)        (((ch) - 1) << 1)
  74 #define OMAP24XX_DMA(name, ch)  (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
  75
  76 /*
  77  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  78  * D+ pullup to allow enumeration.  That's too early for the gadget
  79  * framework to use from usb_endpoint_enable(), which happens after
  80  * enumeration as part of activating an interface.  (But if we add an
  81  * optional new "UDC not yet running" state to the gadget driver model,
  82  * even just during driver binding, the endpoint autoconfig logic is the
  83  * natural spot to manufacture new endpoints.)
  84  *
  85  * So instead of using endpoint enable calls to control the hardware setup,
  86  * this driver defines a "fifo mode" parameter.  It's used during driver
  87  * initialization to choose among a set of pre-defined endpoint configs.
  88  * See omap_udc_setup() for available modes, or to add others.  That code
  89  * lives in an init section, so use this driver as a module if you need
  90  * to change the fifo mode after the kernel boots.
  91  *
  92  * Gadget drivers normally ignore endpoints they don't care about, and
  93  * won't include them in configuration descriptors.  That means only
  94  * misbehaving hosts would even notice they exist.
  95  */
  96 #ifdef  USE_ISO
  97 static unsigned fifo_mode = 3;
  98 #else
  99 static unsigned fifo_mode = 0;
 100 #endif
 101
 102 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 103  * boot parameter "omap_udc:fifo_mode=42"
 104  */
 105 module_param (fifo_mode, uint, 0);
 106 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
 107
 108 #ifdef  USE_DMA
 109 static unsigned use_dma = 1;
 110
 111 /* "modprobe omap_udc use_dma=y", or else as a kernel
 112  * boot parameter "omap_udc:use_dma=y"
 113  */
 114 module_param (use_dma, bool, 0);
 115 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 116 #else   /* !USE_DMA */
 117
 118 /* save a bit of code */
 119 #define use_dma         0
 120 #endif  /* !USE_DMA */
 121
 122
 123 static const char driver_name [] = "omap_udc";
 124 static const char driver_desc [] = DRIVER_DESC;
 125
 126 /*-------------------------------------------------------------------------*/
 127
 128 /* there's a notion of "current endpoint" for modifying endpoint
 129  * state, and PIO access to its FIFO.
 130  */
 131
 132 static void use_ep(struct omap_ep *ep, u16 select)
 133 {
 134         u16     num = ep->bEndpointAddress & 0x0f;
 135
 136         if (ep->bEndpointAddress & USB_DIR_IN)
 137                 num |= UDC_EP_DIR;
 138         UDC_EP_NUM_REG = num | select;
 139         /* when select, MUST deselect later !! */
 140 }
 141
 142 static inline void deselect_ep(void)
 143 {
 144         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
 145         /* 6 wait states before TX will happen */
 146 }
 147
 148 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 149
 150 /*-------------------------------------------------------------------------*/
 151
 152 static int omap_ep_enable(struct usb_ep *_ep,
 153                 const struct usb_endpoint_descriptor *desc)
 154 {
 155         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 156         struct omap_udc *udc;
 157         unsigned long   flags;
 158         u16             maxp;
 159
 160         /* catch various bogus parameters */
 161         if (!_ep || !desc || ep->desc
 162                         || desc->bDescriptorType != USB_DT_ENDPOINT
 163                         || ep->bEndpointAddress != desc->bEndpointAddress
 164                         || ep->maxpacket < le16_to_cpu
 165                                                 (desc->wMaxPacketSize)) {
 166                 DBG("%s, bad ep or descriptor\n", __func__);
 167                 return -EINVAL;
 168         }
 169         maxp = le16_to_cpu (desc->wMaxPacketSize);
 170         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 171                                 && maxp != ep->maxpacket)
 172                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 173                         || !desc->wMaxPacketSize) {
 174                 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
 175                 return -ERANGE;
 176         }
 177
 178 #ifdef  USE_ISO
 179         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 180                                 && desc->bInterval != 1)) {
 181                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 182                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 183                                 1 << (desc->bInterval - 1));
 184                 return -EDOM;
 185         }
 186 #else
 187         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 188                 DBG("%s, ISO nyet\n", _ep->name);
 189                 return -EDOM;
 190         }
 191 #endif
 192
 193         /* xfer types must match, except that interrupt ~= bulk */
 194         if (ep->bmAttributes != desc->bmAttributes
 195                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 196                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 197                 DBG("%s, %s type mismatch\n", __func__, _ep->name);
 198                 return -EINVAL;
 199         }
 200
 201         udc = ep->udc;
 202         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 203                 DBG("%s, bogus device state\n", __func__);
 204                 return -ESHUTDOWN;
 205         }
 206
 207         spin_lock_irqsave(&udc->lock, flags);
 208
 209         ep->desc = desc;
 210         ep->irqs = 0;
 211         ep->stopped = 0;
 212         ep->ep.maxpacket = maxp;
 213
 214         /* set endpoint to initial state */
 215         ep->dma_channel = 0;
 216         ep->has_dma = 0;
 217         ep->lch = -1;
 218         use_ep(ep, UDC_EP_SEL);
 219         UDC_CTRL_REG = udc->clr_halt;
 220         ep->ackwait = 0;
 221         deselect_ep();
 222
 223         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 224                 list_add(&ep->iso, &udc->iso);
 225
 226         /* maybe assign a DMA channel to this endpoint */
 227         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 228                 /* FIXME ISO can dma, but prefers first channel */
 229                 dma_channel_claim(ep, 0);
 230
 231         /* PIO OUT may RX packets */
 232         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 233                         && !ep->has_dma
 234                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 235                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 236                 ep->ackwait = 1 + ep->double_buf;
 237         }
 238
 239         spin_unlock_irqrestore(&udc->lock, flags);
 240         VDBG("%s enabled\n", _ep->name);
 241         return 0;
 242 }
 243
 244 static void nuke(struct omap_ep *, int status);
 245
 246 static int omap_ep_disable(struct usb_ep *_ep)
 247 {
 248         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 249         unsigned long   flags;
 250
 251         if (!_ep || !ep->desc) {
 252                 DBG("%s, %s not enabled\n", __func__,
 253                         _ep ? ep->ep.name : NULL);
 254                 return -EINVAL;
 255         }
 256
 257         spin_lock_irqsave(&ep->udc->lock, flags);
 258         ep->desc = NULL;
 259         nuke (ep, -ESHUTDOWN);
 260         ep->ep.maxpacket = ep->maxpacket;
 261         ep->has_dma = 0;
 262         UDC_CTRL_REG = UDC_SET_HALT;
 263         list_del_init(&ep->iso);
 264         del_timer(&ep->timer);
 265
 266         spin_unlock_irqrestore(&ep->udc->lock, flags);
 267
 268         VDBG("%s disabled\n", _ep->name);
 269         return 0;
 270 }
 271
 272 /*-------------------------------------------------------------------------*/
 273
 274 static struct usb_request *
 275 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 276 {
 277         struct omap_req *req;
 278
 279         req = kzalloc(sizeof(*req), gfp_flags);
 280         if (req) {
 281                 req->req.dma = DMA_ADDR_INVALID;
 282                 INIT_LIST_HEAD (&req->queue);
 283         }
 284         return &req->req;
 285 }
 286
 287 static void
 288 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 289 {
 290         struct omap_req *req = container_of(_req, struct omap_req, req);
 291
 292         if (_req)
 293                 kfree (req);
 294 }
 295
 296 /*-------------------------------------------------------------------------*/
 297
 298 static void
 299 done(struct omap_ep *ep, struct omap_req *req, int status)
 300 {
 301         unsigned                stopped = ep->stopped;
 302
 303         list_del_init(&req->queue);
 304
 305         if (req->req.status == -EINPROGRESS)
 306                 req->req.status = status;
 307         else
 308                 status = req->req.status;
 309
 310         if (use_dma && ep->has_dma) {
 311                 if (req->mapped) {
 312                         dma_unmap_single(ep->udc->gadget.dev.parent,
 313                                 req->req.dma, req->req.length,
 314                                 (ep->bEndpointAddress & USB_DIR_IN)
 315                                         ? DMA_TO_DEVICE
 316                                         : DMA_FROM_DEVICE);
 317                         req->req.dma = DMA_ADDR_INVALID;
 318                         req->mapped = 0;
 319                 } else
 320                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 321                                 req->req.dma, req->req.length,
 322                                 (ep->bEndpointAddress & USB_DIR_IN)
 323                                         ? DMA_TO_DEVICE
 324                                         : DMA_FROM_DEVICE);
 325         }
 326
 327 #ifndef USB_TRACE
 328         if (status && status != -ESHUTDOWN)
 329 #endif
 330                 VDBG("complete %s req %p stat %d len %u/%u\n",
 331                         ep->ep.name, &req->req, status,
 332                         req->req.actual, req->req.length);
 333
 334         /* don't modify queue heads during completion callback */
 335         ep->stopped = 1;
 336         spin_unlock(&ep->udc->lock);
 337         req->req.complete(&ep->ep, &req->req);
 338         spin_lock(&ep->udc->lock);
 339         ep->stopped = stopped;
 340 }
 341
 342 /*-------------------------------------------------------------------------*/
 343
 344 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 345 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 346
 347 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 348 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 349
 350 static inline int
 351 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 352 {
 353         unsigned        len;
 354         u16             *wp;
 355
 356         len = min(req->req.length - req->req.actual, max);
 357         req->req.actual += len;
 358
 359         max = len;
 360         if (likely((((int)buf) & 1) == 0)) {
 361                 wp = (u16 *)buf;
 362                 while (max >= 2) {
 363                         UDC_DATA_REG = *wp++;
 364                         max -= 2;
 365                 }
 366                 buf = (u8 *)wp;
 367         }
 368         while (max--)
 369                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
 370         return len;
 371 }
 372
 373 // FIXME change r/w fifo calling convention
 374
 375
 376 // return:  0 = still running, 1 = completed, negative = errno
 377 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 378 {
 379         u8              *buf;
 380         unsigned        count;
 381         int             is_last;
 382         u16             ep_stat;
 383
 384         buf = req->req.buf + req->req.actual;
 385         prefetch(buf);
 386
 387         /* PIO-IN isn't double buffered except for iso */
 388         ep_stat = UDC_STAT_FLG_REG;
 389         if (ep_stat & UDC_FIFO_UNWRITABLE)
 390                 return 0;
 391
 392         count = ep->ep.maxpacket;
 393         count = write_packet(buf, req, count);
 394         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 395         ep->ackwait = 1;
 396
 397         /* last packet is often short (sometimes a zlp) */
 398         if (count != ep->ep.maxpacket)
 399                 is_last = 1;
 400         else if (req->req.length == req->req.actual
 401                         && !req->req.zero)
 402                 is_last = 1;
 403         else
 404                 is_last = 0;
 405
 406         /* NOTE:  requests complete when all IN data is in a
 407          * FIFO (or sometimes later, if a zlp was needed).
 408          * Use usb_ep_fifo_status() where needed.
 409          */
 410         if (is_last)
 411                 done(ep, req, 0);
 412         return is_last;
 413 }
 414
 415 static inline int
 416 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 417 {
 418         unsigned        len;
 419         u16             *wp;
 420
 421         len = min(req->req.length - req->req.actual, avail);
 422         req->req.actual += len;
 423         avail = len;
 424
 425         if (likely((((int)buf) & 1) == 0)) {
 426                 wp = (u16 *)buf;
 427                 while (avail >= 2) {
 428                         *wp++ = UDC_DATA_REG;
 429                         avail -= 2;
 430                 }
 431                 buf = (u8 *)wp;
 432         }
 433         while (avail--)
 434                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
 435         return len;
 436 }
 437
 438 // return:  0 = still running, 1 = queue empty, negative = errno
 439 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 440 {
 441         u8              *buf;
 442         unsigned        count, avail;
 443         int             is_last;
 444
 445         buf = req->req.buf + req->req.actual;
 446         prefetchw(buf);
 447
 448         for (;;) {
 449                 u16     ep_stat = UDC_STAT_FLG_REG;
 450
 451                 is_last = 0;
 452                 if (ep_stat & FIFO_EMPTY) {
 453                         if (!ep->double_buf)
 454                                 break;
 455                         ep->fnf = 1;
 456                 }
 457                 if (ep_stat & UDC_EP_HALTED)
 458                         break;
 459
 460                 if (ep_stat & UDC_FIFO_FULL)
 461                         avail = ep->ep.maxpacket;
 462                 else  {
 463                         avail = UDC_RXFSTAT_REG;
 464                         ep->fnf = ep->double_buf;
 465                 }
 466                 count = read_packet(buf, req, avail);
 467
 468                 /* partial packet reads may not be errors */
 469                 if (count < ep->ep.maxpacket) {
 470                         is_last = 1;
 471                         /* overflowed this request?  flush extra data */
 472                         if (count != avail) {
 473                                 req->req.status = -EOVERFLOW;
 474                                 avail -= count;
 475                                 while (avail--)
 476                                         (void) *(volatile u8 *)&UDC_DATA_REG;
 477                         }
 478                 } else if (req->req.length == req->req.actual)
 479                         is_last = 1;
 480                 else
 481                         is_last = 0;
 482
 483                 if (!ep->bEndpointAddress)
 484                         break;
 485                 if (is_last)
 486                         done(ep, req, 0);
 487                 break;
 488         }
 489         return is_last;
 490 }
 491
 492 /*-------------------------------------------------------------------------*/
 493
 494 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 495 {
 496         dma_addr_t      end;
 497
 498         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 499          * the last transfer's bytecount by more than a FIFO's worth.
 500          */
 501         if (cpu_is_omap15xx())
 502                 return 0;
 503
 504         end = omap_get_dma_src_pos(ep->lch);
 505         if (end == ep->dma_counter)
 506                 return 0;
 507
 508         end |= start & (0xffff << 16);
 509         if (end < start)
 510                 end += 0x10000;
 511         return end - start;
 512 }
 513
 514 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 515 {
 516         dma_addr_t      end;
 517
 518         end = omap_get_dma_dst_pos(ep->lch);
 519         if (end == ep->dma_counter)
 520                 return 0;
 521
 522         end |= start & (0xffff << 16);
 523         if (cpu_is_omap15xx())
 524                 end++;
 525         if (end < start)
 526                 end += 0x10000;
 527         return end - start;
 528 }
 529
 530
 531 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 532  * When DMA completion isn't request completion, the UDC continues with
 533  * the next DMA transfer for that USB transfer.
 534  */
 535
 536 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 537 {
 538         u16             txdma_ctrl;
 539         unsigned        length = req->req.length - req->req.actual;
 540         const int       sync_mode = cpu_is_omap15xx()
 541                                 ? OMAP_DMA_SYNC_FRAME
 542                                 : OMAP_DMA_SYNC_ELEMENT;
 543         int             dma_trigger = 0;
 544
 545         if (cpu_is_omap24xx())
 546                 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
 547
 548         /* measure length in either bytes or packets */
 549         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 550                         || (cpu_is_omap24xx() && length < ep->maxpacket)
 551                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 552                 txdma_ctrl = UDC_TXN_EOT | length;
 553                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 554                                 length, 1, sync_mode, dma_trigger, 0);
 555         } else {
 556                 length = min(length / ep->maxpacket,
 557                                 (unsigned) UDC_TXN_TSC + 1);
 558                 txdma_ctrl = length;
 559                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 560                                 ep->ep.maxpacket >> 1, length, sync_mode,
 561                                 dma_trigger, 0);
 562                 length *= ep->maxpacket;
 563         }
 564         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 565                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 566                 0, 0);
 567
 568         omap_start_dma(ep->lch);
 569         ep->dma_counter = omap_get_dma_src_pos(ep->lch);
 570         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
 571         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
 572         req->dma_bytes = length;
 573 }
 574
 575 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 576 {
 577         if (status == 0) {
 578                 req->req.actual += req->dma_bytes;
 579
 580                 /* return if this request needs to send data or zlp */
 581                 if (req->req.actual < req->req.length)
 582                         return;
 583                 if (req->req.zero
 584                                 && req->dma_bytes != 0
 585                                 && (req->req.actual % ep->maxpacket) == 0)
 586                         return;
 587         } else
 588                 req->req.actual += dma_src_len(ep, req->req.dma
 589                                                         + req->req.actual);
 590
 591         /* tx completion */
 592         omap_stop_dma(ep->lch);
 593         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
 594         done(ep, req, status);
 595 }
 596
 597 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 598 {
 599         unsigned packets = req->req.length - req->req.actual;
 600         int dma_trigger = 0;
 601
 602         if (cpu_is_omap24xx())
 603                 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
 604
 605         /* NOTE:  we filtered out "short reads" before, so we know
 606          * the buffer has only whole numbers of packets.
 607          * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
 608          */
 609         if (cpu_is_omap24xx() && packets < ep->maxpacket) {
 610                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 611                                 packets, 1, OMAP_DMA_SYNC_ELEMENT,
 612                                 dma_trigger, 0);
 613                 req->dma_bytes = packets;
 614         } else {
 615                 /* set up this DMA transfer, enable the fifo, start */
 616                 packets /= ep->ep.maxpacket;
 617                 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 618                 req->dma_bytes = packets * ep->ep.maxpacket;
 619                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 620                                 ep->ep.maxpacket >> 1, packets,
 621                                 OMAP_DMA_SYNC_ELEMENT,
 622                                 dma_trigger, 0);
 623         }
 624         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 625                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 626                 0, 0);
 627         ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
 628
 629         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
 630         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
 631         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
 632         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 633
 634         omap_start_dma(ep->lch);
 635 }
 636
 637 static void
 638 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 639 {
 640         u16     count;
 641
 642         if (status == 0)
 643                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 644         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 645         count += req->req.actual;
 646         if (one)
 647                 count--;
 648         if (count <= req->req.length)
 649                 req->req.actual = count;
 650
 651         if (count != req->dma_bytes || status)
 652                 omap_stop_dma(ep->lch);
 653
 654         /* if this wasn't short, request may need another transfer */
 655         else if (req->req.actual < req->req.length)
 656                 return;
 657
 658         /* rx completion */
 659         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
 660         done(ep, req, status);
 661 }
 662
 663 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 664 {
 665         u16             dman_stat = UDC_DMAN_STAT_REG;
 666         struct omap_ep  *ep;
 667         struct omap_req *req;
 668
 669         /* IN dma: tx to host */
 670         if (irq_src & UDC_TXN_DONE) {
 671                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 672                 ep->irqs++;
 673                 /* can see TXN_DONE after dma abort */
 674                 if (!list_empty(&ep->queue)) {
 675                         req = container_of(ep->queue.next,
 676                                                 struct omap_req, queue);
 677                         finish_in_dma(ep, req, 0);
 678                 }
 679                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
 680
 681                 if (!list_empty (&ep->queue)) {
 682                         req = container_of(ep->queue.next,
 683                                         struct omap_req, queue);
 684                         next_in_dma(ep, req);
 685                 }
 686         }
 687
 688         /* OUT dma: rx from host */
 689         if (irq_src & UDC_RXN_EOT) {
 690                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 691                 ep->irqs++;
 692                 /* can see RXN_EOT after dma abort */
 693                 if (!list_empty(&ep->queue)) {
 694                         req = container_of(ep->queue.next,
 695                                         struct omap_req, queue);
 696                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 697                 }
 698                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
 699
 700                 if (!list_empty (&ep->queue)) {
 701                         req = container_of(ep->queue.next,
 702                                         struct omap_req, queue);
 703                         next_out_dma(ep, req);
 704                 }
 705         }
 706
 707         if (irq_src & UDC_RXN_CNT) {
 708                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 709                 ep->irqs++;
 710                 /* omap15xx does this unasked... */
 711                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 712                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
 713         }
 714 }
 715
 716 static void dma_error(int lch, u16 ch_status, void *data)
 717 {
 718         struct omap_ep  *ep = data;
 719
 720         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 721         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 722         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 723
 724         /* complete current transfer ... */
 725 }
 726
 727 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 728 {
 729         u16     reg;
 730         int     status, restart, is_in;
 731         int     dma_channel;
 732
 733         is_in = ep->bEndpointAddress & USB_DIR_IN;
 734         if (is_in)
 735                 reg = UDC_TXDMA_CFG_REG;
 736         else
 737                 reg = UDC_RXDMA_CFG_REG;
 738         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 739
 740         ep->dma_channel = 0;
 741         ep->lch = -1;
 742         if (channel == 0 || channel > 3) {
 743                 if ((reg & 0x0f00) == 0)
 744                         channel = 3;
 745                 else if ((reg & 0x00f0) == 0)
 746                         channel = 2;
 747                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 748                         channel = 1;
 749                 else {
 750                         status = -EMLINK;
 751                         goto just_restart;
 752                 }
 753         }
 754         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 755         ep->dma_channel = channel;
 756
 757         if (is_in) {
 758                 if (cpu_is_omap24xx())
 759                         dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
 760                 else
 761                         dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
 762                 status = omap_request_dma(dma_channel,
 763                         ep->ep.name, dma_error, ep, &ep->lch);
 764                 if (status == 0) {
 765                         UDC_TXDMA_CFG_REG = reg;
 766                         /* EMIFF or SDRC */
 767                         omap_set_dma_src_burst_mode(ep->lch,
 768                                                 OMAP_DMA_DATA_BURST_4);
 769                         omap_set_dma_src_data_pack(ep->lch, 1);
 770                         /* TIPB */
 771                         omap_set_dma_dest_params(ep->lch,
 772                                 OMAP_DMA_PORT_TIPB,
 773                                 OMAP_DMA_AMODE_CONSTANT,
 774                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 775                                 0, 0);
 776                 }
 777         } else {
 778                 if (cpu_is_omap24xx())
 779                         dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
 780                 else
 781                         dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
 782
 783                 status = omap_request_dma(dma_channel,
 784                         ep->ep.name, dma_error, ep, &ep->lch);
 785                 if (status == 0) {
 786                         UDC_RXDMA_CFG_REG = reg;
 787                         /* TIPB */
 788                         omap_set_dma_src_params(ep->lch,
 789                                 OMAP_DMA_PORT_TIPB,
 790                                 OMAP_DMA_AMODE_CONSTANT,
 791                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 792                                 0, 0);
 793                         /* EMIFF or SDRC */
 794                         omap_set_dma_dest_burst_mode(ep->lch,
 795                                                 OMAP_DMA_DATA_BURST_4);
 796                         omap_set_dma_dest_data_pack(ep->lch, 1);
 797                 }
 798         }
 799         if (status)
 800                 ep->dma_channel = 0;
 801         else {
 802                 ep->has_dma = 1;
 803                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 804
 805                 /* channel type P: hw synch (fifo) */
 806                 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
 807                         omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
 808         }
 809
 810 just_restart:
 811         /* restart any queue, even if the claim failed  */
 812         restart = !ep->stopped && !list_empty(&ep->queue);
 813
 814         if (status)
 815                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 816                         restart ? " (restart)" : "");
 817         else
 818                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 819                         is_in ? 't' : 'r',
 820                         ep->dma_channel - 1, ep->lch,
 821                         restart ? " (restart)" : "");
 822
 823         if (restart) {
 824                 struct omap_req *req;
 825                 req = container_of(ep->queue.next, struct omap_req, queue);
 826                 if (ep->has_dma)
 827                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 828                 else {
 829                         use_ep(ep, UDC_EP_SEL);
 830                         (is_in ? write_fifo : read_fifo)(ep, req);
 831                         deselect_ep();
 832                         if (!is_in) {
 833                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 834                                 ep->ackwait = 1 + ep->double_buf;
 835                         }
 836                         /* IN: 6 wait states before it'll tx */
 837                 }
 838         }
 839 }
 840
 841 static void dma_channel_release(struct omap_ep *ep)
 842 {
 843         int             shift = 4 * (ep->dma_channel - 1);
 844         u16             mask = 0x0f << shift;
 845         struct omap_req *req;
 846         int             active;
 847
 848         /* abort any active usb transfer request */
 849         if (!list_empty(&ep->queue))
 850                 req = container_of(ep->queue.next, struct omap_req, queue);
 851         else
 852                 req = NULL;
 853
 854         active = omap_get_dma_active_status(ep->lch);
 855
 856         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 857                         active ? "active" : "idle",
 858                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 859                         ep->dma_channel - 1, req);
 860
 861         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 862          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 863          */
 864
 865         /* wait till current packet DMA finishes, and fifo empties */
 866         if (ep->bEndpointAddress & USB_DIR_IN) {
 867                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 868
 869                 if (req) {
 870                         finish_in_dma(ep, req, -ECONNRESET);
 871
 872                         /* clear FIFO; hosts probably won't empty it */
 873                         use_ep(ep, UDC_EP_SEL);
 874                         UDC_CTRL_REG = UDC_CLR_EP;
 875                         deselect_ep();
 876                 }
 877                 while (UDC_TXDMA_CFG_REG & mask)
 878                         udelay(10);
 879         } else {
 880                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 881
 882                 /* dma empties the fifo */
 883                 while (UDC_RXDMA_CFG_REG & mask)
 884                         udelay(10);
 885                 if (req)
 886                         finish_out_dma(ep, req, -ECONNRESET, 0);
 887         }
 888         omap_free_dma(ep->lch);
 889         ep->dma_channel = 0;
 890         ep->lch = -1;
 891         /* has_dma still set, till endpoint is fully quiesced */
 892 }
 893
 894
 895 /*-------------------------------------------------------------------------*/
 896
 897 static int
 898 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 899 {
 900         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 901         struct omap_req *req = container_of(_req, struct omap_req, req);
 902         struct omap_udc *udc;
 903         unsigned long   flags;
 904         int             is_iso = 0;
 905
 906         /* catch various bogus parameters */
 907         if (!_req || !req->req.complete || !req->req.buf
 908                         || !list_empty(&req->queue)) {
 909                 DBG("%s, bad params\n", __func__);
 910                 return -EINVAL;
 911         }
 912         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 913                 DBG("%s, bad ep\n", __func__);
 914                 return -EINVAL;
 915         }
 916         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 917                 if (req->req.length > ep->ep.maxpacket)
 918                         return -EMSGSIZE;
 919                 is_iso = 1;
 920         }
 921
 922         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 923          * have a hard time with partial packet reads...  reject it.
 924          * Except OMAP2 can handle the small packets.
 925          */
 926         if (use_dma
 927                         && ep->has_dma
 928                         && ep->bEndpointAddress != 0
 929                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 930                         && !cpu_class_is_omap2()
 931                         && (req->req.length % ep->ep.maxpacket) != 0) {
 932                 DBG("%s, no partial packet OUT reads\n", __func__);
 933                 return -EMSGSIZE;
 934         }
 935
 936         udc = ep->udc;
 937         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 938                 return -ESHUTDOWN;
 939
 940         if (use_dma && ep->has_dma) {
 941                 if (req->req.dma == DMA_ADDR_INVALID) {
 942                         req->req.dma = dma_map_single(
 943                                 ep->udc->gadget.dev.parent,
 944                                 req->req.buf,
 945                                 req->req.length,
 946                                 (ep->bEndpointAddress & USB_DIR_IN)
 947                                         ? DMA_TO_DEVICE
 948                                         : DMA_FROM_DEVICE);
 949                         req->mapped = 1;
 950                 } else {
 951                         dma_sync_single_for_device(
 952                                 ep->udc->gadget.dev.parent,
 953                                 req->req.dma, req->req.length,
 954                                 (ep->bEndpointAddress & USB_DIR_IN)
 955                                         ? DMA_TO_DEVICE
 956                                         : DMA_FROM_DEVICE);
 957                         req->mapped = 0;
 958                 }
 959         }
 960
 961         VDBG("%s queue req %p, len %d buf %p\n",
 962                 ep->ep.name, _req, _req->length, _req->buf);
 963
 964         spin_lock_irqsave(&udc->lock, flags);
 965
 966         req->req.status = -EINPROGRESS;
 967         req->req.actual = 0;
 968
 969         /* maybe kickstart non-iso i/o queues */
 970         if (is_iso)
 971                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
 972         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
 973                 int     is_in;
 974
 975                 if (ep->bEndpointAddress == 0) {
 976                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
 977                                 spin_unlock_irqrestore(&udc->lock, flags);
 978                                 return -EL2HLT;
 979                         }
 980
 981                         /* empty DATA stage? */
 982                         is_in = udc->ep0_in;
 983                         if (!req->req.length) {
 984
 985                                 /* chip became CONFIGURED or ADDRESSED
 986                                  * earlier; drivers may already have queued
 987                                  * requests to non-control endpoints
 988                                  */
 989                                 if (udc->ep0_set_config) {
 990                                         u16     irq_en = UDC_IRQ_EN_REG;
 991
 992                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
 993                                         if (!udc->ep0_reset_config)
 994                                                 irq_en |= UDC_EPN_RX_IE
 995                                                         | UDC_EPN_TX_IE;
 996                                         UDC_IRQ_EN_REG = irq_en;
 997                                 }
 998
 999                                 /* STATUS for zero length DATA stages is
1000                                  * always an IN ... even for IN transfers,
1001                                  * a weird case which seem to stall OMAP.
1002                                  */
1003                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1004                                 UDC_CTRL_REG = UDC_CLR_EP;
1005                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1006                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1007
1008                                 /* cleanup */
1009                                 udc->ep0_pending = 0;
1010                                 done(ep, req, 0);
1011                                 req = NULL;
1012
1013                         /* non-empty DATA stage */
1014                         } else if (is_in) {
1015                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1016                         } else {
1017                                 if (udc->ep0_setup)
1018                                         goto irq_wait;
1019                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1020                         }
1021                 } else {
1022                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1023                         if (!ep->has_dma)
1024                                 use_ep(ep, UDC_EP_SEL);
1025                         /* if ISO: SOF IRQs must be enabled/disabled! */
1026                 }
1027
1028                 if (ep->has_dma)
1029                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1030                 else if (req) {
1031                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1032                                 req = NULL;
1033                         deselect_ep();
1034                         if (!is_in) {
1035                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1036                                 ep->ackwait = 1 + ep->double_buf;
1037                         }
1038                         /* IN: 6 wait states before it'll tx */
1039                 }
1040         }
1041
1042 irq_wait:
1043         /* irq handler advances the queue */
1044         if (req != NULL)
1045                 list_add_tail(&req->queue, &ep->queue);
1046         spin_unlock_irqrestore(&udc->lock, flags);
1047
1048         return 0;
1049 }
1050
1051 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1052 {
1053         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1054         struct omap_req *req;
1055         unsigned long   flags;
1056
1057         if (!_ep || !_req)
1058                 return -EINVAL;
1059
1060         spin_lock_irqsave(&ep->udc->lock, flags);
1061
1062         /* make sure it's actually queued on this endpoint */
1063         list_for_each_entry (req, &ep->queue, queue) {
1064                 if (&req->req == _req)
1065                         break;
1066         }
1067         if (&req->req != _req) {
1068                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1069                 return -EINVAL;
1070         }
1071
1072         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1073                 int channel = ep->dma_channel;
1074
1075                 /* releasing the channel cancels the request,
1076                  * reclaiming the channel restarts the queue
1077                  */
1078                 dma_channel_release(ep);
1079                 dma_channel_claim(ep, channel);
1080         } else
1081                 done(ep, req, -ECONNRESET);
1082         spin_unlock_irqrestore(&ep->udc->lock, flags);
1083         return 0;
1084 }
1085
1086 /*-------------------------------------------------------------------------*/
1087
1088 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1089 {
1090         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1091         unsigned long   flags;
1092         int             status = -EOPNOTSUPP;
1093
1094         spin_lock_irqsave(&ep->udc->lock, flags);
1095
1096         /* just use protocol stalls for ep0; real halts are annoying */
1097         if (ep->bEndpointAddress == 0) {
1098                 if (!ep->udc->ep0_pending)
1099                         status = -EINVAL;
1100                 else if (value) {
1101                         if (ep->udc->ep0_set_config) {
1102                                 WARN("error changing config?\n");
1103                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1104                         }
1105                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1106                         ep->udc->ep0_pending = 0;
1107                         status = 0;
1108                 } else /* NOP */
1109                         status = 0;
1110
1111         /* otherwise, all active non-ISO endpoints can halt */
1112         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1113
1114                 /* IN endpoints must already be idle */
1115                 if ((ep->bEndpointAddress & USB_DIR_IN)
1116                                 && !list_empty(&ep->queue)) {
1117                         status = -EAGAIN;
1118                         goto done;
1119                 }
1120
1121                 if (value) {
1122                         int     channel;
1123
1124                         if (use_dma && ep->dma_channel
1125                                         && !list_empty(&ep->queue)) {
1126                                 channel = ep->dma_channel;
1127                                 dma_channel_release(ep);
1128                         } else
1129                                 channel = 0;
1130
1131                         use_ep(ep, UDC_EP_SEL);
1132                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1133                                 UDC_CTRL_REG = UDC_SET_HALT;
1134                                 status = 0;
1135                         } else
1136                                 status = -EAGAIN;
1137                         deselect_ep();
1138
1139                         if (channel)
1140                                 dma_channel_claim(ep, channel);
1141                 } else {
1142                         use_ep(ep, 0);
1143                         UDC_CTRL_REG = ep->udc->clr_halt;
1144                         ep->ackwait = 0;
1145                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1146                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1147                                 ep->ackwait = 1 + ep->double_buf;
1148                         }
1149                 }
1150         }
1151 done:
1152         VDBG("%s %s halt stat %d\n", ep->ep.name,
1153                 value ? "set" : "clear", status);
1154
1155         spin_unlock_irqrestore(&ep->udc->lock, flags);
1156         return status;
1157 }
1158
1159 static struct usb_ep_ops omap_ep_ops = {
1160         .enable         = omap_ep_enable,
1161         .disable        = omap_ep_disable,
1162
1163         .alloc_request  = omap_alloc_request,
1164         .free_request   = omap_free_request,
1165
1166         .queue          = omap_ep_queue,
1167         .dequeue        = omap_ep_dequeue,
1168
1169         .set_halt       = omap_ep_set_halt,
1170         // fifo_status ... report bytes in fifo
1171         // fifo_flush ... flush fifo
1172 };
1173
1174 /*-------------------------------------------------------------------------*/
1175
1176 static int omap_get_frame(struct usb_gadget *gadget)
1177 {
1178         u16     sof = UDC_SOF_REG;
1179         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1180 }
1181
1182 static int omap_wakeup(struct usb_gadget *gadget)
1183 {
1184         struct omap_udc *udc;
1185         unsigned long   flags;
1186         int             retval = -EHOSTUNREACH;
1187
1188         udc = container_of(gadget, struct omap_udc, gadget);
1189
1190         spin_lock_irqsave(&udc->lock, flags);
1191         if (udc->devstat & UDC_SUS) {
1192                 /* NOTE:  OTG spec erratum says that OTG devices may
1193                  * issue wakeups without host enable.
1194                  */
1195                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1196                         DBG("remote wakeup...\n");
1197                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1198                         retval = 0;
1199                 }
1200
1201         /* NOTE:  non-OTG systems may use SRP TOO... */
1202         } else if (!(udc->devstat & UDC_ATT)) {
1203                 if (udc->transceiver)
1204                         retval = otg_start_srp(udc->transceiver);
1205         }
1206         spin_unlock_irqrestore(&udc->lock, flags);
1207
1208         return retval;
1209 }
1210
1211 static int
1212 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1213 {
1214         struct omap_udc *udc;
1215         unsigned long   flags;
1216         u16             syscon1;
1217
1218         udc = container_of(gadget, struct omap_udc, gadget);
1219         spin_lock_irqsave(&udc->lock, flags);
1220         syscon1 = UDC_SYSCON1_REG;
1221         if (is_selfpowered)
1222                 syscon1 |= UDC_SELF_PWR;
1223         else
1224                 syscon1 &= ~UDC_SELF_PWR;
1225         UDC_SYSCON1_REG = syscon1;
1226         spin_unlock_irqrestore(&udc->lock, flags);
1227
1228         return 0;
1229 }
1230
1231 static int can_pullup(struct omap_udc *udc)
1232 {
1233         return udc->driver && udc->softconnect && udc->vbus_active;
1234 }
1235
1236 static void pullup_enable(struct omap_udc *udc)
1237 {
1238         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1239         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1240                 OTG_CTRL_REG |= OTG_BSESSVLD;
1241         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1242 }
1243
1244 static void pullup_disable(struct omap_udc *udc)
1245 {
1246         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1247                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1248         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1249         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1250 }
1251
1252 static struct omap_udc *udc;
1253
1254 static void omap_udc_enable_clock(int enable)
1255 {
1256         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1257                 return;
1258
1259         if (enable) {
1260                 clk_enable(udc->dc_clk);
1261                 clk_enable(udc->hhc_clk);
1262                 udelay(100);
1263         } else {
1264                 clk_disable(udc->hhc_clk);
1265                 clk_disable(udc->dc_clk);
1266         }
1267 }
1268
1269 /*
1270  * Called by whatever detects VBUS sessions:  external transceiver
1271  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1272  */
1273 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1274 {
1275         struct omap_udc *udc;
1276         unsigned long   flags;
1277
1278         udc = container_of(gadget, struct omap_udc, gadget);
1279         spin_lock_irqsave(&udc->lock, flags);
1280         VDBG("VBUS %s\n", is_active ? "on" : "off");
1281         udc->vbus_active = (is_active != 0);
1282         if (cpu_is_omap15xx()) {
1283                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1284                 if (is_active)
1285                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1286                 else
1287                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1288         }
1289         if (udc->dc_clk != NULL && is_active) {
1290                 if (!udc->clk_requested) {
1291                         omap_udc_enable_clock(1);
1292                         udc->clk_requested = 1;
1293                 }
1294         }
1295         if (can_pullup(udc))
1296                 pullup_enable(udc);
1297         else
1298                 pullup_disable(udc);
1299         if (udc->dc_clk != NULL && !is_active) {
1300                 if (udc->clk_requested) {
1301                         omap_udc_enable_clock(0);
1302                         udc->clk_requested = 0;
1303                 }
1304         }
1305         spin_unlock_irqrestore(&udc->lock, flags);
1306         return 0;
1307 }
1308
1309 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1310 {
1311         struct omap_udc *udc;
1312
1313         udc = container_of(gadget, struct omap_udc, gadget);
1314         if (udc->transceiver)
1315                 return otg_set_power(udc->transceiver, mA);
1316         return -EOPNOTSUPP;
1317 }
1318
1319 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1320 {
1321         struct omap_udc *udc;
1322         unsigned long   flags;
1323
1324         udc = container_of(gadget, struct omap_udc, gadget);
1325         spin_lock_irqsave(&udc->lock, flags);
1326         udc->softconnect = (is_on != 0);
1327         if (can_pullup(udc))
1328                 pullup_enable(udc);
1329         else
1330                 pullup_disable(udc);
1331         spin_unlock_irqrestore(&udc->lock, flags);
1332         return 0;
1333 }
1334
1335 static struct usb_gadget_ops omap_gadget_ops = {
1336         .get_frame              = omap_get_frame,
1337         .wakeup                 = omap_wakeup,
1338         .set_selfpowered        = omap_set_selfpowered,
1339         .vbus_session           = omap_vbus_session,
1340         .vbus_draw              = omap_vbus_draw,
1341         .pullup                 = omap_pullup,
1342 };
1343
1344 /*-------------------------------------------------------------------------*/
1345
1346 /* dequeue ALL requests; caller holds udc->lock */
1347 static void nuke(struct omap_ep *ep, int status)
1348 {
1349         struct omap_req *req;
1350
1351         ep->stopped = 1;
1352
1353         if (use_dma && ep->dma_channel)
1354                 dma_channel_release(ep);
1355
1356         use_ep(ep, 0);
1357         UDC_CTRL_REG = UDC_CLR_EP;
1358         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1359                 UDC_CTRL_REG = UDC_SET_HALT;
1360
1361         while (!list_empty(&ep->queue)) {
1362                 req = list_entry(ep->queue.next, struct omap_req, queue);
1363                 done(ep, req, status);
1364         }
1365 }
1366
1367 /* caller holds udc->lock */
1368 static void udc_quiesce(struct omap_udc *udc)
1369 {
1370         struct omap_ep  *ep;
1371
1372         udc->gadget.speed = USB_SPEED_UNKNOWN;
1373         nuke(&udc->ep[0], -ESHUTDOWN);
1374         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1375                 nuke(ep, -ESHUTDOWN);
1376 }
1377
1378 /*-------------------------------------------------------------------------*/
1379
1380 static void update_otg(struct omap_udc *udc)
1381 {
1382         u16     devstat;
1383
1384         if (!gadget_is_otg(&udc->gadget))
1385                 return;
1386
1387         if (OTG_CTRL_REG & OTG_ID)
1388                 devstat = UDC_DEVSTAT_REG;
1389         else
1390                 devstat = 0;
1391
1392         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1393         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1394         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1395
1396         /* Enable HNP early, avoiding races on suspend irq path.
1397          * ASSUMES OTG state machine B_BUS_REQ input is true.
1398          */
1399         if (udc->gadget.b_hnp_enable)
1400                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1401                                 & ~OTG_PULLUP;
1402 }
1403
1404 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1405 {
1406         struct omap_ep  *ep0 = &udc->ep[0];
1407         struct omap_req *req = NULL;
1408
1409         ep0->irqs++;
1410
1411         /* Clear any pending requests and then scrub any rx/tx state
1412          * before starting to handle the SETUP request.
1413          */
1414         if (irq_src & UDC_SETUP) {
1415                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1416
1417                 nuke(ep0, 0);
1418                 if (ack) {
1419                         UDC_IRQ_SRC_REG = ack;
1420                         irq_src = UDC_SETUP;
1421                 }
1422         }
1423
1424         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1425          * This driver uses only uses protocol stalls (ep0 never halts),
1426          * and if we got this far the gadget driver already had a
1427          * chance to stall.  Tries to be forgiving of host oddities.
1428          *
1429          * NOTE:  the last chance gadget drivers have to stall control
1430          * requests is during their request completion callback.
1431          */
1432         if (!list_empty(&ep0->queue))
1433                 req = container_of(ep0->queue.next, struct omap_req, queue);
1434
1435         /* IN == TX to host */
1436         if (irq_src & UDC_EP0_TX) {
1437                 int     stat;
1438
1439                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1440                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1441                 stat = UDC_STAT_FLG_REG;
1442                 if (stat & UDC_ACK) {
1443                         if (udc->ep0_in) {
1444                                 /* write next IN packet from response,
1445                                  * or set up the status stage.
1446                                  */
1447                                 if (req)
1448                                         stat = write_fifo(ep0, req);
1449                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1450                                 if (!req && udc->ep0_pending) {
1451                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1452                                         UDC_CTRL_REG = UDC_CLR_EP;
1453                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1454                                         UDC_EP_NUM_REG = 0;
1455                                         udc->ep0_pending = 0;
1456                                 } /* else:  6 wait states before it'll tx */
1457                         } else {
1458                                 /* ack status stage of OUT transfer */
1459                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1460                                 if (req)
1461                                         done(ep0, req, 0);
1462                         }
1463                         req = NULL;
1464                 } else if (stat & UDC_STALL) {
1465                         UDC_CTRL_REG = UDC_CLR_HALT;
1466                         UDC_EP_NUM_REG = UDC_EP_DIR;
1467                 } else {
1468                         UDC_EP_NUM_REG = UDC_EP_DIR;
1469                 }
1470         }
1471
1472         /* OUT == RX from host */
1473         if (irq_src & UDC_EP0_RX) {
1474                 int     stat;
1475
1476                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1477                 UDC_EP_NUM_REG = UDC_EP_SEL;
1478                 stat = UDC_STAT_FLG_REG;
1479                 if (stat & UDC_ACK) {
1480                         if (!udc->ep0_in) {
1481                                 stat = 0;
1482                                 /* read next OUT packet of request, maybe
1483                                  * reactiviting the fifo; stall on errors.
1484                                  */
1485                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1486                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1487                                         udc->ep0_pending = 0;
1488                                         stat = 0;
1489                                 } else if (stat == 0)
1490                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1491                                 UDC_EP_NUM_REG = 0;
1492
1493                                 /* activate status stage */
1494                                 if (stat == 1) {
1495                                         done(ep0, req, 0);
1496                                         /* that may have STALLed ep0... */
1497                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1498                                         UDC_CTRL_REG = UDC_CLR_EP;
1499                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1500                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1501                                         udc->ep0_pending = 0;
1502                                 }
1503                         } else {
1504                                 /* ack status stage of IN transfer */
1505                                 UDC_EP_NUM_REG = 0;
1506                                 if (req)
1507                                         done(ep0, req, 0);
1508                         }
1509                 } else if (stat & UDC_STALL) {
1510                         UDC_CTRL_REG = UDC_CLR_HALT;
1511                         UDC_EP_NUM_REG = 0;
1512                 } else {
1513                         UDC_EP_NUM_REG = 0;
1514                 }
1515         }
1516
1517         /* SETUP starts all control transfers */
1518         if (irq_src & UDC_SETUP) {
1519                 union u {
1520                         u16                     word[4];
1521                         struct usb_ctrlrequest  r;
1522                 } u;
1523                 int                     status = -EINVAL;
1524                 struct omap_ep          *ep;
1525
1526                 /* read the (latest) SETUP message */
1527                 do {
1528                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1529                         /* two bytes at a time */
1530                         u.word[0] = UDC_DATA_REG;
1531                         u.word[1] = UDC_DATA_REG;
1532                         u.word[2] = UDC_DATA_REG;
1533                         u.word[3] = UDC_DATA_REG;
1534                         UDC_EP_NUM_REG = 0;
1535                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1536
1537 #define w_value         le16_to_cpu(u.r.wValue)
1538 #define w_index         le16_to_cpu(u.r.wIndex)
1539 #define w_length        le16_to_cpu(u.r.wLength)
1540
1541                 /* Delegate almost all control requests to the gadget driver,
1542                  * except for a handful of ch9 status/feature requests that
1543                  * hardware doesn't autodecode _and_ the gadget API hides.
1544                  */
1545                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1546                 udc->ep0_set_config = 0;
1547                 udc->ep0_pending = 1;
1548                 ep0->stopped = 0;
1549                 ep0->ackwait = 0;
1550                 switch (u.r.bRequest) {
1551                 case USB_REQ_SET_CONFIGURATION:
1552                         /* udc needs to know when ep != 0 is valid */
1553                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1554                                 goto delegate;
1555                         if (w_length != 0)
1556                                 goto do_stall;
1557                         udc->ep0_set_config = 1;
1558                         udc->ep0_reset_config = (w_value == 0);
1559                         VDBG("set config %d\n", w_value);
1560
1561                         /* update udc NOW since gadget driver may start
1562                          * queueing requests immediately; clear config
1563                          * later if it fails the request.
1564                          */
1565                         if (udc->ep0_reset_config)
1566                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1567                         else
1568                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1569                         update_otg(udc);
1570                         goto delegate;
1571                 case USB_REQ_CLEAR_FEATURE:
1572                         /* clear endpoint halt */
1573                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1574                                 goto delegate;
1575                         if (w_value != USB_ENDPOINT_HALT
1576                                         || w_length != 0)
1577                                 goto do_stall;
1578                         ep = &udc->ep[w_index & 0xf];
1579                         if (ep != ep0) {
1580                                 if (w_index & USB_DIR_IN)
1581                                         ep += 16;
1582                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1583                                                 || !ep->desc)
1584                                         goto do_stall;
1585                                 use_ep(ep, 0);
1586                                 UDC_CTRL_REG = udc->clr_halt;
1587                                 ep->ackwait = 0;
1588                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1589                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1590                                         ep->ackwait = 1 + ep->double_buf;
1591                                 }
1592                                 /* NOTE:  assumes the host behaves sanely,
1593                                  * only clearing real halts.  Else we may
1594                                  * need to kill pending transfers and then
1595                                  * restart the queue... very messy for DMA!
1596                                  */
1597                         }
1598                         VDBG("%s halt cleared by host\n", ep->name);
1599                         goto ep0out_status_stage;
1600                 case USB_REQ_SET_FEATURE:
1601                         /* set endpoint halt */
1602                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1603                                 goto delegate;
1604                         if (w_value != USB_ENDPOINT_HALT
1605                                         || w_length != 0)
1606                                 goto do_stall;
1607                         ep = &udc->ep[w_index & 0xf];
1608                         if (w_index & USB_DIR_IN)
1609                                 ep += 16;
1610                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1611                                         || ep == ep0 || !ep->desc)
1612                                 goto do_stall;
1613                         if (use_dma && ep->has_dma) {
1614                                 /* this has rude side-effects (aborts) and
1615                                  * can't really work if DMA-IN is active
1616                                  */
1617                                 DBG("%s host set_halt, NYET \n", ep->name);
1618                                 goto do_stall;
1619                         }
1620                         use_ep(ep, 0);
1621                         /* can't halt if fifo isn't empty... */
1622                         UDC_CTRL_REG = UDC_CLR_EP;
1623                         UDC_CTRL_REG = UDC_SET_HALT;
1624                         VDBG("%s halted by host\n", ep->name);
1625 ep0out_status_stage:
1626                         status = 0;
1627                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1628                         UDC_CTRL_REG = UDC_CLR_EP;
1629                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1630                         UDC_EP_NUM_REG = UDC_EP_DIR;
1631                         udc->ep0_pending = 0;
1632                         break;
1633                 case USB_REQ_GET_STATUS:
1634                         /* USB_ENDPOINT_HALT status? */
1635                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1636                                 goto intf_status;
1637
1638                         /* ep0 never stalls */
1639                         if (!(w_index & 0xf))
1640                                 goto zero_status;
1641
1642                         /* only active endpoints count */
1643                         ep = &udc->ep[w_index & 0xf];
1644                         if (w_index & USB_DIR_IN)
1645                                 ep += 16;
1646                         if (!ep->desc)
1647                                 goto do_stall;
1648
1649                         /* iso never stalls */
1650                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1651                                 goto zero_status;
1652
1653                         /* FIXME don't assume non-halted endpoints!! */
1654                         ERR("%s status, can't report\n", ep->ep.name);
1655                         goto do_stall;
1656
1657 intf_status:
1658                         /* return interface status.  if we were pedantic,
1659                          * we'd detect non-existent interfaces, and stall.
1660                          */
1661                         if (u.r.bRequestType
1662                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1663                                 goto delegate;
1664
1665 zero_status:
1666                         /* return two zero bytes */
1667                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1668                         UDC_DATA_REG = 0;
1669                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1670                         UDC_EP_NUM_REG = UDC_EP_DIR;
1671                         status = 0;
1672                         VDBG("GET_STATUS, interface %d\n", w_index);
1673                         /* next, status stage */
1674                         break;
1675                 default:
1676 delegate:
1677                         /* activate the ep0out fifo right away */
1678                         if (!udc->ep0_in && w_length) {
1679                                 UDC_EP_NUM_REG = 0;
1680                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1681                         }
1682
1683                         /* gadget drivers see class/vendor specific requests,
1684                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1685                          * and more
1686                          */
1687                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1688                                 u.r.bRequestType, u.r.bRequest,
1689                                 w_value, w_index, w_length);
1690
1691 #undef  w_value
1692 #undef  w_index
1693 #undef  w_length
1694
1695                         /* The gadget driver may return an error here,
1696                          * causing an immediate protocol stall.
1697                          *
1698                          * Else it must issue a response, either queueing a
1699                          * response buffer for the DATA stage, or halting ep0
1700                          * (causing a protocol stall, not a real halt).  A
1701                          * zero length buffer means no DATA stage.
1702                          *
1703                          * It's fine to issue that response after the setup()
1704                          * call returns, and this IRQ was handled.
1705                          */
1706                         udc->ep0_setup = 1;
1707                         spin_unlock(&udc->lock);
1708                         status = udc->driver->setup (&udc->gadget, &u.r);
1709                         spin_lock(&udc->lock);
1710                         udc->ep0_setup = 0;
1711                 }
1712
1713                 if (status < 0) {
1714 do_stall:
1715                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1716                                         u.r.bRequestType, u.r.bRequest, status);
1717                         if (udc->ep0_set_config) {
1718                                 if (udc->ep0_reset_config)
1719                                         WARN("error resetting config?\n");
1720                                 else
1721                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1722                         }
1723                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1724                         udc->ep0_pending = 0;
1725                 }
1726         }
1727 }
1728
1729 /*-------------------------------------------------------------------------*/
1730
1731 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1732
1733 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1734 {
1735         u16     devstat, change;
1736
1737         devstat = UDC_DEVSTAT_REG;
1738         change = devstat ^ udc->devstat;
1739         udc->devstat = devstat;
1740
1741         if (change & (UDC_USB_RESET|UDC_ATT)) {
1742                 udc_quiesce(udc);
1743
1744                 if (change & UDC_ATT) {
1745                         /* driver for any external transceiver will
1746                          * have called omap_vbus_session() already
1747                          */
1748                         if (devstat & UDC_ATT) {
1749                                 udc->gadget.speed = USB_SPEED_FULL;
1750                                 VDBG("connect\n");
1751                                 if (!udc->transceiver)
1752                                         pullup_enable(udc);
1753                                 // if (driver->connect) call it
1754                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1755                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1756                                 if (!udc->transceiver)
1757                                         pullup_disable(udc);
1758                                 DBG("disconnect, gadget %s\n",
1759                                         udc->driver->driver.name);
1760                                 if (udc->driver->disconnect) {
1761                                         spin_unlock(&udc->lock);
1762                                         udc->driver->disconnect(&udc->gadget);
1763                                         spin_lock(&udc->lock);
1764                                 }
1765                         }
1766                         change &= ~UDC_ATT;
1767                 }
1768
1769                 if (change & UDC_USB_RESET) {
1770                         if (devstat & UDC_USB_RESET) {
1771                                 VDBG("RESET=1\n");
1772                         } else {
1773                                 udc->gadget.speed = USB_SPEED_FULL;
1774                                 INFO("USB reset done, gadget %s\n",
1775                                         udc->driver->driver.name);
1776                                 /* ep0 traffic is legal from now on */
1777                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1778                         }
1779                         change &= ~UDC_USB_RESET;
1780                 }
1781         }
1782         if (change & UDC_SUS) {
1783                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1784                         // FIXME tell isp1301 to suspend/resume (?)
1785                         if (devstat & UDC_SUS) {
1786                                 VDBG("suspend\n");
1787                                 update_otg(udc);
1788                                 /* HNP could be under way already */
1789                                 if (udc->gadget.speed == USB_SPEED_FULL
1790                                                 && udc->driver->suspend) {
1791                                         spin_unlock(&udc->lock);
1792                                         udc->driver->suspend(&udc->gadget);
1793                                         spin_lock(&udc->lock);
1794                                 }
1795                                 if (udc->transceiver)
1796                                         otg_set_suspend(udc->transceiver, 1);
1797                         } else {
1798                                 VDBG("resume\n");
1799                                 if (udc->transceiver)
1800                                         otg_set_suspend(udc->transceiver, 0);
1801                                 if (udc->gadget.speed == USB_SPEED_FULL
1802                                                 && udc->driver->resume) {
1803                                         spin_unlock(&udc->lock);
1804                                         udc->driver->resume(&udc->gadget);
1805                                         spin_lock(&udc->lock);
1806                                 }
1807                         }
1808                 }
1809                 change &= ~UDC_SUS;
1810         }
1811         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1812                 update_otg(udc);
1813                 change &= ~OTG_FLAGS;
1814         }
1815
1816         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1817         if (change)
1818                 VDBG("devstat %03x, ignore change %03x\n",
1819                         devstat,  change);
1820
1821         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1822 }
1823
1824 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1825 {
1826         struct omap_udc *udc = _udc;
1827         u16             irq_src;
1828         irqreturn_t     status = IRQ_NONE;
1829         unsigned long   flags;
1830
1831         spin_lock_irqsave(&udc->lock, flags);
1832         irq_src = UDC_IRQ_SRC_REG;
1833
1834         /* Device state change (usb ch9 stuff) */
1835         if (irq_src & UDC_DS_CHG) {
1836                 devstate_irq(_udc, irq_src);
1837                 status = IRQ_HANDLED;
1838                 irq_src &= ~UDC_DS_CHG;
1839         }
1840
1841         /* EP0 control transfers */
1842         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1843                 ep0_irq(_udc, irq_src);
1844                 status = IRQ_HANDLED;
1845                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1846         }
1847
1848         /* DMA transfer completion */
1849         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1850                 dma_irq(_udc, irq_src);
1851                 status = IRQ_HANDLED;
1852                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1853         }
1854
1855         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1856         if (irq_src)
1857                 DBG("udc_irq, unhandled %03x\n", irq_src);
1858         spin_unlock_irqrestore(&udc->lock, flags);
1859
1860         return status;
1861 }
1862
1863 /* workaround for seemingly-lost IRQs for RX ACKs... */
1864 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1865 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1866
1867 static void pio_out_timer(unsigned long _ep)
1868 {
1869         struct omap_ep  *ep = (void *) _ep;
1870         unsigned long   flags;
1871         u16             stat_flg;
1872
1873         spin_lock_irqsave(&ep->udc->lock, flags);
1874         if (!list_empty(&ep->queue) && ep->ackwait) {
1875                 use_ep(ep, UDC_EP_SEL);
1876                 stat_flg = UDC_STAT_FLG_REG;
1877
1878                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1879                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1880                         struct omap_req *req;
1881
1882                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1883                         req = container_of(ep->queue.next,
1884                                         struct omap_req, queue);
1885                         (void) read_fifo(ep, req);
1886                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1887                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1888                         ep->ackwait = 1 + ep->double_buf;
1889                 } else
1890                         deselect_ep();
1891         }
1892         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1893         spin_unlock_irqrestore(&ep->udc->lock, flags);
1894 }
1895
1896 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1897 {
1898         u16             epn_stat, irq_src;
1899         irqreturn_t     status = IRQ_NONE;
1900         struct omap_ep  *ep;
1901         int             epnum;
1902         struct omap_udc *udc = _dev;
1903         struct omap_req *req;
1904         unsigned long   flags;
1905
1906         spin_lock_irqsave(&udc->lock, flags);
1907         epn_stat = UDC_EPN_STAT_REG;
1908         irq_src = UDC_IRQ_SRC_REG;
1909
1910         /* handle OUT first, to avoid some wasteful NAKs */
1911         if (irq_src & UDC_EPN_RX) {
1912                 epnum = (epn_stat >> 8) & 0x0f;
1913                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1914                 status = IRQ_HANDLED;
1915                 ep = &udc->ep[epnum];
1916                 ep->irqs++;
1917
1918                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1919                 ep->fnf = 0;
1920                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1921                         ep->ackwait--;
1922                         if (!list_empty(&ep->queue)) {
1923                                 int stat;
1924                                 req = container_of(ep->queue.next,
1925                                                 struct omap_req, queue);
1926                                 stat = read_fifo(ep, req);
1927                                 if (!ep->double_buf)
1928                                         ep->fnf = 1;
1929                         }
1930                 }
1931                 /* min 6 clock delay before clearing EP_SEL ... */
1932                 epn_stat = UDC_EPN_STAT_REG;
1933                 epn_stat = UDC_EPN_STAT_REG;
1934                 UDC_EP_NUM_REG = epnum;
1935
1936                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1937                  * reduces lossage; timer still needed though (sigh).
1938                  */
1939                 if (ep->fnf) {
1940                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1941                         ep->ackwait = 1 + ep->double_buf;
1942                 }
1943                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1944         }
1945
1946         /* then IN transfers */
1947         else if (irq_src & UDC_EPN_TX) {
1948                 epnum = epn_stat & 0x0f;
1949                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1950                 status = IRQ_HANDLED;
1951                 ep = &udc->ep[16 + epnum];
1952                 ep->irqs++;
1953
1954                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1955                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1956                         ep->ackwait = 0;
1957                         if (!list_empty(&ep->queue)) {
1958                                 req = container_of(ep->queue.next,
1959                                                 struct omap_req, queue);
1960                                 (void) write_fifo(ep, req);
1961                         }
1962                 }
1963                 /* min 6 clock delay before clearing EP_SEL ... */
1964                 epn_stat = UDC_EPN_STAT_REG;
1965                 epn_stat = UDC_EPN_STAT_REG;
1966                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
1967                 /* then 6 clocks before it'd tx */
1968         }
1969
1970         spin_unlock_irqrestore(&udc->lock, flags);
1971         return status;
1972 }
1973
1974 #ifdef  USE_ISO
1975 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1976 {
1977         struct omap_udc *udc = _dev;
1978         struct omap_ep  *ep;
1979         int             pending = 0;
1980         unsigned long   flags;
1981
1982         spin_lock_irqsave(&udc->lock, flags);
1983
1984         /* handle all non-DMA ISO transfers */
1985         list_for_each_entry (ep, &udc->iso, iso) {
1986                 u16             stat;
1987                 struct omap_req *req;
1988
1989                 if (ep->has_dma || list_empty(&ep->queue))
1990                         continue;
1991                 req = list_entry(ep->queue.next, struct omap_req, queue);
1992
1993                 use_ep(ep, UDC_EP_SEL);
1994                 stat = UDC_STAT_FLG_REG;
1995
1996                 /* NOTE: like the other controller drivers, this isn't
1997                  * currently reporting lost or damaged frames.
1998                  */
1999                 if (ep->bEndpointAddress & USB_DIR_IN) {
2000                         if (stat & UDC_MISS_IN)
2001                                 /* done(ep, req, -EPROTO) */;
2002                         else
2003                                 write_fifo(ep, req);
2004                 } else {
2005                         int     status = 0;
2006
2007                         if (stat & UDC_NO_RXPACKET)
2008                                 status = -EREMOTEIO;
2009                         else if (stat & UDC_ISO_ERR)
2010                                 status = -EILSEQ;
2011                         else if (stat & UDC_DATA_FLUSH)
2012                                 status = -ENOSR;
2013
2014                         if (status)
2015                                 /* done(ep, req, status) */;
2016                         else
2017                                 read_fifo(ep, req);
2018                 }
2019                 deselect_ep();
2020                 /* 6 wait states before next EP */
2021
2022                 ep->irqs++;
2023                 if (!list_empty(&ep->queue))
2024                         pending = 1;
2025         }
2026         if (!pending)
2027                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2028         UDC_IRQ_SRC_REG = UDC_SOF;
2029
2030         spin_unlock_irqrestore(&udc->lock, flags);
2031         return IRQ_HANDLED;
2032 }
2033 #endif
2034
2035 /*-------------------------------------------------------------------------*/
2036
2037 static inline int machine_without_vbus_sense(void)
2038 {
2039         return (machine_is_omap_innovator()
2040                 || machine_is_omap_osk()
2041                 || machine_is_omap_apollon()
2042 #ifndef CONFIG_MACH_OMAP_H4_OTG
2043                 || machine_is_omap_h4()
2044 #endif
2045                 || machine_is_sx1()
2046                 );
2047 }
2048
2049 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2050 {
2051         int             status = -ENODEV;
2052         struct omap_ep  *ep;
2053         unsigned long   flags;
2054
2055         /* basic sanity tests */
2056         if (!udc)
2057                 return -ENODEV;
2058         if (!driver
2059                         // FIXME if otg, check:  driver->is_otg
2060                         || driver->speed < USB_SPEED_FULL
2061                         || !driver->bind
2062                         || !driver->setup)
2063                 return -EINVAL;
2064
2065         spin_lock_irqsave(&udc->lock, flags);
2066         if (udc->driver) {
2067                 spin_unlock_irqrestore(&udc->lock, flags);
2068                 return -EBUSY;
2069         }
2070
2071         /* reset state */
2072         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2073                 ep->irqs = 0;
2074                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2075                         continue;
2076                 use_ep(ep, 0);
2077                 UDC_CTRL_REG = UDC_SET_HALT;
2078         }
2079         udc->ep0_pending = 0;
2080         udc->ep[0].irqs = 0;
2081         udc->softconnect = 1;
2082
2083         /* hook up the driver */
2084         driver->driver.bus = NULL;
2085         udc->driver = driver;
2086         udc->gadget.dev.driver = &driver->driver;
2087         spin_unlock_irqrestore(&udc->lock, flags);
2088
2089         if (udc->dc_clk != NULL)
2090                 omap_udc_enable_clock(1);
2091
2092         status = driver->bind (&udc->gadget);
2093         if (status) {
2094                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2095                 udc->gadget.dev.driver = NULL;
2096                 udc->driver = NULL;
2097                 goto done;
2098         }
2099         DBG("bound to driver %s\n", driver->driver.name);
2100
2101         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2102
2103         /* connect to bus through transceiver */
2104         if (udc->transceiver) {
2105                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2106                 if (status < 0) {
2107                         ERR("can't bind to transceiver\n");
2108                         if (driver->unbind) {
2109                                 driver->unbind (&udc->gadget);
2110                                 udc->gadget.dev.driver = NULL;
2111                                 udc->driver = NULL;
2112                         }
2113                         goto done;
2114                 }
2115         } else {
2116                 if (can_pullup(udc))
2117                         pullup_enable (udc);
2118                 else
2119                         pullup_disable (udc);
2120         }
2121
2122         /* boards that don't have VBUS sensing can't autogate 48MHz;
2123          * can't enter deep sleep while a gadget driver is active.
2124          */
2125         if (machine_without_vbus_sense())
2126                 omap_vbus_session(&udc->gadget, 1);
2127
2128 done:
2129         if (udc->dc_clk != NULL)
2130                 omap_udc_enable_clock(0);
2131         return status;
2132 }
2133 EXPORT_SYMBOL(usb_gadget_register_driver);
2134
2135 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2136 {
2137         unsigned long   flags;
2138         int             status = -ENODEV;
2139
2140         if (!udc)
2141                 return -ENODEV;
2142         if (!driver || driver != udc->driver || !driver->unbind)
2143                 return -EINVAL;
2144
2145         if (udc->dc_clk != NULL)
2146                 omap_udc_enable_clock(1);
2147
2148         if (machine_without_vbus_sense())
2149                 omap_vbus_session(&udc->gadget, 0);
2150
2151         if (udc->transceiver)
2152                 (void) otg_set_peripheral(udc->transceiver, NULL);
2153         else
2154                 pullup_disable(udc);
2155
2156         spin_lock_irqsave(&udc->lock, flags);
2157         udc_quiesce(udc);
2158         spin_unlock_irqrestore(&udc->lock, flags);
2159
2160         driver->unbind(&udc->gadget);
2161         udc->gadget.dev.driver = NULL;
2162         udc->driver = NULL;
2163
2164         if (udc->dc_clk != NULL)
2165                 omap_udc_enable_clock(0);
2166         DBG("unregistered driver '%s'\n", driver->driver.name);
2167         return status;
2168 }
2169 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2170
2171
2172 /*-------------------------------------------------------------------------*/
2173
2174 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2175
2176 #include <linux/seq_file.h>
2177
2178 static const char proc_filename[] = "driver/udc";
2179
2180 #define FOURBITS "%s%s%s%s"
2181 #define EIGHTBITS FOURBITS FOURBITS
2182
2183 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2184 {
2185         u16             stat_flg;
2186         struct omap_req *req;
2187         char            buf[20];
2188
2189         use_ep(ep, 0);
2190
2191         if (use_dma && ep->has_dma)
2192                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2193                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2194                         ep->dma_channel - 1, ep->lch);
2195         else
2196                 buf[0] = 0;
2197
2198         stat_flg = UDC_STAT_FLG_REG;
2199         seq_printf(s,
2200                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2201                 ep->name, buf,
2202                 ep->double_buf ? "dbuf " : "",
2203                 ({char *s; switch(ep->ackwait){
2204                 case 0: s = ""; break;
2205                 case 1: s = "(ackw) "; break;
2206                 case 2: s = "(ackw2) "; break;
2207                 default: s = "(?) "; break;
2208                 } s;}),
2209                 ep->irqs, stat_flg,
2210                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2211                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2212                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2213                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2214                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2215                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2216                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2217                 (stat_flg & UDC_STALL) ? "STALL " : "",
2218                 (stat_flg & UDC_NAK) ? "NAK " : "",
2219                 (stat_flg & UDC_ACK) ? "ACK " : "",
2220                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2221                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2222                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2223
2224         if (list_empty (&ep->queue))
2225                 seq_printf(s, "\t(queue empty)\n");
2226         else
2227                 list_for_each_entry (req, &ep->queue, queue) {
2228                         unsigned        length = req->req.actual;
2229
2230                         if (use_dma && buf[0]) {
2231                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2232                                                 ? dma_src_len : dma_dest_len)
2233                                         (ep, req->req.dma + length);
2234                                 buf[0] = 0;
2235                         }
2236                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2237                                         &req->req, length,
2238                                         req->req.length, req->req.buf);
2239                 }
2240 }
2241
2242 static char *trx_mode(unsigned m, int enabled)
2243 {
2244         switch (m) {
2245         case 0:         return enabled ? "*6wire" : "unused";
2246         case 1:         return "4wire";
2247         case 2:         return "3wire";
2248         case 3:         return "6wire";
2249         default:        return "unknown";
2250         }
2251 }
2252
2253 static int proc_otg_show(struct seq_file *s)
2254 {
2255         u32             tmp;
2256         u32             trans;
2257         char            *ctrl_name;
2258
2259         tmp = OTG_REV_REG;
2260         if (cpu_is_omap24xx()) {
2261                 ctrl_name = "control_devconf";
2262                 trans = CONTROL_DEVCONF_REG;
2263         } else {
2264                 ctrl_name = "tranceiver_ctrl";
2265                 trans = USB_TRANSCEIVER_CTRL_REG;
2266         }
2267         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2268                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2269         tmp = OTG_SYSCON_1_REG;
2270         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2271                         FOURBITS "\n", tmp,
2272                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2273                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2274                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2275                         ? "internal"
2276                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2277                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2278                 (tmp & HST_IDLE_EN) ? " !host" : "",
2279                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2280                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2281         tmp = OTG_SYSCON_2_REG;
2282         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2283                         " b_ase_brst=%d hmc=%d\n", tmp,
2284                 (tmp & OTG_EN) ? " otg_en" : "",
2285                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2286                 // much more SRP stuff
2287                 (tmp & SRP_DATA) ? " srp_data" : "",
2288                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2289                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2290                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2291                 (tmp & UHOST_EN) ? " uhost_en" : "",
2292                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2293                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2294                 B_ASE_BRST(tmp),
2295                 OTG_HMC(tmp));
2296         tmp = OTG_CTRL_REG;
2297         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2298                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2299                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2300                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2301                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2302                 (tmp & OTG_ID) ? " id" : "",
2303                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2304                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2305                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2306                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2307                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2308                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2309                 (tmp & OTG_PULLDOWN) ? " down" : "",
2310                 (tmp & OTG_PULLUP) ? " up" : "",
2311                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2312                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2313                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2314                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2315                 );
2316         tmp = OTG_IRQ_EN_REG;
2317         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2318         tmp = OTG_IRQ_SRC_REG;
2319         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2320         tmp = OTG_OUTCTRL_REG;
2321         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2322         tmp = OTG_TEST_REG;
2323         seq_printf(s, "otg_test    %04x" "\n", tmp);
2324         return 0;
2325 }
2326
2327 static int proc_udc_show(struct seq_file *s, void *_)
2328 {
2329         u32             tmp;
2330         struct omap_ep  *ep;
2331         unsigned long   flags;
2332
2333         spin_lock_irqsave(&udc->lock, flags);
2334
2335         seq_printf(s, "%s, version: " DRIVER_VERSION
2336 #ifdef  USE_ISO
2337                 " (iso)"
2338 #endif
2339                 "%s\n",
2340                 driver_desc,
2341                 use_dma ?  " (dma)" : "");
2342
2343         tmp = UDC_REV_REG & 0xff;
2344         seq_printf(s,
2345                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2346                 "hmc %d, transceiver %s\n",
2347                 tmp >> 4, tmp & 0xf,
2348                 fifo_mode,
2349                 udc->driver ? udc->driver->driver.name : "(none)",
2350                 HMC,
2351                 udc->transceiver
2352                         ? udc->transceiver->label
2353                         : ((cpu_is_omap1710() || cpu_is_omap24xx())
2354                                 ? "external" : "(none)"));
2355         if (cpu_class_is_omap1()) {
2356                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2357                         __REG16(ULPD_CLOCK_CTRL),
2358                         __REG16(ULPD_SOFT_REQ),
2359                         __REG16(ULPD_STATUS_REQ));
2360         }
2361
2362         /* OTG controller registers */
2363         if (!cpu_is_omap15xx())
2364                 proc_otg_show(s);
2365
2366         tmp = UDC_SYSCON1_REG;
2367         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2368                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2369                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2370                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2371                 (tmp & UDC_NAK_EN) ? " nak" : "",
2372                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2373                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2374                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2375                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2376         // syscon2 is write-only
2377
2378         /* UDC controller registers */
2379         if (!(tmp & UDC_PULLUP_EN)) {
2380                 seq_printf(s, "(suspended)\n");
2381                 spin_unlock_irqrestore(&udc->lock, flags);
2382                 return 0;
2383         }
2384
2385         tmp = UDC_DEVSTAT_REG;
2386         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2387                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2388                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2389                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2390                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2391                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2392                 (tmp & UDC_SUS) ? " SUS" : "",
2393                 (tmp & UDC_CFG) ? " CFG" : "",
2394                 (tmp & UDC_ADD) ? " ADD" : "",
2395                 (tmp & UDC_DEF) ? " DEF" : "",
2396                 (tmp & UDC_ATT) ? " ATT" : "");
2397         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2398         tmp = UDC_IRQ_EN_REG;
2399         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2400                 (tmp & UDC_SOF_IE) ? " sof" : "",
2401                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2402                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2403                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2404                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2405         tmp = UDC_IRQ_SRC_REG;
2406         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2407                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2408                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2409                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2410                 (tmp & UDC_SOF) ? " sof" : "",
2411                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2412                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2413                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2414                 (tmp & UDC_SETUP) ? " setup" : "",
2415                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2416                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2417         if (use_dma) {
2418                 unsigned i;
2419
2420                 tmp = UDC_DMA_IRQ_EN_REG;
2421                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2422                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2423                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2424                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2425
2426                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2427                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2428                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2429
2430                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2431                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2432                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2433
2434                 tmp = UDC_RXDMA_CFG_REG;
2435                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2436                 if (tmp) {
2437                         for (i = 0; i < 3; i++) {
2438                                 if ((tmp & (0x0f << (i * 4))) == 0)
2439                                         continue;
2440                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2441                                                 UDC_RXDMA_REG(i + 1));
2442                         }
2443                 }
2444                 tmp = UDC_TXDMA_CFG_REG;
2445                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2446                 if (tmp) {
2447                         for (i = 0; i < 3; i++) {
2448                                 if (!(tmp & (0x0f << (i * 4))))
2449                                         continue;
2450                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2451                                                 UDC_TXDMA_REG(i + 1));
2452                         }
2453                 }
2454         }
2455
2456         tmp = UDC_DEVSTAT_REG;
2457         if (tmp & UDC_ATT) {
2458                 proc_ep_show(s, &udc->ep[0]);
2459                 if (tmp & UDC_ADD) {
2460                         list_for_each_entry (ep, &udc->gadget.ep_list,
2461                                         ep.ep_list) {
2462                                 if (ep->desc)
2463                                         proc_ep_show(s, ep);
2464                         }
2465                 }
2466         }
2467         spin_unlock_irqrestore(&udc->lock, flags);
2468         return 0;
2469 }
2470
2471 static int proc_udc_open(struct inode *inode, struct file *file)
2472 {
2473         return single_open(file, proc_udc_show, NULL);
2474 }
2475
2476 static const struct file_operations proc_ops = {
2477         .owner          = THIS_MODULE,
2478         .open           = proc_udc_open,
2479         .read           = seq_read,
2480         .llseek         = seq_lseek,
2481         .release        = single_release,
2482 };
2483
2484 static void create_proc_file(void)
2485 {
2486         proc_create(proc_filename, 0, NULL, &proc_ops);
2487 }
2488
2489 static void remove_proc_file(void)
2490 {
2491         remove_proc_entry(proc_filename, NULL);
2492 }
2493
2494 #else
2495
2496 static inline void create_proc_file(void) {}
2497 static inline void remove_proc_file(void) {}
2498
2499 #endif
2500
2501 /*-------------------------------------------------------------------------*/
2502
2503 /* Before this controller can enumerate, we need to pick an endpoint
2504  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2505  * buffer space among the endpoints we'll be operating.
2506  *
2507  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2508  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2509  * capability yet though.
2510  */
2511 static unsigned __init
2512 omap_ep_setup(char *name, u8 addr, u8 type,
2513                 unsigned buf, unsigned maxp, int dbuf)
2514 {
2515         struct omap_ep  *ep;
2516         u16             epn_rxtx = 0;
2517
2518         /* OUT endpoints first, then IN */
2519         ep = &udc->ep[addr & 0xf];
2520         if (addr & USB_DIR_IN)
2521                 ep += 16;
2522
2523         /* in case of ep init table bugs */
2524         BUG_ON(ep->name[0]);
2525
2526         /* chip setup ... bit values are same for IN, OUT */
2527         if (type == USB_ENDPOINT_XFER_ISOC) {
2528                 switch (maxp) {
2529                 case 8:         epn_rxtx = 0 << 12; break;
2530                 case 16:        epn_rxtx = 1 << 12; break;
2531                 case 32:        epn_rxtx = 2 << 12; break;
2532                 case 64:        epn_rxtx = 3 << 12; break;
2533                 case 128:       epn_rxtx = 4 << 12; break;
2534                 case 256:       epn_rxtx = 5 << 12; break;
2535                 case 512:       epn_rxtx = 6 << 12; break;
2536                 default:        BUG();
2537                 }
2538                 epn_rxtx |= UDC_EPN_RX_ISO;
2539                 dbuf = 1;
2540         } else {
2541                 /* double-buffering "not supported" on 15xx,
2542                  * and ignored for PIO-IN on newer chips
2543                  * (for more reliable behavior)
2544                  */
2545                 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2546                         dbuf = 0;
2547
2548                 switch (maxp) {
2549                 case 8:         epn_rxtx = 0 << 12; break;
2550                 case 16:        epn_rxtx = 1 << 12; break;
2551                 case 32:        epn_rxtx = 2 << 12; break;
2552                 case 64:        epn_rxtx = 3 << 12; break;
2553                 default:        BUG();
2554                 }
2555                 if (dbuf && addr)
2556                         epn_rxtx |= UDC_EPN_RX_DB;
2557                 init_timer(&ep->timer);
2558                 ep->timer.function = pio_out_timer;
2559                 ep->timer.data = (unsigned long) ep;
2560         }
2561         if (addr)
2562                 epn_rxtx |= UDC_EPN_RX_VALID;
2563         BUG_ON(buf & 0x07);
2564         epn_rxtx |= buf >> 3;
2565
2566         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2567                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2568
2569         if (addr & USB_DIR_IN)
2570                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2571         else
2572                 UDC_EP_RX_REG(addr) = epn_rxtx;
2573
2574         /* next endpoint's buffer starts after this one's */
2575         buf += maxp;
2576         if (dbuf)
2577                 buf += maxp;
2578         BUG_ON(buf > 2048);
2579
2580         /* set up driver data structures */
2581         BUG_ON(strlen(name) >= sizeof ep->name);
2582         strlcpy(ep->name, name, sizeof ep->name);
2583         INIT_LIST_HEAD(&ep->queue);
2584         INIT_LIST_HEAD(&ep->iso);
2585         ep->bEndpointAddress = addr;
2586         ep->bmAttributes = type;
2587         ep->double_buf = dbuf;
2588         ep->udc = udc;
2589
2590         ep->ep.name = ep->name;
2591         ep->ep.ops = &omap_ep_ops;
2592         ep->ep.maxpacket = ep->maxpacket = maxp;
2593         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2594
2595         return buf;
2596 }
2597
2598 static void omap_udc_release(struct device *dev)
2599 {
2600         complete(udc->done);
2601         kfree (udc);
2602         udc = NULL;
2603 }
2604
2605 static int __init
2606 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2607 {
2608         unsigned        tmp, buf;
2609
2610         /* abolish any previous hardware state */
2611         UDC_SYSCON1_REG = 0;
2612         UDC_IRQ_EN_REG = 0;
2613         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2614         UDC_DMA_IRQ_EN_REG = 0;
2615         UDC_RXDMA_CFG_REG = 0;
2616         UDC_TXDMA_CFG_REG = 0;
2617
2618         /* UDC_PULLUP_EN gates the chip clock */
2619         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2620
2621         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2622         if (!udc)
2623                 return -ENOMEM;
2624
2625         spin_lock_init (&udc->lock);
2626
2627         udc->gadget.ops = &omap_gadget_ops;
2628         udc->gadget.ep0 = &udc->ep[0].ep;
2629         INIT_LIST_HEAD(&udc->gadget.ep_list);
2630         INIT_LIST_HEAD(&udc->iso);
2631         udc->gadget.speed = USB_SPEED_UNKNOWN;
2632         udc->gadget.name = driver_name;
2633
2634         device_initialize(&udc->gadget.dev);
2635         strcpy (udc->gadget.dev.bus_id, "gadget");
2636         udc->gadget.dev.release = omap_udc_release;
2637         udc->gadget.dev.parent = &odev->dev;
2638         if (use_dma)
2639                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2640
2641         udc->transceiver = xceiv;
2642
2643         /* ep0 is special; put it right after the SETUP buffer */
2644         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2645                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2646         list_del_init(&udc->ep[0].ep.ep_list);
2647
2648         /* initially disable all non-ep0 endpoints */
2649         for (tmp = 1; tmp < 15; tmp++) {
2650                 UDC_EP_RX_REG(tmp) = 0;
2651                 UDC_EP_TX_REG(tmp) = 0;
2652         }
2653
2654 #define OMAP_BULK_EP(name,addr) \
2655         buf = omap_ep_setup(name "-bulk", addr, \
2656                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2657 #define OMAP_INT_EP(name,addr, maxp) \
2658         buf = omap_ep_setup(name "-int", addr, \
2659                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2660 #define OMAP_ISO_EP(name,addr, maxp) \
2661         buf = omap_ep_setup(name "-iso", addr, \
2662                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2663
2664         switch (fifo_mode) {
2665         case 0:
2666                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2667                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2668                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2669                 break;
2670         case 1:
2671                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2672                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2673                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2674
2675                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2676                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2677                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2678
2679                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2680                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2681                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2682
2683                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2684                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2685                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2686
2687                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2688                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2689                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2690                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2691
2692                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2693                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2694                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2695                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2696
2697                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2698                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2699
2700                 break;
2701
2702 #ifdef  USE_ISO
2703         case 2:                 /* mixed iso/bulk */
2704                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2705                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2706                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2707                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2708
2709                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2710
2711                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2712                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2713                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2714                 break;
2715         case 3:                 /* mixed bulk/iso */
2716                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2717                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2718                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2719
2720                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2721                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2722                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2723
2724                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2725                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2726                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2727                 break;
2728 #endif
2729
2730         /* add more modes as needed */
2731
2732         default:
2733                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2734                 return -ENODEV;
2735         }
2736         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2737         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2738         return 0;
2739 }
2740
2741 static int __init omap_udc_probe(struct platform_device *pdev)
2742 {
2743         int                     status = -ENODEV;
2744         int                     hmc;
2745         struct otg_transceiver  *xceiv = NULL;
2746         const char              *type = NULL;
2747         struct omap_usb_config  *config = pdev->dev.platform_data;
2748         struct clk              *dc_clk;
2749         struct clk              *hhc_clk;
2750
2751         /* NOTE:  "knows" the order of the resources! */
2752         if (!request_mem_region(pdev->resource[0].start,
2753                         pdev->resource[0].end - pdev->resource[0].start + 1,
2754                         driver_name)) {
2755                 DBG("request_mem_region failed\n");
2756                 return -EBUSY;
2757         }
2758
2759         if (cpu_is_omap16xx()) {
2760                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2761                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2762                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2763                 /* can't use omap_udc_enable_clock yet */
2764                 clk_enable(dc_clk);
2765                 clk_enable(hhc_clk);
2766                 udelay(100);
2767         }
2768
2769         if (cpu_is_omap24xx()) {
2770                 dc_clk = clk_get(&pdev->dev, "usb_fck");
2771                 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2772                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2773                 /* can't use omap_udc_enable_clock yet */
2774                 clk_enable(dc_clk);
2775                 clk_enable(hhc_clk);
2776                 udelay(100);
2777         }
2778
2779         INFO("OMAP UDC rev %d.%d%s\n",
2780                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2781                 config->otg ? ", Mini-AB" : "");
2782
2783         /* use the mode given to us by board init code */
2784         if (cpu_is_omap15xx()) {
2785                 hmc = HMC_1510;
2786                 type = "(unknown)";
2787
2788                 if (machine_without_vbus_sense()) {
2789                         /* just set up software VBUS detect, and then
2790                          * later rig it so we always report VBUS.
2791                          * FIXME without really sensing VBUS, we can't
2792                          * know when to turn PULLUP_EN on/off; and that
2793                          * means we always "need" the 48MHz clock.
2794                          */
2795                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2796
2797                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2798                         tmp |= VBUS_MODE_1510;
2799                         tmp &= ~VBUS_CTRL_1510;
2800                         FUNC_MUX_CTRL_0_REG = tmp;
2801                 }
2802         } else {
2803                 /* The transceiver may package some GPIO logic or handle
2804                  * loopback and/or transceiverless setup; if we find one,
2805                  * use it.  Except for OTG, we don't _need_ to talk to one;
2806                  * but not having one probably means no VBUS detection.
2807                  */
2808                 xceiv = otg_get_transceiver();
2809                 if (xceiv)
2810                         type = xceiv->label;
2811                 else if (config->otg) {
2812                         DBG("OTG requires external transceiver!\n");
2813                         goto cleanup0;
2814                 }
2815
2816                 hmc = HMC_1610;
2817
2818                 if (cpu_is_omap24xx()) {
2819                         /* this could be transceiverless in one of the
2820                          * "we don't need to know" modes.
2821                          */
2822                         type = "external";
2823                         goto known;
2824                 }
2825
2826                 switch (hmc) {
2827                 case 0:                 /* POWERUP DEFAULT == 0 */
2828                 case 4:
2829                 case 12:
2830                 case 20:
2831                         if (!cpu_is_omap1710()) {
2832                                 type = "integrated";
2833                                 break;
2834                         }
2835                         /* FALL THROUGH */
2836                 case 3:
2837                 case 11:
2838                 case 16:
2839                 case 19:
2840                 case 25:
2841                         if (!xceiv) {
2842                                 DBG("external transceiver not registered!\n");
2843                                 type = "unknown";
2844                         }
2845                         break;
2846                 case 21:                        /* internal loopback */
2847                         type = "loopback";
2848                         break;
2849                 case 14:                        /* transceiverless */
2850                         if (cpu_is_omap1710())
2851                                 goto bad_on_1710;
2852                         /* FALL THROUGH */
2853                 case 13:
2854                 case 15:
2855                         type = "no";
2856                         break;
2857
2858                 default:
2859 bad_on_1710:
2860                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2861                         goto cleanup0;
2862                 }
2863         }
2864 known:
2865         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2866
2867         /* a "gadget" abstracts/virtualizes the controller */
2868         status = omap_udc_setup(pdev, xceiv);
2869         if (status) {
2870                 goto cleanup0;
2871         }
2872         xceiv = NULL;
2873         // "udc" is now valid
2874         pullup_disable(udc);
2875 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2876         udc->gadget.is_otg = (config->otg != 0);
2877 #endif
2878
2879         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2880         if (UDC_REV_REG >= 0x61)
2881                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2882         else
2883                 udc->clr_halt = UDC_RESET_EP;
2884
2885         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2886         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2887                         IRQF_SAMPLE_RANDOM, driver_name, udc);
2888         if (status != 0) {
2889                 ERR("can't get irq %d, err %d\n",
2890                         (int) pdev->resource[1].start, status);
2891                 goto cleanup1;
2892         }
2893
2894         /* USB "non-iso" IRQ (PIO for all but ep0) */
2895         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2896                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2897         if (status != 0) {
2898                 ERR("can't get irq %d, err %d\n",
2899                         (int) pdev->resource[2].start, status);
2900                 goto cleanup2;
2901         }
2902 #ifdef  USE_ISO
2903         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2904                         IRQF_DISABLED, "omap_udc iso", udc);
2905         if (status != 0) {
2906                 ERR("can't get irq %d, err %d\n",
2907                         (int) pdev->resource[3].start, status);
2908                 goto cleanup3;
2909         }
2910 #endif
2911         if (cpu_is_omap16xx()) {
2912                 udc->dc_clk = dc_clk;
2913                 udc->hhc_clk = hhc_clk;
2914                 clk_disable(hhc_clk);
2915                 clk_disable(dc_clk);
2916         }
2917
2918         if (cpu_is_omap24xx()) {
2919                 udc->dc_clk = dc_clk;
2920                 udc->hhc_clk = hhc_clk;
2921                 /* FIXME OMAP2 don't release hhc & dc clock */
2922 #if 0
2923                 clk_disable(hhc_clk);
2924                 clk_disable(dc_clk);
2925 #endif
2926         }
2927
2928         create_proc_file();
2929         status = device_add(&udc->gadget.dev);
2930         if (!status)
2931                 return status;
2932         /* If fail, fall through */
2933 #ifdef  USE_ISO
2934 cleanup3:
2935         free_irq(pdev->resource[2].start, udc);
2936 #endif
2937
2938 cleanup2:
2939         free_irq(pdev->resource[1].start, udc);
2940
2941 cleanup1:
2942         kfree (udc);
2943         udc = NULL;
2944
2945 cleanup0:
2946         if (xceiv)
2947                 put_device(xceiv->dev);
2948
2949         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
2950                 clk_disable(hhc_clk);
2951                 clk_disable(dc_clk);
2952                 clk_put(hhc_clk);
2953                 clk_put(dc_clk);
2954         }
2955
2956         release_mem_region(pdev->resource[0].start,
2957                         pdev->resource[0].end - pdev->resource[0].start + 1);
2958
2959         return status;
2960 }
2961
2962 static int __exit omap_udc_remove(struct platform_device *pdev)
2963 {
2964         DECLARE_COMPLETION_ONSTACK(done);
2965
2966         if (!udc)
2967                 return -ENODEV;
2968         if (udc->driver)
2969                 return -EBUSY;
2970
2971         udc->done = &done;
2972
2973         pullup_disable(udc);
2974         if (udc->transceiver) {
2975                 put_device(udc->transceiver->dev);
2976                 udc->transceiver = NULL;
2977         }
2978         UDC_SYSCON1_REG = 0;
2979
2980         remove_proc_file();
2981
2982 #ifdef  USE_ISO
2983         free_irq(pdev->resource[3].start, udc);
2984 #endif
2985         free_irq(pdev->resource[2].start, udc);
2986         free_irq(pdev->resource[1].start, udc);
2987
2988         if (udc->dc_clk) {
2989                 if (udc->clk_requested)
2990                         omap_udc_enable_clock(0);
2991                 clk_put(udc->hhc_clk);
2992                 clk_put(udc->dc_clk);
2993         }
2994
2995         release_mem_region(pdev->resource[0].start,
2996                         pdev->resource[0].end - pdev->resource[0].start + 1);
2997
2998         device_unregister(&udc->gadget.dev);
2999         wait_for_completion(&done);
3000
3001         return 0;
3002 }
3003
3004 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3005  * system is forced into deep sleep
3006  *
3007  * REVISIT we should probably reject suspend requests when there's a host
3008  * session active, rather than disconnecting, at least on boards that can
3009  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
3010  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3011  * may involve talking to an external transceiver (e.g. isp1301).
3012  */
3013
3014 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3015 {
3016         u32     devstat;
3017
3018         devstat = UDC_DEVSTAT_REG;
3019
3020         /* we're requesting 48 MHz clock if the pullup is enabled
3021          * (== we're attached to the host) and we're not suspended,
3022          * which would prevent entry to deep sleep...
3023          */
3024         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3025                 WARN("session active; suspend requires disconnect\n");
3026                 omap_pullup(&udc->gadget, 0);
3027         }
3028
3029         return 0;
3030 }
3031
3032 static int omap_udc_resume(struct platform_device *dev)
3033 {
3034         DBG("resume + wakeup/SRP\n");
3035         omap_pullup(&udc->gadget, 1);
3036
3037         /* maybe the host would enumerate us if we nudged it */
3038         msleep(100);
3039         return omap_wakeup(&udc->gadget);
3040 }
3041
3042 /*-------------------------------------------------------------------------*/
3043
3044 static struct platform_driver udc_driver = {
3045         .probe          = omap_udc_probe,
3046         .remove         = __exit_p(omap_udc_remove),
3047         .suspend        = omap_udc_suspend,
3048         .resume         = omap_udc_resume,
3049         .driver         = {
3050                 .owner  = THIS_MODULE,
3051                 .name   = (char *) driver_name,
3052         },
3053 };
3054
3055 static int __init udc_init(void)
3056 {
3057         INFO("%s, version: " DRIVER_VERSION
3058 #ifdef  USE_ISO
3059                 " (iso)"
3060 #endif
3061                 "%s\n", driver_desc,
3062                 use_dma ?  " (dma)" : "");
3063         return platform_driver_register(&udc_driver);
3064 }
3065 module_init(udc_init);
3066
3067 static void __exit udc_exit(void)
3068 {
3069         platform_driver_unregister(&udc_driver);
3070 }
3071 module_exit(udc_exit);
3072
3073 MODULE_DESCRIPTION(DRIVER_DESC);
3074 MODULE_LICENSE("GPL");
3075 MODULE_ALIAS("platform:omap_udc");