drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #undef  DEBUG
  25 #undef  VERBOSE
  26
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/ioport.h>
  30 #include <linux/types.h>
  31 #include <linux/errno.h>
  32 #include <linux/delay.h>
  33 #include <linux/slab.h>
  34 #include <linux/init.h>
  35 #include <linux/timer.h>
  36 #include <linux/list.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/proc_fs.h>
  39 #include <linux/mm.h>
  40 #include <linux/moduleparam.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/usb/ch9.h>
  43 #include <linux/usb/gadget.h>
  44 #include <linux/usb/otg.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/clk.h>
  47
  48 #include <asm/byteorder.h>
  49 #include <asm/io.h>
  50 #include <asm/irq.h>
  51 #include <asm/system.h>
  52 #include <asm/unaligned.h>
  53 #include <asm/mach-types.h>
  54
  55 #include <asm/arch/dma.h>
  56 #include <asm/arch/usb.h>
  57 #include <asm/arch/control.h>
  58
  59 #include "omap_udc.h"
  60
  61 #undef  USB_TRACE
  62
  63 /* bulk DMA seems to be behaving for both IN and OUT */
  64 #define USE_DMA
  65
  66 /* ISO too */
  67 #define USE_ISO
  68
  69 #define DRIVER_DESC     "OMAP UDC driver"
  70 #define DRIVER_VERSION  "4 October 2004"
  71
  72 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  73
  74 #define OMAP2_DMA_CH(ch)        (((ch) - 1) << 1)
  75 #define OMAP24XX_DMA(name, ch)  (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
  76
  77 /*
  78  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  79  * D+ pullup to allow enumeration.  That's too early for the gadget
  80  * framework to use from usb_endpoint_enable(), which happens after
  81  * enumeration as part of activating an interface.  (But if we add an
  82  * optional new "UDC not yet running" state to the gadget driver model,
  83  * even just during driver binding, the endpoint autoconfig logic is the
  84  * natural spot to manufacture new endpoints.)
  85  *
  86  * So instead of using endpoint enable calls to control the hardware setup,
  87  * this driver defines a "fifo mode" parameter.  It's used during driver
  88  * initialization to choose among a set of pre-defined endpoint configs.
  89  * See omap_udc_setup() for available modes, or to add others.  That code
  90  * lives in an init section, so use this driver as a module if you need
  91  * to change the fifo mode after the kernel boots.
  92  *
  93  * Gadget drivers normally ignore endpoints they don't care about, and
  94  * won't include them in configuration descriptors.  That means only
  95  * misbehaving hosts would even notice they exist.
  96  */
  97 #ifdef  USE_ISO
  98 static unsigned fifo_mode = 3;
  99 #else
 100 static unsigned fifo_mode = 0;
 101 #endif
 102
 103 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 104  * boot parameter "omap_udc:fifo_mode=42"
 105  */
 106 module_param (fifo_mode, uint, 0);
 107 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
 108
 109 #ifdef  USE_DMA
 110 static unsigned use_dma = 1;
 111
 112 /* "modprobe omap_udc use_dma=y", or else as a kernel
 113  * boot parameter "omap_udc:use_dma=y"
 114  */
 115 module_param (use_dma, bool, 0);
 116 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 117 #else   /* !USE_DMA */
 118
 119 /* save a bit of code */
 120 #define use_dma         0
 121 #endif  /* !USE_DMA */
 122
 123
 124 static const char driver_name [] = "omap_udc";
 125 static const char driver_desc [] = DRIVER_DESC;
 126
 127 /*-------------------------------------------------------------------------*/
 128
 129 /* there's a notion of "current endpoint" for modifying endpoint
 130  * state, and PIO access to its FIFO.
 131  */
 132
 133 static void use_ep(struct omap_ep *ep, u16 select)
 134 {
 135         u16     num = ep->bEndpointAddress & 0x0f;
 136
 137         if (ep->bEndpointAddress & USB_DIR_IN)
 138                 num |= UDC_EP_DIR;
 139         UDC_EP_NUM_REG = num | select;
 140         /* when select, MUST deselect later !! */
 141 }
 142
 143 static inline void deselect_ep(void)
 144 {
 145         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
 146         /* 6 wait states before TX will happen */
 147 }
 148
 149 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 150
 151 /*-------------------------------------------------------------------------*/
 152
 153 static int omap_ep_enable(struct usb_ep *_ep,
 154                 const struct usb_endpoint_descriptor *desc)
 155 {
 156         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 157         struct omap_udc *udc;
 158         unsigned long   flags;
 159         u16             maxp;
 160
 161         /* catch various bogus parameters */
 162         if (!_ep || !desc || ep->desc
 163                         || desc->bDescriptorType != USB_DT_ENDPOINT
 164                         || ep->bEndpointAddress != desc->bEndpointAddress
 165                         || ep->maxpacket < le16_to_cpu
 166                                                 (desc->wMaxPacketSize)) {
 167                 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
 168                 return -EINVAL;
 169         }
 170         maxp = le16_to_cpu (desc->wMaxPacketSize);
 171         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 172                                 && maxp != ep->maxpacket)
 173                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 174                         || !desc->wMaxPacketSize) {
 175                 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 176                 return -ERANGE;
 177         }
 178
 179 #ifdef  USE_ISO
 180         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 181                                 && desc->bInterval != 1)) {
 182                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 183                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 184                                 1 << (desc->bInterval - 1));
 185                 return -EDOM;
 186         }
 187 #else
 188         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 189                 DBG("%s, ISO nyet\n", _ep->name);
 190                 return -EDOM;
 191         }
 192 #endif
 193
 194         /* xfer types must match, except that interrupt ~= bulk */
 195         if (ep->bmAttributes != desc->bmAttributes
 196                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 197                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 198                 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 199                 return -EINVAL;
 200         }
 201
 202         udc = ep->udc;
 203         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 204                 DBG("%s, bogus device state\n", __FUNCTION__);
 205                 return -ESHUTDOWN;
 206         }
 207
 208         spin_lock_irqsave(&udc->lock, flags);
 209
 210         ep->desc = desc;
 211         ep->irqs = 0;
 212         ep->stopped = 0;
 213         ep->ep.maxpacket = maxp;
 214
 215         /* set endpoint to initial state */
 216         ep->dma_channel = 0;
 217         ep->has_dma = 0;
 218         ep->lch = -1;
 219         use_ep(ep, UDC_EP_SEL);
 220         UDC_CTRL_REG = udc->clr_halt;
 221         ep->ackwait = 0;
 222         deselect_ep();
 223
 224         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 225                 list_add(&ep->iso, &udc->iso);
 226
 227         /* maybe assign a DMA channel to this endpoint */
 228         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 229                 /* FIXME ISO can dma, but prefers first channel */
 230                 dma_channel_claim(ep, 0);
 231
 232         /* PIO OUT may RX packets */
 233         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 234                         && !ep->has_dma
 235                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 236                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 237                 ep->ackwait = 1 + ep->double_buf;
 238         }
 239
 240         spin_unlock_irqrestore(&udc->lock, flags);
 241         VDBG("%s enabled\n", _ep->name);
 242         return 0;
 243 }
 244
 245 static void nuke(struct omap_ep *, int status);
 246
 247 static int omap_ep_disable(struct usb_ep *_ep)
 248 {
 249         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 250         unsigned long   flags;
 251
 252         if (!_ep || !ep->desc) {
 253                 DBG("%s, %s not enabled\n", __FUNCTION__,
 254                         _ep ? ep->ep.name : NULL);
 255                 return -EINVAL;
 256         }
 257
 258         spin_lock_irqsave(&ep->udc->lock, flags);
 259         ep->desc = NULL;
 260         nuke (ep, -ESHUTDOWN);
 261         ep->ep.maxpacket = ep->maxpacket;
 262         ep->has_dma = 0;
 263         UDC_CTRL_REG = UDC_SET_HALT;
 264         list_del_init(&ep->iso);
 265         del_timer(&ep->timer);
 266
 267         spin_unlock_irqrestore(&ep->udc->lock, flags);
 268
 269         VDBG("%s disabled\n", _ep->name);
 270         return 0;
 271 }
 272
 273 /*-------------------------------------------------------------------------*/
 274
 275 static struct usb_request *
 276 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 277 {
 278         struct omap_req *req;
 279
 280         req = kzalloc(sizeof(*req), gfp_flags);
 281         if (req) {
 282                 req->req.dma = DMA_ADDR_INVALID;
 283                 INIT_LIST_HEAD (&req->queue);
 284         }
 285         return &req->req;
 286 }
 287
 288 static void
 289 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 290 {
 291         struct omap_req *req = container_of(_req, struct omap_req, req);
 292
 293         if (_req)
 294                 kfree (req);
 295 }
 296
 297 /*-------------------------------------------------------------------------*/
 298
 299 static void
 300 done(struct omap_ep *ep, struct omap_req *req, int status)
 301 {
 302         unsigned                stopped = ep->stopped;
 303
 304         list_del_init(&req->queue);
 305
 306         if (req->req.status == -EINPROGRESS)
 307                 req->req.status = status;
 308         else
 309                 status = req->req.status;
 310
 311         if (use_dma && ep->has_dma) {
 312                 if (req->mapped) {
 313                         dma_unmap_single(ep->udc->gadget.dev.parent,
 314                                 req->req.dma, req->req.length,
 315                                 (ep->bEndpointAddress & USB_DIR_IN)
 316                                         ? DMA_TO_DEVICE
 317                                         : DMA_FROM_DEVICE);
 318                         req->req.dma = DMA_ADDR_INVALID;
 319                         req->mapped = 0;
 320                 } else
 321                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 322                                 req->req.dma, req->req.length,
 323                                 (ep->bEndpointAddress & USB_DIR_IN)
 324                                         ? DMA_TO_DEVICE
 325                                         : DMA_FROM_DEVICE);
 326         }
 327
 328 #ifndef USB_TRACE
 329         if (status && status != -ESHUTDOWN)
 330 #endif
 331                 VDBG("complete %s req %p stat %d len %u/%u\n",
 332                         ep->ep.name, &req->req, status,
 333                         req->req.actual, req->req.length);
 334
 335         /* don't modify queue heads during completion callback */
 336         ep->stopped = 1;
 337         spin_unlock(&ep->udc->lock);
 338         req->req.complete(&ep->ep, &req->req);
 339         spin_lock(&ep->udc->lock);
 340         ep->stopped = stopped;
 341 }
 342
 343 /*-------------------------------------------------------------------------*/
 344
 345 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 346 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 347
 348 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 349 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 350
 351 static inline int
 352 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 353 {
 354         unsigned        len;
 355         u16             *wp;
 356
 357         len = min(req->req.length - req->req.actual, max);
 358         req->req.actual += len;
 359
 360         max = len;
 361         if (likely((((int)buf) & 1) == 0)) {
 362                 wp = (u16 *)buf;
 363                 while (max >= 2) {
 364                         UDC_DATA_REG = *wp++;
 365                         max -= 2;
 366                 }
 367                 buf = (u8 *)wp;
 368         }
 369         while (max--)
 370                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
 371         return len;
 372 }
 373
 374 // FIXME change r/w fifo calling convention
 375
 376
 377 // return:  0 = still running, 1 = completed, negative = errno
 378 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 379 {
 380         u8              *buf;
 381         unsigned        count;
 382         int             is_last;
 383         u16             ep_stat;
 384
 385         buf = req->req.buf + req->req.actual;
 386         prefetch(buf);
 387
 388         /* PIO-IN isn't double buffered except for iso */
 389         ep_stat = UDC_STAT_FLG_REG;
 390         if (ep_stat & UDC_FIFO_UNWRITABLE)
 391                 return 0;
 392
 393         count = ep->ep.maxpacket;
 394         count = write_packet(buf, req, count);
 395         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 396         ep->ackwait = 1;
 397
 398         /* last packet is often short (sometimes a zlp) */
 399         if (count != ep->ep.maxpacket)
 400                 is_last = 1;
 401         else if (req->req.length == req->req.actual
 402                         && !req->req.zero)
 403                 is_last = 1;
 404         else
 405                 is_last = 0;
 406
 407         /* NOTE:  requests complete when all IN data is in a
 408          * FIFO (or sometimes later, if a zlp was needed).
 409          * Use usb_ep_fifo_status() where needed.
 410          */
 411         if (is_last)
 412                 done(ep, req, 0);
 413         return is_last;
 414 }
 415
 416 static inline int
 417 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 418 {
 419         unsigned        len;
 420         u16             *wp;
 421
 422         len = min(req->req.length - req->req.actual, avail);
 423         req->req.actual += len;
 424         avail = len;
 425
 426         if (likely((((int)buf) & 1) == 0)) {
 427                 wp = (u16 *)buf;
 428                 while (avail >= 2) {
 429                         *wp++ = UDC_DATA_REG;
 430                         avail -= 2;
 431                 }
 432                 buf = (u8 *)wp;
 433         }
 434         while (avail--)
 435                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
 436         return len;
 437 }
 438
 439 // return:  0 = still running, 1 = queue empty, negative = errno
 440 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 441 {
 442         u8              *buf;
 443         unsigned        count, avail;
 444         int             is_last;
 445
 446         buf = req->req.buf + req->req.actual;
 447         prefetchw(buf);
 448
 449         for (;;) {
 450                 u16     ep_stat = UDC_STAT_FLG_REG;
 451
 452                 is_last = 0;
 453                 if (ep_stat & FIFO_EMPTY) {
 454                         if (!ep->double_buf)
 455                                 break;
 456                         ep->fnf = 1;
 457                 }
 458                 if (ep_stat & UDC_EP_HALTED)
 459                         break;
 460
 461                 if (ep_stat & UDC_FIFO_FULL)
 462                         avail = ep->ep.maxpacket;
 463                 else  {
 464                         avail = UDC_RXFSTAT_REG;
 465                         ep->fnf = ep->double_buf;
 466                 }
 467                 count = read_packet(buf, req, avail);
 468
 469                 /* partial packet reads may not be errors */
 470                 if (count < ep->ep.maxpacket) {
 471                         is_last = 1;
 472                         /* overflowed this request?  flush extra data */
 473                         if (count != avail) {
 474                                 req->req.status = -EOVERFLOW;
 475                                 avail -= count;
 476                                 while (avail--)
 477                                         (void) *(volatile u8 *)&UDC_DATA_REG;
 478                         }
 479                 } else if (req->req.length == req->req.actual)
 480                         is_last = 1;
 481                 else
 482                         is_last = 0;
 483
 484                 if (!ep->bEndpointAddress)
 485                         break;
 486                 if (is_last)
 487                         done(ep, req, 0);
 488                 break;
 489         }
 490         return is_last;
 491 }
 492
 493 /*-------------------------------------------------------------------------*/
 494
 495 static inline dma_addr_t dma_csac(unsigned lch)
 496 {
 497         dma_addr_t      csac;
 498
 499         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 500          * read before the DMA controller finished disabling the channel.
 501          */
 502         csac = OMAP_DMA_CSAC_REG(lch);
 503         if (csac == 0)
 504                 csac = OMAP_DMA_CSAC_REG(lch);
 505         return csac;
 506 }
 507
 508 static inline dma_addr_t dma_cdac(unsigned lch)
 509 {
 510         dma_addr_t      cdac;
 511
 512         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 513          * read before the DMA controller finished disabling the channel.
 514          */
 515         cdac = OMAP_DMA_CDAC_REG(lch);
 516         if (cdac == 0)
 517                 cdac = OMAP_DMA_CDAC_REG(lch);
 518         return cdac;
 519 }
 520
 521 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 522 {
 523         dma_addr_t      end;
 524
 525         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 526          * the last transfer's bytecount by more than a FIFO's worth.
 527          */
 528         if (cpu_is_omap15xx())
 529                 return 0;
 530
 531         end = dma_csac(ep->lch);
 532         if (end == ep->dma_counter)
 533                 return 0;
 534
 535         end |= start & (0xffff << 16);
 536         if (end < start)
 537                 end += 0x10000;
 538         return end - start;
 539 }
 540
 541 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
 542                 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
 543                 : dma_cdac(x))
 544
 545 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 546 {
 547         dma_addr_t      end;
 548
 549         end = DMA_DEST_LAST(ep->lch);
 550         if (end == ep->dma_counter)
 551                 return 0;
 552
 553         end |= start & (0xffff << 16);
 554         if (cpu_is_omap15xx())
 555                 end++;
 556         if (end < start)
 557                 end += 0x10000;
 558         return end - start;
 559 }
 560
 561
 562 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 563  * When DMA completion isn't request completion, the UDC continues with
 564  * the next DMA transfer for that USB transfer.
 565  */
 566
 567 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 568 {
 569         u16             txdma_ctrl;
 570         unsigned        length = req->req.length - req->req.actual;
 571         const int       sync_mode = cpu_is_omap15xx()
 572                                 ? OMAP_DMA_SYNC_FRAME
 573                                 : OMAP_DMA_SYNC_ELEMENT;
 574         int             dma_trigger = 0;
 575
 576         if (cpu_is_omap24xx())
 577                 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
 578
 579         /* measure length in either bytes or packets */
 580         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 581                         || (cpu_is_omap24xx() && length < ep->maxpacket)
 582                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 583                 txdma_ctrl = UDC_TXN_EOT | length;
 584                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 585                                 length, 1, sync_mode, dma_trigger, 0);
 586         } else {
 587                 length = min(length / ep->maxpacket,
 588                                 (unsigned) UDC_TXN_TSC + 1);
 589                 txdma_ctrl = length;
 590                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 591                                 ep->ep.maxpacket >> 1, length, sync_mode,
 592                                 dma_trigger, 0);
 593                 length *= ep->maxpacket;
 594         }
 595         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 596                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 597                 0, 0);
 598
 599         omap_start_dma(ep->lch);
 600         ep->dma_counter = dma_csac(ep->lch);
 601         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
 602         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
 603         req->dma_bytes = length;
 604 }
 605
 606 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 607 {
 608         if (status == 0) {
 609                 req->req.actual += req->dma_bytes;
 610
 611                 /* return if this request needs to send data or zlp */
 612                 if (req->req.actual < req->req.length)
 613                         return;
 614                 if (req->req.zero
 615                                 && req->dma_bytes != 0
 616                                 && (req->req.actual % ep->maxpacket) == 0)
 617                         return;
 618         } else
 619                 req->req.actual += dma_src_len(ep, req->req.dma
 620                                                         + req->req.actual);
 621
 622         /* tx completion */
 623         omap_stop_dma(ep->lch);
 624         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
 625         done(ep, req, status);
 626 }
 627
 628 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 629 {
 630         unsigned packets = req->req.length - req->req.actual;
 631         int dma_trigger = 0;
 632
 633         if (cpu_is_omap24xx())
 634                 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
 635
 636         /* NOTE:  we filtered out "short reads" before, so we know
 637          * the buffer has only whole numbers of packets.
 638          * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
 639          */
 640         if (cpu_is_omap24xx() && packets < ep->maxpacket) {
 641                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 642                                 packets, 1, OMAP_DMA_SYNC_ELEMENT,
 643                                 dma_trigger, 0);
 644                 req->dma_bytes = packets;
 645         } else {
 646                 /* set up this DMA transfer, enable the fifo, start */
 647                 packets /= ep->ep.maxpacket;
 648                 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 649                 req->dma_bytes = packets * ep->ep.maxpacket;
 650                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 651                                 ep->ep.maxpacket >> 1, packets,
 652                                 OMAP_DMA_SYNC_ELEMENT,
 653                                 dma_trigger, 0);
 654         }
 655         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 656                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 657                 0, 0);
 658         ep->dma_counter = DMA_DEST_LAST(ep->lch);
 659
 660         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
 661         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
 662         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
 663         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 664
 665         omap_start_dma(ep->lch);
 666 }
 667
 668 static void
 669 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 670 {
 671         u16     count;
 672
 673         if (status == 0)
 674                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 675         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 676         count += req->req.actual;
 677         if (one)
 678                 count--;
 679         if (count <= req->req.length)
 680                 req->req.actual = count;
 681
 682         if (count != req->dma_bytes || status)
 683                 omap_stop_dma(ep->lch);
 684
 685         /* if this wasn't short, request may need another transfer */
 686         else if (req->req.actual < req->req.length)
 687                 return;
 688
 689         /* rx completion */
 690         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
 691         done(ep, req, status);
 692 }
 693
 694 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 695 {
 696         u16             dman_stat = UDC_DMAN_STAT_REG;
 697         struct omap_ep  *ep;
 698         struct omap_req *req;
 699
 700         /* IN dma: tx to host */
 701         if (irq_src & UDC_TXN_DONE) {
 702                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 703                 ep->irqs++;
 704                 /* can see TXN_DONE after dma abort */
 705                 if (!list_empty(&ep->queue)) {
 706                         req = container_of(ep->queue.next,
 707                                                 struct omap_req, queue);
 708                         finish_in_dma(ep, req, 0);
 709                 }
 710                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
 711
 712                 if (!list_empty (&ep->queue)) {
 713                         req = container_of(ep->queue.next,
 714                                         struct omap_req, queue);
 715                         next_in_dma(ep, req);
 716                 }
 717         }
 718
 719         /* OUT dma: rx from host */
 720         if (irq_src & UDC_RXN_EOT) {
 721                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 722                 ep->irqs++;
 723                 /* can see RXN_EOT after dma abort */
 724                 if (!list_empty(&ep->queue)) {
 725                         req = container_of(ep->queue.next,
 726                                         struct omap_req, queue);
 727                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 728                 }
 729                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
 730
 731                 if (!list_empty (&ep->queue)) {
 732                         req = container_of(ep->queue.next,
 733                                         struct omap_req, queue);
 734                         next_out_dma(ep, req);
 735                 }
 736         }
 737
 738         if (irq_src & UDC_RXN_CNT) {
 739                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 740                 ep->irqs++;
 741                 /* omap15xx does this unasked... */
 742                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 743                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
 744         }
 745 }
 746
 747 static void dma_error(int lch, u16 ch_status, void *data)
 748 {
 749         struct omap_ep  *ep = data;
 750
 751         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 752         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 753         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 754
 755         /* complete current transfer ... */
 756 }
 757
 758 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 759 {
 760         u16     reg;
 761         int     status, restart, is_in;
 762         int     dma_channel;
 763
 764         is_in = ep->bEndpointAddress & USB_DIR_IN;
 765         if (is_in)
 766                 reg = UDC_TXDMA_CFG_REG;
 767         else
 768                 reg = UDC_RXDMA_CFG_REG;
 769         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 770
 771         ep->dma_channel = 0;
 772         ep->lch = -1;
 773         if (channel == 0 || channel > 3) {
 774                 if ((reg & 0x0f00) == 0)
 775                         channel = 3;
 776                 else if ((reg & 0x00f0) == 0)
 777                         channel = 2;
 778                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 779                         channel = 1;
 780                 else {
 781                         status = -EMLINK;
 782                         goto just_restart;
 783                 }
 784         }
 785         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 786         ep->dma_channel = channel;
 787
 788         if (is_in) {
 789                 if (cpu_is_omap24xx())
 790                         dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
 791                 else
 792                         dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
 793                 status = omap_request_dma(dma_channel,
 794                         ep->ep.name, dma_error, ep, &ep->lch);
 795                 if (status == 0) {
 796                         UDC_TXDMA_CFG_REG = reg;
 797                         /* EMIFF or SDRC */
 798                         omap_set_dma_src_burst_mode(ep->lch,
 799                                                 OMAP_DMA_DATA_BURST_4);
 800                         omap_set_dma_src_data_pack(ep->lch, 1);
 801                         /* TIPB */
 802                         omap_set_dma_dest_params(ep->lch,
 803                                 OMAP_DMA_PORT_TIPB,
 804                                 OMAP_DMA_AMODE_CONSTANT,
 805                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 806                                 0, 0);
 807                 }
 808         } else {
 809                 if (cpu_is_omap24xx())
 810                         dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
 811                 else
 812                         dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
 813
 814                 status = omap_request_dma(dma_channel,
 815                         ep->ep.name, dma_error, ep, &ep->lch);
 816                 if (status == 0) {
 817                         UDC_RXDMA_CFG_REG = reg;
 818                         /* TIPB */
 819                         omap_set_dma_src_params(ep->lch,
 820                                 OMAP_DMA_PORT_TIPB,
 821                                 OMAP_DMA_AMODE_CONSTANT,
 822                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 823                                 0, 0);
 824                         /* EMIFF or SDRC */
 825                         omap_set_dma_dest_burst_mode(ep->lch,
 826                                                 OMAP_DMA_DATA_BURST_4);
 827                         omap_set_dma_dest_data_pack(ep->lch, 1);
 828                 }
 829         }
 830         if (status)
 831                 ep->dma_channel = 0;
 832         else {
 833                 ep->has_dma = 1;
 834                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 835
 836                 /* channel type P: hw synch (fifo) */
 837                 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
 838                         OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
 839         }
 840
 841 just_restart:
 842         /* restart any queue, even if the claim failed  */
 843         restart = !ep->stopped && !list_empty(&ep->queue);
 844
 845         if (status)
 846                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 847                         restart ? " (restart)" : "");
 848         else
 849                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 850                         is_in ? 't' : 'r',
 851                         ep->dma_channel - 1, ep->lch,
 852                         restart ? " (restart)" : "");
 853
 854         if (restart) {
 855                 struct omap_req *req;
 856                 req = container_of(ep->queue.next, struct omap_req, queue);
 857                 if (ep->has_dma)
 858                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 859                 else {
 860                         use_ep(ep, UDC_EP_SEL);
 861                         (is_in ? write_fifo : read_fifo)(ep, req);
 862                         deselect_ep();
 863                         if (!is_in) {
 864                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 865                                 ep->ackwait = 1 + ep->double_buf;
 866                         }
 867                         /* IN: 6 wait states before it'll tx */
 868                 }
 869         }
 870 }
 871
 872 static void dma_channel_release(struct omap_ep *ep)
 873 {
 874         int             shift = 4 * (ep->dma_channel - 1);
 875         u16             mask = 0x0f << shift;
 876         struct omap_req *req;
 877         int             active;
 878
 879         /* abort any active usb transfer request */
 880         if (!list_empty(&ep->queue))
 881                 req = container_of(ep->queue.next, struct omap_req, queue);
 882         else
 883                 req = NULL;
 884
 885         active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
 886
 887         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 888                         active ? "active" : "idle",
 889                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 890                         ep->dma_channel - 1, req);
 891
 892         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 893          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 894          */
 895
 896         /* wait till current packet DMA finishes, and fifo empties */
 897         if (ep->bEndpointAddress & USB_DIR_IN) {
 898                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 899
 900                 if (req) {
 901                         finish_in_dma(ep, req, -ECONNRESET);
 902
 903                         /* clear FIFO; hosts probably won't empty it */
 904                         use_ep(ep, UDC_EP_SEL);
 905                         UDC_CTRL_REG = UDC_CLR_EP;
 906                         deselect_ep();
 907                 }
 908                 while (UDC_TXDMA_CFG_REG & mask)
 909                         udelay(10);
 910         } else {
 911                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 912
 913                 /* dma empties the fifo */
 914                 while (UDC_RXDMA_CFG_REG & mask)
 915                         udelay(10);
 916                 if (req)
 917                         finish_out_dma(ep, req, -ECONNRESET, 0);
 918         }
 919         omap_free_dma(ep->lch);
 920         ep->dma_channel = 0;
 921         ep->lch = -1;
 922         /* has_dma still set, till endpoint is fully quiesced */
 923 }
 924
 925
 926 /*-------------------------------------------------------------------------*/
 927
 928 static int
 929 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 930 {
 931         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 932         struct omap_req *req = container_of(_req, struct omap_req, req);
 933         struct omap_udc *udc;
 934         unsigned long   flags;
 935         int             is_iso = 0;
 936
 937         /* catch various bogus parameters */
 938         if (!_req || !req->req.complete || !req->req.buf
 939                         || !list_empty(&req->queue)) {
 940                 DBG("%s, bad params\n", __FUNCTION__);
 941                 return -EINVAL;
 942         }
 943         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 944                 DBG("%s, bad ep\n", __FUNCTION__);
 945                 return -EINVAL;
 946         }
 947         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 948                 if (req->req.length > ep->ep.maxpacket)
 949                         return -EMSGSIZE;
 950                 is_iso = 1;
 951         }
 952
 953         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 954          * have a hard time with partial packet reads...  reject it.
 955          * Except OMAP2 can handle the small packets.
 956          */
 957         if (use_dma
 958                         && ep->has_dma
 959                         && ep->bEndpointAddress != 0
 960                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 961                         && !cpu_class_is_omap2()
 962                         && (req->req.length % ep->ep.maxpacket) != 0) {
 963                 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
 964                 return -EMSGSIZE;
 965         }
 966
 967         udc = ep->udc;
 968         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 969                 return -ESHUTDOWN;
 970
 971         if (use_dma && ep->has_dma) {
 972                 if (req->req.dma == DMA_ADDR_INVALID) {
 973                         req->req.dma = dma_map_single(
 974                                 ep->udc->gadget.dev.parent,
 975                                 req->req.buf,
 976                                 req->req.length,
 977                                 (ep->bEndpointAddress & USB_DIR_IN)
 978                                         ? DMA_TO_DEVICE
 979                                         : DMA_FROM_DEVICE);
 980                         req->mapped = 1;
 981                 } else {
 982                         dma_sync_single_for_device(
 983                                 ep->udc->gadget.dev.parent,
 984                                 req->req.dma, req->req.length,
 985                                 (ep->bEndpointAddress & USB_DIR_IN)
 986                                         ? DMA_TO_DEVICE
 987                                         : DMA_FROM_DEVICE);
 988                         req->mapped = 0;
 989                 }
 990         }
 991
 992         VDBG("%s queue req %p, len %d buf %p\n",
 993                 ep->ep.name, _req, _req->length, _req->buf);
 994
 995         spin_lock_irqsave(&udc->lock, flags);
 996
 997         req->req.status = -EINPROGRESS;
 998         req->req.actual = 0;
 999
1000         /* maybe kickstart non-iso i/o queues */
1001         if (is_iso)
1002                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1003         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1004                 int     is_in;
1005
1006                 if (ep->bEndpointAddress == 0) {
1007                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1008                                 spin_unlock_irqrestore(&udc->lock, flags);
1009                                 return -EL2HLT;
1010                         }
1011
1012                         /* empty DATA stage? */
1013                         is_in = udc->ep0_in;
1014                         if (!req->req.length) {
1015
1016                                 /* chip became CONFIGURED or ADDRESSED
1017                                  * earlier; drivers may already have queued
1018                                  * requests to non-control endpoints
1019                                  */
1020                                 if (udc->ep0_set_config) {
1021                                         u16     irq_en = UDC_IRQ_EN_REG;
1022
1023                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1024                                         if (!udc->ep0_reset_config)
1025                                                 irq_en |= UDC_EPN_RX_IE
1026                                                         | UDC_EPN_TX_IE;
1027                                         UDC_IRQ_EN_REG = irq_en;
1028                                 }
1029
1030                                 /* STATUS for zero length DATA stages is
1031                                  * always an IN ... even for IN transfers,
1032                                  * a weird case which seem to stall OMAP.
1033                                  */
1034                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1035                                 UDC_CTRL_REG = UDC_CLR_EP;
1036                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1037                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1038
1039                                 /* cleanup */
1040                                 udc->ep0_pending = 0;
1041                                 done(ep, req, 0);
1042                                 req = NULL;
1043
1044                         /* non-empty DATA stage */
1045                         } else if (is_in) {
1046                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1047                         } else {
1048                                 if (udc->ep0_setup)
1049                                         goto irq_wait;
1050                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1051                         }
1052                 } else {
1053                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1054                         if (!ep->has_dma)
1055                                 use_ep(ep, UDC_EP_SEL);
1056                         /* if ISO: SOF IRQs must be enabled/disabled! */
1057                 }
1058
1059                 if (ep->has_dma)
1060                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1061                 else if (req) {
1062                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1063                                 req = NULL;
1064                         deselect_ep();
1065                         if (!is_in) {
1066                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1067                                 ep->ackwait = 1 + ep->double_buf;
1068                         }
1069                         /* IN: 6 wait states before it'll tx */
1070                 }
1071         }
1072
1073 irq_wait:
1074         /* irq handler advances the queue */
1075         if (req != NULL)
1076                 list_add_tail(&req->queue, &ep->queue);
1077         spin_unlock_irqrestore(&udc->lock, flags);
1078
1079         return 0;
1080 }
1081
1082 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1083 {
1084         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1085         struct omap_req *req;
1086         unsigned long   flags;
1087
1088         if (!_ep || !_req)
1089                 return -EINVAL;
1090
1091         spin_lock_irqsave(&ep->udc->lock, flags);
1092
1093         /* make sure it's actually queued on this endpoint */
1094         list_for_each_entry (req, &ep->queue, queue) {
1095                 if (&req->req == _req)
1096                         break;
1097         }
1098         if (&req->req != _req) {
1099                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1100                 return -EINVAL;
1101         }
1102
1103         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1104                 int channel = ep->dma_channel;
1105
1106                 /* releasing the channel cancels the request,
1107                  * reclaiming the channel restarts the queue
1108                  */
1109                 dma_channel_release(ep);
1110                 dma_channel_claim(ep, channel);
1111         } else
1112                 done(ep, req, -ECONNRESET);
1113         spin_unlock_irqrestore(&ep->udc->lock, flags);
1114         return 0;
1115 }
1116
1117 /*-------------------------------------------------------------------------*/
1118
1119 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1120 {
1121         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1122         unsigned long   flags;
1123         int             status = -EOPNOTSUPP;
1124
1125         spin_lock_irqsave(&ep->udc->lock, flags);
1126
1127         /* just use protocol stalls for ep0; real halts are annoying */
1128         if (ep->bEndpointAddress == 0) {
1129                 if (!ep->udc->ep0_pending)
1130                         status = -EINVAL;
1131                 else if (value) {
1132                         if (ep->udc->ep0_set_config) {
1133                                 WARN("error changing config?\n");
1134                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1135                         }
1136                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1137                         ep->udc->ep0_pending = 0;
1138                         status = 0;
1139                 } else /* NOP */
1140                         status = 0;
1141
1142         /* otherwise, all active non-ISO endpoints can halt */
1143         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1144
1145                 /* IN endpoints must already be idle */
1146                 if ((ep->bEndpointAddress & USB_DIR_IN)
1147                                 && !list_empty(&ep->queue)) {
1148                         status = -EAGAIN;
1149                         goto done;
1150                 }
1151
1152                 if (value) {
1153                         int     channel;
1154
1155                         if (use_dma && ep->dma_channel
1156                                         && !list_empty(&ep->queue)) {
1157                                 channel = ep->dma_channel;
1158                                 dma_channel_release(ep);
1159                         } else
1160                                 channel = 0;
1161
1162                         use_ep(ep, UDC_EP_SEL);
1163                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1164                                 UDC_CTRL_REG = UDC_SET_HALT;
1165                                 status = 0;
1166                         } else
1167                                 status = -EAGAIN;
1168                         deselect_ep();
1169
1170                         if (channel)
1171                                 dma_channel_claim(ep, channel);
1172                 } else {
1173                         use_ep(ep, 0);
1174                         UDC_CTRL_REG = ep->udc->clr_halt;
1175                         ep->ackwait = 0;
1176                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1177                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1178                                 ep->ackwait = 1 + ep->double_buf;
1179                         }
1180                 }
1181         }
1182 done:
1183         VDBG("%s %s halt stat %d\n", ep->ep.name,
1184                 value ? "set" : "clear", status);
1185
1186         spin_unlock_irqrestore(&ep->udc->lock, flags);
1187         return status;
1188 }
1189
1190 static struct usb_ep_ops omap_ep_ops = {
1191         .enable         = omap_ep_enable,
1192         .disable        = omap_ep_disable,
1193
1194         .alloc_request  = omap_alloc_request,
1195         .free_request   = omap_free_request,
1196
1197         .queue          = omap_ep_queue,
1198         .dequeue        = omap_ep_dequeue,
1199
1200         .set_halt       = omap_ep_set_halt,
1201         // fifo_status ... report bytes in fifo
1202         // fifo_flush ... flush fifo
1203 };
1204
1205 /*-------------------------------------------------------------------------*/
1206
1207 static int omap_get_frame(struct usb_gadget *gadget)
1208 {
1209         u16     sof = UDC_SOF_REG;
1210         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1211 }
1212
1213 static int omap_wakeup(struct usb_gadget *gadget)
1214 {
1215         struct omap_udc *udc;
1216         unsigned long   flags;
1217         int             retval = -EHOSTUNREACH;
1218
1219         udc = container_of(gadget, struct omap_udc, gadget);
1220
1221         spin_lock_irqsave(&udc->lock, flags);
1222         if (udc->devstat & UDC_SUS) {
1223                 /* NOTE:  OTG spec erratum says that OTG devices may
1224                  * issue wakeups without host enable.
1225                  */
1226                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1227                         DBG("remote wakeup...\n");
1228                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1229                         retval = 0;
1230                 }
1231
1232         /* NOTE:  non-OTG systems may use SRP TOO... */
1233         } else if (!(udc->devstat & UDC_ATT)) {
1234                 if (udc->transceiver)
1235                         retval = otg_start_srp(udc->transceiver);
1236         }
1237         spin_unlock_irqrestore(&udc->lock, flags);
1238
1239         return retval;
1240 }
1241
1242 static int
1243 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1244 {
1245         struct omap_udc *udc;
1246         unsigned long   flags;
1247         u16             syscon1;
1248
1249         udc = container_of(gadget, struct omap_udc, gadget);
1250         spin_lock_irqsave(&udc->lock, flags);
1251         syscon1 = UDC_SYSCON1_REG;
1252         if (is_selfpowered)
1253                 syscon1 |= UDC_SELF_PWR;
1254         else
1255                 syscon1 &= ~UDC_SELF_PWR;
1256         UDC_SYSCON1_REG = syscon1;
1257         spin_unlock_irqrestore(&udc->lock, flags);
1258
1259         return 0;
1260 }
1261
1262 static int can_pullup(struct omap_udc *udc)
1263 {
1264         return udc->driver && udc->softconnect && udc->vbus_active;
1265 }
1266
1267 static void pullup_enable(struct omap_udc *udc)
1268 {
1269         udc->gadget.dev.parent->power.power_state = PMSG_ON;
1270         udc->gadget.dev.power.power_state = PMSG_ON;
1271         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1272         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1273                 OTG_CTRL_REG |= OTG_BSESSVLD;
1274         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1275 }
1276
1277 static void pullup_disable(struct omap_udc *udc)
1278 {
1279         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1280                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1281         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1282         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1283 }
1284
1285 static struct omap_udc *udc;
1286
1287 static void omap_udc_enable_clock(int enable)
1288 {
1289         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1290                 return;
1291
1292         if (enable) {
1293                 clk_enable(udc->dc_clk);
1294                 clk_enable(udc->hhc_clk);
1295                 udelay(100);
1296         } else {
1297                 clk_disable(udc->hhc_clk);
1298                 clk_disable(udc->dc_clk);
1299         }
1300 }
1301
1302 /*
1303  * Called by whatever detects VBUS sessions:  external transceiver
1304  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1305  */
1306 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1307 {
1308         struct omap_udc *udc;
1309         unsigned long   flags;
1310
1311         udc = container_of(gadget, struct omap_udc, gadget);
1312         spin_lock_irqsave(&udc->lock, flags);
1313         VDBG("VBUS %s\n", is_active ? "on" : "off");
1314         udc->vbus_active = (is_active != 0);
1315         if (cpu_is_omap15xx()) {
1316                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1317                 if (is_active)
1318                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1319                 else
1320                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1321         }
1322         if (udc->dc_clk != NULL && is_active) {
1323                 if (!udc->clk_requested) {
1324                         omap_udc_enable_clock(1);
1325                         udc->clk_requested = 1;
1326                 }
1327         }
1328         if (can_pullup(udc))
1329                 pullup_enable(udc);
1330         else
1331                 pullup_disable(udc);
1332         if (udc->dc_clk != NULL && !is_active) {
1333                 if (udc->clk_requested) {
1334                         omap_udc_enable_clock(0);
1335                         udc->clk_requested = 0;
1336                 }
1337         }
1338         spin_unlock_irqrestore(&udc->lock, flags);
1339         return 0;
1340 }
1341
1342 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1343 {
1344         struct omap_udc *udc;
1345
1346         udc = container_of(gadget, struct omap_udc, gadget);
1347         if (udc->transceiver)
1348                 return otg_set_power(udc->transceiver, mA);
1349         return -EOPNOTSUPP;
1350 }
1351
1352 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1353 {
1354         struct omap_udc *udc;
1355         unsigned long   flags;
1356
1357         udc = container_of(gadget, struct omap_udc, gadget);
1358         spin_lock_irqsave(&udc->lock, flags);
1359         udc->softconnect = (is_on != 0);
1360         if (can_pullup(udc))
1361                 pullup_enable(udc);
1362         else
1363                 pullup_disable(udc);
1364         spin_unlock_irqrestore(&udc->lock, flags);
1365         return 0;
1366 }
1367
1368 static struct usb_gadget_ops omap_gadget_ops = {
1369         .get_frame              = omap_get_frame,
1370         .wakeup                 = omap_wakeup,
1371         .set_selfpowered        = omap_set_selfpowered,
1372         .vbus_session           = omap_vbus_session,
1373         .vbus_draw              = omap_vbus_draw,
1374         .pullup                 = omap_pullup,
1375 };
1376
1377 /*-------------------------------------------------------------------------*/
1378
1379 /* dequeue ALL requests; caller holds udc->lock */
1380 static void nuke(struct omap_ep *ep, int status)
1381 {
1382         struct omap_req *req;
1383
1384         ep->stopped = 1;
1385
1386         if (use_dma && ep->dma_channel)
1387                 dma_channel_release(ep);
1388
1389         use_ep(ep, 0);
1390         UDC_CTRL_REG = UDC_CLR_EP;
1391         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1392                 UDC_CTRL_REG = UDC_SET_HALT;
1393
1394         while (!list_empty(&ep->queue)) {
1395                 req = list_entry(ep->queue.next, struct omap_req, queue);
1396                 done(ep, req, status);
1397         }
1398 }
1399
1400 /* caller holds udc->lock */
1401 static void udc_quiesce(struct omap_udc *udc)
1402 {
1403         struct omap_ep  *ep;
1404
1405         udc->gadget.speed = USB_SPEED_UNKNOWN;
1406         nuke(&udc->ep[0], -ESHUTDOWN);
1407         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1408                 nuke(ep, -ESHUTDOWN);
1409 }
1410
1411 /*-------------------------------------------------------------------------*/
1412
1413 static void update_otg(struct omap_udc *udc)
1414 {
1415         u16     devstat;
1416
1417         if (!gadget_is_otg(&udc->gadget))
1418                 return;
1419
1420         if (OTG_CTRL_REG & OTG_ID)
1421                 devstat = UDC_DEVSTAT_REG;
1422         else
1423                 devstat = 0;
1424
1425         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1426         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1427         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1428
1429         /* Enable HNP early, avoiding races on suspend irq path.
1430          * ASSUMES OTG state machine B_BUS_REQ input is true.
1431          */
1432         if (udc->gadget.b_hnp_enable)
1433                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1434                                 & ~OTG_PULLUP;
1435 }
1436
1437 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1438 {
1439         struct omap_ep  *ep0 = &udc->ep[0];
1440         struct omap_req *req = NULL;
1441
1442         ep0->irqs++;
1443
1444         /* Clear any pending requests and then scrub any rx/tx state
1445          * before starting to handle the SETUP request.
1446          */
1447         if (irq_src & UDC_SETUP) {
1448                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1449
1450                 nuke(ep0, 0);
1451                 if (ack) {
1452                         UDC_IRQ_SRC_REG = ack;
1453                         irq_src = UDC_SETUP;
1454                 }
1455         }
1456
1457         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1458          * This driver uses only uses protocol stalls (ep0 never halts),
1459          * and if we got this far the gadget driver already had a
1460          * chance to stall.  Tries to be forgiving of host oddities.
1461          *
1462          * NOTE:  the last chance gadget drivers have to stall control
1463          * requests is during their request completion callback.
1464          */
1465         if (!list_empty(&ep0->queue))
1466                 req = container_of(ep0->queue.next, struct omap_req, queue);
1467
1468         /* IN == TX to host */
1469         if (irq_src & UDC_EP0_TX) {
1470                 int     stat;
1471
1472                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1473                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1474                 stat = UDC_STAT_FLG_REG;
1475                 if (stat & UDC_ACK) {
1476                         if (udc->ep0_in) {
1477                                 /* write next IN packet from response,
1478                                  * or set up the status stage.
1479                                  */
1480                                 if (req)
1481                                         stat = write_fifo(ep0, req);
1482                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1483                                 if (!req && udc->ep0_pending) {
1484                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1485                                         UDC_CTRL_REG = UDC_CLR_EP;
1486                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1487                                         UDC_EP_NUM_REG = 0;
1488                                         udc->ep0_pending = 0;
1489                                 } /* else:  6 wait states before it'll tx */
1490                         } else {
1491                                 /* ack status stage of OUT transfer */
1492                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1493                                 if (req)
1494                                         done(ep0, req, 0);
1495                         }
1496                         req = NULL;
1497                 } else if (stat & UDC_STALL) {
1498                         UDC_CTRL_REG = UDC_CLR_HALT;
1499                         UDC_EP_NUM_REG = UDC_EP_DIR;
1500                 } else {
1501                         UDC_EP_NUM_REG = UDC_EP_DIR;
1502                 }
1503         }
1504
1505         /* OUT == RX from host */
1506         if (irq_src & UDC_EP0_RX) {
1507                 int     stat;
1508
1509                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1510                 UDC_EP_NUM_REG = UDC_EP_SEL;
1511                 stat = UDC_STAT_FLG_REG;
1512                 if (stat & UDC_ACK) {
1513                         if (!udc->ep0_in) {
1514                                 stat = 0;
1515                                 /* read next OUT packet of request, maybe
1516                                  * reactiviting the fifo; stall on errors.
1517                                  */
1518                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1519                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1520                                         udc->ep0_pending = 0;
1521                                         stat = 0;
1522                                 } else if (stat == 0)
1523                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1524                                 UDC_EP_NUM_REG = 0;
1525
1526                                 /* activate status stage */
1527                                 if (stat == 1) {
1528                                         done(ep0, req, 0);
1529                                         /* that may have STALLed ep0... */
1530                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1531                                         UDC_CTRL_REG = UDC_CLR_EP;
1532                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1533                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1534                                         udc->ep0_pending = 0;
1535                                 }
1536                         } else {
1537                                 /* ack status stage of IN transfer */
1538                                 UDC_EP_NUM_REG = 0;
1539                                 if (req)
1540                                         done(ep0, req, 0);
1541                         }
1542                 } else if (stat & UDC_STALL) {
1543                         UDC_CTRL_REG = UDC_CLR_HALT;
1544                         UDC_EP_NUM_REG = 0;
1545                 } else {
1546                         UDC_EP_NUM_REG = 0;
1547                 }
1548         }
1549
1550         /* SETUP starts all control transfers */
1551         if (irq_src & UDC_SETUP) {
1552                 union u {
1553                         u16                     word[4];
1554                         struct usb_ctrlrequest  r;
1555                 } u;
1556                 int                     status = -EINVAL;
1557                 struct omap_ep          *ep;
1558
1559                 /* read the (latest) SETUP message */
1560                 do {
1561                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1562                         /* two bytes at a time */
1563                         u.word[0] = UDC_DATA_REG;
1564                         u.word[1] = UDC_DATA_REG;
1565                         u.word[2] = UDC_DATA_REG;
1566                         u.word[3] = UDC_DATA_REG;
1567                         UDC_EP_NUM_REG = 0;
1568                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1569
1570 #define w_value         le16_to_cpu(u.r.wValue)
1571 #define w_index         le16_to_cpu(u.r.wIndex)
1572 #define w_length        le16_to_cpu(u.r.wLength)
1573
1574                 /* Delegate almost all control requests to the gadget driver,
1575                  * except for a handful of ch9 status/feature requests that
1576                  * hardware doesn't autodecode _and_ the gadget API hides.
1577                  */
1578                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1579                 udc->ep0_set_config = 0;
1580                 udc->ep0_pending = 1;
1581                 ep0->stopped = 0;
1582                 ep0->ackwait = 0;
1583                 switch (u.r.bRequest) {
1584                 case USB_REQ_SET_CONFIGURATION:
1585                         /* udc needs to know when ep != 0 is valid */
1586                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1587                                 goto delegate;
1588                         if (w_length != 0)
1589                                 goto do_stall;
1590                         udc->ep0_set_config = 1;
1591                         udc->ep0_reset_config = (w_value == 0);
1592                         VDBG("set config %d\n", w_value);
1593
1594                         /* update udc NOW since gadget driver may start
1595                          * queueing requests immediately; clear config
1596                          * later if it fails the request.
1597                          */
1598                         if (udc->ep0_reset_config)
1599                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1600                         else
1601                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1602                         update_otg(udc);
1603                         goto delegate;
1604                 case USB_REQ_CLEAR_FEATURE:
1605                         /* clear endpoint halt */
1606                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1607                                 goto delegate;
1608                         if (w_value != USB_ENDPOINT_HALT
1609                                         || w_length != 0)
1610                                 goto do_stall;
1611                         ep = &udc->ep[w_index & 0xf];
1612                         if (ep != ep0) {
1613                                 if (w_index & USB_DIR_IN)
1614                                         ep += 16;
1615                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1616                                                 || !ep->desc)
1617                                         goto do_stall;
1618                                 use_ep(ep, 0);
1619                                 UDC_CTRL_REG = udc->clr_halt;
1620                                 ep->ackwait = 0;
1621                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1622                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1623                                         ep->ackwait = 1 + ep->double_buf;
1624                                 }
1625                                 /* NOTE:  assumes the host behaves sanely,
1626                                  * only clearing real halts.  Else we may
1627                                  * need to kill pending transfers and then
1628                                  * restart the queue... very messy for DMA!
1629                                  */
1630                         }
1631                         VDBG("%s halt cleared by host\n", ep->name);
1632                         goto ep0out_status_stage;
1633                 case USB_REQ_SET_FEATURE:
1634                         /* set endpoint halt */
1635                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1636                                 goto delegate;
1637                         if (w_value != USB_ENDPOINT_HALT
1638                                         || w_length != 0)
1639                                 goto do_stall;
1640                         ep = &udc->ep[w_index & 0xf];
1641                         if (w_index & USB_DIR_IN)
1642                                 ep += 16;
1643                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1644                                         || ep == ep0 || !ep->desc)
1645                                 goto do_stall;
1646                         if (use_dma && ep->has_dma) {
1647                                 /* this has rude side-effects (aborts) and
1648                                  * can't really work if DMA-IN is active
1649                                  */
1650                                 DBG("%s host set_halt, NYET \n", ep->name);
1651                                 goto do_stall;
1652                         }
1653                         use_ep(ep, 0);
1654                         /* can't halt if fifo isn't empty... */
1655                         UDC_CTRL_REG = UDC_CLR_EP;
1656                         UDC_CTRL_REG = UDC_SET_HALT;
1657                         VDBG("%s halted by host\n", ep->name);
1658 ep0out_status_stage:
1659                         status = 0;
1660                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1661                         UDC_CTRL_REG = UDC_CLR_EP;
1662                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1663                         UDC_EP_NUM_REG = UDC_EP_DIR;
1664                         udc->ep0_pending = 0;
1665                         break;
1666                 case USB_REQ_GET_STATUS:
1667                         /* USB_ENDPOINT_HALT status? */
1668                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1669                                 goto intf_status;
1670
1671                         /* ep0 never stalls */
1672                         if (!(w_index & 0xf))
1673                                 goto zero_status;
1674
1675                         /* only active endpoints count */
1676                         ep = &udc->ep[w_index & 0xf];
1677                         if (w_index & USB_DIR_IN)
1678                                 ep += 16;
1679                         if (!ep->desc)
1680                                 goto do_stall;
1681
1682                         /* iso never stalls */
1683                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1684                                 goto zero_status;
1685
1686                         /* FIXME don't assume non-halted endpoints!! */
1687                         ERR("%s status, can't report\n", ep->ep.name);
1688                         goto do_stall;
1689
1690 intf_status:
1691                         /* return interface status.  if we were pedantic,
1692                          * we'd detect non-existent interfaces, and stall.
1693                          */
1694                         if (u.r.bRequestType
1695                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1696                                 goto delegate;
1697
1698 zero_status:
1699                         /* return two zero bytes */
1700                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1701                         UDC_DATA_REG = 0;
1702                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1703                         UDC_EP_NUM_REG = UDC_EP_DIR;
1704                         status = 0;
1705                         VDBG("GET_STATUS, interface %d\n", w_index);
1706                         /* next, status stage */
1707                         break;
1708                 default:
1709 delegate:
1710                         /* activate the ep0out fifo right away */
1711                         if (!udc->ep0_in && w_length) {
1712                                 UDC_EP_NUM_REG = 0;
1713                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1714                         }
1715
1716                         /* gadget drivers see class/vendor specific requests,
1717                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1718                          * and more
1719                          */
1720                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1721                                 u.r.bRequestType, u.r.bRequest,
1722                                 w_value, w_index, w_length);
1723
1724 #undef  w_value
1725 #undef  w_index
1726 #undef  w_length
1727
1728                         /* The gadget driver may return an error here,
1729                          * causing an immediate protocol stall.
1730                          *
1731                          * Else it must issue a response, either queueing a
1732                          * response buffer for the DATA stage, or halting ep0
1733                          * (causing a protocol stall, not a real halt).  A
1734                          * zero length buffer means no DATA stage.
1735                          *
1736                          * It's fine to issue that response after the setup()
1737                          * call returns, and this IRQ was handled.
1738                          */
1739                         udc->ep0_setup = 1;
1740                         spin_unlock(&udc->lock);
1741                         status = udc->driver->setup (&udc->gadget, &u.r);
1742                         spin_lock(&udc->lock);
1743                         udc->ep0_setup = 0;
1744                 }
1745
1746                 if (status < 0) {
1747 do_stall:
1748                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1749                                         u.r.bRequestType, u.r.bRequest, status);
1750                         if (udc->ep0_set_config) {
1751                                 if (udc->ep0_reset_config)
1752                                         WARN("error resetting config?\n");
1753                                 else
1754                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1755                         }
1756                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1757                         udc->ep0_pending = 0;
1758                 }
1759         }
1760 }
1761
1762 /*-------------------------------------------------------------------------*/
1763
1764 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1765
1766 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1767 {
1768         u16     devstat, change;
1769
1770         devstat = UDC_DEVSTAT_REG;
1771         change = devstat ^ udc->devstat;
1772         udc->devstat = devstat;
1773
1774         if (change & (UDC_USB_RESET|UDC_ATT)) {
1775                 udc_quiesce(udc);
1776
1777                 if (change & UDC_ATT) {
1778                         /* driver for any external transceiver will
1779                          * have called omap_vbus_session() already
1780                          */
1781                         if (devstat & UDC_ATT) {
1782                                 udc->gadget.speed = USB_SPEED_FULL;
1783                                 VDBG("connect\n");
1784                                 if (!udc->transceiver)
1785                                         pullup_enable(udc);
1786                                 // if (driver->connect) call it
1787                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1788                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1789                                 if (!udc->transceiver)
1790                                         pullup_disable(udc);
1791                                 DBG("disconnect, gadget %s\n",
1792                                         udc->driver->driver.name);
1793                                 if (udc->driver->disconnect) {
1794                                         spin_unlock(&udc->lock);
1795                                         udc->driver->disconnect(&udc->gadget);
1796                                         spin_lock(&udc->lock);
1797                                 }
1798                         }
1799                         change &= ~UDC_ATT;
1800                 }
1801
1802                 if (change & UDC_USB_RESET) {
1803                         if (devstat & UDC_USB_RESET) {
1804                                 VDBG("RESET=1\n");
1805                         } else {
1806                                 udc->gadget.speed = USB_SPEED_FULL;
1807                                 INFO("USB reset done, gadget %s\n",
1808                                         udc->driver->driver.name);
1809                                 /* ep0 traffic is legal from now on */
1810                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1811                         }
1812                         change &= ~UDC_USB_RESET;
1813                 }
1814         }
1815         if (change & UDC_SUS) {
1816                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1817                         // FIXME tell isp1301 to suspend/resume (?)
1818                         if (devstat & UDC_SUS) {
1819                                 VDBG("suspend\n");
1820                                 update_otg(udc);
1821                                 /* HNP could be under way already */
1822                                 if (udc->gadget.speed == USB_SPEED_FULL
1823                                                 && udc->driver->suspend) {
1824                                         spin_unlock(&udc->lock);
1825                                         udc->driver->suspend(&udc->gadget);
1826                                         spin_lock(&udc->lock);
1827                                 }
1828                                 if (udc->transceiver)
1829                                         otg_set_suspend(udc->transceiver, 1);
1830                         } else {
1831                                 VDBG("resume\n");
1832                                 if (udc->transceiver)
1833                                         otg_set_suspend(udc->transceiver, 0);
1834                                 if (udc->gadget.speed == USB_SPEED_FULL
1835                                                 && udc->driver->resume) {
1836                                         spin_unlock(&udc->lock);
1837                                         udc->driver->resume(&udc->gadget);
1838                                         spin_lock(&udc->lock);
1839                                 }
1840                         }
1841                 }
1842                 change &= ~UDC_SUS;
1843         }
1844         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1845                 update_otg(udc);
1846                 change &= ~OTG_FLAGS;
1847         }
1848
1849         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1850         if (change)
1851                 VDBG("devstat %03x, ignore change %03x\n",
1852                         devstat,  change);
1853
1854         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1855 }
1856
1857 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1858 {
1859         struct omap_udc *udc = _udc;
1860         u16             irq_src;
1861         irqreturn_t     status = IRQ_NONE;
1862         unsigned long   flags;
1863
1864         spin_lock_irqsave(&udc->lock, flags);
1865         irq_src = UDC_IRQ_SRC_REG;
1866
1867         /* Device state change (usb ch9 stuff) */
1868         if (irq_src & UDC_DS_CHG) {
1869                 devstate_irq(_udc, irq_src);
1870                 status = IRQ_HANDLED;
1871                 irq_src &= ~UDC_DS_CHG;
1872         }
1873
1874         /* EP0 control transfers */
1875         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1876                 ep0_irq(_udc, irq_src);
1877                 status = IRQ_HANDLED;
1878                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1879         }
1880
1881         /* DMA transfer completion */
1882         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1883                 dma_irq(_udc, irq_src);
1884                 status = IRQ_HANDLED;
1885                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1886         }
1887
1888         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1889         if (irq_src)
1890                 DBG("udc_irq, unhandled %03x\n", irq_src);
1891         spin_unlock_irqrestore(&udc->lock, flags);
1892
1893         return status;
1894 }
1895
1896 /* workaround for seemingly-lost IRQs for RX ACKs... */
1897 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1898 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1899
1900 static void pio_out_timer(unsigned long _ep)
1901 {
1902         struct omap_ep  *ep = (void *) _ep;
1903         unsigned long   flags;
1904         u16             stat_flg;
1905
1906         spin_lock_irqsave(&ep->udc->lock, flags);
1907         if (!list_empty(&ep->queue) && ep->ackwait) {
1908                 use_ep(ep, UDC_EP_SEL);
1909                 stat_flg = UDC_STAT_FLG_REG;
1910
1911                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1912                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1913                         struct omap_req *req;
1914
1915                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1916                         req = container_of(ep->queue.next,
1917                                         struct omap_req, queue);
1918                         (void) read_fifo(ep, req);
1919                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1920                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1921                         ep->ackwait = 1 + ep->double_buf;
1922                 } else
1923                         deselect_ep();
1924         }
1925         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1926         spin_unlock_irqrestore(&ep->udc->lock, flags);
1927 }
1928
1929 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1930 {
1931         u16             epn_stat, irq_src;
1932         irqreturn_t     status = IRQ_NONE;
1933         struct omap_ep  *ep;
1934         int             epnum;
1935         struct omap_udc *udc = _dev;
1936         struct omap_req *req;
1937         unsigned long   flags;
1938
1939         spin_lock_irqsave(&udc->lock, flags);
1940         epn_stat = UDC_EPN_STAT_REG;
1941         irq_src = UDC_IRQ_SRC_REG;
1942
1943         /* handle OUT first, to avoid some wasteful NAKs */
1944         if (irq_src & UDC_EPN_RX) {
1945                 epnum = (epn_stat >> 8) & 0x0f;
1946                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1947                 status = IRQ_HANDLED;
1948                 ep = &udc->ep[epnum];
1949                 ep->irqs++;
1950
1951                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1952                 ep->fnf = 0;
1953                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1954                         ep->ackwait--;
1955                         if (!list_empty(&ep->queue)) {
1956                                 int stat;
1957                                 req = container_of(ep->queue.next,
1958                                                 struct omap_req, queue);
1959                                 stat = read_fifo(ep, req);
1960                                 if (!ep->double_buf)
1961                                         ep->fnf = 1;
1962                         }
1963                 }
1964                 /* min 6 clock delay before clearing EP_SEL ... */
1965                 epn_stat = UDC_EPN_STAT_REG;
1966                 epn_stat = UDC_EPN_STAT_REG;
1967                 UDC_EP_NUM_REG = epnum;
1968
1969                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1970                  * reduces lossage; timer still needed though (sigh).
1971                  */
1972                 if (ep->fnf) {
1973                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1974                         ep->ackwait = 1 + ep->double_buf;
1975                 }
1976                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1977         }
1978
1979         /* then IN transfers */
1980         else if (irq_src & UDC_EPN_TX) {
1981                 epnum = epn_stat & 0x0f;
1982                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1983                 status = IRQ_HANDLED;
1984                 ep = &udc->ep[16 + epnum];
1985                 ep->irqs++;
1986
1987                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1988                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1989                         ep->ackwait = 0;
1990                         if (!list_empty(&ep->queue)) {
1991                                 req = container_of(ep->queue.next,
1992                                                 struct omap_req, queue);
1993                                 (void) write_fifo(ep, req);
1994                         }
1995                 }
1996                 /* min 6 clock delay before clearing EP_SEL ... */
1997                 epn_stat = UDC_EPN_STAT_REG;
1998                 epn_stat = UDC_EPN_STAT_REG;
1999                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
2000                 /* then 6 clocks before it'd tx */
2001         }
2002
2003         spin_unlock_irqrestore(&udc->lock, flags);
2004         return status;
2005 }
2006
2007 #ifdef  USE_ISO
2008 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2009 {
2010         struct omap_udc *udc = _dev;
2011         struct omap_ep  *ep;
2012         int             pending = 0;
2013         unsigned long   flags;
2014
2015         spin_lock_irqsave(&udc->lock, flags);
2016
2017         /* handle all non-DMA ISO transfers */
2018         list_for_each_entry (ep, &udc->iso, iso) {
2019                 u16             stat;
2020                 struct omap_req *req;
2021
2022                 if (ep->has_dma || list_empty(&ep->queue))
2023                         continue;
2024                 req = list_entry(ep->queue.next, struct omap_req, queue);
2025
2026                 use_ep(ep, UDC_EP_SEL);
2027                 stat = UDC_STAT_FLG_REG;
2028
2029                 /* NOTE: like the other controller drivers, this isn't
2030                  * currently reporting lost or damaged frames.
2031                  */
2032                 if (ep->bEndpointAddress & USB_DIR_IN) {
2033                         if (stat & UDC_MISS_IN)
2034                                 /* done(ep, req, -EPROTO) */;
2035                         else
2036                                 write_fifo(ep, req);
2037                 } else {
2038                         int     status = 0;
2039
2040                         if (stat & UDC_NO_RXPACKET)
2041                                 status = -EREMOTEIO;
2042                         else if (stat & UDC_ISO_ERR)
2043                                 status = -EILSEQ;
2044                         else if (stat & UDC_DATA_FLUSH)
2045                                 status = -ENOSR;
2046
2047                         if (status)
2048                                 /* done(ep, req, status) */;
2049                         else
2050                                 read_fifo(ep, req);
2051                 }
2052                 deselect_ep();
2053                 /* 6 wait states before next EP */
2054
2055                 ep->irqs++;
2056                 if (!list_empty(&ep->queue))
2057                         pending = 1;
2058         }
2059         if (!pending)
2060                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2061         UDC_IRQ_SRC_REG = UDC_SOF;
2062
2063         spin_unlock_irqrestore(&udc->lock, flags);
2064         return IRQ_HANDLED;
2065 }
2066 #endif
2067
2068 /*-------------------------------------------------------------------------*/
2069
2070 static inline int machine_without_vbus_sense(void)
2071 {
2072         return (machine_is_omap_innovator()
2073                 || machine_is_omap_osk()
2074                 || machine_is_omap_apollon()
2075 #ifndef CONFIG_MACH_OMAP_H4_OTG
2076                 || machine_is_omap_h4()
2077 #endif
2078                 || machine_is_sx1()
2079                 );
2080 }
2081
2082 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2083 {
2084         int             status = -ENODEV;
2085         struct omap_ep  *ep;
2086         unsigned long   flags;
2087
2088         /* basic sanity tests */
2089         if (!udc)
2090                 return -ENODEV;
2091         if (!driver
2092                         // FIXME if otg, check:  driver->is_otg
2093                         || driver->speed < USB_SPEED_FULL
2094                         || !driver->bind
2095                         || !driver->setup)
2096                 return -EINVAL;
2097
2098         spin_lock_irqsave(&udc->lock, flags);
2099         if (udc->driver) {
2100                 spin_unlock_irqrestore(&udc->lock, flags);
2101                 return -EBUSY;
2102         }
2103
2104         /* reset state */
2105         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2106                 ep->irqs = 0;
2107                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2108                         continue;
2109                 use_ep(ep, 0);
2110                 UDC_CTRL_REG = UDC_SET_HALT;
2111         }
2112         udc->ep0_pending = 0;
2113         udc->ep[0].irqs = 0;
2114         udc->softconnect = 1;
2115
2116         /* hook up the driver */
2117         driver->driver.bus = NULL;
2118         udc->driver = driver;
2119         udc->gadget.dev.driver = &driver->driver;
2120         spin_unlock_irqrestore(&udc->lock, flags);
2121
2122         if (udc->dc_clk != NULL)
2123                 omap_udc_enable_clock(1);
2124
2125         status = driver->bind (&udc->gadget);
2126         if (status) {
2127                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2128                 udc->gadget.dev.driver = NULL;
2129                 udc->driver = NULL;
2130                 goto done;
2131         }
2132         DBG("bound to driver %s\n", driver->driver.name);
2133
2134         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2135
2136         /* connect to bus through transceiver */
2137         if (udc->transceiver) {
2138                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2139                 if (status < 0) {
2140                         ERR("can't bind to transceiver\n");
2141                         if (driver->unbind) {
2142                                 driver->unbind (&udc->gadget);
2143                                 udc->gadget.dev.driver = NULL;
2144                                 udc->driver = NULL;
2145                         }
2146                         goto done;
2147                 }
2148         } else {
2149                 if (can_pullup(udc))
2150                         pullup_enable (udc);
2151                 else
2152                         pullup_disable (udc);
2153         }
2154
2155         /* boards that don't have VBUS sensing can't autogate 48MHz;
2156          * can't enter deep sleep while a gadget driver is active.
2157          */
2158         if (machine_without_vbus_sense())
2159                 omap_vbus_session(&udc->gadget, 1);
2160
2161 done:
2162         if (udc->dc_clk != NULL)
2163                 omap_udc_enable_clock(0);
2164         return status;
2165 }
2166 EXPORT_SYMBOL(usb_gadget_register_driver);
2167
2168 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2169 {
2170         unsigned long   flags;
2171         int             status = -ENODEV;
2172
2173         if (!udc)
2174                 return -ENODEV;
2175         if (!driver || driver != udc->driver || !driver->unbind)
2176                 return -EINVAL;
2177
2178         if (udc->dc_clk != NULL)
2179                 omap_udc_enable_clock(1);
2180
2181         if (machine_without_vbus_sense())
2182                 omap_vbus_session(&udc->gadget, 0);
2183
2184         if (udc->transceiver)
2185                 (void) otg_set_peripheral(udc->transceiver, NULL);
2186         else
2187                 pullup_disable(udc);
2188
2189         spin_lock_irqsave(&udc->lock, flags);
2190         udc_quiesce(udc);
2191         spin_unlock_irqrestore(&udc->lock, flags);
2192
2193         driver->unbind(&udc->gadget);
2194         udc->gadget.dev.driver = NULL;
2195         udc->driver = NULL;
2196
2197         if (udc->dc_clk != NULL)
2198                 omap_udc_enable_clock(0);
2199         DBG("unregistered driver '%s'\n", driver->driver.name);
2200         return status;
2201 }
2202 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2203
2204
2205 /*-------------------------------------------------------------------------*/
2206
2207 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2208
2209 #include <linux/seq_file.h>
2210
2211 static const char proc_filename[] = "driver/udc";
2212
2213 #define FOURBITS "%s%s%s%s"
2214 #define EIGHTBITS FOURBITS FOURBITS
2215
2216 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2217 {
2218         u16             stat_flg;
2219         struct omap_req *req;
2220         char            buf[20];
2221
2222         use_ep(ep, 0);
2223
2224         if (use_dma && ep->has_dma)
2225                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2226                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2227                         ep->dma_channel - 1, ep->lch);
2228         else
2229                 buf[0] = 0;
2230
2231         stat_flg = UDC_STAT_FLG_REG;
2232         seq_printf(s,
2233                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2234                 ep->name, buf,
2235                 ep->double_buf ? "dbuf " : "",
2236                 ({char *s; switch(ep->ackwait){
2237                 case 0: s = ""; break;
2238                 case 1: s = "(ackw) "; break;
2239                 case 2: s = "(ackw2) "; break;
2240                 default: s = "(?) "; break;
2241                 } s;}),
2242                 ep->irqs, stat_flg,
2243                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2244                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2245                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2246                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2247                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2248                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2249                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2250                 (stat_flg & UDC_STALL) ? "STALL " : "",
2251                 (stat_flg & UDC_NAK) ? "NAK " : "",
2252                 (stat_flg & UDC_ACK) ? "ACK " : "",
2253                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2254                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2255                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2256
2257         if (list_empty (&ep->queue))
2258                 seq_printf(s, "\t(queue empty)\n");
2259         else
2260                 list_for_each_entry (req, &ep->queue, queue) {
2261                         unsigned        length = req->req.actual;
2262
2263                         if (use_dma && buf[0]) {
2264                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2265                                                 ? dma_src_len : dma_dest_len)
2266                                         (ep, req->req.dma + length);
2267                                 buf[0] = 0;
2268                         }
2269                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2270                                         &req->req, length,
2271                                         req->req.length, req->req.buf);
2272                 }
2273 }
2274
2275 static char *trx_mode(unsigned m, int enabled)
2276 {
2277         switch (m) {
2278         case 0:         return enabled ? "*6wire" : "unused";
2279         case 1:         return "4wire";
2280         case 2:         return "3wire";
2281         case 3:         return "6wire";
2282         default:        return "unknown";
2283         }
2284 }
2285
2286 static int proc_otg_show(struct seq_file *s)
2287 {
2288         u32             tmp;
2289         u32             trans;
2290         char            *ctrl_name;
2291
2292         tmp = OTG_REV_REG;
2293         if (cpu_is_omap24xx()) {
2294                 /*
2295                  * REVISIT: Not clear how this works on OMAP2.  trans
2296                  * is ANDed to produce bits 7 and 8, which might make
2297                  * sense for USB_TRANSCEIVER_CTRL_REG on OMAP1,
2298                  * but with CONTROL_DEVCONF, these bits have something to
2299                  * do with the frame adjustment counter and McBSP2.
2300                  */
2301                 ctrl_name = "control_devconf";
2302                 trans = ctrl_read_reg(OMAP2_CONTROL_DEVCONF0);
2303         } else {
2304                 ctrl_name = "tranceiver_ctrl";
2305                 trans = USB_TRANSCEIVER_CTRL_REG;
2306         }
2307         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2308                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2309         tmp = OTG_SYSCON_1_REG;
2310         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2311                         FOURBITS "\n", tmp,
2312                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2313                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2314                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2315                         ? "internal"
2316                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2317                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2318                 (tmp & HST_IDLE_EN) ? " !host" : "",
2319                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2320                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2321         tmp = OTG_SYSCON_2_REG;
2322         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2323                         " b_ase_brst=%d hmc=%d\n", tmp,
2324                 (tmp & OTG_EN) ? " otg_en" : "",
2325                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2326                 // much more SRP stuff
2327                 (tmp & SRP_DATA) ? " srp_data" : "",
2328                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2329                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2330                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2331                 (tmp & UHOST_EN) ? " uhost_en" : "",
2332                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2333                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2334                 B_ASE_BRST(tmp),
2335                 OTG_HMC(tmp));
2336         tmp = OTG_CTRL_REG;
2337         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2338                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2339                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2340                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2341                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2342                 (tmp & OTG_ID) ? " id" : "",
2343                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2344                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2345                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2346                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2347                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2348                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2349                 (tmp & OTG_PULLDOWN) ? " down" : "",
2350                 (tmp & OTG_PULLUP) ? " up" : "",
2351                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2352                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2353                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2354                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2355                 );
2356         tmp = OTG_IRQ_EN_REG;
2357         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2358         tmp = OTG_IRQ_SRC_REG;
2359         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2360         tmp = OTG_OUTCTRL_REG;
2361         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2362         tmp = OTG_TEST_REG;
2363         seq_printf(s, "otg_test    %04x" "\n", tmp);
2364         return 0;
2365 }
2366
2367 static int proc_udc_show(struct seq_file *s, void *_)
2368 {
2369         u32             tmp;
2370         struct omap_ep  *ep;
2371         unsigned long   flags;
2372
2373         spin_lock_irqsave(&udc->lock, flags);
2374
2375         seq_printf(s, "%s, version: " DRIVER_VERSION
2376 #ifdef  USE_ISO
2377                 " (iso)"
2378 #endif
2379                 "%s\n",
2380                 driver_desc,
2381                 use_dma ?  " (dma)" : "");
2382
2383         tmp = UDC_REV_REG & 0xff;
2384         seq_printf(s,
2385                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2386                 "hmc %d, transceiver %s\n",
2387                 tmp >> 4, tmp & 0xf,
2388                 fifo_mode,
2389                 udc->driver ? udc->driver->driver.name : "(none)",
2390                 HMC,
2391                 udc->transceiver
2392                         ? udc->transceiver->label
2393                         : ((cpu_is_omap1710() || cpu_is_omap24xx())
2394                                 ? "external" : "(none)"));
2395         if (cpu_class_is_omap1()) {
2396                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2397                         __REG16(ULPD_CLOCK_CTRL),
2398                         __REG16(ULPD_SOFT_REQ),
2399                         __REG16(ULPD_STATUS_REQ));
2400         }
2401
2402         /* OTG controller registers */
2403         if (!cpu_is_omap15xx())
2404                 proc_otg_show(s);
2405
2406         tmp = UDC_SYSCON1_REG;
2407         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2408                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2409                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2410                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2411                 (tmp & UDC_NAK_EN) ? " nak" : "",
2412                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2413                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2414                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2415                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2416         // syscon2 is write-only
2417
2418         /* UDC controller registers */
2419         if (!(tmp & UDC_PULLUP_EN)) {
2420                 seq_printf(s, "(suspended)\n");
2421                 spin_unlock_irqrestore(&udc->lock, flags);
2422                 return 0;
2423         }
2424
2425         tmp = UDC_DEVSTAT_REG;
2426         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2427                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2428                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2429                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2430                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2431                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2432                 (tmp & UDC_SUS) ? " SUS" : "",
2433                 (tmp & UDC_CFG) ? " CFG" : "",
2434                 (tmp & UDC_ADD) ? " ADD" : "",
2435                 (tmp & UDC_DEF) ? " DEF" : "",
2436                 (tmp & UDC_ATT) ? " ATT" : "");
2437         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2438         tmp = UDC_IRQ_EN_REG;
2439         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2440                 (tmp & UDC_SOF_IE) ? " sof" : "",
2441                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2442                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2443                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2444                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2445         tmp = UDC_IRQ_SRC_REG;
2446         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2447                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2448                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2449                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2450                 (tmp & UDC_SOF) ? " sof" : "",
2451                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2452                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2453                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2454                 (tmp & UDC_SETUP) ? " setup" : "",
2455                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2456                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2457         if (use_dma) {
2458                 unsigned i;
2459
2460                 tmp = UDC_DMA_IRQ_EN_REG;
2461                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2462                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2463                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2464                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2465
2466                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2467                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2468                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2469
2470                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2471                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2472                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2473
2474                 tmp = UDC_RXDMA_CFG_REG;
2475                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2476                 if (tmp) {
2477                         for (i = 0; i < 3; i++) {
2478                                 if ((tmp & (0x0f << (i * 4))) == 0)
2479                                         continue;
2480                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2481                                                 UDC_RXDMA_REG(i + 1));
2482                         }
2483                 }
2484                 tmp = UDC_TXDMA_CFG_REG;
2485                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2486                 if (tmp) {
2487                         for (i = 0; i < 3; i++) {
2488                                 if (!(tmp & (0x0f << (i * 4))))
2489                                         continue;
2490                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2491                                                 UDC_TXDMA_REG(i + 1));
2492                         }
2493                 }
2494         }
2495
2496         tmp = UDC_DEVSTAT_REG;
2497         if (tmp & UDC_ATT) {
2498                 proc_ep_show(s, &udc->ep[0]);
2499                 if (tmp & UDC_ADD) {
2500                         list_for_each_entry (ep, &udc->gadget.ep_list,
2501                                         ep.ep_list) {
2502                                 if (ep->desc)
2503                                         proc_ep_show(s, ep);
2504                         }
2505                 }
2506         }
2507         spin_unlock_irqrestore(&udc->lock, flags);
2508         return 0;
2509 }
2510
2511 static int proc_udc_open(struct inode *inode, struct file *file)
2512 {
2513         return single_open(file, proc_udc_show, NULL);
2514 }
2515
2516 static const struct file_operations proc_ops = {
2517         .open           = proc_udc_open,
2518         .read           = seq_read,
2519         .llseek         = seq_lseek,
2520         .release        = single_release,
2521 };
2522
2523 static void create_proc_file(void)
2524 {
2525         struct proc_dir_entry *pde;
2526
2527         pde = create_proc_entry (proc_filename, 0, NULL);
2528         if (pde)
2529                 pde->proc_fops = &proc_ops;
2530 }
2531
2532 static void remove_proc_file(void)
2533 {
2534         remove_proc_entry(proc_filename, NULL);
2535 }
2536
2537 #else
2538
2539 static inline void create_proc_file(void) {}
2540 static inline void remove_proc_file(void) {}
2541
2542 #endif
2543
2544 /*-------------------------------------------------------------------------*/
2545
2546 /* Before this controller can enumerate, we need to pick an endpoint
2547  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2548  * buffer space among the endpoints we'll be operating.
2549  *
2550  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2551  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2552  * capability yet though.
2553  */
2554 static unsigned __init
2555 omap_ep_setup(char *name, u8 addr, u8 type,
2556                 unsigned buf, unsigned maxp, int dbuf)
2557 {
2558         struct omap_ep  *ep;
2559         u16             epn_rxtx = 0;
2560
2561         /* OUT endpoints first, then IN */
2562         ep = &udc->ep[addr & 0xf];
2563         if (addr & USB_DIR_IN)
2564                 ep += 16;
2565
2566         /* in case of ep init table bugs */
2567         BUG_ON(ep->name[0]);
2568
2569         /* chip setup ... bit values are same for IN, OUT */
2570         if (type == USB_ENDPOINT_XFER_ISOC) {
2571                 switch (maxp) {
2572                 case 8:         epn_rxtx = 0 << 12; break;
2573                 case 16:        epn_rxtx = 1 << 12; break;
2574                 case 32:        epn_rxtx = 2 << 12; break;
2575                 case 64:        epn_rxtx = 3 << 12; break;
2576                 case 128:       epn_rxtx = 4 << 12; break;
2577                 case 256:       epn_rxtx = 5 << 12; break;
2578                 case 512:       epn_rxtx = 6 << 12; break;
2579                 default:        BUG();
2580                 }
2581                 epn_rxtx |= UDC_EPN_RX_ISO;
2582                 dbuf = 1;
2583         } else {
2584                 /* double-buffering "not supported" on 15xx,
2585                  * and ignored for PIO-IN on newer chips
2586                  * (for more reliable behavior)
2587                  */
2588                 if ((!use_dma && (addr & USB_DIR_IN))
2589                                 || machine_is_omap_apollon()
2590                                 || cpu_is_omap15xx())
2591                         dbuf = 0;
2592
2593                 switch (maxp) {
2594                 case 8:         epn_rxtx = 0 << 12; break;
2595                 case 16:        epn_rxtx = 1 << 12; break;
2596                 case 32:        epn_rxtx = 2 << 12; break;
2597                 case 64:        epn_rxtx = 3 << 12; break;
2598                 default:        BUG();
2599                 }
2600                 if (dbuf && addr)
2601                         epn_rxtx |= UDC_EPN_RX_DB;
2602                 init_timer(&ep->timer);
2603                 ep->timer.function = pio_out_timer;
2604                 ep->timer.data = (unsigned long) ep;
2605         }
2606         if (addr)
2607                 epn_rxtx |= UDC_EPN_RX_VALID;
2608         BUG_ON(buf & 0x07);
2609         epn_rxtx |= buf >> 3;
2610
2611         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2612                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2613
2614         if (addr & USB_DIR_IN)
2615                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2616         else
2617                 UDC_EP_RX_REG(addr) = epn_rxtx;
2618
2619         /* next endpoint's buffer starts after this one's */
2620         buf += maxp;
2621         if (dbuf)
2622                 buf += maxp;
2623         BUG_ON(buf > 2048);
2624
2625         /* set up driver data structures */
2626         BUG_ON(strlen(name) >= sizeof ep->name);
2627         strlcpy(ep->name, name, sizeof ep->name);
2628         INIT_LIST_HEAD(&ep->queue);
2629         INIT_LIST_HEAD(&ep->iso);
2630         ep->bEndpointAddress = addr;
2631         ep->bmAttributes = type;
2632         ep->double_buf = dbuf;
2633         ep->udc = udc;
2634
2635         ep->ep.name = ep->name;
2636         ep->ep.ops = &omap_ep_ops;
2637         ep->ep.maxpacket = ep->maxpacket = maxp;
2638         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2639
2640         return buf;
2641 }
2642
2643 static void omap_udc_release(struct device *dev)
2644 {
2645         complete(udc->done);
2646         kfree (udc);
2647         udc = NULL;
2648 }
2649
2650 static int __init
2651 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2652 {
2653         unsigned        tmp, buf;
2654
2655         /* abolish any previous hardware state */
2656         UDC_SYSCON1_REG = 0;
2657         UDC_IRQ_EN_REG = 0;
2658         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2659         UDC_DMA_IRQ_EN_REG = 0;
2660         UDC_RXDMA_CFG_REG = 0;
2661         UDC_TXDMA_CFG_REG = 0;
2662
2663         /* UDC_PULLUP_EN gates the chip clock */
2664         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2665
2666         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2667         if (!udc)
2668                 return -ENOMEM;
2669
2670         spin_lock_init (&udc->lock);
2671
2672         udc->gadget.ops = &omap_gadget_ops;
2673         udc->gadget.ep0 = &udc->ep[0].ep;
2674         INIT_LIST_HEAD(&udc->gadget.ep_list);
2675         INIT_LIST_HEAD(&udc->iso);
2676         udc->gadget.speed = USB_SPEED_UNKNOWN;
2677         udc->gadget.name = driver_name;
2678
2679         device_initialize(&udc->gadget.dev);
2680         strcpy (udc->gadget.dev.bus_id, "gadget");
2681         udc->gadget.dev.release = omap_udc_release;
2682         udc->gadget.dev.parent = &odev->dev;
2683         if (use_dma)
2684                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2685
2686         udc->transceiver = xceiv;
2687
2688         /* ep0 is special; put it right after the SETUP buffer */
2689         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2690                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2691         list_del_init(&udc->ep[0].ep.ep_list);
2692
2693         /* initially disable all non-ep0 endpoints */
2694         for (tmp = 1; tmp < 15; tmp++) {
2695                 UDC_EP_RX_REG(tmp) = 0;
2696                 UDC_EP_TX_REG(tmp) = 0;
2697         }
2698
2699 #define OMAP_BULK_EP(name,addr) \
2700         buf = omap_ep_setup(name "-bulk", addr, \
2701                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2702 #define OMAP_INT_EP(name,addr, maxp) \
2703         buf = omap_ep_setup(name "-int", addr, \
2704                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2705 #define OMAP_ISO_EP(name,addr, maxp) \
2706         buf = omap_ep_setup(name "-iso", addr, \
2707                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2708
2709         switch (fifo_mode) {
2710         case 0:
2711                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2712                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2713                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2714                 break;
2715         case 1:
2716                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2717                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2718                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2719
2720                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2721                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2722                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2723
2724                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2725                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2726                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2727
2728                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2729                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2730                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2731
2732                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2733                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2734                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2735                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2736
2737                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2738                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2739                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2740                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2741
2742                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2743                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2744
2745                 break;
2746
2747 #ifdef  USE_ISO
2748         case 2:                 /* mixed iso/bulk */
2749                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2750                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2751                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2752                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2753
2754                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2755
2756                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2757                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2758                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2759                 break;
2760         case 3:                 /* mixed bulk/iso */
2761                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2762                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2763                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2764
2765                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2766                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2767                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2768
2769                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2770                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2771                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2772                 break;
2773 #endif
2774
2775         /* add more modes as needed */
2776
2777         default:
2778                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2779                 return -ENODEV;
2780         }
2781         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2782         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2783         return 0;
2784 }
2785
2786 static int __init omap_udc_probe(struct platform_device *pdev)
2787 {
2788         int                     status = -ENODEV;
2789         int                     hmc;
2790         struct otg_transceiver  *xceiv = NULL;
2791         const char              *type = NULL;
2792         struct omap_usb_config  *config = pdev->dev.platform_data;
2793         struct clk              *dc_clk;
2794         struct clk              *hhc_clk;
2795
2796         /* NOTE:  "knows" the order of the resources! */
2797         if (!request_mem_region(pdev->resource[0].start,
2798                         pdev->resource[0].end - pdev->resource[0].start + 1,
2799                         driver_name)) {
2800                 DBG("request_mem_region failed\n");
2801                 return -EBUSY;
2802         }
2803
2804         if (cpu_is_omap16xx()) {
2805                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2806                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2807                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2808                 /* can't use omap_udc_enable_clock yet */
2809                 clk_enable(dc_clk);
2810                 clk_enable(hhc_clk);
2811                 udelay(100);
2812         }
2813
2814         if (cpu_is_omap24xx()) {
2815                 dc_clk = clk_get(&pdev->dev, "usb_fck");
2816                 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2817                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2818                 /* can't use omap_udc_enable_clock yet */
2819                 clk_enable(dc_clk);
2820                 clk_enable(hhc_clk);
2821                 udelay(100);
2822         }
2823
2824         INFO("OMAP UDC rev %d.%d%s\n",
2825                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2826                 config->otg ? ", Mini-AB" : "");
2827
2828         /* use the mode given to us by board init code */
2829         if (cpu_is_omap15xx()) {
2830                 hmc = HMC_1510;
2831                 type = "(unknown)";
2832
2833                 if (machine_without_vbus_sense()) {
2834                         /* just set up software VBUS detect, and then
2835                          * later rig it so we always report VBUS.
2836                          * FIXME without really sensing VBUS, we can't
2837                          * know when to turn PULLUP_EN on/off; and that
2838                          * means we always "need" the 48MHz clock.
2839                          */
2840                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2841
2842                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2843                         tmp |= VBUS_MODE_1510;
2844                         tmp &= ~VBUS_CTRL_1510;
2845                         FUNC_MUX_CTRL_0_REG = tmp;
2846                 }
2847         } else {
2848                 /* The transceiver may package some GPIO logic or handle
2849                  * loopback and/or transceiverless setup; if we find one,
2850                  * use it.  Except for OTG, we don't _need_ to talk to one;
2851                  * but not having one probably means no VBUS detection.
2852                  */
2853                 xceiv = otg_get_transceiver();
2854                 if (xceiv)
2855                         type = xceiv->label;
2856                 else if (config->otg) {
2857                         DBG("OTG requires external transceiver!\n");
2858                         goto cleanup0;
2859                 }
2860
2861                 hmc = HMC_1610;
2862
2863                 if (cpu_is_omap24xx()) {
2864                         /* this could be transceiverless in one of the
2865                          * "we don't need to know" modes.
2866                          */
2867                         type = "external";
2868                         goto known;
2869                 }
2870
2871                 switch (hmc) {
2872                 case 0:                 /* POWERUP DEFAULT == 0 */
2873                 case 4:
2874                 case 12:
2875                 case 20:
2876                         if (!cpu_is_omap1710()) {
2877                                 type = "integrated";
2878                                 break;
2879                         }
2880                         /* FALL THROUGH */
2881                 case 3:
2882                 case 11:
2883                 case 16:
2884                 case 19:
2885                 case 25:
2886                         if (!xceiv) {
2887                                 DBG("external transceiver not registered!\n");
2888                                 type = "unknown";
2889                         }
2890                         break;
2891                 case 21:                        /* internal loopback */
2892                         type = "loopback";
2893                         break;
2894                 case 14:                        /* transceiverless */
2895                         if (cpu_is_omap1710())
2896                                 goto bad_on_1710;
2897                         /* FALL THROUGH */
2898                 case 13:
2899                 case 15:
2900                         type = "no";
2901                         break;
2902
2903                 default:
2904 bad_on_1710:
2905                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2906                         goto cleanup0;
2907                 }
2908         }
2909 known:
2910         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2911
2912         /* a "gadget" abstracts/virtualizes the controller */
2913         status = omap_udc_setup(pdev, xceiv);
2914         if (status) {
2915                 goto cleanup0;
2916         }
2917         xceiv = NULL;
2918         // "udc" is now valid
2919         pullup_disable(udc);
2920 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2921         udc->gadget.is_otg = (config->otg != 0);
2922 #endif
2923
2924         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2925         if (UDC_REV_REG >= 0x61)
2926                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2927         else
2928                 udc->clr_halt = UDC_RESET_EP;
2929
2930         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2931         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2932                         IRQF_SAMPLE_RANDOM, driver_name, udc);
2933         if (status != 0) {
2934                 ERR("can't get irq %d, err %d\n",
2935                         (int) pdev->resource[1].start, status);
2936                 goto cleanup1;
2937         }
2938
2939         /* USB "non-iso" IRQ (PIO for all but ep0) */
2940         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2941                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2942         if (status != 0) {
2943                 ERR("can't get irq %d, err %d\n",
2944                         (int) pdev->resource[2].start, status);
2945                 goto cleanup2;
2946         }
2947 #ifdef  USE_ISO
2948         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2949                         IRQF_DISABLED, "omap_udc iso", udc);
2950         if (status != 0) {
2951                 ERR("can't get irq %d, err %d\n",
2952                         (int) pdev->resource[3].start, status);
2953                 goto cleanup3;
2954         }
2955 #endif
2956         if (cpu_is_omap16xx()) {
2957                 udc->dc_clk = dc_clk;
2958                 udc->hhc_clk = hhc_clk;
2959                 clk_disable(hhc_clk);
2960                 clk_disable(dc_clk);
2961         }
2962
2963         if (cpu_is_omap24xx()) {
2964                 udc->dc_clk = dc_clk;
2965                 udc->hhc_clk = hhc_clk;
2966                 /* FIXME OMAP2 don't release hhc & dc clock */
2967 #if 0
2968                 clk_disable(hhc_clk);
2969                 clk_disable(dc_clk);
2970 #endif
2971         }
2972
2973         create_proc_file();
2974         status = device_add(&udc->gadget.dev);
2975         if (!status)
2976                 return status;
2977         /* If fail, fall through */
2978 #ifdef  USE_ISO
2979 cleanup3:
2980         free_irq(pdev->resource[2].start, udc);
2981 #endif
2982
2983 cleanup2:
2984         free_irq(pdev->resource[1].start, udc);
2985
2986 cleanup1:
2987         kfree (udc);
2988         udc = NULL;
2989
2990 cleanup0:
2991         if (xceiv)
2992                 put_device(xceiv->dev);
2993
2994         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
2995                 clk_disable(hhc_clk);
2996                 clk_disable(dc_clk);
2997                 clk_put(hhc_clk);
2998                 clk_put(dc_clk);
2999         }
3000
3001         release_mem_region(pdev->resource[0].start,
3002                         pdev->resource[0].end - pdev->resource[0].start + 1);
3003
3004         return status;
3005 }
3006
3007 static int __exit omap_udc_remove(struct platform_device *pdev)
3008 {
3009         DECLARE_COMPLETION_ONSTACK(done);
3010
3011         if (!udc)
3012                 return -ENODEV;
3013         if (udc->driver)
3014                 return -EBUSY;
3015
3016         udc->done = &done;
3017
3018         pullup_disable(udc);
3019         if (udc->transceiver) {
3020                 put_device(udc->transceiver->dev);
3021                 udc->transceiver = NULL;
3022         }
3023         UDC_SYSCON1_REG = 0;
3024
3025         remove_proc_file();
3026
3027 #ifdef  USE_ISO
3028         free_irq(pdev->resource[3].start, udc);
3029 #endif
3030         free_irq(pdev->resource[2].start, udc);
3031         free_irq(pdev->resource[1].start, udc);
3032
3033         if (udc->dc_clk) {
3034                 if (udc->clk_requested)
3035                         omap_udc_enable_clock(0);
3036                 clk_put(udc->hhc_clk);
3037                 clk_put(udc->dc_clk);
3038         }
3039
3040         release_mem_region(pdev->resource[0].start,
3041                         pdev->resource[0].end - pdev->resource[0].start + 1);
3042
3043         device_unregister(&udc->gadget.dev);
3044         wait_for_completion(&done);
3045
3046         return 0;
3047 }
3048
3049 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3050  * system is forced into deep sleep
3051  *
3052  * REVISIT we should probably reject suspend requests when there's a host
3053  * session active, rather than disconnecting, at least on boards that can
3054  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
3055  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3056  * may involve talking to an external transceiver (e.g. isp1301).
3057  */
3058
3059 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3060 {
3061         u32     devstat;
3062
3063         devstat = UDC_DEVSTAT_REG;
3064
3065         /* we're requesting 48 MHz clock if the pullup is enabled
3066          * (== we're attached to the host) and we're not suspended,
3067          * which would prevent entry to deep sleep...
3068          */
3069         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3070                 WARN("session active; suspend requires disconnect\n");
3071                 omap_pullup(&udc->gadget, 0);
3072         }
3073
3074         udc->gadget.dev.power.power_state = PMSG_SUSPEND;
3075         udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
3076         return 0;
3077 }
3078
3079 static int omap_udc_resume(struct platform_device *dev)
3080 {
3081         DBG("resume + wakeup/SRP\n");
3082         omap_pullup(&udc->gadget, 1);
3083
3084         /* maybe the host would enumerate us if we nudged it */
3085         msleep(100);
3086         return omap_wakeup(&udc->gadget);
3087 }
3088
3089 /*-------------------------------------------------------------------------*/
3090
3091 static struct platform_driver udc_driver = {
3092         .probe          = omap_udc_probe,
3093         .remove         = __exit_p(omap_udc_remove),
3094         .suspend        = omap_udc_suspend,
3095         .resume         = omap_udc_resume,
3096         .driver         = {
3097                 .owner  = THIS_MODULE,
3098                 .name   = (char *) driver_name,
3099         },
3100 };
3101
3102 static int __init udc_init(void)
3103 {
3104         INFO("%s, version: " DRIVER_VERSION
3105 #ifdef  USE_ISO
3106                 " (iso)"
3107 #endif
3108                 "%s\n", driver_desc,
3109                 use_dma ?  " (dma)" : "");
3110         return platform_driver_register(&udc_driver);
3111 }
3112 module_init(udc_init);
3113
3114 static void __exit udc_exit(void)
3115 {
3116         platform_driver_unregister(&udc_driver);
3117 }
3118 module_exit(udc_exit);
3119
3120 MODULE_DESCRIPTION(DRIVER_DESC);
3121 MODULE_LICENSE("GPL");
3122