drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #undef  DEBUG
  23 #undef  VERBOSE
  24
  25 #include <linux/config.h>
  26 #include <linux/module.h>
  27 #include <linux/kernel.h>
  28 #include <linux/ioport.h>
  29 #include <linux/types.h>
  30 #include <linux/errno.h>
  31 #include <linux/delay.h>
  32 #include <linux/sched.h>
  33 #include <linux/slab.h>
  34 #include <linux/init.h>
  35 #include <linux/timer.h>
  36 #include <linux/list.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/proc_fs.h>
  39 #include <linux/mm.h>
  40 #include <linux/moduleparam.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/usb_ch9.h>
  43 #include <linux/usb_gadget.h>
  44 #include <linux/usb_otg.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/clk.h>
  47
  48 #include <asm/byteorder.h>
  49 #include <asm/io.h>
  50 #include <asm/irq.h>
  51 #include <asm/system.h>
  52 #include <asm/unaligned.h>
  53 #include <asm/mach-types.h>
  54
  55 #include <asm/arch/dma.h>
  56 #include <asm/arch/usb.h>
  57
  58 #include "omap_udc.h"
  59
  60 #undef  USB_TRACE
  61
  62 /* bulk DMA seems to be behaving for both IN and OUT */
  63 #define USE_DMA
  64
  65 /* ISO too */
  66 #define USE_ISO
  67
  68 #define DRIVER_DESC     "OMAP UDC driver"
  69 #define DRIVER_VERSION  "4 October 2004"
  70
  71 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  72
  73
  74 /*
  75  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  76  * D+ pullup to allow enumeration.  That's too early for the gadget
  77  * framework to use from usb_endpoint_enable(), which happens after
  78  * enumeration as part of activating an interface.  (But if we add an
  79  * optional new "UDC not yet running" state to the gadget driver model,
  80  * even just during driver binding, the endpoint autoconfig logic is the
  81  * natural spot to manufacture new endpoints.)
  82  *
  83  * So instead of using endpoint enable calls to control the hardware setup,
  84  * this driver defines a "fifo mode" parameter.  It's used during driver
  85  * initialization to choose among a set of pre-defined endpoint configs.
  86  * See omap_udc_setup() for available modes, or to add others.  That code
  87  * lives in an init section, so use this driver as a module if you need
  88  * to change the fifo mode after the kernel boots.
  89  *
  90  * Gadget drivers normally ignore endpoints they don't care about, and
  91  * won't include them in configuration descriptors.  That means only
  92  * misbehaving hosts would even notice they exist.
  93  */
  94 #ifdef  USE_ISO
  95 static unsigned fifo_mode = 3;
  96 #else
  97 static unsigned fifo_mode = 0;
  98 #endif
  99
 100 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 101  * boot parameter "omap_udc:fifo_mode=42"
 102  */
 103 module_param (fifo_mode, uint, 0);
 104 MODULE_PARM_DESC (fifo_mode, "endpoint setup (0 == default)");
 105
 106 #ifdef  USE_DMA
 107 static unsigned use_dma = 1;
 108
 109 /* "modprobe omap_udc use_dma=y", or else as a kernel
 110  * boot parameter "omap_udc:use_dma=y"
 111  */
 112 module_param (use_dma, bool, 0);
 113 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 114 #else   /* !USE_DMA */
 115
 116 /* save a bit of code */
 117 #define use_dma         0
 118 #endif  /* !USE_DMA */
 119
 120
 121 static const char driver_name [] = "omap_udc";
 122 static const char driver_desc [] = DRIVER_DESC;
 123
 124 /*-------------------------------------------------------------------------*/
 125
 126 /* there's a notion of "current endpoint" for modifying endpoint
 127  * state, and PIO access to its FIFO.
 128  */
 129
 130 static void use_ep(struct omap_ep *ep, u16 select)
 131 {
 132         u16     num = ep->bEndpointAddress & 0x0f;
 133
 134         if (ep->bEndpointAddress & USB_DIR_IN)
 135                 num |= UDC_EP_DIR;
 136         UDC_EP_NUM_REG = num | select;
 137         /* when select, MUST deselect later !! */
 138 }
 139
 140 static inline void deselect_ep(void)
 141 {
 142         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
 143         /* 6 wait states before TX will happen */
 144 }
 145
 146 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 147
 148 /*-------------------------------------------------------------------------*/
 149
 150 static int omap_ep_enable(struct usb_ep *_ep,
 151                 const struct usb_endpoint_descriptor *desc)
 152 {
 153         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 154         struct omap_udc *udc;
 155         unsigned long   flags;
 156         u16             maxp;
 157
 158         /* catch various bogus parameters */
 159         if (!_ep || !desc || ep->desc
 160                         || desc->bDescriptorType != USB_DT_ENDPOINT
 161                         || ep->bEndpointAddress != desc->bEndpointAddress
 162                         || ep->maxpacket < le16_to_cpu
 163                                                 (desc->wMaxPacketSize)) {
 164                 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
 165                 return -EINVAL;
 166         }
 167         maxp = le16_to_cpu (desc->wMaxPacketSize);
 168         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 169                                 && maxp != ep->maxpacket)
 170                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 171                         || !desc->wMaxPacketSize) {
 172                 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 173                 return -ERANGE;
 174         }
 175
 176 #ifdef  USE_ISO
 177         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 178                                 && desc->bInterval != 1)) {
 179                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 180                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 181                                 1 << (desc->bInterval - 1));
 182                 return -EDOM;
 183         }
 184 #else
 185         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 186                 DBG("%s, ISO nyet\n", _ep->name);
 187                 return -EDOM;
 188         }
 189 #endif
 190
 191         /* xfer types must match, except that interrupt ~= bulk */
 192         if (ep->bmAttributes != desc->bmAttributes
 193                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 194                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 195                 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 196                 return -EINVAL;
 197         }
 198
 199         udc = ep->udc;
 200         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 201                 DBG("%s, bogus device state\n", __FUNCTION__);
 202                 return -ESHUTDOWN;
 203         }
 204
 205         spin_lock_irqsave(&udc->lock, flags);
 206
 207         ep->desc = desc;
 208         ep->irqs = 0;
 209         ep->stopped = 0;
 210         ep->ep.maxpacket = maxp;
 211
 212         /* set endpoint to initial state */
 213         ep->dma_channel = 0;
 214         ep->has_dma = 0;
 215         ep->lch = -1;
 216         use_ep(ep, UDC_EP_SEL);
 217         UDC_CTRL_REG = udc->clr_halt;
 218         ep->ackwait = 0;
 219         deselect_ep();
 220
 221         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 222                 list_add(&ep->iso, &udc->iso);
 223
 224         /* maybe assign a DMA channel to this endpoint */
 225         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 226                 /* FIXME ISO can dma, but prefers first channel */
 227                 dma_channel_claim(ep, 0);
 228
 229         /* PIO OUT may RX packets */
 230         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 231                         && !ep->has_dma
 232                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 233                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 234                 ep->ackwait = 1 + ep->double_buf;
 235         }
 236
 237         spin_unlock_irqrestore(&udc->lock, flags);
 238         VDBG("%s enabled\n", _ep->name);
 239         return 0;
 240 }
 241
 242 static void nuke(struct omap_ep *, int status);
 243
 244 static int omap_ep_disable(struct usb_ep *_ep)
 245 {
 246         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 247         unsigned long   flags;
 248
 249         if (!_ep || !ep->desc) {
 250                 DBG("%s, %s not enabled\n", __FUNCTION__,
 251                         _ep ? ep->ep.name : NULL);
 252                 return -EINVAL;
 253         }
 254
 255         spin_lock_irqsave(&ep->udc->lock, flags);
 256         ep->desc = NULL;
 257         nuke (ep, -ESHUTDOWN);
 258         ep->ep.maxpacket = ep->maxpacket;
 259         ep->has_dma = 0;
 260         UDC_CTRL_REG = UDC_SET_HALT;
 261         list_del_init(&ep->iso);
 262         del_timer(&ep->timer);
 263
 264         spin_unlock_irqrestore(&ep->udc->lock, flags);
 265
 266         VDBG("%s disabled\n", _ep->name);
 267         return 0;
 268 }
 269
 270 /*-------------------------------------------------------------------------*/
 271
 272 static struct usb_request *
 273 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 274 {
 275         struct omap_req *req;
 276
 277         req = kzalloc(sizeof(*req), gfp_flags);
 278         if (req) {
 279                 req->req.dma = DMA_ADDR_INVALID;
 280                 INIT_LIST_HEAD (&req->queue);
 281         }
 282         return &req->req;
 283 }
 284
 285 static void
 286 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 287 {
 288         struct omap_req *req = container_of(_req, struct omap_req, req);
 289
 290         if (_req)
 291                 kfree (req);
 292 }
 293
 294 /*-------------------------------------------------------------------------*/
 295
 296 static void *
 297 omap_alloc_buffer(
 298         struct usb_ep   *_ep,
 299         unsigned        bytes,
 300         dma_addr_t      *dma,
 301         gfp_t           gfp_flags
 302 )
 303 {
 304         void            *retval;
 305         struct omap_ep  *ep;
 306
 307         ep = container_of(_ep, struct omap_ep, ep);
 308         if (use_dma && ep->has_dma) {
 309                 static int      warned;
 310                 if (!warned && bytes < PAGE_SIZE) {
 311                         dev_warn(ep->udc->gadget.dev.parent,
 312                                 "using dma_alloc_coherent for "
 313                                 "small allocations wastes memory\n");
 314                         warned++;
 315                 }
 316                 return dma_alloc_coherent(ep->udc->gadget.dev.parent,
 317                                 bytes, dma, gfp_flags);
 318         }
 319
 320         retval = kmalloc(bytes, gfp_flags);
 321         if (retval)
 322                 *dma = virt_to_phys(retval);
 323         return retval;
 324 }
 325
 326 static void omap_free_buffer(
 327         struct usb_ep   *_ep,
 328         void            *buf,
 329         dma_addr_t      dma,
 330         unsigned        bytes
 331 )
 332 {
 333         struct omap_ep  *ep;
 334
 335         ep = container_of(_ep, struct omap_ep, ep);
 336         if (use_dma && _ep && ep->has_dma)
 337                 dma_free_coherent(ep->udc->gadget.dev.parent, bytes, buf, dma);
 338         else
 339                 kfree (buf);
 340 }
 341
 342 /*-------------------------------------------------------------------------*/
 343
 344 static void
 345 done(struct omap_ep *ep, struct omap_req *req, int status)
 346 {
 347         unsigned                stopped = ep->stopped;
 348
 349         list_del_init(&req->queue);
 350
 351         if (req->req.status == -EINPROGRESS)
 352                 req->req.status = status;
 353         else
 354                 status = req->req.status;
 355
 356         if (use_dma && ep->has_dma) {
 357                 if (req->mapped) {
 358                         dma_unmap_single(ep->udc->gadget.dev.parent,
 359                                 req->req.dma, req->req.length,
 360                                 (ep->bEndpointAddress & USB_DIR_IN)
 361                                         ? DMA_TO_DEVICE
 362                                         : DMA_FROM_DEVICE);
 363                         req->req.dma = DMA_ADDR_INVALID;
 364                         req->mapped = 0;
 365                 } else
 366                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 367                                 req->req.dma, req->req.length,
 368                                 (ep->bEndpointAddress & USB_DIR_IN)
 369                                         ? DMA_TO_DEVICE
 370                                         : DMA_FROM_DEVICE);
 371         }
 372
 373 #ifndef USB_TRACE
 374         if (status && status != -ESHUTDOWN)
 375 #endif
 376                 VDBG("complete %s req %p stat %d len %u/%u\n",
 377                         ep->ep.name, &req->req, status,
 378                         req->req.actual, req->req.length);
 379
 380         /* don't modify queue heads during completion callback */
 381         ep->stopped = 1;
 382         spin_unlock(&ep->udc->lock);
 383         req->req.complete(&ep->ep, &req->req);
 384         spin_lock(&ep->udc->lock);
 385         ep->stopped = stopped;
 386 }
 387
 388 /*-------------------------------------------------------------------------*/
 389
 390 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 391 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 392
 393 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 394 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 395
 396 static inline int
 397 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 398 {
 399         unsigned        len;
 400         u16             *wp;
 401
 402         len = min(req->req.length - req->req.actual, max);
 403         req->req.actual += len;
 404
 405         max = len;
 406         if (likely((((int)buf) & 1) == 0)) {
 407                 wp = (u16 *)buf;
 408                 while (max >= 2) {
 409                         UDC_DATA_REG = *wp++;
 410                         max -= 2;
 411                 }
 412                 buf = (u8 *)wp;
 413         }
 414         while (max--)
 415                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
 416         return len;
 417 }
 418
 419 // FIXME change r/w fifo calling convention
 420
 421
 422 // return:  0 = still running, 1 = completed, negative = errno
 423 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 424 {
 425         u8              *buf;
 426         unsigned        count;
 427         int             is_last;
 428         u16             ep_stat;
 429
 430         buf = req->req.buf + req->req.actual;
 431         prefetch(buf);
 432
 433         /* PIO-IN isn't double buffered except for iso */
 434         ep_stat = UDC_STAT_FLG_REG;
 435         if (ep_stat & UDC_FIFO_UNWRITABLE)
 436                 return 0;
 437
 438         count = ep->ep.maxpacket;
 439         count = write_packet(buf, req, count);
 440         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 441         ep->ackwait = 1;
 442
 443         /* last packet is often short (sometimes a zlp) */
 444         if (count != ep->ep.maxpacket)
 445                 is_last = 1;
 446         else if (req->req.length == req->req.actual
 447                         && !req->req.zero)
 448                 is_last = 1;
 449         else
 450                 is_last = 0;
 451
 452         /* NOTE:  requests complete when all IN data is in a
 453          * FIFO (or sometimes later, if a zlp was needed).
 454          * Use usb_ep_fifo_status() where needed.
 455          */
 456         if (is_last)
 457                 done(ep, req, 0);
 458         return is_last;
 459 }
 460
 461 static inline int
 462 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 463 {
 464         unsigned        len;
 465         u16             *wp;
 466
 467         len = min(req->req.length - req->req.actual, avail);
 468         req->req.actual += len;
 469         avail = len;
 470
 471         if (likely((((int)buf) & 1) == 0)) {
 472                 wp = (u16 *)buf;
 473                 while (avail >= 2) {
 474                         *wp++ = UDC_DATA_REG;
 475                         avail -= 2;
 476                 }
 477                 buf = (u8 *)wp;
 478         }
 479         while (avail--)
 480                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
 481         return len;
 482 }
 483
 484 // return:  0 = still running, 1 = queue empty, negative = errno
 485 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 486 {
 487         u8              *buf;
 488         unsigned        count, avail;
 489         int             is_last;
 490
 491         buf = req->req.buf + req->req.actual;
 492         prefetchw(buf);
 493
 494         for (;;) {
 495                 u16     ep_stat = UDC_STAT_FLG_REG;
 496
 497                 is_last = 0;
 498                 if (ep_stat & FIFO_EMPTY) {
 499                         if (!ep->double_buf)
 500                                 break;
 501                         ep->fnf = 1;
 502                 }
 503                 if (ep_stat & UDC_EP_HALTED)
 504                         break;
 505
 506                 if (ep_stat & UDC_FIFO_FULL)
 507                         avail = ep->ep.maxpacket;
 508                 else  {
 509                         avail = UDC_RXFSTAT_REG;
 510                         ep->fnf = ep->double_buf;
 511                 }
 512                 count = read_packet(buf, req, avail);
 513
 514                 /* partial packet reads may not be errors */
 515                 if (count < ep->ep.maxpacket) {
 516                         is_last = 1;
 517                         /* overflowed this request?  flush extra data */
 518                         if (count != avail) {
 519                                 req->req.status = -EOVERFLOW;
 520                                 avail -= count;
 521                                 while (avail--)
 522                                         (void) *(volatile u8 *)&UDC_DATA_REG;
 523                         }
 524                 } else if (req->req.length == req->req.actual)
 525                         is_last = 1;
 526                 else
 527                         is_last = 0;
 528
 529                 if (!ep->bEndpointAddress)
 530                         break;
 531                 if (is_last)
 532                         done(ep, req, 0);
 533                 break;
 534         }
 535         return is_last;
 536 }
 537
 538 /*-------------------------------------------------------------------------*/
 539
 540 static inline dma_addr_t dma_csac(unsigned lch)
 541 {
 542         dma_addr_t      csac;
 543
 544         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 545          * read before the DMA controller finished disabling the channel.
 546          */
 547         csac = OMAP_DMA_CSAC_REG(lch);
 548         if (csac == 0)
 549                 csac = OMAP_DMA_CSAC_REG(lch);
 550         return csac;
 551 }
 552
 553 static inline dma_addr_t dma_cdac(unsigned lch)
 554 {
 555         dma_addr_t      cdac;
 556
 557         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 558          * read before the DMA controller finished disabling the channel.
 559          */
 560         cdac = OMAP_DMA_CDAC_REG(lch);
 561         if (cdac == 0)
 562                 cdac = OMAP_DMA_CDAC_REG(lch);
 563         return cdac;
 564 }
 565
 566 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 567 {
 568         dma_addr_t      end;
 569
 570         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 571          * the last transfer's bytecount by more than a FIFO's worth.
 572          */
 573         if (cpu_is_omap15xx())
 574                 return 0;
 575
 576         end = dma_csac(ep->lch);
 577         if (end == ep->dma_counter)
 578                 return 0;
 579
 580         end |= start & (0xffff << 16);
 581         if (end < start)
 582                 end += 0x10000;
 583         return end - start;
 584 }
 585
 586 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
 587                 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
 588                 : dma_cdac(x))
 589
 590 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 591 {
 592         dma_addr_t      end;
 593
 594         end = DMA_DEST_LAST(ep->lch);
 595         if (end == ep->dma_counter)
 596                 return 0;
 597
 598         end |= start & (0xffff << 16);
 599         if (cpu_is_omap15xx())
 600                 end++;
 601         if (end < start)
 602                 end += 0x10000;
 603         return end - start;
 604 }
 605
 606
 607 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 608  * When DMA completion isn't request completion, the UDC continues with
 609  * the next DMA transfer for that USB transfer.
 610  */
 611
 612 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 613 {
 614         u16             txdma_ctrl;
 615         unsigned        length = req->req.length - req->req.actual;
 616         const int       sync_mode = cpu_is_omap15xx()
 617                                 ? OMAP_DMA_SYNC_FRAME
 618                                 : OMAP_DMA_SYNC_ELEMENT;
 619
 620         /* measure length in either bytes or packets */
 621         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 622                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 623                 txdma_ctrl = UDC_TXN_EOT | length;
 624                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 625                                 length, 1, sync_mode, 0, 0);
 626         } else {
 627                 length = min(length / ep->maxpacket,
 628                                 (unsigned) UDC_TXN_TSC + 1);
 629                 txdma_ctrl = length;
 630                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 631                                 ep->ep.maxpacket >> 1, length, sync_mode,
 632                                 0, 0);
 633                 length *= ep->maxpacket;
 634         }
 635         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 636                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 637                 0, 0);
 638
 639         omap_start_dma(ep->lch);
 640         ep->dma_counter = dma_csac(ep->lch);
 641         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
 642         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
 643         req->dma_bytes = length;
 644 }
 645
 646 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 647 {
 648         if (status == 0) {
 649                 req->req.actual += req->dma_bytes;
 650
 651                 /* return if this request needs to send data or zlp */
 652                 if (req->req.actual < req->req.length)
 653                         return;
 654                 if (req->req.zero
 655                                 && req->dma_bytes != 0
 656                                 && (req->req.actual % ep->maxpacket) == 0)
 657                         return;
 658         } else
 659                 req->req.actual += dma_src_len(ep, req->req.dma
 660                                                         + req->req.actual);
 661
 662         /* tx completion */
 663         omap_stop_dma(ep->lch);
 664         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
 665         done(ep, req, status);
 666 }
 667
 668 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 669 {
 670         unsigned packets;
 671
 672         /* NOTE:  we filtered out "short reads" before, so we know
 673          * the buffer has only whole numbers of packets.
 674          */
 675
 676         /* set up this DMA transfer, enable the fifo, start */
 677         packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
 678         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 679         req->dma_bytes = packets * ep->ep.maxpacket;
 680         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 681                         ep->ep.maxpacket >> 1, packets,
 682                         OMAP_DMA_SYNC_ELEMENT,
 683                         0, 0);
 684         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 685                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 686                 0, 0);
 687         ep->dma_counter = DMA_DEST_LAST(ep->lch);
 688
 689         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
 690         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
 691         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
 692         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 693
 694         omap_start_dma(ep->lch);
 695 }
 696
 697 static void
 698 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 699 {
 700         u16     count;
 701
 702         if (status == 0)
 703                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 704         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 705         count += req->req.actual;
 706         if (one)
 707                 count--;
 708         if (count <= req->req.length)
 709                 req->req.actual = count;
 710
 711         if (count != req->dma_bytes || status)
 712                 omap_stop_dma(ep->lch);
 713
 714         /* if this wasn't short, request may need another transfer */
 715         else if (req->req.actual < req->req.length)
 716                 return;
 717
 718         /* rx completion */
 719         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
 720         done(ep, req, status);
 721 }
 722
 723 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 724 {
 725         u16             dman_stat = UDC_DMAN_STAT_REG;
 726         struct omap_ep  *ep;
 727         struct omap_req *req;
 728
 729         /* IN dma: tx to host */
 730         if (irq_src & UDC_TXN_DONE) {
 731                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 732                 ep->irqs++;
 733                 /* can see TXN_DONE after dma abort */
 734                 if (!list_empty(&ep->queue)) {
 735                         req = container_of(ep->queue.next,
 736                                                 struct omap_req, queue);
 737                         finish_in_dma(ep, req, 0);
 738                 }
 739                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
 740
 741                 if (!list_empty (&ep->queue)) {
 742                         req = container_of(ep->queue.next,
 743                                         struct omap_req, queue);
 744                         next_in_dma(ep, req);
 745                 }
 746         }
 747
 748         /* OUT dma: rx from host */
 749         if (irq_src & UDC_RXN_EOT) {
 750                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 751                 ep->irqs++;
 752                 /* can see RXN_EOT after dma abort */
 753                 if (!list_empty(&ep->queue)) {
 754                         req = container_of(ep->queue.next,
 755                                         struct omap_req, queue);
 756                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 757                 }
 758                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
 759
 760                 if (!list_empty (&ep->queue)) {
 761                         req = container_of(ep->queue.next,
 762                                         struct omap_req, queue);
 763                         next_out_dma(ep, req);
 764                 }
 765         }
 766
 767         if (irq_src & UDC_RXN_CNT) {
 768                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 769                 ep->irqs++;
 770                 /* omap15xx does this unasked... */
 771                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 772                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
 773         }
 774 }
 775
 776 static void dma_error(int lch, u16 ch_status, void *data)
 777 {
 778         struct omap_ep  *ep = data;
 779
 780         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 781         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 782         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 783
 784         /* complete current transfer ... */
 785 }
 786
 787 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 788 {
 789         u16     reg;
 790         int     status, restart, is_in;
 791
 792         is_in = ep->bEndpointAddress & USB_DIR_IN;
 793         if (is_in)
 794                 reg = UDC_TXDMA_CFG_REG;
 795         else
 796                 reg = UDC_RXDMA_CFG_REG;
 797         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 798
 799         ep->dma_channel = 0;
 800         ep->lch = -1;
 801         if (channel == 0 || channel > 3) {
 802                 if ((reg & 0x0f00) == 0)
 803                         channel = 3;
 804                 else if ((reg & 0x00f0) == 0)
 805                         channel = 2;
 806                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 807                         channel = 1;
 808                 else {
 809                         status = -EMLINK;
 810                         goto just_restart;
 811                 }
 812         }
 813         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 814         ep->dma_channel = channel;
 815
 816         if (is_in) {
 817                 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
 818                         ep->ep.name, dma_error, ep, &ep->lch);
 819                 if (status == 0) {
 820                         UDC_TXDMA_CFG_REG = reg;
 821                         /* EMIFF */
 822                         omap_set_dma_src_burst_mode(ep->lch,
 823                                                 OMAP_DMA_DATA_BURST_4);
 824                         omap_set_dma_src_data_pack(ep->lch, 1);
 825                         /* TIPB */
 826                         omap_set_dma_dest_params(ep->lch,
 827                                 OMAP_DMA_PORT_TIPB,
 828                                 OMAP_DMA_AMODE_CONSTANT,
 829                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 830                                 0, 0);
 831                 }
 832         } else {
 833                 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
 834                         ep->ep.name, dma_error, ep, &ep->lch);
 835                 if (status == 0) {
 836                         UDC_RXDMA_CFG_REG = reg;
 837                         /* TIPB */
 838                         omap_set_dma_src_params(ep->lch,
 839                                 OMAP_DMA_PORT_TIPB,
 840                                 OMAP_DMA_AMODE_CONSTANT,
 841                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 842                                 0, 0);
 843                         /* EMIFF */
 844                         omap_set_dma_dest_burst_mode(ep->lch,
 845                                                 OMAP_DMA_DATA_BURST_4);
 846                         omap_set_dma_dest_data_pack(ep->lch, 1);
 847                 }
 848         }
 849         if (status)
 850                 ep->dma_channel = 0;
 851         else {
 852                 ep->has_dma = 1;
 853                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 854
 855                 /* channel type P: hw synch (fifo) */
 856                 if (!cpu_is_omap15xx())
 857                         OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
 858         }
 859
 860 just_restart:
 861         /* restart any queue, even if the claim failed  */
 862         restart = !ep->stopped && !list_empty(&ep->queue);
 863
 864         if (status)
 865                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 866                         restart ? " (restart)" : "");
 867         else
 868                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 869                         is_in ? 't' : 'r',
 870                         ep->dma_channel - 1, ep->lch,
 871                         restart ? " (restart)" : "");
 872
 873         if (restart) {
 874                 struct omap_req *req;
 875                 req = container_of(ep->queue.next, struct omap_req, queue);
 876                 if (ep->has_dma)
 877                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 878                 else {
 879                         use_ep(ep, UDC_EP_SEL);
 880                         (is_in ? write_fifo : read_fifo)(ep, req);
 881                         deselect_ep();
 882                         if (!is_in) {
 883                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 884                                 ep->ackwait = 1 + ep->double_buf;
 885                         }
 886                         /* IN: 6 wait states before it'll tx */
 887                 }
 888         }
 889 }
 890
 891 static void dma_channel_release(struct omap_ep *ep)
 892 {
 893         int             shift = 4 * (ep->dma_channel - 1);
 894         u16             mask = 0x0f << shift;
 895         struct omap_req *req;
 896         int             active;
 897
 898         /* abort any active usb transfer request */
 899         if (!list_empty(&ep->queue))
 900                 req = container_of(ep->queue.next, struct omap_req, queue);
 901         else
 902                 req = NULL;
 903
 904         active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
 905
 906         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 907                         active ? "active" : "idle",
 908                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 909                         ep->dma_channel - 1, req);
 910
 911         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 912          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 913          */
 914
 915         /* wait till current packet DMA finishes, and fifo empties */
 916         if (ep->bEndpointAddress & USB_DIR_IN) {
 917                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 918
 919                 if (req) {
 920                         finish_in_dma(ep, req, -ECONNRESET);
 921
 922                         /* clear FIFO; hosts probably won't empty it */
 923                         use_ep(ep, UDC_EP_SEL);
 924                         UDC_CTRL_REG = UDC_CLR_EP;
 925                         deselect_ep();
 926                 }
 927                 while (UDC_TXDMA_CFG_REG & mask)
 928                         udelay(10);
 929         } else {
 930                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 931
 932                 /* dma empties the fifo */
 933                 while (UDC_RXDMA_CFG_REG & mask)
 934                         udelay(10);
 935                 if (req)
 936                         finish_out_dma(ep, req, -ECONNRESET, 0);
 937         }
 938         omap_free_dma(ep->lch);
 939         ep->dma_channel = 0;
 940         ep->lch = -1;
 941         /* has_dma still set, till endpoint is fully quiesced */
 942 }
 943
 944
 945 /*-------------------------------------------------------------------------*/
 946
 947 static int
 948 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 949 {
 950         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 951         struct omap_req *req = container_of(_req, struct omap_req, req);
 952         struct omap_udc *udc;
 953         unsigned long   flags;
 954         int             is_iso = 0;
 955
 956         /* catch various bogus parameters */
 957         if (!_req || !req->req.complete || !req->req.buf
 958                         || !list_empty(&req->queue)) {
 959                 DBG("%s, bad params\n", __FUNCTION__);
 960                 return -EINVAL;
 961         }
 962         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 963                 DBG("%s, bad ep\n", __FUNCTION__);
 964                 return -EINVAL;
 965         }
 966         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 967                 if (req->req.length > ep->ep.maxpacket)
 968                         return -EMSGSIZE;
 969                 is_iso = 1;
 970         }
 971
 972         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 973          * have a hard time with partial packet reads...  reject it.
 974          */
 975         if (use_dma
 976                         && ep->has_dma
 977                         && ep->bEndpointAddress != 0
 978                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 979                         && (req->req.length % ep->ep.maxpacket) != 0) {
 980                 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
 981                 return -EMSGSIZE;
 982         }
 983
 984         udc = ep->udc;
 985         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 986                 return -ESHUTDOWN;
 987
 988         if (use_dma && ep->has_dma) {
 989                 if (req->req.dma == DMA_ADDR_INVALID) {
 990                         req->req.dma = dma_map_single(
 991                                 ep->udc->gadget.dev.parent,
 992                                 req->req.buf,
 993                                 req->req.length,
 994                                 (ep->bEndpointAddress & USB_DIR_IN)
 995                                         ? DMA_TO_DEVICE
 996                                         : DMA_FROM_DEVICE);
 997                         req->mapped = 1;
 998                 } else {
 999                         dma_sync_single_for_device(
1000                                 ep->udc->gadget.dev.parent,
1001                                 req->req.dma, req->req.length,
1002                                 (ep->bEndpointAddress & USB_DIR_IN)
1003                                         ? DMA_TO_DEVICE
1004                                         : DMA_FROM_DEVICE);
1005                         req->mapped = 0;
1006                 }
1007         }
1008
1009         VDBG("%s queue req %p, len %d buf %p\n",
1010                 ep->ep.name, _req, _req->length, _req->buf);
1011
1012         spin_lock_irqsave(&udc->lock, flags);
1013
1014         req->req.status = -EINPROGRESS;
1015         req->req.actual = 0;
1016
1017         /* maybe kickstart non-iso i/o queues */
1018         if (is_iso)
1019                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1020         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1021                 int     is_in;
1022
1023                 if (ep->bEndpointAddress == 0) {
1024                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1025                                 spin_unlock_irqrestore(&udc->lock, flags);
1026                                 return -EL2HLT;
1027                         }
1028
1029                         /* empty DATA stage? */
1030                         is_in = udc->ep0_in;
1031                         if (!req->req.length) {
1032
1033                                 /* chip became CONFIGURED or ADDRESSED
1034                                  * earlier; drivers may already have queued
1035                                  * requests to non-control endpoints
1036                                  */
1037                                 if (udc->ep0_set_config) {
1038                                         u16     irq_en = UDC_IRQ_EN_REG;
1039
1040                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1041                                         if (!udc->ep0_reset_config)
1042                                                 irq_en |= UDC_EPN_RX_IE
1043                                                         | UDC_EPN_TX_IE;
1044                                         UDC_IRQ_EN_REG = irq_en;
1045                                 }
1046
1047                                 /* STATUS for zero length DATA stages is
1048                                  * always an IN ... even for IN transfers,
1049                                  * a wierd case which seem to stall OMAP.
1050                                  */
1051                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1052                                 UDC_CTRL_REG = UDC_CLR_EP;
1053                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1054                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1055
1056                                 /* cleanup */
1057                                 udc->ep0_pending = 0;
1058                                 done(ep, req, 0);
1059                                 req = NULL;
1060
1061                         /* non-empty DATA stage */
1062                         } else if (is_in) {
1063                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1064                         } else {
1065                                 if (udc->ep0_setup)
1066                                         goto irq_wait;
1067                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1068                         }
1069                 } else {
1070                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1071                         if (!ep->has_dma)
1072                                 use_ep(ep, UDC_EP_SEL);
1073                         /* if ISO: SOF IRQs must be enabled/disabled! */
1074                 }
1075
1076                 if (ep->has_dma)
1077                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1078                 else if (req) {
1079                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1080                                 req = NULL;
1081                         deselect_ep();
1082                         if (!is_in) {
1083                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1084                                 ep->ackwait = 1 + ep->double_buf;
1085                         }
1086                         /* IN: 6 wait states before it'll tx */
1087                 }
1088         }
1089
1090 irq_wait:
1091         /* irq handler advances the queue */
1092         if (req != NULL)
1093                 list_add_tail(&req->queue, &ep->queue);
1094         spin_unlock_irqrestore(&udc->lock, flags);
1095
1096         return 0;
1097 }
1098
1099 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1100 {
1101         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1102         struct omap_req *req;
1103         unsigned long   flags;
1104
1105         if (!_ep || !_req)
1106                 return -EINVAL;
1107
1108         spin_lock_irqsave(&ep->udc->lock, flags);
1109
1110         /* make sure it's actually queued on this endpoint */
1111         list_for_each_entry (req, &ep->queue, queue) {
1112                 if (&req->req == _req)
1113                         break;
1114         }
1115         if (&req->req != _req) {
1116                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1117                 return -EINVAL;
1118         }
1119
1120         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1121                 int channel = ep->dma_channel;
1122
1123                 /* releasing the channel cancels the request,
1124                  * reclaiming the channel restarts the queue
1125                  */
1126                 dma_channel_release(ep);
1127                 dma_channel_claim(ep, channel);
1128         } else
1129                 done(ep, req, -ECONNRESET);
1130         spin_unlock_irqrestore(&ep->udc->lock, flags);
1131         return 0;
1132 }
1133
1134 /*-------------------------------------------------------------------------*/
1135
1136 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1137 {
1138         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1139         unsigned long   flags;
1140         int             status = -EOPNOTSUPP;
1141
1142         spin_lock_irqsave(&ep->udc->lock, flags);
1143
1144         /* just use protocol stalls for ep0; real halts are annoying */
1145         if (ep->bEndpointAddress == 0) {
1146                 if (!ep->udc->ep0_pending)
1147                         status = -EINVAL;
1148                 else if (value) {
1149                         if (ep->udc->ep0_set_config) {
1150                                 WARN("error changing config?\n");
1151                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1152                         }
1153                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1154                         ep->udc->ep0_pending = 0;
1155                         status = 0;
1156                 } else /* NOP */
1157                         status = 0;
1158
1159         /* otherwise, all active non-ISO endpoints can halt */
1160         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1161
1162                 /* IN endpoints must already be idle */
1163                 if ((ep->bEndpointAddress & USB_DIR_IN)
1164                                 && !list_empty(&ep->queue)) {
1165                         status = -EAGAIN;
1166                         goto done;
1167                 }
1168
1169                 if (value) {
1170                         int     channel;
1171
1172                         if (use_dma && ep->dma_channel
1173                                         && !list_empty(&ep->queue)) {
1174                                 channel = ep->dma_channel;
1175                                 dma_channel_release(ep);
1176                         } else
1177                                 channel = 0;
1178
1179                         use_ep(ep, UDC_EP_SEL);
1180                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1181                                 UDC_CTRL_REG = UDC_SET_HALT;
1182                                 status = 0;
1183                         } else
1184                                 status = -EAGAIN;
1185                         deselect_ep();
1186
1187                         if (channel)
1188                                 dma_channel_claim(ep, channel);
1189                 } else {
1190                         use_ep(ep, 0);
1191                         UDC_CTRL_REG = ep->udc->clr_halt;
1192                         ep->ackwait = 0;
1193                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1194                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1195                                 ep->ackwait = 1 + ep->double_buf;
1196                         }
1197                 }
1198         }
1199 done:
1200         VDBG("%s %s halt stat %d\n", ep->ep.name,
1201                 value ? "set" : "clear", status);
1202
1203         spin_unlock_irqrestore(&ep->udc->lock, flags);
1204         return status;
1205 }
1206
1207 static struct usb_ep_ops omap_ep_ops = {
1208         .enable         = omap_ep_enable,
1209         .disable        = omap_ep_disable,
1210
1211         .alloc_request  = omap_alloc_request,
1212         .free_request   = omap_free_request,
1213
1214         .alloc_buffer   = omap_alloc_buffer,
1215         .free_buffer    = omap_free_buffer,
1216
1217         .queue          = omap_ep_queue,
1218         .dequeue        = omap_ep_dequeue,
1219
1220         .set_halt       = omap_ep_set_halt,
1221         // fifo_status ... report bytes in fifo
1222         // fifo_flush ... flush fifo
1223 };
1224
1225 /*-------------------------------------------------------------------------*/
1226
1227 static int omap_get_frame(struct usb_gadget *gadget)
1228 {
1229         u16     sof = UDC_SOF_REG;
1230         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1231 }
1232
1233 static int omap_wakeup(struct usb_gadget *gadget)
1234 {
1235         struct omap_udc *udc;
1236         unsigned long   flags;
1237         int             retval = -EHOSTUNREACH;
1238
1239         udc = container_of(gadget, struct omap_udc, gadget);
1240
1241         spin_lock_irqsave(&udc->lock, flags);
1242         if (udc->devstat & UDC_SUS) {
1243                 /* NOTE:  OTG spec erratum says that OTG devices may
1244                  * issue wakeups without host enable.
1245                  */
1246                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1247                         DBG("remote wakeup...\n");
1248                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1249                         retval = 0;
1250                 }
1251
1252         /* NOTE:  non-OTG systems may use SRP TOO... */
1253         } else if (!(udc->devstat & UDC_ATT)) {
1254                 if (udc->transceiver)
1255                         retval = otg_start_srp(udc->transceiver);
1256         }
1257         spin_unlock_irqrestore(&udc->lock, flags);
1258
1259         return retval;
1260 }
1261
1262 static int
1263 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1264 {
1265         struct omap_udc *udc;
1266         unsigned long   flags;
1267         u16             syscon1;
1268
1269         udc = container_of(gadget, struct omap_udc, gadget);
1270         spin_lock_irqsave(&udc->lock, flags);
1271         syscon1 = UDC_SYSCON1_REG;
1272         if (is_selfpowered)
1273                 syscon1 |= UDC_SELF_PWR;
1274         else
1275                 syscon1 &= ~UDC_SELF_PWR;
1276         UDC_SYSCON1_REG = syscon1;
1277         spin_unlock_irqrestore(&udc->lock, flags);
1278
1279         return 0;
1280 }
1281
1282 static int can_pullup(struct omap_udc *udc)
1283 {
1284         return udc->driver && udc->softconnect && udc->vbus_active;
1285 }
1286
1287 static void pullup_enable(struct omap_udc *udc)
1288 {
1289         udc->gadget.dev.parent->power.power_state = PMSG_ON;
1290         udc->gadget.dev.power.power_state = PMSG_ON;
1291         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1292 #ifndef CONFIG_USB_OTG
1293         if (!cpu_is_omap15xx())
1294                 OTG_CTRL_REG |= OTG_BSESSVLD;
1295 #endif
1296         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1297 }
1298
1299 static void pullup_disable(struct omap_udc *udc)
1300 {
1301 #ifndef CONFIG_USB_OTG
1302         if (!cpu_is_omap15xx())
1303                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1304 #endif
1305         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1306         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1307 }
1308
1309 static struct omap_udc *udc;
1310
1311 static void omap_udc_enable_clock(int enable)
1312 {
1313         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1314                 return;
1315
1316         if (enable) {
1317                 clk_enable(udc->dc_clk);
1318                 clk_enable(udc->hhc_clk);
1319                 udelay(100);
1320         } else {
1321                 clk_disable(udc->hhc_clk);
1322                 clk_disable(udc->dc_clk);
1323         }
1324 }
1325
1326 /*
1327  * Called by whatever detects VBUS sessions:  external transceiver
1328  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1329  */
1330 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1331 {
1332         struct omap_udc *udc;
1333         unsigned long   flags;
1334
1335         udc = container_of(gadget, struct omap_udc, gadget);
1336         spin_lock_irqsave(&udc->lock, flags);
1337         VDBG("VBUS %s\n", is_active ? "on" : "off");
1338         udc->vbus_active = (is_active != 0);
1339         if (cpu_is_omap15xx()) {
1340                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1341                 if (is_active)
1342                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1343                 else
1344                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1345         }
1346         if (udc->dc_clk != NULL && is_active) {
1347                 if (!udc->clk_requested) {
1348                         omap_udc_enable_clock(1);
1349                         udc->clk_requested = 1;
1350                 }
1351         }
1352         if (can_pullup(udc))
1353                 pullup_enable(udc);
1354         else
1355                 pullup_disable(udc);
1356         if (udc->dc_clk != NULL && !is_active) {
1357                 if (udc->clk_requested) {
1358                         omap_udc_enable_clock(0);
1359                         udc->clk_requested = 0;
1360                 }
1361         }
1362         spin_unlock_irqrestore(&udc->lock, flags);
1363         return 0;
1364 }
1365
1366 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1367 {
1368         struct omap_udc *udc;
1369
1370         udc = container_of(gadget, struct omap_udc, gadget);
1371         if (udc->transceiver)
1372                 return otg_set_power(udc->transceiver, mA);
1373         return -EOPNOTSUPP;
1374 }
1375
1376 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1377 {
1378         struct omap_udc *udc;
1379         unsigned long   flags;
1380
1381         udc = container_of(gadget, struct omap_udc, gadget);
1382         spin_lock_irqsave(&udc->lock, flags);
1383         udc->softconnect = (is_on != 0);
1384         if (can_pullup(udc))
1385                 pullup_enable(udc);
1386         else
1387                 pullup_disable(udc);
1388         spin_unlock_irqrestore(&udc->lock, flags);
1389         return 0;
1390 }
1391
1392 static struct usb_gadget_ops omap_gadget_ops = {
1393         .get_frame              = omap_get_frame,
1394         .wakeup                 = omap_wakeup,
1395         .set_selfpowered        = omap_set_selfpowered,
1396         .vbus_session           = omap_vbus_session,
1397         .vbus_draw              = omap_vbus_draw,
1398         .pullup                 = omap_pullup,
1399 };
1400
1401 /*-------------------------------------------------------------------------*/
1402
1403 /* dequeue ALL requests; caller holds udc->lock */
1404 static void nuke(struct omap_ep *ep, int status)
1405 {
1406         struct omap_req *req;
1407
1408         ep->stopped = 1;
1409
1410         if (use_dma && ep->dma_channel)
1411                 dma_channel_release(ep);
1412
1413         use_ep(ep, 0);
1414         UDC_CTRL_REG = UDC_CLR_EP;
1415         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1416                 UDC_CTRL_REG = UDC_SET_HALT;
1417
1418         while (!list_empty(&ep->queue)) {
1419                 req = list_entry(ep->queue.next, struct omap_req, queue);
1420                 done(ep, req, status);
1421         }
1422 }
1423
1424 /* caller holds udc->lock */
1425 static void udc_quiesce(struct omap_udc *udc)
1426 {
1427         struct omap_ep  *ep;
1428
1429         udc->gadget.speed = USB_SPEED_UNKNOWN;
1430         nuke(&udc->ep[0], -ESHUTDOWN);
1431         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1432                 nuke(ep, -ESHUTDOWN);
1433 }
1434
1435 /*-------------------------------------------------------------------------*/
1436
1437 static void update_otg(struct omap_udc *udc)
1438 {
1439         u16     devstat;
1440
1441         if (!udc->gadget.is_otg)
1442                 return;
1443
1444         if (OTG_CTRL_REG & OTG_ID)
1445                 devstat = UDC_DEVSTAT_REG;
1446         else
1447                 devstat = 0;
1448
1449         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1450         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1451         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1452
1453         /* Enable HNP early, avoiding races on suspend irq path.
1454          * ASSUMES OTG state machine B_BUS_REQ input is true.
1455          */
1456         if (udc->gadget.b_hnp_enable)
1457                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1458                                 & ~OTG_PULLUP;
1459 }
1460
1461 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1462 {
1463         struct omap_ep  *ep0 = &udc->ep[0];
1464         struct omap_req *req = NULL;
1465
1466         ep0->irqs++;
1467
1468         /* Clear any pending requests and then scrub any rx/tx state
1469          * before starting to handle the SETUP request.
1470          */
1471         if (irq_src & UDC_SETUP) {
1472                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1473
1474                 nuke(ep0, 0);
1475                 if (ack) {
1476                         UDC_IRQ_SRC_REG = ack;
1477                         irq_src = UDC_SETUP;
1478                 }
1479         }
1480
1481         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1482          * This driver uses only uses protocol stalls (ep0 never halts),
1483          * and if we got this far the gadget driver already had a
1484          * chance to stall.  Tries to be forgiving of host oddities.
1485          *
1486          * NOTE:  the last chance gadget drivers have to stall control
1487          * requests is during their request completion callback.
1488          */
1489         if (!list_empty(&ep0->queue))
1490                 req = container_of(ep0->queue.next, struct omap_req, queue);
1491
1492         /* IN == TX to host */
1493         if (irq_src & UDC_EP0_TX) {
1494                 int     stat;
1495
1496                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1497                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1498                 stat = UDC_STAT_FLG_REG;
1499                 if (stat & UDC_ACK) {
1500                         if (udc->ep0_in) {
1501                                 /* write next IN packet from response,
1502                                  * or set up the status stage.
1503                                  */
1504                                 if (req)
1505                                         stat = write_fifo(ep0, req);
1506                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1507                                 if (!req && udc->ep0_pending) {
1508                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1509                                         UDC_CTRL_REG = UDC_CLR_EP;
1510                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1511                                         UDC_EP_NUM_REG = 0;
1512                                         udc->ep0_pending = 0;
1513                                 } /* else:  6 wait states before it'll tx */
1514                         } else {
1515                                 /* ack status stage of OUT transfer */
1516                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1517                                 if (req)
1518                                         done(ep0, req, 0);
1519                         }
1520                         req = NULL;
1521                 } else if (stat & UDC_STALL) {
1522                         UDC_CTRL_REG = UDC_CLR_HALT;
1523                         UDC_EP_NUM_REG = UDC_EP_DIR;
1524                 } else {
1525                         UDC_EP_NUM_REG = UDC_EP_DIR;
1526                 }
1527         }
1528
1529         /* OUT == RX from host */
1530         if (irq_src & UDC_EP0_RX) {
1531                 int     stat;
1532
1533                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1534                 UDC_EP_NUM_REG = UDC_EP_SEL;
1535                 stat = UDC_STAT_FLG_REG;
1536                 if (stat & UDC_ACK) {
1537                         if (!udc->ep0_in) {
1538                                 stat = 0;
1539                                 /* read next OUT packet of request, maybe
1540                                  * reactiviting the fifo; stall on errors.
1541                                  */
1542                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1543                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1544                                         udc->ep0_pending = 0;
1545                                         stat = 0;
1546                                 } else if (stat == 0)
1547                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1548                                 UDC_EP_NUM_REG = 0;
1549
1550                                 /* activate status stage */
1551                                 if (stat == 1) {
1552                                         done(ep0, req, 0);
1553                                         /* that may have STALLed ep0... */
1554                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1555                                         UDC_CTRL_REG = UDC_CLR_EP;
1556                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1557                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1558                                         udc->ep0_pending = 0;
1559                                 }
1560                         } else {
1561                                 /* ack status stage of IN transfer */
1562                                 UDC_EP_NUM_REG = 0;
1563                                 if (req)
1564                                         done(ep0, req, 0);
1565                         }
1566                 } else if (stat & UDC_STALL) {
1567                         UDC_CTRL_REG = UDC_CLR_HALT;
1568                         UDC_EP_NUM_REG = 0;
1569                 } else {
1570                         UDC_EP_NUM_REG = 0;
1571                 }
1572         }
1573
1574         /* SETUP starts all control transfers */
1575         if (irq_src & UDC_SETUP) {
1576                 union u {
1577                         u16                     word[4];
1578                         struct usb_ctrlrequest  r;
1579                 } u;
1580                 int                     status = -EINVAL;
1581                 struct omap_ep          *ep;
1582
1583                 /* read the (latest) SETUP message */
1584                 do {
1585                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1586                         /* two bytes at a time */
1587                         u.word[0] = UDC_DATA_REG;
1588                         u.word[1] = UDC_DATA_REG;
1589                         u.word[2] = UDC_DATA_REG;
1590                         u.word[3] = UDC_DATA_REG;
1591                         UDC_EP_NUM_REG = 0;
1592                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1593
1594 #define w_value         le16_to_cpup (&u.r.wValue)
1595 #define w_index         le16_to_cpup (&u.r.wIndex)
1596 #define w_length        le16_to_cpup (&u.r.wLength)
1597
1598                 /* Delegate almost all control requests to the gadget driver,
1599                  * except for a handful of ch9 status/feature requests that
1600                  * hardware doesn't autodecode _and_ the gadget API hides.
1601                  */
1602                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1603                 udc->ep0_set_config = 0;
1604                 udc->ep0_pending = 1;
1605                 ep0->stopped = 0;
1606                 ep0->ackwait = 0;
1607                 switch (u.r.bRequest) {
1608                 case USB_REQ_SET_CONFIGURATION:
1609                         /* udc needs to know when ep != 0 is valid */
1610                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1611                                 goto delegate;
1612                         if (w_length != 0)
1613                                 goto do_stall;
1614                         udc->ep0_set_config = 1;
1615                         udc->ep0_reset_config = (w_value == 0);
1616                         VDBG("set config %d\n", w_value);
1617
1618                         /* update udc NOW since gadget driver may start
1619                          * queueing requests immediately; clear config
1620                          * later if it fails the request.
1621                          */
1622                         if (udc->ep0_reset_config)
1623                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1624                         else
1625                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1626                         update_otg(udc);
1627                         goto delegate;
1628                 case USB_REQ_CLEAR_FEATURE:
1629                         /* clear endpoint halt */
1630                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1631                                 goto delegate;
1632                         if (w_value != USB_ENDPOINT_HALT
1633                                         || w_length != 0)
1634                                 goto do_stall;
1635                         ep = &udc->ep[w_index & 0xf];
1636                         if (ep != ep0) {
1637                                 if (w_index & USB_DIR_IN)
1638                                         ep += 16;
1639                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1640                                                 || !ep->desc)
1641                                         goto do_stall;
1642                                 use_ep(ep, 0);
1643                                 UDC_CTRL_REG = udc->clr_halt;
1644                                 ep->ackwait = 0;
1645                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1646                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1647                                         ep->ackwait = 1 + ep->double_buf;
1648                                 }
1649                                 /* NOTE:  assumes the host behaves sanely,
1650                                  * only clearing real halts.  Else we may
1651                                  * need to kill pending transfers and then
1652                                  * restart the queue... very messy for DMA!
1653                                  */
1654                         }
1655                         VDBG("%s halt cleared by host\n", ep->name);
1656                         goto ep0out_status_stage;
1657                 case USB_REQ_SET_FEATURE:
1658                         /* set endpoint halt */
1659                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1660                                 goto delegate;
1661                         if (w_value != USB_ENDPOINT_HALT
1662                                         || w_length != 0)
1663                                 goto do_stall;
1664                         ep = &udc->ep[w_index & 0xf];
1665                         if (w_index & USB_DIR_IN)
1666                                 ep += 16;
1667                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1668                                         || ep == ep0 || !ep->desc)
1669                                 goto do_stall;
1670                         if (use_dma && ep->has_dma) {
1671                                 /* this has rude side-effects (aborts) and
1672                                  * can't really work if DMA-IN is active
1673                                  */
1674                                 DBG("%s host set_halt, NYET \n", ep->name);
1675                                 goto do_stall;
1676                         }
1677                         use_ep(ep, 0);
1678                         /* can't halt if fifo isn't empty... */
1679                         UDC_CTRL_REG = UDC_CLR_EP;
1680                         UDC_CTRL_REG = UDC_SET_HALT;
1681                         VDBG("%s halted by host\n", ep->name);
1682 ep0out_status_stage:
1683                         status = 0;
1684                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1685                         UDC_CTRL_REG = UDC_CLR_EP;
1686                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1687                         UDC_EP_NUM_REG = UDC_EP_DIR;
1688                         udc->ep0_pending = 0;
1689                         break;
1690                 case USB_REQ_GET_STATUS:
1691                         /* return interface status.  if we were pedantic,
1692                          * we'd detect non-existent interfaces, and stall.
1693                          */
1694                         if (u.r.bRequestType
1695                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1696                                 goto delegate;
1697                         /* return two zero bytes */
1698                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1699                         UDC_DATA_REG = 0;
1700                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1701                         UDC_EP_NUM_REG = UDC_EP_DIR;
1702                         status = 0;
1703                         VDBG("GET_STATUS, interface %d\n", w_index);
1704                         /* next, status stage */
1705                         break;
1706                 default:
1707 delegate:
1708                         /* activate the ep0out fifo right away */
1709                         if (!udc->ep0_in && w_length) {
1710                                 UDC_EP_NUM_REG = 0;
1711                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1712                         }
1713
1714                         /* gadget drivers see class/vendor specific requests,
1715                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1716                          * and more
1717                          */
1718                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1719                                 u.r.bRequestType, u.r.bRequest,
1720                                 w_value, w_index, w_length);
1721
1722 #undef  w_value
1723 #undef  w_index
1724 #undef  w_length
1725
1726                         /* The gadget driver may return an error here,
1727                          * causing an immediate protocol stall.
1728                          *
1729                          * Else it must issue a response, either queueing a
1730                          * response buffer for the DATA stage, or halting ep0
1731                          * (causing a protocol stall, not a real halt).  A
1732                          * zero length buffer means no DATA stage.
1733                          *
1734                          * It's fine to issue that response after the setup()
1735                          * call returns, and this IRQ was handled.
1736                          */
1737                         udc->ep0_setup = 1;
1738                         spin_unlock(&udc->lock);
1739                         status = udc->driver->setup (&udc->gadget, &u.r);
1740                         spin_lock(&udc->lock);
1741                         udc->ep0_setup = 0;
1742                 }
1743
1744                 if (status < 0) {
1745 do_stall:
1746                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1747                                         u.r.bRequestType, u.r.bRequest, status);
1748                         if (udc->ep0_set_config) {
1749                                 if (udc->ep0_reset_config)
1750                                         WARN("error resetting config?\n");
1751                                 else
1752                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1753                         }
1754                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1755                         udc->ep0_pending = 0;
1756                 }
1757         }
1758 }
1759
1760 /*-------------------------------------------------------------------------*/
1761
1762 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1763
1764 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1765 {
1766         u16     devstat, change;
1767
1768         devstat = UDC_DEVSTAT_REG;
1769         change = devstat ^ udc->devstat;
1770         udc->devstat = devstat;
1771
1772         if (change & (UDC_USB_RESET|UDC_ATT)) {
1773                 udc_quiesce(udc);
1774
1775                 if (change & UDC_ATT) {
1776                         /* driver for any external transceiver will
1777                          * have called omap_vbus_session() already
1778                          */
1779                         if (devstat & UDC_ATT) {
1780                                 udc->gadget.speed = USB_SPEED_FULL;
1781                                 VDBG("connect\n");
1782                                 if (!udc->transceiver)
1783                                         pullup_enable(udc);
1784                                 // if (driver->connect) call it
1785                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1786                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1787                                 if (!udc->transceiver)
1788                                         pullup_disable(udc);
1789                                 DBG("disconnect, gadget %s\n",
1790                                         udc->driver->driver.name);
1791                                 if (udc->driver->disconnect) {
1792                                         spin_unlock(&udc->lock);
1793                                         udc->driver->disconnect(&udc->gadget);
1794                                         spin_lock(&udc->lock);
1795                                 }
1796                         }
1797                         change &= ~UDC_ATT;
1798                 }
1799
1800                 if (change & UDC_USB_RESET) {
1801                         if (devstat & UDC_USB_RESET) {
1802                                 VDBG("RESET=1\n");
1803                         } else {
1804                                 udc->gadget.speed = USB_SPEED_FULL;
1805                                 INFO("USB reset done, gadget %s\n",
1806                                         udc->driver->driver.name);
1807                                 /* ep0 traffic is legal from now on */
1808                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1809                         }
1810                         change &= ~UDC_USB_RESET;
1811                 }
1812         }
1813         if (change & UDC_SUS) {
1814                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1815                         // FIXME tell isp1301 to suspend/resume (?)
1816                         if (devstat & UDC_SUS) {
1817                                 VDBG("suspend\n");
1818                                 update_otg(udc);
1819                                 /* HNP could be under way already */
1820                                 if (udc->gadget.speed == USB_SPEED_FULL
1821                                                 && udc->driver->suspend) {
1822                                         spin_unlock(&udc->lock);
1823                                         udc->driver->suspend(&udc->gadget);
1824                                         spin_lock(&udc->lock);
1825                                 }
1826                                 if (udc->transceiver)
1827                                         otg_set_suspend(udc->transceiver, 1);
1828                         } else {
1829                                 VDBG("resume\n");
1830                                 if (udc->transceiver)
1831                                         otg_set_suspend(udc->transceiver, 0);
1832                                 if (udc->gadget.speed == USB_SPEED_FULL
1833                                                 && udc->driver->resume) {
1834                                         spin_unlock(&udc->lock);
1835                                         udc->driver->resume(&udc->gadget);
1836                                         spin_lock(&udc->lock);
1837                                 }
1838                         }
1839                 }
1840                 change &= ~UDC_SUS;
1841         }
1842         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1843                 update_otg(udc);
1844                 change &= ~OTG_FLAGS;
1845         }
1846
1847         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1848         if (change)
1849                 VDBG("devstat %03x, ignore change %03x\n",
1850                         devstat,  change);
1851
1852         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1853 }
1854
1855 static irqreturn_t
1856 omap_udc_irq(int irq, void *_udc, struct pt_regs *r)
1857 {
1858         struct omap_udc *udc = _udc;
1859         u16             irq_src;
1860         irqreturn_t     status = IRQ_NONE;
1861         unsigned long   flags;
1862
1863         spin_lock_irqsave(&udc->lock, flags);
1864         irq_src = UDC_IRQ_SRC_REG;
1865
1866         /* Device state change (usb ch9 stuff) */
1867         if (irq_src & UDC_DS_CHG) {
1868                 devstate_irq(_udc, irq_src);
1869                 status = IRQ_HANDLED;
1870                 irq_src &= ~UDC_DS_CHG;
1871         }
1872
1873         /* EP0 control transfers */
1874         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1875                 ep0_irq(_udc, irq_src);
1876                 status = IRQ_HANDLED;
1877                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1878         }
1879
1880         /* DMA transfer completion */
1881         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1882                 dma_irq(_udc, irq_src);
1883                 status = IRQ_HANDLED;
1884                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1885         }
1886
1887         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1888         if (irq_src)
1889                 DBG("udc_irq, unhandled %03x\n", irq_src);
1890         spin_unlock_irqrestore(&udc->lock, flags);
1891
1892         return status;
1893 }
1894
1895 /* workaround for seemingly-lost IRQs for RX ACKs... */
1896 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1897 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1898
1899 static void pio_out_timer(unsigned long _ep)
1900 {
1901         struct omap_ep  *ep = (void *) _ep;
1902         unsigned long   flags;
1903         u16             stat_flg;
1904
1905         spin_lock_irqsave(&ep->udc->lock, flags);
1906         if (!list_empty(&ep->queue) && ep->ackwait) {
1907                 use_ep(ep, UDC_EP_SEL);
1908                 stat_flg = UDC_STAT_FLG_REG;
1909
1910                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1911                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1912                         struct omap_req *req;
1913
1914                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1915                         req = container_of(ep->queue.next,
1916                                         struct omap_req, queue);
1917                         (void) read_fifo(ep, req);
1918                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1919                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1920                         ep->ackwait = 1 + ep->double_buf;
1921                 }
1922                 else {
1923                     deselect_ep();
1924                 }
1925         }
1926         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1927         spin_unlock_irqrestore(&ep->udc->lock, flags);
1928 }
1929
1930 static irqreturn_t
1931 omap_udc_pio_irq(int irq, void *_dev, struct pt_regs *r)
1932 {
1933         u16             epn_stat, irq_src;
1934         irqreturn_t     status = IRQ_NONE;
1935         struct omap_ep  *ep;
1936         int             epnum;
1937         struct omap_udc *udc = _dev;
1938         struct omap_req *req;
1939         unsigned long   flags;
1940
1941         spin_lock_irqsave(&udc->lock, flags);
1942         epn_stat = UDC_EPN_STAT_REG;
1943         irq_src = UDC_IRQ_SRC_REG;
1944
1945         /* handle OUT first, to avoid some wasteful NAKs */
1946         if (irq_src & UDC_EPN_RX) {
1947                 epnum = (epn_stat >> 8) & 0x0f;
1948                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1949                 status = IRQ_HANDLED;
1950                 ep = &udc->ep[epnum];
1951                 ep->irqs++;
1952
1953                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1954                 ep->fnf = 0;
1955                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1956                         ep->ackwait--;
1957                         if (!list_empty(&ep->queue)) {
1958                                 int stat;
1959                                 req = container_of(ep->queue.next,
1960                                                 struct omap_req, queue);
1961                                 stat = read_fifo(ep, req);
1962                                 if (!ep->double_buf)
1963                                         ep->fnf = 1;
1964                         }
1965                 }
1966                 /* min 6 clock delay before clearing EP_SEL ... */
1967                 epn_stat = UDC_EPN_STAT_REG;
1968                 epn_stat = UDC_EPN_STAT_REG;
1969                 UDC_EP_NUM_REG = epnum;
1970
1971                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1972                  * reduces lossage; timer still needed though (sigh).
1973                  */
1974                 if (ep->fnf) {
1975                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1976                         ep->ackwait = 1 + ep->double_buf;
1977                 }
1978                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1979         }
1980
1981         /* then IN transfers */
1982         else if (irq_src & UDC_EPN_TX) {
1983                 epnum = epn_stat & 0x0f;
1984                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1985                 status = IRQ_HANDLED;
1986                 ep = &udc->ep[16 + epnum];
1987                 ep->irqs++;
1988
1989                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1990                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1991                         ep->ackwait = 0;
1992                         if (!list_empty(&ep->queue)) {
1993                                 req = container_of(ep->queue.next,
1994                                                 struct omap_req, queue);
1995                                 (void) write_fifo(ep, req);
1996                         }
1997                 }
1998                 /* min 6 clock delay before clearing EP_SEL ... */
1999                 epn_stat = UDC_EPN_STAT_REG;
2000                 epn_stat = UDC_EPN_STAT_REG;
2001                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
2002                 /* then 6 clocks before it'd tx */
2003         }
2004
2005         spin_unlock_irqrestore(&udc->lock, flags);
2006         return status;
2007 }
2008
2009 #ifdef  USE_ISO
2010 static irqreturn_t
2011 omap_udc_iso_irq(int irq, void *_dev, struct pt_regs *r)
2012 {
2013         struct omap_udc *udc = _dev;
2014         struct omap_ep  *ep;
2015         int             pending = 0;
2016         unsigned long   flags;
2017
2018         spin_lock_irqsave(&udc->lock, flags);
2019
2020         /* handle all non-DMA ISO transfers */
2021         list_for_each_entry (ep, &udc->iso, iso) {
2022                 u16             stat;
2023                 struct omap_req *req;
2024
2025                 if (ep->has_dma || list_empty(&ep->queue))
2026                         continue;
2027                 req = list_entry(ep->queue.next, struct omap_req, queue);
2028
2029                 use_ep(ep, UDC_EP_SEL);
2030                 stat = UDC_STAT_FLG_REG;
2031
2032                 /* NOTE: like the other controller drivers, this isn't
2033                  * currently reporting lost or damaged frames.
2034                  */
2035                 if (ep->bEndpointAddress & USB_DIR_IN) {
2036                         if (stat & UDC_MISS_IN)
2037                                 /* done(ep, req, -EPROTO) */;
2038                         else
2039                                 write_fifo(ep, req);
2040                 } else {
2041                         int     status = 0;
2042
2043                         if (stat & UDC_NO_RXPACKET)
2044                                 status = -EREMOTEIO;
2045                         else if (stat & UDC_ISO_ERR)
2046                                 status = -EILSEQ;
2047                         else if (stat & UDC_DATA_FLUSH)
2048                                 status = -ENOSR;
2049
2050                         if (status)
2051                                 /* done(ep, req, status) */;
2052                         else
2053                                 read_fifo(ep, req);
2054                 }
2055                 deselect_ep();
2056                 /* 6 wait states before next EP */
2057
2058                 ep->irqs++;
2059                 if (!list_empty(&ep->queue))
2060                         pending = 1;
2061         }
2062         if (!pending)
2063                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2064         UDC_IRQ_SRC_REG = UDC_SOF;
2065
2066         spin_unlock_irqrestore(&udc->lock, flags);
2067         return IRQ_HANDLED;
2068 }
2069 #endif
2070
2071 /*-------------------------------------------------------------------------*/
2072
2073
2074 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2075 {
2076         int             status = -ENODEV;
2077         struct omap_ep  *ep;
2078         unsigned long   flags;
2079
2080         /* basic sanity tests */
2081         if (!udc)
2082                 return -ENODEV;
2083         if (!driver
2084                         // FIXME if otg, check:  driver->is_otg
2085                         || driver->speed < USB_SPEED_FULL
2086                         || !driver->bind
2087                         || !driver->unbind
2088                         || !driver->setup)
2089                 return -EINVAL;
2090
2091         spin_lock_irqsave(&udc->lock, flags);
2092         if (udc->driver) {
2093                 spin_unlock_irqrestore(&udc->lock, flags);
2094                 return -EBUSY;
2095         }
2096
2097         /* reset state */
2098         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2099                 ep->irqs = 0;
2100                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2101                         continue;
2102                 use_ep(ep, 0);
2103                 UDC_CTRL_REG = UDC_SET_HALT;
2104         }
2105         udc->ep0_pending = 0;
2106         udc->ep[0].irqs = 0;
2107         udc->softconnect = 1;
2108
2109         /* hook up the driver */
2110         driver->driver.bus = NULL;
2111         udc->driver = driver;
2112         udc->gadget.dev.driver = &driver->driver;
2113         spin_unlock_irqrestore(&udc->lock, flags);
2114
2115         if (udc->dc_clk != NULL)
2116                 omap_udc_enable_clock(1);
2117
2118         status = driver->bind (&udc->gadget);
2119         if (status) {
2120                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2121                 udc->gadget.dev.driver = NULL;
2122                 udc->driver = NULL;
2123                 goto done;
2124         }
2125         DBG("bound to driver %s\n", driver->driver.name);
2126
2127         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2128
2129         /* connect to bus through transceiver */
2130         if (udc->transceiver) {
2131                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2132                 if (status < 0) {
2133                         ERR("can't bind to transceiver\n");
2134                         driver->unbind (&udc->gadget);
2135                         udc->gadget.dev.driver = NULL;
2136                         udc->driver = NULL;
2137                         goto done;
2138                 }
2139         } else {
2140                 if (can_pullup(udc))
2141                         pullup_enable (udc);
2142                 else
2143                         pullup_disable (udc);
2144         }
2145
2146         /* boards that don't have VBUS sensing can't autogate 48MHz;
2147          * can't enter deep sleep while a gadget driver is active.
2148          */
2149         if (machine_is_omap_innovator() || machine_is_omap_osk())
2150                 omap_vbus_session(&udc->gadget, 1);
2151
2152 done:
2153         if (udc->dc_clk != NULL)
2154                 omap_udc_enable_clock(0);
2155         return status;
2156 }
2157 EXPORT_SYMBOL(usb_gadget_register_driver);
2158
2159 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2160 {
2161         unsigned long   flags;
2162         int             status = -ENODEV;
2163
2164         if (!udc)
2165                 return -ENODEV;
2166         if (!driver || driver != udc->driver)
2167                 return -EINVAL;
2168
2169         if (udc->dc_clk != NULL)
2170                 omap_udc_enable_clock(1);
2171
2172         if (machine_is_omap_innovator() || machine_is_omap_osk())
2173                 omap_vbus_session(&udc->gadget, 0);
2174
2175         if (udc->transceiver)
2176                 (void) otg_set_peripheral(udc->transceiver, NULL);
2177         else
2178                 pullup_disable(udc);
2179
2180         spin_lock_irqsave(&udc->lock, flags);
2181         udc_quiesce(udc);
2182         spin_unlock_irqrestore(&udc->lock, flags);
2183
2184         driver->unbind(&udc->gadget);
2185         udc->gadget.dev.driver = NULL;
2186         udc->driver = NULL;
2187
2188         if (udc->dc_clk != NULL)
2189                 omap_udc_enable_clock(0);
2190         DBG("unregistered driver '%s'\n", driver->driver.name);
2191         return status;
2192 }
2193 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2194
2195
2196 /*-------------------------------------------------------------------------*/
2197
2198 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2199
2200 #include <linux/seq_file.h>
2201
2202 static const char proc_filename[] = "driver/udc";
2203
2204 #define FOURBITS "%s%s%s%s"
2205 #define EIGHTBITS FOURBITS FOURBITS
2206
2207 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2208 {
2209         u16             stat_flg;
2210         struct omap_req *req;
2211         char            buf[20];
2212
2213         use_ep(ep, 0);
2214
2215         if (use_dma && ep->has_dma)
2216                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2217                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2218                         ep->dma_channel - 1, ep->lch);
2219         else
2220                 buf[0] = 0;
2221
2222         stat_flg = UDC_STAT_FLG_REG;
2223         seq_printf(s,
2224                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2225                 ep->name, buf,
2226                 ep->double_buf ? "dbuf " : "",
2227                 ({char *s; switch(ep->ackwait){
2228                 case 0: s = ""; break;
2229                 case 1: s = "(ackw) "; break;
2230                 case 2: s = "(ackw2) "; break;
2231                 default: s = "(?) "; break;
2232                 } s;}),
2233                 ep->irqs, stat_flg,
2234                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2235                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2236                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2237                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2238                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2239                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2240                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2241                 (stat_flg & UDC_STALL) ? "STALL " : "",
2242                 (stat_flg & UDC_NAK) ? "NAK " : "",
2243                 (stat_flg & UDC_ACK) ? "ACK " : "",
2244                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2245                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2246                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2247
2248         if (list_empty (&ep->queue))
2249                 seq_printf(s, "\t(queue empty)\n");
2250         else
2251                 list_for_each_entry (req, &ep->queue, queue) {
2252                         unsigned        length = req->req.actual;
2253
2254                         if (use_dma && buf[0]) {
2255                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2256                                                 ? dma_src_len : dma_dest_len)
2257                                         (ep, req->req.dma + length);
2258                                 buf[0] = 0;
2259                         }
2260                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2261                                         &req->req, length,
2262                                         req->req.length, req->req.buf);
2263                 }
2264 }
2265
2266 static char *trx_mode(unsigned m, int enabled)
2267 {
2268         switch (m) {
2269         case 0:         return enabled ? "*6wire" : "unused";
2270         case 1:         return "4wire";
2271         case 2:         return "3wire";
2272         case 3:         return "6wire";
2273         default:        return "unknown";
2274         }
2275 }
2276
2277 static int proc_otg_show(struct seq_file *s)
2278 {
2279         u32             tmp;
2280         u32             trans;
2281
2282         tmp = OTG_REV_REG;
2283         trans = USB_TRANSCEIVER_CTRL_REG;
2284         seq_printf(s, "\nOTG rev %d.%d, transceiver_ctrl %05x\n",
2285                 tmp >> 4, tmp & 0xf, trans);
2286         tmp = OTG_SYSCON_1_REG;
2287         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2288                         FOURBITS "\n", tmp,
2289                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2290                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2291                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2292                         ? "internal"
2293                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2294                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2295                 (tmp & HST_IDLE_EN) ? " !host" : "",
2296                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2297                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2298         tmp = OTG_SYSCON_2_REG;
2299         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2300                         " b_ase_brst=%d hmc=%d\n", tmp,
2301                 (tmp & OTG_EN) ? " otg_en" : "",
2302                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2303                 // much more SRP stuff
2304                 (tmp & SRP_DATA) ? " srp_data" : "",
2305                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2306                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2307                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2308                 (tmp & UHOST_EN) ? " uhost_en" : "",
2309                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2310                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2311                 B_ASE_BRST(tmp),
2312                 OTG_HMC(tmp));
2313         tmp = OTG_CTRL_REG;
2314         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2315                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2316                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2317                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2318                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2319                 (tmp & OTG_ID) ? " id" : "",
2320                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2321                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2322                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2323                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2324                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2325                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2326                 (tmp & OTG_PULLDOWN) ? " down" : "",
2327                 (tmp & OTG_PULLUP) ? " up" : "",
2328                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2329                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2330                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2331                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2332                 );
2333         tmp = OTG_IRQ_EN_REG;
2334         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2335         tmp = OTG_IRQ_SRC_REG;
2336         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2337         tmp = OTG_OUTCTRL_REG;
2338         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2339         tmp = OTG_TEST_REG;
2340         seq_printf(s, "otg_test    %04x" "\n", tmp);
2341         return 0;
2342 }
2343
2344 static int proc_udc_show(struct seq_file *s, void *_)
2345 {
2346         u32             tmp;
2347         struct omap_ep  *ep;
2348         unsigned long   flags;
2349
2350         spin_lock_irqsave(&udc->lock, flags);
2351
2352         seq_printf(s, "%s, version: " DRIVER_VERSION
2353 #ifdef  USE_ISO
2354                 " (iso)"
2355 #endif
2356                 "%s\n",
2357                 driver_desc,
2358                 use_dma ?  " (dma)" : "");
2359
2360         tmp = UDC_REV_REG & 0xff;
2361         seq_printf(s,
2362                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2363                 "hmc %d, transceiver %s\n",
2364                 tmp >> 4, tmp & 0xf,
2365                 fifo_mode,
2366                 udc->driver ? udc->driver->driver.name : "(none)",
2367                 HMC,
2368                 udc->transceiver ? udc->transceiver->label : "(none)");
2369         seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2370                 __REG16(ULPD_CLOCK_CTRL),
2371                 __REG16(ULPD_SOFT_REQ),
2372                 __REG16(ULPD_STATUS_REQ));
2373
2374         /* OTG controller registers */
2375         if (!cpu_is_omap15xx())
2376                 proc_otg_show(s);
2377
2378         tmp = UDC_SYSCON1_REG;
2379         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2380                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2381                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2382                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2383                 (tmp & UDC_NAK_EN) ? " nak" : "",
2384                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2385                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2386                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2387                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2388         // syscon2 is write-only
2389
2390         /* UDC controller registers */
2391         if (!(tmp & UDC_PULLUP_EN)) {
2392                 seq_printf(s, "(suspended)\n");
2393                 spin_unlock_irqrestore(&udc->lock, flags);
2394                 return 0;
2395         }
2396
2397         tmp = UDC_DEVSTAT_REG;
2398         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2399                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2400                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2401                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2402                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2403                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2404                 (tmp & UDC_SUS) ? " SUS" : "",
2405                 (tmp & UDC_CFG) ? " CFG" : "",
2406                 (tmp & UDC_ADD) ? " ADD" : "",
2407                 (tmp & UDC_DEF) ? " DEF" : "",
2408                 (tmp & UDC_ATT) ? " ATT" : "");
2409         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2410         tmp = UDC_IRQ_EN_REG;
2411         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2412                 (tmp & UDC_SOF_IE) ? " sof" : "",
2413                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2414                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2415                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2416                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2417         tmp = UDC_IRQ_SRC_REG;
2418         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2419                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2420                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2421                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2422                 (tmp & UDC_SOF) ? " sof" : "",
2423                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2424                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2425                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2426                 (tmp & UDC_SETUP) ? " setup" : "",
2427                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2428                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2429         if (use_dma) {
2430                 unsigned i;
2431
2432                 tmp = UDC_DMA_IRQ_EN_REG;
2433                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2434                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2435                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2436                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2437
2438                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2439                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2440                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2441
2442                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2443                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2444                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2445
2446                 tmp = UDC_RXDMA_CFG_REG;
2447                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2448                 if (tmp) {
2449                         for (i = 0; i < 3; i++) {
2450                                 if ((tmp & (0x0f << (i * 4))) == 0)
2451                                         continue;
2452                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2453                                                 UDC_RXDMA_REG(i + 1));
2454                         }
2455                 }
2456                 tmp = UDC_TXDMA_CFG_REG;
2457                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2458                 if (tmp) {
2459                         for (i = 0; i < 3; i++) {
2460                                 if (!(tmp & (0x0f << (i * 4))))
2461                                         continue;
2462                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2463                                                 UDC_TXDMA_REG(i + 1));
2464                         }
2465                 }
2466         }
2467
2468         tmp = UDC_DEVSTAT_REG;
2469         if (tmp & UDC_ATT) {
2470                 proc_ep_show(s, &udc->ep[0]);
2471                 if (tmp & UDC_ADD) {
2472                         list_for_each_entry (ep, &udc->gadget.ep_list,
2473                                         ep.ep_list) {
2474                                 if (ep->desc)
2475                                         proc_ep_show(s, ep);
2476                         }
2477                 }
2478         }
2479         spin_unlock_irqrestore(&udc->lock, flags);
2480         return 0;
2481 }
2482
2483 static int proc_udc_open(struct inode *inode, struct file *file)
2484 {
2485         return single_open(file, proc_udc_show, NULL);
2486 }
2487
2488 static struct file_operations proc_ops = {
2489         .open           = proc_udc_open,
2490         .read           = seq_read,
2491         .llseek         = seq_lseek,
2492         .release        = single_release,
2493 };
2494
2495 static void create_proc_file(void)
2496 {
2497         struct proc_dir_entry *pde;
2498
2499         pde = create_proc_entry (proc_filename, 0, NULL);
2500         if (pde)
2501                 pde->proc_fops = &proc_ops;
2502 }
2503
2504 static void remove_proc_file(void)
2505 {
2506         remove_proc_entry(proc_filename, NULL);
2507 }
2508
2509 #else
2510
2511 static inline void create_proc_file(void) {}
2512 static inline void remove_proc_file(void) {}
2513
2514 #endif
2515
2516 /*-------------------------------------------------------------------------*/
2517
2518 /* Before this controller can enumerate, we need to pick an endpoint
2519  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2520  * buffer space among the endpoints we'll be operating.
2521  *
2522  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2523  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2524  * capability yet though.
2525  */
2526 static unsigned __init
2527 omap_ep_setup(char *name, u8 addr, u8 type,
2528                 unsigned buf, unsigned maxp, int dbuf)
2529 {
2530         struct omap_ep  *ep;
2531         u16             epn_rxtx = 0;
2532
2533         /* OUT endpoints first, then IN */
2534         ep = &udc->ep[addr & 0xf];
2535         if (addr & USB_DIR_IN)
2536                 ep += 16;
2537
2538         /* in case of ep init table bugs */
2539         BUG_ON(ep->name[0]);
2540
2541         /* chip setup ... bit values are same for IN, OUT */
2542         if (type == USB_ENDPOINT_XFER_ISOC) {
2543                 switch (maxp) {
2544                 case 8:         epn_rxtx = 0 << 12; break;
2545                 case 16:        epn_rxtx = 1 << 12; break;
2546                 case 32:        epn_rxtx = 2 << 12; break;
2547                 case 64:        epn_rxtx = 3 << 12; break;
2548                 case 128:       epn_rxtx = 4 << 12; break;
2549                 case 256:       epn_rxtx = 5 << 12; break;
2550                 case 512:       epn_rxtx = 6 << 12; break;
2551                 default:        BUG();
2552                 }
2553                 epn_rxtx |= UDC_EPN_RX_ISO;
2554                 dbuf = 1;
2555         } else {
2556                 /* double-buffering "not supported" on 15xx,
2557                  * and ignored for PIO-IN on 16xx
2558                  */
2559                 if (!use_dma || cpu_is_omap15xx())
2560                         dbuf = 0;
2561
2562                 switch (maxp) {
2563                 case 8:         epn_rxtx = 0 << 12; break;
2564                 case 16:        epn_rxtx = 1 << 12; break;
2565                 case 32:        epn_rxtx = 2 << 12; break;
2566                 case 64:        epn_rxtx = 3 << 12; break;
2567                 default:        BUG();
2568                 }
2569                 if (dbuf && addr)
2570                         epn_rxtx |= UDC_EPN_RX_DB;
2571                 init_timer(&ep->timer);
2572                 ep->timer.function = pio_out_timer;
2573                 ep->timer.data = (unsigned long) ep;
2574         }
2575         if (addr)
2576                 epn_rxtx |= UDC_EPN_RX_VALID;
2577         BUG_ON(buf & 0x07);
2578         epn_rxtx |= buf >> 3;
2579
2580         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2581                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2582
2583         if (addr & USB_DIR_IN)
2584                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2585         else
2586                 UDC_EP_RX_REG(addr) = epn_rxtx;
2587
2588         /* next endpoint's buffer starts after this one's */
2589         buf += maxp;
2590         if (dbuf)
2591                 buf += maxp;
2592         BUG_ON(buf > 2048);
2593
2594         /* set up driver data structures */
2595         BUG_ON(strlen(name) >= sizeof ep->name);
2596         strlcpy(ep->name, name, sizeof ep->name);
2597         INIT_LIST_HEAD(&ep->queue);
2598         INIT_LIST_HEAD(&ep->iso);
2599         ep->bEndpointAddress = addr;
2600         ep->bmAttributes = type;
2601         ep->double_buf = dbuf;
2602         ep->udc = udc;
2603
2604         ep->ep.name = ep->name;
2605         ep->ep.ops = &omap_ep_ops;
2606         ep->ep.maxpacket = ep->maxpacket = maxp;
2607         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2608
2609         return buf;
2610 }
2611
2612 static void omap_udc_release(struct device *dev)
2613 {
2614         complete(udc->done);
2615         kfree (udc);
2616         udc = NULL;
2617 }
2618
2619 static int __init
2620 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2621 {
2622         unsigned        tmp, buf;
2623
2624         /* abolish any previous hardware state */
2625         UDC_SYSCON1_REG = 0;
2626         UDC_IRQ_EN_REG = 0;
2627         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2628         UDC_DMA_IRQ_EN_REG = 0;
2629         UDC_RXDMA_CFG_REG = 0;
2630         UDC_TXDMA_CFG_REG = 0;
2631
2632         /* UDC_PULLUP_EN gates the chip clock */
2633         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2634
2635         udc = kzalloc(sizeof(*udc), SLAB_KERNEL);
2636         if (!udc)
2637                 return -ENOMEM;
2638
2639         spin_lock_init (&udc->lock);
2640
2641         udc->gadget.ops = &omap_gadget_ops;
2642         udc->gadget.ep0 = &udc->ep[0].ep;
2643         INIT_LIST_HEAD(&udc->gadget.ep_list);
2644         INIT_LIST_HEAD(&udc->iso);
2645         udc->gadget.speed = USB_SPEED_UNKNOWN;
2646         udc->gadget.name = driver_name;
2647
2648         device_initialize(&udc->gadget.dev);
2649         strcpy (udc->gadget.dev.bus_id, "gadget");
2650         udc->gadget.dev.release = omap_udc_release;
2651         udc->gadget.dev.parent = &odev->dev;
2652         if (use_dma)
2653                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2654
2655         udc->transceiver = xceiv;
2656
2657         /* ep0 is special; put it right after the SETUP buffer */
2658         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2659                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2660         list_del_init(&udc->ep[0].ep.ep_list);
2661
2662         /* initially disable all non-ep0 endpoints */
2663         for (tmp = 1; tmp < 15; tmp++) {
2664                 UDC_EP_RX_REG(tmp) = 0;
2665                 UDC_EP_TX_REG(tmp) = 0;
2666         }
2667
2668 #define OMAP_BULK_EP(name,addr) \
2669         buf = omap_ep_setup(name "-bulk", addr, \
2670                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2671 #define OMAP_INT_EP(name,addr, maxp) \
2672         buf = omap_ep_setup(name "-int", addr, \
2673                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2674 #define OMAP_ISO_EP(name,addr, maxp) \
2675         buf = omap_ep_setup(name "-iso", addr, \
2676                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2677
2678         switch (fifo_mode) {
2679         case 0:
2680                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2681                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2682                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2683                 break;
2684         case 1:
2685                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2686                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2687                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2688
2689                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2690                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2691                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2692
2693                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2694                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2695                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2696
2697                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2698                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2699                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2700
2701                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2702                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2703                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2704                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2705
2706                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2707                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2708                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2709                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2710
2711                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2712                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2713
2714                 break;
2715
2716 #ifdef  USE_ISO
2717         case 2:                 /* mixed iso/bulk */
2718                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2719                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2720                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2721                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2722
2723                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2724
2725                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2726                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2727                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2728                 break;
2729         case 3:                 /* mixed bulk/iso */
2730                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2731                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2732                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2733
2734                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2735                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2736                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2737
2738                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2739                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2740                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2741                 break;
2742 #endif
2743
2744         /* add more modes as needed */
2745
2746         default:
2747                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2748                 return -ENODEV;
2749         }
2750         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2751         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2752         return 0;
2753 }
2754
2755 static int __init omap_udc_probe(struct platform_device *pdev)
2756 {
2757         int                     status = -ENODEV;
2758         int                     hmc;
2759         struct otg_transceiver  *xceiv = NULL;
2760         const char              *type = NULL;
2761         struct omap_usb_config  *config = pdev->dev.platform_data;
2762         struct clk              *dc_clk;
2763         struct clk              *hhc_clk;
2764
2765         /* NOTE:  "knows" the order of the resources! */
2766         if (!request_mem_region(pdev->resource[0].start,
2767                         pdev->resource[0].end - pdev->resource[0].start + 1,
2768                         driver_name)) {
2769                 DBG("request_mem_region failed\n");
2770                 return -EBUSY;
2771         }
2772
2773         if (cpu_is_omap16xx()) {
2774                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2775                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2776                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2777                 /* can't use omap_udc_enable_clock yet */
2778                 clk_enable(dc_clk);
2779                 clk_enable(hhc_clk);
2780                 udelay(100);
2781         }
2782
2783         INFO("OMAP UDC rev %d.%d%s\n",
2784                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2785                 config->otg ? ", Mini-AB" : "");
2786
2787         /* use the mode given to us by board init code */
2788         if (cpu_is_omap15xx()) {
2789                 hmc = HMC_1510;
2790                 type = "(unknown)";
2791
2792                 if (machine_is_omap_innovator()) {
2793                         /* just set up software VBUS detect, and then
2794                          * later rig it so we always report VBUS.
2795                          * FIXME without really sensing VBUS, we can't
2796                          * know when to turn PULLUP_EN on/off; and that
2797                          * means we always "need" the 48MHz clock.
2798                          */
2799                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2800
2801                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2802                         tmp |= VBUS_MODE_1510;
2803                         tmp &= ~VBUS_CTRL_1510;
2804                         FUNC_MUX_CTRL_0_REG = tmp;
2805                 }
2806         } else {
2807                 /* The transceiver may package some GPIO logic or handle
2808                  * loopback and/or transceiverless setup; if we find one,
2809                  * use it.  Except for OTG, we don't _need_ to talk to one;
2810                  * but not having one probably means no VBUS detection.
2811                  */
2812                 xceiv = otg_get_transceiver();
2813                 if (xceiv)
2814                         type = xceiv->label;
2815                 else if (config->otg) {
2816                         DBG("OTG requires external transceiver!\n");
2817                         goto cleanup0;
2818                 }
2819
2820                 hmc = HMC_1610;
2821                 switch (hmc) {
2822                 case 0:                 /* POWERUP DEFAULT == 0 */
2823                 case 4:
2824                 case 12:
2825                 case 20:
2826                         if (!cpu_is_omap1710()) {
2827                                 type = "integrated";
2828                                 break;
2829                         }
2830                         /* FALL THROUGH */
2831                 case 3:
2832                 case 11:
2833                 case 16:
2834                 case 19:
2835                 case 25:
2836                         if (!xceiv) {
2837                                 DBG("external transceiver not registered!\n");
2838                                 type = "unknown";
2839                         }
2840                         break;
2841                 case 21:                        /* internal loopback */
2842                         type = "loopback";
2843                         break;
2844                 case 14:                        /* transceiverless */
2845                         if (cpu_is_omap1710())
2846                                 goto bad_on_1710;
2847                         /* FALL THROUGH */
2848                 case 13:
2849                 case 15:
2850                         type = "no";
2851                         break;
2852
2853                 default:
2854 bad_on_1710:
2855                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2856                         goto cleanup0;
2857                 }
2858         }
2859         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2860
2861         /* a "gadget" abstracts/virtualizes the controller */
2862         status = omap_udc_setup(pdev, xceiv);
2863         if (status) {
2864                 goto cleanup0;
2865         }
2866         xceiv = NULL;
2867         // "udc" is now valid
2868         pullup_disable(udc);
2869 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2870         udc->gadget.is_otg = (config->otg != 0);
2871 #endif
2872
2873         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2874         if (UDC_REV_REG >= 0x61)
2875                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2876         else
2877                 udc->clr_halt = UDC_RESET_EP;
2878
2879         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2880         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2881                         SA_SAMPLE_RANDOM, driver_name, udc);
2882         if (status != 0) {
2883                 ERR( "can't get irq %ld, err %d\n",
2884                         pdev->resource[1].start, status);
2885                 goto cleanup1;
2886         }
2887
2888         /* USB "non-iso" IRQ (PIO for all but ep0) */
2889         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2890                         SA_SAMPLE_RANDOM, "omap_udc pio", udc);
2891         if (status != 0) {
2892                 ERR( "can't get irq %ld, err %d\n",
2893                         pdev->resource[2].start, status);
2894                 goto cleanup2;
2895         }
2896 #ifdef  USE_ISO
2897         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2898                         SA_INTERRUPT, "omap_udc iso", udc);
2899         if (status != 0) {
2900                 ERR("can't get irq %ld, err %d\n",
2901                         pdev->resource[3].start, status);
2902                 goto cleanup3;
2903         }
2904 #endif
2905         if (cpu_is_omap16xx()) {
2906                 udc->dc_clk = dc_clk;
2907                 udc->hhc_clk = hhc_clk;
2908                 clk_disable(hhc_clk);
2909                 clk_disable(dc_clk);
2910         }
2911
2912         create_proc_file();
2913         device_add(&udc->gadget.dev);
2914         return 0;
2915
2916 #ifdef  USE_ISO
2917 cleanup3:
2918         free_irq(pdev->resource[2].start, udc);
2919 #endif
2920
2921 cleanup2:
2922         free_irq(pdev->resource[1].start, udc);
2923
2924 cleanup1:
2925         kfree (udc);
2926         udc = NULL;
2927
2928 cleanup0:
2929         if (xceiv)
2930                 put_device(xceiv->dev);
2931
2932         if (cpu_is_omap16xx()) {
2933                 clk_disable(hhc_clk);
2934                 clk_disable(dc_clk);
2935                 clk_put(hhc_clk);
2936                 clk_put(dc_clk);
2937         }
2938
2939         release_mem_region(pdev->resource[0].start,
2940                         pdev->resource[0].end - pdev->resource[0].start + 1);
2941
2942         return status;
2943 }
2944
2945 static int __exit omap_udc_remove(struct platform_device *pdev)
2946 {
2947         DECLARE_COMPLETION(done);
2948
2949         if (!udc)
2950                 return -ENODEV;
2951
2952         udc->done = &done;
2953
2954         pullup_disable(udc);
2955         if (udc->transceiver) {
2956                 put_device(udc->transceiver->dev);
2957                 udc->transceiver = NULL;
2958         }
2959         UDC_SYSCON1_REG = 0;
2960
2961         remove_proc_file();
2962
2963 #ifdef  USE_ISO
2964         free_irq(pdev->resource[3].start, udc);
2965 #endif
2966         free_irq(pdev->resource[2].start, udc);
2967         free_irq(pdev->resource[1].start, udc);
2968
2969         if (udc->dc_clk) {
2970                 if (udc->clk_requested)
2971                         omap_udc_enable_clock(0);
2972                 clk_put(udc->hhc_clk);
2973                 clk_put(udc->dc_clk);
2974         }
2975
2976         release_mem_region(pdev->resource[0].start,
2977                         pdev->resource[0].end - pdev->resource[0].start + 1);
2978
2979         device_unregister(&udc->gadget.dev);
2980         wait_for_completion(&done);
2981
2982         return 0;
2983 }
2984
2985 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
2986  * system is forced into deep sleep
2987  *
2988  * REVISIT we should probably reject suspend requests when there's a host
2989  * session active, rather than disconnecting, at least on boards that can
2990  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
2991  * make host resumes and VBUS detection trigger OMAP wakeup events; that
2992  * may involve talking to an external transceiver (e.g. isp1301).
2993  */
2994
2995 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
2996 {
2997         u32     devstat;
2998
2999         devstat = UDC_DEVSTAT_REG;
3000
3001         /* we're requesting 48 MHz clock if the pullup is enabled
3002          * (== we're attached to the host) and we're not suspended,
3003          * which would prevent entry to deep sleep...
3004          */
3005         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3006                 WARN("session active; suspend requires disconnect\n");
3007                 omap_pullup(&udc->gadget, 0);
3008         }
3009
3010         udc->gadget.dev.power.power_state = PMSG_SUSPEND;
3011         udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
3012         return 0;
3013 }
3014
3015 static int omap_udc_resume(struct platform_device *dev)
3016 {
3017         DBG("resume + wakeup/SRP\n");
3018         omap_pullup(&udc->gadget, 1);
3019
3020         /* maybe the host would enumerate us if we nudged it */
3021         msleep(100);
3022         return omap_wakeup(&udc->gadget);
3023 }
3024
3025 /*-------------------------------------------------------------------------*/
3026
3027 static struct platform_driver udc_driver = {
3028         .probe          = omap_udc_probe,
3029         .remove         = __exit_p(omap_udc_remove),
3030         .suspend        = omap_udc_suspend,
3031         .resume         = omap_udc_resume,
3032         .driver         = {
3033                 .owner  = THIS_MODULE,
3034                 .name   = (char *) driver_name,
3035         },
3036 };
3037
3038 static int __init udc_init(void)
3039 {
3040         INFO("%s, version: " DRIVER_VERSION
3041 #ifdef  USE_ISO
3042                 " (iso)"
3043 #endif
3044                 "%s\n", driver_desc,
3045                 use_dma ?  " (dma)" : "");
3046         return platform_driver_register(&udc_driver);
3047 }
3048 module_init(udc_init);
3049
3050 static void __exit udc_exit(void)
3051 {
3052         platform_driver_unregister(&udc_driver);
3053 }
3054 module_exit(udc_exit);
3055
3056 MODULE_DESCRIPTION(DRIVER_DESC);
3057 MODULE_LICENSE("GPL");
3058