drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #undef  DEBUG
  25 #undef  VERBOSE
  26
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/ioport.h>
  30 #include <linux/types.h>
  31 #include <linux/errno.h>
  32 #include <linux/delay.h>
  33 #include <linux/slab.h>
  34 #include <linux/init.h>
  35 #include <linux/timer.h>
  36 #include <linux/list.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/proc_fs.h>
  39 #include <linux/mm.h>
  40 #include <linux/moduleparam.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/usb/ch9.h>
  43 #include <linux/usb/gadget.h>
  44 #include <linux/usb/otg.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/clk.h>
  47
  48 #include <asm/byteorder.h>
  49 #include <asm/io.h>
  50 #include <asm/irq.h>
  51 #include <asm/system.h>
  52 #include <asm/unaligned.h>
  53 #include <asm/mach-types.h>
  54
  55 #include <asm/arch/dma.h>
  56 #include <asm/arch/usb.h>
  57 #include <asm/arch/control.h>
  58
  59 #include "omap_udc.h"
  60
  61 #undef  USB_TRACE
  62
  63 /* bulk DMA seems to be behaving for both IN and OUT */
  64 #define USE_DMA
  65
  66 /* ISO too */
  67 #define USE_ISO
  68
  69 #define DRIVER_DESC     "OMAP UDC driver"
  70 #define DRIVER_VERSION  "4 October 2004"
  71
  72 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  73
  74 #define OMAP2_DMA_CH(ch)        (((ch) - 1) << 1)
  75 #define OMAP24XX_DMA(name, ch)  (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
  76
  77 /*
  78  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  79  * D+ pullup to allow enumeration.  That's too early for the gadget
  80  * framework to use from usb_endpoint_enable(), which happens after
  81  * enumeration as part of activating an interface.  (But if we add an
  82  * optional new "UDC not yet running" state to the gadget driver model,
  83  * even just during driver binding, the endpoint autoconfig logic is the
  84  * natural spot to manufacture new endpoints.)
  85  *
  86  * So instead of using endpoint enable calls to control the hardware setup,
  87  * this driver defines a "fifo mode" parameter.  It's used during driver
  88  * initialization to choose among a set of pre-defined endpoint configs.
  89  * See omap_udc_setup() for available modes, or to add others.  That code
  90  * lives in an init section, so use this driver as a module if you need
  91  * to change the fifo mode after the kernel boots.
  92  *
  93  * Gadget drivers normally ignore endpoints they don't care about, and
  94  * won't include them in configuration descriptors.  That means only
  95  * misbehaving hosts would even notice they exist.
  96  */
  97 #ifdef  USE_ISO
  98 static unsigned fifo_mode = 3;
  99 #else
 100 static unsigned fifo_mode = 0;
 101 #endif
 102
 103 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 104  * boot parameter "omap_udc:fifo_mode=42"
 105  */
 106 module_param (fifo_mode, uint, 0);
 107 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
 108
 109 #ifdef  USE_DMA
 110 static unsigned use_dma = 1;
 111
 112 /* "modprobe omap_udc use_dma=y", or else as a kernel
 113  * boot parameter "omap_udc:use_dma=y"
 114  */
 115 module_param (use_dma, bool, 0);
 116 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 117 #else   /* !USE_DMA */
 118
 119 /* save a bit of code */
 120 #define use_dma         0
 121 #endif  /* !USE_DMA */
 122
 123
 124 static const char driver_name [] = "omap_udc";
 125 static const char driver_desc [] = DRIVER_DESC;
 126
 127 /*-------------------------------------------------------------------------*/
 128
 129 /* there's a notion of "current endpoint" for modifying endpoint
 130  * state, and PIO access to its FIFO.
 131  */
 132
 133 static void use_ep(struct omap_ep *ep, u16 select)
 134 {
 135         u16     num = ep->bEndpointAddress & 0x0f;
 136
 137         if (ep->bEndpointAddress & USB_DIR_IN)
 138                 num |= UDC_EP_DIR;
 139         UDC_EP_NUM_REG = num | select;
 140         /* when select, MUST deselect later !! */
 141 }
 142
 143 static inline void deselect_ep(void)
 144 {
 145         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
 146         /* 6 wait states before TX will happen */
 147 }
 148
 149 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 150
 151 /*-------------------------------------------------------------------------*/
 152
 153 static int omap_ep_enable(struct usb_ep *_ep,
 154                 const struct usb_endpoint_descriptor *desc)
 155 {
 156         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 157         struct omap_udc *udc;
 158         unsigned long   flags;
 159         u16             maxp;
 160
 161         /* catch various bogus parameters */
 162         if (!_ep || !desc || ep->desc
 163                         || desc->bDescriptorType != USB_DT_ENDPOINT
 164                         || ep->bEndpointAddress != desc->bEndpointAddress
 165                         || ep->maxpacket < le16_to_cpu
 166                                                 (desc->wMaxPacketSize)) {
 167                 DBG("%s, bad ep or descriptor\n", __func__);
 168                 return -EINVAL;
 169         }
 170         maxp = le16_to_cpu (desc->wMaxPacketSize);
 171         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 172                                 && maxp != ep->maxpacket)
 173                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 174                         || !desc->wMaxPacketSize) {
 175                 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
 176                 return -ERANGE;
 177         }
 178
 179 #ifdef  USE_ISO
 180         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 181                                 && desc->bInterval != 1)) {
 182                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 183                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 184                                 1 << (desc->bInterval - 1));
 185                 return -EDOM;
 186         }
 187 #else
 188         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 189                 DBG("%s, ISO nyet\n", _ep->name);
 190                 return -EDOM;
 191         }
 192 #endif
 193
 194         /* xfer types must match, except that interrupt ~= bulk */
 195         if (ep->bmAttributes != desc->bmAttributes
 196                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 197                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 198                 DBG("%s, %s type mismatch\n", __func__, _ep->name);
 199                 return -EINVAL;
 200         }
 201
 202         udc = ep->udc;
 203         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 204                 DBG("%s, bogus device state\n", __func__);
 205                 return -ESHUTDOWN;
 206         }
 207
 208         spin_lock_irqsave(&udc->lock, flags);
 209
 210         ep->desc = desc;
 211         ep->irqs = 0;
 212         ep->stopped = 0;
 213         ep->ep.maxpacket = maxp;
 214
 215         /* set endpoint to initial state */
 216         ep->dma_channel = 0;
 217         ep->has_dma = 0;
 218         ep->lch = -1;
 219         use_ep(ep, UDC_EP_SEL);
 220         UDC_CTRL_REG = udc->clr_halt;
 221         ep->ackwait = 0;
 222         deselect_ep();
 223
 224         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 225                 list_add(&ep->iso, &udc->iso);
 226
 227         /* maybe assign a DMA channel to this endpoint */
 228         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 229                 /* FIXME ISO can dma, but prefers first channel */
 230                 dma_channel_claim(ep, 0);
 231
 232         /* PIO OUT may RX packets */
 233         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 234                         && !ep->has_dma
 235                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 236                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 237                 ep->ackwait = 1 + ep->double_buf;
 238         }
 239
 240         spin_unlock_irqrestore(&udc->lock, flags);
 241         VDBG("%s enabled\n", _ep->name);
 242         return 0;
 243 }
 244
 245 static void nuke(struct omap_ep *, int status);
 246
 247 static int omap_ep_disable(struct usb_ep *_ep)
 248 {
 249         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 250         unsigned long   flags;
 251
 252         if (!_ep || !ep->desc) {
 253                 DBG("%s, %s not enabled\n", __func__,
 254                         _ep ? ep->ep.name : NULL);
 255                 return -EINVAL;
 256         }
 257
 258         spin_lock_irqsave(&ep->udc->lock, flags);
 259         ep->desc = NULL;
 260         nuke (ep, -ESHUTDOWN);
 261         ep->ep.maxpacket = ep->maxpacket;
 262         ep->has_dma = 0;
 263         UDC_CTRL_REG = UDC_SET_HALT;
 264         list_del_init(&ep->iso);
 265         del_timer(&ep->timer);
 266
 267         spin_unlock_irqrestore(&ep->udc->lock, flags);
 268
 269         VDBG("%s disabled\n", _ep->name);
 270         return 0;
 271 }
 272
 273 /*-------------------------------------------------------------------------*/
 274
 275 static struct usb_request *
 276 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 277 {
 278         struct omap_req *req;
 279
 280         req = kzalloc(sizeof(*req), gfp_flags);
 281         if (req) {
 282                 req->req.dma = DMA_ADDR_INVALID;
 283                 INIT_LIST_HEAD (&req->queue);
 284         }
 285         return &req->req;
 286 }
 287
 288 static void
 289 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 290 {
 291         struct omap_req *req = container_of(_req, struct omap_req, req);
 292
 293         if (_req)
 294                 kfree (req);
 295 }
 296
 297 /*-------------------------------------------------------------------------*/
 298
 299 static void
 300 done(struct omap_ep *ep, struct omap_req *req, int status)
 301 {
 302         unsigned                stopped = ep->stopped;
 303
 304         list_del_init(&req->queue);
 305
 306         if (req->req.status == -EINPROGRESS)
 307                 req->req.status = status;
 308         else
 309                 status = req->req.status;
 310
 311         if (use_dma && ep->has_dma) {
 312                 if (req->mapped) {
 313                         dma_unmap_single(ep->udc->gadget.dev.parent,
 314                                 req->req.dma, req->req.length,
 315                                 (ep->bEndpointAddress & USB_DIR_IN)
 316                                         ? DMA_TO_DEVICE
 317                                         : DMA_FROM_DEVICE);
 318                         req->req.dma = DMA_ADDR_INVALID;
 319                         req->mapped = 0;
 320                 } else
 321                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 322                                 req->req.dma, req->req.length,
 323                                 (ep->bEndpointAddress & USB_DIR_IN)
 324                                         ? DMA_TO_DEVICE
 325                                         : DMA_FROM_DEVICE);
 326         }
 327
 328 #ifndef USB_TRACE
 329         if (status && status != -ESHUTDOWN)
 330 #endif
 331                 VDBG("complete %s req %p stat %d len %u/%u\n",
 332                         ep->ep.name, &req->req, status,
 333                         req->req.actual, req->req.length);
 334
 335         /* don't modify queue heads during completion callback */
 336         ep->stopped = 1;
 337         spin_unlock(&ep->udc->lock);
 338         req->req.complete(&ep->ep, &req->req);
 339         spin_lock(&ep->udc->lock);
 340         ep->stopped = stopped;
 341 }
 342
 343 /*-------------------------------------------------------------------------*/
 344
 345 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 346 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 347
 348 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 349 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 350
 351 static inline int
 352 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 353 {
 354         unsigned        len;
 355         u16             *wp;
 356
 357         len = min(req->req.length - req->req.actual, max);
 358         req->req.actual += len;
 359
 360         max = len;
 361         if (likely((((int)buf) & 1) == 0)) {
 362                 wp = (u16 *)buf;
 363                 while (max >= 2) {
 364                         UDC_DATA_REG = *wp++;
 365                         max -= 2;
 366                 }
 367                 buf = (u8 *)wp;
 368         }
 369         while (max--)
 370                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
 371         return len;
 372 }
 373
 374 // FIXME change r/w fifo calling convention
 375
 376
 377 // return:  0 = still running, 1 = completed, negative = errno
 378 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 379 {
 380         u8              *buf;
 381         unsigned        count;
 382         int             is_last;
 383         u16             ep_stat;
 384
 385         buf = req->req.buf + req->req.actual;
 386         prefetch(buf);
 387
 388         /* PIO-IN isn't double buffered except for iso */
 389         ep_stat = UDC_STAT_FLG_REG;
 390         if (ep_stat & UDC_FIFO_UNWRITABLE)
 391                 return 0;
 392
 393         count = ep->ep.maxpacket;
 394         count = write_packet(buf, req, count);
 395         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 396         ep->ackwait = 1;
 397
 398         /* last packet is often short (sometimes a zlp) */
 399         if (count != ep->ep.maxpacket)
 400                 is_last = 1;
 401         else if (req->req.length == req->req.actual
 402                         && !req->req.zero)
 403                 is_last = 1;
 404         else
 405                 is_last = 0;
 406
 407         /* NOTE:  requests complete when all IN data is in a
 408          * FIFO (or sometimes later, if a zlp was needed).
 409          * Use usb_ep_fifo_status() where needed.
 410          */
 411         if (is_last)
 412                 done(ep, req, 0);
 413         return is_last;
 414 }
 415
 416 static inline int
 417 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 418 {
 419         unsigned        len;
 420         u16             *wp;
 421
 422         len = min(req->req.length - req->req.actual, avail);
 423         req->req.actual += len;
 424         avail = len;
 425
 426         if (likely((((int)buf) & 1) == 0)) {
 427                 wp = (u16 *)buf;
 428                 while (avail >= 2) {
 429                         *wp++ = UDC_DATA_REG;
 430                         avail -= 2;
 431                 }
 432                 buf = (u8 *)wp;
 433         }
 434         while (avail--)
 435                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
 436         return len;
 437 }
 438
 439 // return:  0 = still running, 1 = queue empty, negative = errno
 440 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 441 {
 442         u8              *buf;
 443         unsigned        count, avail;
 444         int             is_last;
 445
 446         buf = req->req.buf + req->req.actual;
 447         prefetchw(buf);
 448
 449         for (;;) {
 450                 u16     ep_stat = UDC_STAT_FLG_REG;
 451
 452                 is_last = 0;
 453                 if (ep_stat & FIFO_EMPTY) {
 454                         if (!ep->double_buf)
 455                                 break;
 456                         ep->fnf = 1;
 457                 }
 458                 if (ep_stat & UDC_EP_HALTED)
 459                         break;
 460
 461                 if (ep_stat & UDC_FIFO_FULL)
 462                         avail = ep->ep.maxpacket;
 463                 else  {
 464                         avail = UDC_RXFSTAT_REG;
 465                         ep->fnf = ep->double_buf;
 466                 }
 467                 count = read_packet(buf, req, avail);
 468
 469                 /* partial packet reads may not be errors */
 470                 if (count < ep->ep.maxpacket) {
 471                         is_last = 1;
 472                         /* overflowed this request?  flush extra data */
 473                         if (count != avail) {
 474                                 req->req.status = -EOVERFLOW;
 475                                 avail -= count;
 476                                 while (avail--)
 477                                         (void) *(volatile u8 *)&UDC_DATA_REG;
 478                         }
 479                 } else if (req->req.length == req->req.actual)
 480                         is_last = 1;
 481                 else
 482                         is_last = 0;
 483
 484                 if (!ep->bEndpointAddress)
 485                         break;
 486                 if (is_last)
 487                         done(ep, req, 0);
 488                 break;
 489         }
 490         return is_last;
 491 }
 492
 493 /*-------------------------------------------------------------------------*/
 494
 495 static inline dma_addr_t dma_csac(unsigned lch)
 496 {
 497         dma_addr_t      csac;
 498
 499         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 500          * read before the DMA controller finished disabling the channel.
 501          */
 502         csac = OMAP_DMA_CSAC_REG(lch);
 503         if (csac == 0)
 504                 csac = OMAP_DMA_CSAC_REG(lch);
 505         return csac;
 506 }
 507
 508 static inline dma_addr_t dma_cdac(unsigned lch)
 509 {
 510         dma_addr_t      cdac;
 511
 512         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 513          * read before the DMA controller finished disabling the channel.
 514          */
 515         cdac = OMAP_DMA_CDAC_REG(lch);
 516         if (cdac == 0)
 517                 cdac = OMAP_DMA_CDAC_REG(lch);
 518         return cdac;
 519 }
 520
 521 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 522 {
 523         dma_addr_t      end;
 524
 525         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 526          * the last transfer's bytecount by more than a FIFO's worth.
 527          */
 528         if (cpu_is_omap15xx())
 529                 return 0;
 530
 531         end = dma_csac(ep->lch);
 532         if (end == ep->dma_counter)
 533                 return 0;
 534
 535         end |= start & (0xffff << 16);
 536         if (end < start)
 537                 end += 0x10000;
 538         return end - start;
 539 }
 540
 541 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
 542                 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
 543                 : dma_cdac(x))
 544
 545 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 546 {
 547         dma_addr_t      end;
 548
 549         end = DMA_DEST_LAST(ep->lch);
 550         if (end == ep->dma_counter)
 551                 return 0;
 552
 553         end |= start & (0xffff << 16);
 554         if (cpu_is_omap15xx())
 555                 end++;
 556         if (end < start)
 557                 end += 0x10000;
 558         return end - start;
 559 }
 560
 561
 562 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 563  * When DMA completion isn't request completion, the UDC continues with
 564  * the next DMA transfer for that USB transfer.
 565  */
 566
 567 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 568 {
 569         u16             txdma_ctrl;
 570         unsigned        length = req->req.length - req->req.actual;
 571         const int       sync_mode = cpu_is_omap15xx()
 572                                 ? OMAP_DMA_SYNC_FRAME
 573                                 : OMAP_DMA_SYNC_ELEMENT;
 574         int             dma_trigger = 0;
 575
 576         if (cpu_is_omap24xx())
 577                 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
 578
 579         /* measure length in either bytes or packets */
 580         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 581                         || (cpu_is_omap24xx() && length < ep->maxpacket)
 582                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 583                 txdma_ctrl = UDC_TXN_EOT | length;
 584                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 585                                 length, 1, sync_mode, dma_trigger, 0);
 586         } else {
 587                 length = min(length / ep->maxpacket,
 588                                 (unsigned) UDC_TXN_TSC + 1);
 589                 txdma_ctrl = length;
 590                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 591                                 ep->ep.maxpacket >> 1, length, sync_mode,
 592                                 dma_trigger, 0);
 593                 length *= ep->maxpacket;
 594         }
 595         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 596                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 597                 0, 0);
 598
 599         omap_start_dma(ep->lch);
 600         ep->dma_counter = dma_csac(ep->lch);
 601         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
 602         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
 603         req->dma_bytes = length;
 604 }
 605
 606 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 607 {
 608         if (status == 0) {
 609                 req->req.actual += req->dma_bytes;
 610
 611                 /* return if this request needs to send data or zlp */
 612                 if (req->req.actual < req->req.length)
 613                         return;
 614                 if (req->req.zero
 615                                 && req->dma_bytes != 0
 616                                 && (req->req.actual % ep->maxpacket) == 0)
 617                         return;
 618         } else
 619                 req->req.actual += dma_src_len(ep, req->req.dma
 620                                                         + req->req.actual);
 621
 622         /* tx completion */
 623         omap_stop_dma(ep->lch);
 624         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
 625         done(ep, req, status);
 626 }
 627
 628 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 629 {
 630         unsigned packets = req->req.length - req->req.actual;
 631         int dma_trigger = 0;
 632
 633         if (cpu_is_omap24xx())
 634                 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
 635
 636         /* NOTE:  we filtered out "short reads" before, so we know
 637          * the buffer has only whole numbers of packets.
 638          * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
 639          */
 640         if (cpu_is_omap24xx() && packets < ep->maxpacket) {
 641                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 642                                 packets, 1, OMAP_DMA_SYNC_ELEMENT,
 643                                 dma_trigger, 0);
 644                 req->dma_bytes = packets;
 645         } else {
 646                 /* set up this DMA transfer, enable the fifo, start */
 647                 packets /= ep->ep.maxpacket;
 648                 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 649                 req->dma_bytes = packets * ep->ep.maxpacket;
 650                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 651                                 ep->ep.maxpacket >> 1, packets,
 652                                 OMAP_DMA_SYNC_ELEMENT,
 653                                 dma_trigger, 0);
 654         }
 655         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 656                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 657                 0, 0);
 658         ep->dma_counter = DMA_DEST_LAST(ep->lch);
 659
 660         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
 661         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
 662         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
 663         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 664
 665         omap_start_dma(ep->lch);
 666 }
 667
 668 static void
 669 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 670 {
 671         u16     count;
 672
 673         if (status == 0)
 674                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 675         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 676         count += req->req.actual;
 677         if (one)
 678                 count--;
 679         if (count <= req->req.length)
 680                 req->req.actual = count;
 681
 682         if (count != req->dma_bytes || status)
 683                 omap_stop_dma(ep->lch);
 684
 685         /* if this wasn't short, request may need another transfer */
 686         else if (req->req.actual < req->req.length)
 687                 return;
 688
 689         /* rx completion */
 690         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
 691         done(ep, req, status);
 692 }
 693
 694 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 695 {
 696         u16             dman_stat = UDC_DMAN_STAT_REG;
 697         struct omap_ep  *ep;
 698         struct omap_req *req;
 699
 700         /* IN dma: tx to host */
 701         if (irq_src & UDC_TXN_DONE) {
 702                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 703                 ep->irqs++;
 704                 /* can see TXN_DONE after dma abort */
 705                 if (!list_empty(&ep->queue)) {
 706                         req = container_of(ep->queue.next,
 707                                                 struct omap_req, queue);
 708                         finish_in_dma(ep, req, 0);
 709                 }
 710                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
 711
 712                 if (!list_empty (&ep->queue)) {
 713                         req = container_of(ep->queue.next,
 714                                         struct omap_req, queue);
 715                         next_in_dma(ep, req);
 716                 }
 717         }
 718
 719         /* OUT dma: rx from host */
 720         if (irq_src & UDC_RXN_EOT) {
 721                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 722                 ep->irqs++;
 723                 /* can see RXN_EOT after dma abort */
 724                 if (!list_empty(&ep->queue)) {
 725                         req = container_of(ep->queue.next,
 726                                         struct omap_req, queue);
 727                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 728                 }
 729                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
 730
 731                 if (!list_empty (&ep->queue)) {
 732                         req = container_of(ep->queue.next,
 733                                         struct omap_req, queue);
 734                         next_out_dma(ep, req);
 735                 }
 736         }
 737
 738         if (irq_src & UDC_RXN_CNT) {
 739                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 740                 ep->irqs++;
 741                 /* omap15xx does this unasked... */
 742                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 743                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
 744         }
 745 }
 746
 747 static void dma_error(int lch, u16 ch_status, void *data)
 748 {
 749         struct omap_ep  *ep = data;
 750
 751         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 752         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 753         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 754
 755         /* complete current transfer ... */
 756 }
 757
 758 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 759 {
 760         u16     reg;
 761         int     status, restart, is_in;
 762         int     dma_channel;
 763
 764         is_in = ep->bEndpointAddress & USB_DIR_IN;
 765         if (is_in)
 766                 reg = UDC_TXDMA_CFG_REG;
 767         else
 768                 reg = UDC_RXDMA_CFG_REG;
 769         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 770
 771         ep->dma_channel = 0;
 772         ep->lch = -1;
 773         if (channel == 0 || channel > 3) {
 774                 if ((reg & 0x0f00) == 0)
 775                         channel = 3;
 776                 else if ((reg & 0x00f0) == 0)
 777                         channel = 2;
 778                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 779                         channel = 1;
 780                 else {
 781                         status = -EMLINK;
 782                         goto just_restart;
 783                 }
 784         }
 785         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 786         ep->dma_channel = channel;
 787
 788         if (is_in) {
 789                 if (cpu_is_omap24xx())
 790                         dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
 791                 else
 792                         dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
 793                 status = omap_request_dma(dma_channel,
 794                         ep->ep.name, dma_error, ep, &ep->lch);
 795                 if (status == 0) {
 796                         UDC_TXDMA_CFG_REG = reg;
 797                         /* EMIFF or SDRC */
 798                         omap_set_dma_src_burst_mode(ep->lch,
 799                                                 OMAP_DMA_DATA_BURST_4);
 800                         omap_set_dma_src_data_pack(ep->lch, 1);
 801                         /* TIPB */
 802                         omap_set_dma_dest_params(ep->lch,
 803                                 OMAP_DMA_PORT_TIPB,
 804                                 OMAP_DMA_AMODE_CONSTANT,
 805                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 806                                 0, 0);
 807                 }
 808         } else {
 809                 if (cpu_is_omap24xx())
 810                         dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
 811                 else
 812                         dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
 813
 814                 status = omap_request_dma(dma_channel,
 815                         ep->ep.name, dma_error, ep, &ep->lch);
 816                 if (status == 0) {
 817                         UDC_RXDMA_CFG_REG = reg;
 818                         /* TIPB */
 819                         omap_set_dma_src_params(ep->lch,
 820                                 OMAP_DMA_PORT_TIPB,
 821                                 OMAP_DMA_AMODE_CONSTANT,
 822                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 823                                 0, 0);
 824                         /* EMIFF or SDRC */
 825                         omap_set_dma_dest_burst_mode(ep->lch,
 826                                                 OMAP_DMA_DATA_BURST_4);
 827                         omap_set_dma_dest_data_pack(ep->lch, 1);
 828                 }
 829         }
 830         if (status)
 831                 ep->dma_channel = 0;
 832         else {
 833                 ep->has_dma = 1;
 834                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 835
 836                 /* channel type P: hw synch (fifo) */
 837                 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
 838                         OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
 839         }
 840
 841 just_restart:
 842         /* restart any queue, even if the claim failed  */
 843         restart = !ep->stopped && !list_empty(&ep->queue);
 844
 845         if (status)
 846                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 847                         restart ? " (restart)" : "");
 848         else
 849                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 850                         is_in ? 't' : 'r',
 851                         ep->dma_channel - 1, ep->lch,
 852                         restart ? " (restart)" : "");
 853
 854         if (restart) {
 855                 struct omap_req *req;
 856                 req = container_of(ep->queue.next, struct omap_req, queue);
 857                 if (ep->has_dma)
 858                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 859                 else {
 860                         use_ep(ep, UDC_EP_SEL);
 861                         (is_in ? write_fifo : read_fifo)(ep, req);
 862                         deselect_ep();
 863                         if (!is_in) {
 864                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 865                                 ep->ackwait = 1 + ep->double_buf;
 866                         }
 867                         /* IN: 6 wait states before it'll tx */
 868                 }
 869         }
 870 }
 871
 872 static void dma_channel_release(struct omap_ep *ep)
 873 {
 874         int             shift = 4 * (ep->dma_channel - 1);
 875         u16             mask = 0x0f << shift;
 876         struct omap_req *req;
 877         int             active;
 878
 879         /* abort any active usb transfer request */
 880         if (!list_empty(&ep->queue))
 881                 req = container_of(ep->queue.next, struct omap_req, queue);
 882         else
 883                 req = NULL;
 884
 885         active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
 886
 887         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 888                         active ? "active" : "idle",
 889                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 890                         ep->dma_channel - 1, req);
 891
 892         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 893          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 894          */
 895
 896         /* wait till current packet DMA finishes, and fifo empties */
 897         if (ep->bEndpointAddress & USB_DIR_IN) {
 898                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 899
 900                 if (req) {
 901                         finish_in_dma(ep, req, -ECONNRESET);
 902
 903                         /* clear FIFO; hosts probably won't empty it */
 904                         use_ep(ep, UDC_EP_SEL);
 905                         UDC_CTRL_REG = UDC_CLR_EP;
 906                         deselect_ep();
 907                 }
 908                 while (UDC_TXDMA_CFG_REG & mask)
 909                         udelay(10);
 910         } else {
 911                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 912
 913                 /* dma empties the fifo */
 914                 while (UDC_RXDMA_CFG_REG & mask)
 915                         udelay(10);
 916                 if (req)
 917                         finish_out_dma(ep, req, -ECONNRESET, 0);
 918         }
 919         omap_free_dma(ep->lch);
 920         ep->dma_channel = 0;
 921         ep->lch = -1;
 922         /* has_dma still set, till endpoint is fully quiesced */
 923 }
 924
 925
 926 /*-------------------------------------------------------------------------*/
 927
 928 static int
 929 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 930 {
 931         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 932         struct omap_req *req = container_of(_req, struct omap_req, req);
 933         struct omap_udc *udc;
 934         unsigned long   flags;
 935         int             is_iso = 0;
 936
 937         /* catch various bogus parameters */
 938         if (!_req || !req->req.complete || !req->req.buf
 939                         || !list_empty(&req->queue)) {
 940                 DBG("%s, bad params\n", __func__);
 941                 return -EINVAL;
 942         }
 943         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 944                 DBG("%s, bad ep\n", __func__);
 945                 return -EINVAL;
 946         }
 947         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 948                 if (req->req.length > ep->ep.maxpacket)
 949                         return -EMSGSIZE;
 950                 is_iso = 1;
 951         }
 952
 953         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 954          * have a hard time with partial packet reads...  reject it.
 955          * Except OMAP2 can handle the small packets.
 956          */
 957         if (use_dma
 958                         && ep->has_dma
 959                         && ep->bEndpointAddress != 0
 960                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 961                         && !cpu_class_is_omap2()
 962                         && (req->req.length % ep->ep.maxpacket) != 0) {
 963                 DBG("%s, no partial packet OUT reads\n", __func__);
 964                 return -EMSGSIZE;
 965         }
 966
 967         udc = ep->udc;
 968         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 969                 return -ESHUTDOWN;
 970
 971         if (use_dma && ep->has_dma) {
 972                 if (req->req.dma == DMA_ADDR_INVALID) {
 973                         req->req.dma = dma_map_single(
 974                                 ep->udc->gadget.dev.parent,
 975                                 req->req.buf,
 976                                 req->req.length,
 977                                 (ep->bEndpointAddress & USB_DIR_IN)
 978                                         ? DMA_TO_DEVICE
 979                                         : DMA_FROM_DEVICE);
 980                         req->mapped = 1;
 981                 } else {
 982                         dma_sync_single_for_device(
 983                                 ep->udc->gadget.dev.parent,
 984                                 req->req.dma, req->req.length,
 985                                 (ep->bEndpointAddress & USB_DIR_IN)
 986                                         ? DMA_TO_DEVICE
 987                                         : DMA_FROM_DEVICE);
 988                         req->mapped = 0;
 989                 }
 990         }
 991
 992         VDBG("%s queue req %p, len %d buf %p\n",
 993                 ep->ep.name, _req, _req->length, _req->buf);
 994
 995         spin_lock_irqsave(&udc->lock, flags);
 996
 997         req->req.status = -EINPROGRESS;
 998         req->req.actual = 0;
 999
1000         /* maybe kickstart non-iso i/o queues */
1001         if (is_iso)
1002                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1003         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1004                 int     is_in;
1005
1006                 if (ep->bEndpointAddress == 0) {
1007                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1008                                 spin_unlock_irqrestore(&udc->lock, flags);
1009                                 return -EL2HLT;
1010                         }
1011
1012                         /* empty DATA stage? */
1013                         is_in = udc->ep0_in;
1014                         if (!req->req.length) {
1015
1016                                 /* chip became CONFIGURED or ADDRESSED
1017                                  * earlier; drivers may already have queued
1018                                  * requests to non-control endpoints
1019                                  */
1020                                 if (udc->ep0_set_config) {
1021                                         u16     irq_en = UDC_IRQ_EN_REG;
1022
1023                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1024                                         if (!udc->ep0_reset_config)
1025                                                 irq_en |= UDC_EPN_RX_IE
1026                                                         | UDC_EPN_TX_IE;
1027                                         UDC_IRQ_EN_REG = irq_en;
1028                                 }
1029
1030                                 /* STATUS for zero length DATA stages is
1031                                  * always an IN ... even for IN transfers,
1032                                  * a weird case which seem to stall OMAP.
1033                                  */
1034                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1035                                 UDC_CTRL_REG = UDC_CLR_EP;
1036                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1037                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1038
1039                                 /* cleanup */
1040                                 udc->ep0_pending = 0;
1041                                 done(ep, req, 0);
1042                                 req = NULL;
1043
1044                         /* non-empty DATA stage */
1045                         } else if (is_in) {
1046                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1047                         } else {
1048                                 if (udc->ep0_setup)
1049                                         goto irq_wait;
1050                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1051                         }
1052                 } else {
1053                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1054                         if (!ep->has_dma)
1055                                 use_ep(ep, UDC_EP_SEL);
1056                         /* if ISO: SOF IRQs must be enabled/disabled! */
1057                 }
1058
1059                 if (ep->has_dma)
1060                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1061                 else if (req) {
1062                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1063                                 req = NULL;
1064                         deselect_ep();
1065                         if (!is_in) {
1066                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1067                                 ep->ackwait = 1 + ep->double_buf;
1068                         }
1069                         /* IN: 6 wait states before it'll tx */
1070                 }
1071         }
1072
1073 irq_wait:
1074         /* irq handler advances the queue */
1075         if (req != NULL)
1076                 list_add_tail(&req->queue, &ep->queue);
1077         spin_unlock_irqrestore(&udc->lock, flags);
1078
1079         return 0;
1080 }
1081
1082 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1083 {
1084         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1085         struct omap_req *req;
1086         unsigned long   flags;
1087
1088         if (!_ep || !_req)
1089                 return -EINVAL;
1090
1091         spin_lock_irqsave(&ep->udc->lock, flags);
1092
1093         /* make sure it's actually queued on this endpoint */
1094         list_for_each_entry (req, &ep->queue, queue) {
1095                 if (&req->req == _req)
1096                         break;
1097         }
1098         if (&req->req != _req) {
1099                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1100                 return -EINVAL;
1101         }
1102
1103         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1104                 int channel = ep->dma_channel;
1105
1106                 /* releasing the channel cancels the request,
1107                  * reclaiming the channel restarts the queue
1108                  */
1109                 dma_channel_release(ep);
1110                 dma_channel_claim(ep, channel);
1111         } else
1112                 done(ep, req, -ECONNRESET);
1113         spin_unlock_irqrestore(&ep->udc->lock, flags);
1114         return 0;
1115 }
1116
1117 /*-------------------------------------------------------------------------*/
1118
1119 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1120 {
1121         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1122         unsigned long   flags;
1123         int             status = -EOPNOTSUPP;
1124
1125         spin_lock_irqsave(&ep->udc->lock, flags);
1126
1127         /* just use protocol stalls for ep0; real halts are annoying */
1128         if (ep->bEndpointAddress == 0) {
1129                 if (!ep->udc->ep0_pending)
1130                         status = -EINVAL;
1131                 else if (value) {
1132                         if (ep->udc->ep0_set_config) {
1133                                 WARN("error changing config?\n");
1134                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1135                         }
1136                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1137                         ep->udc->ep0_pending = 0;
1138                         status = 0;
1139                 } else /* NOP */
1140                         status = 0;
1141
1142         /* otherwise, all active non-ISO endpoints can halt */
1143         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1144
1145                 /* IN endpoints must already be idle */
1146                 if ((ep->bEndpointAddress & USB_DIR_IN)
1147                                 && !list_empty(&ep->queue)) {
1148                         status = -EAGAIN;
1149                         goto done;
1150                 }
1151
1152                 if (value) {
1153                         int     channel;
1154
1155                         if (use_dma && ep->dma_channel
1156                                         && !list_empty(&ep->queue)) {
1157                                 channel = ep->dma_channel;
1158                                 dma_channel_release(ep);
1159                         } else
1160                                 channel = 0;
1161
1162                         use_ep(ep, UDC_EP_SEL);
1163                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1164                                 UDC_CTRL_REG = UDC_SET_HALT;
1165                                 status = 0;
1166                         } else
1167                                 status = -EAGAIN;
1168                         deselect_ep();
1169
1170                         if (channel)
1171                                 dma_channel_claim(ep, channel);
1172                 } else {
1173                         use_ep(ep, 0);
1174                         UDC_CTRL_REG = ep->udc->clr_halt;
1175                         ep->ackwait = 0;
1176                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1177                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1178                                 ep->ackwait = 1 + ep->double_buf;
1179                         }
1180                 }
1181         }
1182 done:
1183         VDBG("%s %s halt stat %d\n", ep->ep.name,
1184                 value ? "set" : "clear", status);
1185
1186         spin_unlock_irqrestore(&ep->udc->lock, flags);
1187         return status;
1188 }
1189
1190 static struct usb_ep_ops omap_ep_ops = {
1191         .enable         = omap_ep_enable,
1192         .disable        = omap_ep_disable,
1193
1194         .alloc_request  = omap_alloc_request,
1195         .free_request   = omap_free_request,
1196
1197         .queue          = omap_ep_queue,
1198         .dequeue        = omap_ep_dequeue,
1199
1200         .set_halt       = omap_ep_set_halt,
1201         // fifo_status ... report bytes in fifo
1202         // fifo_flush ... flush fifo
1203 };
1204
1205 /*-------------------------------------------------------------------------*/
1206
1207 static int omap_get_frame(struct usb_gadget *gadget)
1208 {
1209         u16     sof = UDC_SOF_REG;
1210         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1211 }
1212
1213 static int omap_wakeup(struct usb_gadget *gadget)
1214 {
1215         struct omap_udc *udc;
1216         unsigned long   flags;
1217         int             retval = -EHOSTUNREACH;
1218
1219         udc = container_of(gadget, struct omap_udc, gadget);
1220
1221         spin_lock_irqsave(&udc->lock, flags);
1222         if (udc->devstat & UDC_SUS) {
1223                 /* NOTE:  OTG spec erratum says that OTG devices may
1224                  * issue wakeups without host enable.
1225                  */
1226                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1227                         DBG("remote wakeup...\n");
1228                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1229                         retval = 0;
1230                 }
1231
1232         /* NOTE:  non-OTG systems may use SRP TOO... */
1233         } else if (!(udc->devstat & UDC_ATT)) {
1234                 if (udc->transceiver)
1235                         retval = otg_start_srp(udc->transceiver);
1236         }
1237         spin_unlock_irqrestore(&udc->lock, flags);
1238
1239         return retval;
1240 }
1241
1242 static int
1243 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1244 {
1245         struct omap_udc *udc;
1246         unsigned long   flags;
1247         u16             syscon1;
1248
1249         udc = container_of(gadget, struct omap_udc, gadget);
1250         spin_lock_irqsave(&udc->lock, flags);
1251         syscon1 = UDC_SYSCON1_REG;
1252         if (is_selfpowered)
1253                 syscon1 |= UDC_SELF_PWR;
1254         else
1255                 syscon1 &= ~UDC_SELF_PWR;
1256         UDC_SYSCON1_REG = syscon1;
1257         spin_unlock_irqrestore(&udc->lock, flags);
1258
1259         return 0;
1260 }
1261
1262 static int can_pullup(struct omap_udc *udc)
1263 {
1264         return udc->driver && udc->softconnect && udc->vbus_active;
1265 }
1266
1267 static void pullup_enable(struct omap_udc *udc)
1268 {
1269         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1270         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1271                 OTG_CTRL_REG |= OTG_BSESSVLD;
1272         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1273 }
1274
1275 static void pullup_disable(struct omap_udc *udc)
1276 {
1277         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1278                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1279         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1280         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1281 }
1282
1283 static struct omap_udc *udc;
1284
1285 static void omap_udc_enable_clock(int enable)
1286 {
1287         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1288                 return;
1289
1290         if (enable) {
1291                 clk_enable(udc->dc_clk);
1292                 clk_enable(udc->hhc_clk);
1293                 udelay(100);
1294         } else {
1295                 clk_disable(udc->hhc_clk);
1296                 clk_disable(udc->dc_clk);
1297         }
1298 }
1299
1300 /*
1301  * Called by whatever detects VBUS sessions:  external transceiver
1302  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1303  */
1304 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1305 {
1306         struct omap_udc *udc;
1307         unsigned long   flags;
1308
1309         udc = container_of(gadget, struct omap_udc, gadget);
1310         spin_lock_irqsave(&udc->lock, flags);
1311         VDBG("VBUS %s\n", is_active ? "on" : "off");
1312         udc->vbus_active = (is_active != 0);
1313         if (cpu_is_omap15xx()) {
1314                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1315                 if (is_active)
1316                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1317                 else
1318                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1319         }
1320         if (udc->dc_clk != NULL && is_active) {
1321                 if (!udc->clk_requested) {
1322                         omap_udc_enable_clock(1);
1323                         udc->clk_requested = 1;
1324                 }
1325         }
1326         if (can_pullup(udc))
1327                 pullup_enable(udc);
1328         else
1329                 pullup_disable(udc);
1330         if (udc->dc_clk != NULL && !is_active) {
1331                 if (udc->clk_requested) {
1332                         omap_udc_enable_clock(0);
1333                         udc->clk_requested = 0;
1334                 }
1335         }
1336         spin_unlock_irqrestore(&udc->lock, flags);
1337         return 0;
1338 }
1339
1340 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1341 {
1342         struct omap_udc *udc;
1343
1344         udc = container_of(gadget, struct omap_udc, gadget);
1345         if (udc->transceiver)
1346                 return otg_set_power(udc->transceiver, mA);
1347         return -EOPNOTSUPP;
1348 }
1349
1350 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1351 {
1352         struct omap_udc *udc;
1353         unsigned long   flags;
1354
1355         udc = container_of(gadget, struct omap_udc, gadget);
1356         spin_lock_irqsave(&udc->lock, flags);
1357         udc->softconnect = (is_on != 0);
1358         if (can_pullup(udc))
1359                 pullup_enable(udc);
1360         else
1361                 pullup_disable(udc);
1362         spin_unlock_irqrestore(&udc->lock, flags);
1363         return 0;
1364 }
1365
1366 static struct usb_gadget_ops omap_gadget_ops = {
1367         .get_frame              = omap_get_frame,
1368         .wakeup                 = omap_wakeup,
1369         .set_selfpowered        = omap_set_selfpowered,
1370         .vbus_session           = omap_vbus_session,
1371         .vbus_draw              = omap_vbus_draw,
1372         .pullup                 = omap_pullup,
1373 };
1374
1375 /*-------------------------------------------------------------------------*/
1376
1377 /* dequeue ALL requests; caller holds udc->lock */
1378 static void nuke(struct omap_ep *ep, int status)
1379 {
1380         struct omap_req *req;
1381
1382         ep->stopped = 1;
1383
1384         if (use_dma && ep->dma_channel)
1385                 dma_channel_release(ep);
1386
1387         use_ep(ep, 0);
1388         UDC_CTRL_REG = UDC_CLR_EP;
1389         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1390                 UDC_CTRL_REG = UDC_SET_HALT;
1391
1392         while (!list_empty(&ep->queue)) {
1393                 req = list_entry(ep->queue.next, struct omap_req, queue);
1394                 done(ep, req, status);
1395         }
1396 }
1397
1398 /* caller holds udc->lock */
1399 static void udc_quiesce(struct omap_udc *udc)
1400 {
1401         struct omap_ep  *ep;
1402
1403         udc->gadget.speed = USB_SPEED_UNKNOWN;
1404         nuke(&udc->ep[0], -ESHUTDOWN);
1405         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1406                 nuke(ep, -ESHUTDOWN);
1407 }
1408
1409 /*-------------------------------------------------------------------------*/
1410
1411 static void update_otg(struct omap_udc *udc)
1412 {
1413         u16     devstat;
1414
1415         if (!gadget_is_otg(&udc->gadget))
1416                 return;
1417
1418         if (OTG_CTRL_REG & OTG_ID)
1419                 devstat = UDC_DEVSTAT_REG;
1420         else
1421                 devstat = 0;
1422
1423         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1424         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1425         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1426
1427         /* Enable HNP early, avoiding races on suspend irq path.
1428          * ASSUMES OTG state machine B_BUS_REQ input is true.
1429          */
1430         if (udc->gadget.b_hnp_enable)
1431                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1432                                 & ~OTG_PULLUP;
1433 }
1434
1435 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1436 {
1437         struct omap_ep  *ep0 = &udc->ep[0];
1438         struct omap_req *req = NULL;
1439
1440         ep0->irqs++;
1441
1442         /* Clear any pending requests and then scrub any rx/tx state
1443          * before starting to handle the SETUP request.
1444          */
1445         if (irq_src & UDC_SETUP) {
1446                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1447
1448                 nuke(ep0, 0);
1449                 if (ack) {
1450                         UDC_IRQ_SRC_REG = ack;
1451                         irq_src = UDC_SETUP;
1452                 }
1453         }
1454
1455         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1456          * This driver uses only uses protocol stalls (ep0 never halts),
1457          * and if we got this far the gadget driver already had a
1458          * chance to stall.  Tries to be forgiving of host oddities.
1459          *
1460          * NOTE:  the last chance gadget drivers have to stall control
1461          * requests is during their request completion callback.
1462          */
1463         if (!list_empty(&ep0->queue))
1464                 req = container_of(ep0->queue.next, struct omap_req, queue);
1465
1466         /* IN == TX to host */
1467         if (irq_src & UDC_EP0_TX) {
1468                 int     stat;
1469
1470                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1471                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1472                 stat = UDC_STAT_FLG_REG;
1473                 if (stat & UDC_ACK) {
1474                         if (udc->ep0_in) {
1475                                 /* write next IN packet from response,
1476                                  * or set up the status stage.
1477                                  */
1478                                 if (req)
1479                                         stat = write_fifo(ep0, req);
1480                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1481                                 if (!req && udc->ep0_pending) {
1482                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1483                                         UDC_CTRL_REG = UDC_CLR_EP;
1484                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1485                                         UDC_EP_NUM_REG = 0;
1486                                         udc->ep0_pending = 0;
1487                                 } /* else:  6 wait states before it'll tx */
1488                         } else {
1489                                 /* ack status stage of OUT transfer */
1490                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1491                                 if (req)
1492                                         done(ep0, req, 0);
1493                         }
1494                         req = NULL;
1495                 } else if (stat & UDC_STALL) {
1496                         UDC_CTRL_REG = UDC_CLR_HALT;
1497                         UDC_EP_NUM_REG = UDC_EP_DIR;
1498                 } else {
1499                         UDC_EP_NUM_REG = UDC_EP_DIR;
1500                 }
1501         }
1502
1503         /* OUT == RX from host */
1504         if (irq_src & UDC_EP0_RX) {
1505                 int     stat;
1506
1507                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1508                 UDC_EP_NUM_REG = UDC_EP_SEL;
1509                 stat = UDC_STAT_FLG_REG;
1510                 if (stat & UDC_ACK) {
1511                         if (!udc->ep0_in) {
1512                                 stat = 0;
1513                                 /* read next OUT packet of request, maybe
1514                                  * reactiviting the fifo; stall on errors.
1515                                  */
1516                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1517                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1518                                         udc->ep0_pending = 0;
1519                                         stat = 0;
1520                                 } else if (stat == 0)
1521                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1522                                 UDC_EP_NUM_REG = 0;
1523
1524                                 /* activate status stage */
1525                                 if (stat == 1) {
1526                                         done(ep0, req, 0);
1527                                         /* that may have STALLed ep0... */
1528                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1529                                         UDC_CTRL_REG = UDC_CLR_EP;
1530                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1531                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1532                                         udc->ep0_pending = 0;
1533                                 }
1534                         } else {
1535                                 /* ack status stage of IN transfer */
1536                                 UDC_EP_NUM_REG = 0;
1537                                 if (req)
1538                                         done(ep0, req, 0);
1539                         }
1540                 } else if (stat & UDC_STALL) {
1541                         UDC_CTRL_REG = UDC_CLR_HALT;
1542                         UDC_EP_NUM_REG = 0;
1543                 } else {
1544                         UDC_EP_NUM_REG = 0;
1545                 }
1546         }
1547
1548         /* SETUP starts all control transfers */
1549         if (irq_src & UDC_SETUP) {
1550                 union u {
1551                         u16                     word[4];
1552                         struct usb_ctrlrequest  r;
1553                 } u;
1554                 int                     status = -EINVAL;
1555                 struct omap_ep          *ep;
1556
1557                 /* read the (latest) SETUP message */
1558                 do {
1559                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1560                         /* two bytes at a time */
1561                         u.word[0] = UDC_DATA_REG;
1562                         u.word[1] = UDC_DATA_REG;
1563                         u.word[2] = UDC_DATA_REG;
1564                         u.word[3] = UDC_DATA_REG;
1565                         UDC_EP_NUM_REG = 0;
1566                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1567
1568 #define w_value         le16_to_cpu(u.r.wValue)
1569 #define w_index         le16_to_cpu(u.r.wIndex)
1570 #define w_length        le16_to_cpu(u.r.wLength)
1571
1572                 /* Delegate almost all control requests to the gadget driver,
1573                  * except for a handful of ch9 status/feature requests that
1574                  * hardware doesn't autodecode _and_ the gadget API hides.
1575                  */
1576                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1577                 udc->ep0_set_config = 0;
1578                 udc->ep0_pending = 1;
1579                 ep0->stopped = 0;
1580                 ep0->ackwait = 0;
1581                 switch (u.r.bRequest) {
1582                 case USB_REQ_SET_CONFIGURATION:
1583                         /* udc needs to know when ep != 0 is valid */
1584                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1585                                 goto delegate;
1586                         if (w_length != 0)
1587                                 goto do_stall;
1588                         udc->ep0_set_config = 1;
1589                         udc->ep0_reset_config = (w_value == 0);
1590                         VDBG("set config %d\n", w_value);
1591
1592                         /* update udc NOW since gadget driver may start
1593                          * queueing requests immediately; clear config
1594                          * later if it fails the request.
1595                          */
1596                         if (udc->ep0_reset_config)
1597                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1598                         else
1599                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1600                         update_otg(udc);
1601                         goto delegate;
1602                 case USB_REQ_CLEAR_FEATURE:
1603                         /* clear endpoint halt */
1604                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1605                                 goto delegate;
1606                         if (w_value != USB_ENDPOINT_HALT
1607                                         || w_length != 0)
1608                                 goto do_stall;
1609                         ep = &udc->ep[w_index & 0xf];
1610                         if (ep != ep0) {
1611                                 if (w_index & USB_DIR_IN)
1612                                         ep += 16;
1613                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1614                                                 || !ep->desc)
1615                                         goto do_stall;
1616                                 use_ep(ep, 0);
1617                                 UDC_CTRL_REG = udc->clr_halt;
1618                                 ep->ackwait = 0;
1619                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1620                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1621                                         ep->ackwait = 1 + ep->double_buf;
1622                                 }
1623                                 /* NOTE:  assumes the host behaves sanely,
1624                                  * only clearing real halts.  Else we may
1625                                  * need to kill pending transfers and then
1626                                  * restart the queue... very messy for DMA!
1627                                  */
1628                         }
1629                         VDBG("%s halt cleared by host\n", ep->name);
1630                         goto ep0out_status_stage;
1631                 case USB_REQ_SET_FEATURE:
1632                         /* set endpoint halt */
1633                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1634                                 goto delegate;
1635                         if (w_value != USB_ENDPOINT_HALT
1636                                         || w_length != 0)
1637                                 goto do_stall;
1638                         ep = &udc->ep[w_index & 0xf];
1639                         if (w_index & USB_DIR_IN)
1640                                 ep += 16;
1641                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1642                                         || ep == ep0 || !ep->desc)
1643                                 goto do_stall;
1644                         if (use_dma && ep->has_dma) {
1645                                 /* this has rude side-effects (aborts) and
1646                                  * can't really work if DMA-IN is active
1647                                  */
1648                                 DBG("%s host set_halt, NYET \n", ep->name);
1649                                 goto do_stall;
1650                         }
1651                         use_ep(ep, 0);
1652                         /* can't halt if fifo isn't empty... */
1653                         UDC_CTRL_REG = UDC_CLR_EP;
1654                         UDC_CTRL_REG = UDC_SET_HALT;
1655                         VDBG("%s halted by host\n", ep->name);
1656 ep0out_status_stage:
1657                         status = 0;
1658                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1659                         UDC_CTRL_REG = UDC_CLR_EP;
1660                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1661                         UDC_EP_NUM_REG = UDC_EP_DIR;
1662                         udc->ep0_pending = 0;
1663                         break;
1664                 case USB_REQ_GET_STATUS:
1665                         /* USB_ENDPOINT_HALT status? */
1666                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1667                                 goto intf_status;
1668
1669                         /* ep0 never stalls */
1670                         if (!(w_index & 0xf))
1671                                 goto zero_status;
1672
1673                         /* only active endpoints count */
1674                         ep = &udc->ep[w_index & 0xf];
1675                         if (w_index & USB_DIR_IN)
1676                                 ep += 16;
1677                         if (!ep->desc)
1678                                 goto do_stall;
1679
1680                         /* iso never stalls */
1681                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1682                                 goto zero_status;
1683
1684                         /* FIXME don't assume non-halted endpoints!! */
1685                         ERR("%s status, can't report\n", ep->ep.name);
1686                         goto do_stall;
1687
1688 intf_status:
1689                         /* return interface status.  if we were pedantic,
1690                          * we'd detect non-existent interfaces, and stall.
1691                          */
1692                         if (u.r.bRequestType
1693                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1694                                 goto delegate;
1695
1696 zero_status:
1697                         /* return two zero bytes */
1698                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1699                         UDC_DATA_REG = 0;
1700                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1701                         UDC_EP_NUM_REG = UDC_EP_DIR;
1702                         status = 0;
1703                         VDBG("GET_STATUS, interface %d\n", w_index);
1704                         /* next, status stage */
1705                         break;
1706                 default:
1707 delegate:
1708                         /* activate the ep0out fifo right away */
1709                         if (!udc->ep0_in && w_length) {
1710                                 UDC_EP_NUM_REG = 0;
1711                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1712                         }
1713
1714                         /* gadget drivers see class/vendor specific requests,
1715                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1716                          * and more
1717                          */
1718                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1719                                 u.r.bRequestType, u.r.bRequest,
1720                                 w_value, w_index, w_length);
1721
1722 #undef  w_value
1723 #undef  w_index
1724 #undef  w_length
1725
1726                         /* The gadget driver may return an error here,
1727                          * causing an immediate protocol stall.
1728                          *
1729                          * Else it must issue a response, either queueing a
1730                          * response buffer for the DATA stage, or halting ep0
1731                          * (causing a protocol stall, not a real halt).  A
1732                          * zero length buffer means no DATA stage.
1733                          *
1734                          * It's fine to issue that response after the setup()
1735                          * call returns, and this IRQ was handled.
1736                          */
1737                         udc->ep0_setup = 1;
1738                         spin_unlock(&udc->lock);
1739                         status = udc->driver->setup (&udc->gadget, &u.r);
1740                         spin_lock(&udc->lock);
1741                         udc->ep0_setup = 0;
1742                 }
1743
1744                 if (status < 0) {
1745 do_stall:
1746                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1747                                         u.r.bRequestType, u.r.bRequest, status);
1748                         if (udc->ep0_set_config) {
1749                                 if (udc->ep0_reset_config)
1750                                         WARN("error resetting config?\n");
1751                                 else
1752                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1753                         }
1754                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1755                         udc->ep0_pending = 0;
1756                 }
1757         }
1758 }
1759
1760 /*-------------------------------------------------------------------------*/
1761
1762 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1763
1764 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1765 {
1766         u16     devstat, change;
1767
1768         devstat = UDC_DEVSTAT_REG;
1769         change = devstat ^ udc->devstat;
1770         udc->devstat = devstat;
1771
1772         if (change & (UDC_USB_RESET|UDC_ATT)) {
1773                 udc_quiesce(udc);
1774
1775                 if (change & UDC_ATT) {
1776                         /* driver for any external transceiver will
1777                          * have called omap_vbus_session() already
1778                          */
1779                         if (devstat & UDC_ATT) {
1780                                 udc->gadget.speed = USB_SPEED_FULL;
1781                                 VDBG("connect\n");
1782                                 if (!udc->transceiver)
1783                                         pullup_enable(udc);
1784                                 // if (driver->connect) call it
1785                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1786                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1787                                 if (!udc->transceiver)
1788                                         pullup_disable(udc);
1789                                 DBG("disconnect, gadget %s\n",
1790                                         udc->driver->driver.name);
1791                                 if (udc->driver->disconnect) {
1792                                         spin_unlock(&udc->lock);
1793                                         udc->driver->disconnect(&udc->gadget);
1794                                         spin_lock(&udc->lock);
1795                                 }
1796                         }
1797                         change &= ~UDC_ATT;
1798                 }
1799
1800                 if (change & UDC_USB_RESET) {
1801                         if (devstat & UDC_USB_RESET) {
1802                                 VDBG("RESET=1\n");
1803                         } else {
1804                                 udc->gadget.speed = USB_SPEED_FULL;
1805                                 INFO("USB reset done, gadget %s\n",
1806                                         udc->driver->driver.name);
1807                                 /* ep0 traffic is legal from now on */
1808                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1809                         }
1810                         change &= ~UDC_USB_RESET;
1811                 }
1812         }
1813         if (change & UDC_SUS) {
1814                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1815                         // FIXME tell isp1301 to suspend/resume (?)
1816                         if (devstat & UDC_SUS) {
1817                                 VDBG("suspend\n");
1818                                 update_otg(udc);
1819                                 /* HNP could be under way already */
1820                                 if (udc->gadget.speed == USB_SPEED_FULL
1821                                                 && udc->driver->suspend) {
1822                                         spin_unlock(&udc->lock);
1823                                         udc->driver->suspend(&udc->gadget);
1824                                         spin_lock(&udc->lock);
1825                                 }
1826                                 if (udc->transceiver)
1827                                         otg_set_suspend(udc->transceiver, 1);
1828                         } else {
1829                                 VDBG("resume\n");
1830                                 if (udc->transceiver)
1831                                         otg_set_suspend(udc->transceiver, 0);
1832                                 if (udc->gadget.speed == USB_SPEED_FULL
1833                                                 && udc->driver->resume) {
1834                                         spin_unlock(&udc->lock);
1835                                         udc->driver->resume(&udc->gadget);
1836                                         spin_lock(&udc->lock);
1837                                 }
1838                         }
1839                 }
1840                 change &= ~UDC_SUS;
1841         }
1842         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1843                 update_otg(udc);
1844                 change &= ~OTG_FLAGS;
1845         }
1846
1847         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1848         if (change)
1849                 VDBG("devstat %03x, ignore change %03x\n",
1850                         devstat,  change);
1851
1852         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1853 }
1854
1855 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1856 {
1857         struct omap_udc *udc = _udc;
1858         u16             irq_src;
1859         irqreturn_t     status = IRQ_NONE;
1860         unsigned long   flags;
1861
1862         spin_lock_irqsave(&udc->lock, flags);
1863         irq_src = UDC_IRQ_SRC_REG;
1864
1865         /* Device state change (usb ch9 stuff) */
1866         if (irq_src & UDC_DS_CHG) {
1867                 devstate_irq(_udc, irq_src);
1868                 status = IRQ_HANDLED;
1869                 irq_src &= ~UDC_DS_CHG;
1870         }
1871
1872         /* EP0 control transfers */
1873         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1874                 ep0_irq(_udc, irq_src);
1875                 status = IRQ_HANDLED;
1876                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1877         }
1878
1879         /* DMA transfer completion */
1880         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1881                 dma_irq(_udc, irq_src);
1882                 status = IRQ_HANDLED;
1883                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1884         }
1885
1886         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1887         if (irq_src)
1888                 DBG("udc_irq, unhandled %03x\n", irq_src);
1889         spin_unlock_irqrestore(&udc->lock, flags);
1890
1891         return status;
1892 }
1893
1894 /* workaround for seemingly-lost IRQs for RX ACKs... */
1895 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1896 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1897
1898 static void pio_out_timer(unsigned long _ep)
1899 {
1900         struct omap_ep  *ep = (void *) _ep;
1901         unsigned long   flags;
1902         u16             stat_flg;
1903
1904         spin_lock_irqsave(&ep->udc->lock, flags);
1905         if (!list_empty(&ep->queue) && ep->ackwait) {
1906                 use_ep(ep, UDC_EP_SEL);
1907                 stat_flg = UDC_STAT_FLG_REG;
1908
1909                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1910                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1911                         struct omap_req *req;
1912
1913                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1914                         req = container_of(ep->queue.next,
1915                                         struct omap_req, queue);
1916                         (void) read_fifo(ep, req);
1917                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1918                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1919                         ep->ackwait = 1 + ep->double_buf;
1920                 } else
1921                         deselect_ep();
1922         }
1923         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1924         spin_unlock_irqrestore(&ep->udc->lock, flags);
1925 }
1926
1927 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1928 {
1929         u16             epn_stat, irq_src;
1930         irqreturn_t     status = IRQ_NONE;
1931         struct omap_ep  *ep;
1932         int             epnum;
1933         struct omap_udc *udc = _dev;
1934         struct omap_req *req;
1935         unsigned long   flags;
1936
1937         spin_lock_irqsave(&udc->lock, flags);
1938         epn_stat = UDC_EPN_STAT_REG;
1939         irq_src = UDC_IRQ_SRC_REG;
1940
1941         /* handle OUT first, to avoid some wasteful NAKs */
1942         if (irq_src & UDC_EPN_RX) {
1943                 epnum = (epn_stat >> 8) & 0x0f;
1944                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1945                 status = IRQ_HANDLED;
1946                 ep = &udc->ep[epnum];
1947                 ep->irqs++;
1948
1949                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1950                 ep->fnf = 0;
1951                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1952                         ep->ackwait--;
1953                         if (!list_empty(&ep->queue)) {
1954                                 int stat;
1955                                 req = container_of(ep->queue.next,
1956                                                 struct omap_req, queue);
1957                                 stat = read_fifo(ep, req);
1958                                 if (!ep->double_buf)
1959                                         ep->fnf = 1;
1960                         }
1961                 }
1962                 /* min 6 clock delay before clearing EP_SEL ... */
1963                 epn_stat = UDC_EPN_STAT_REG;
1964                 epn_stat = UDC_EPN_STAT_REG;
1965                 UDC_EP_NUM_REG = epnum;
1966
1967                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1968                  * reduces lossage; timer still needed though (sigh).
1969                  */
1970                 if (ep->fnf) {
1971                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1972                         ep->ackwait = 1 + ep->double_buf;
1973                 }
1974                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1975         }
1976
1977         /* then IN transfers */
1978         else if (irq_src & UDC_EPN_TX) {
1979                 epnum = epn_stat & 0x0f;
1980                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1981                 status = IRQ_HANDLED;
1982                 ep = &udc->ep[16 + epnum];
1983                 ep->irqs++;
1984
1985                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1986                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1987                         ep->ackwait = 0;
1988                         if (!list_empty(&ep->queue)) {
1989                                 req = container_of(ep->queue.next,
1990                                                 struct omap_req, queue);
1991                                 (void) write_fifo(ep, req);
1992                         }
1993                 }
1994                 /* min 6 clock delay before clearing EP_SEL ... */
1995                 epn_stat = UDC_EPN_STAT_REG;
1996                 epn_stat = UDC_EPN_STAT_REG;
1997                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
1998                 /* then 6 clocks before it'd tx */
1999         }
2000
2001         spin_unlock_irqrestore(&udc->lock, flags);
2002         return status;
2003 }
2004
2005 #ifdef  USE_ISO
2006 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2007 {
2008         struct omap_udc *udc = _dev;
2009         struct omap_ep  *ep;
2010         int             pending = 0;
2011         unsigned long   flags;
2012
2013         spin_lock_irqsave(&udc->lock, flags);
2014
2015         /* handle all non-DMA ISO transfers */
2016         list_for_each_entry (ep, &udc->iso, iso) {
2017                 u16             stat;
2018                 struct omap_req *req;
2019
2020                 if (ep->has_dma || list_empty(&ep->queue))
2021                         continue;
2022                 req = list_entry(ep->queue.next, struct omap_req, queue);
2023
2024                 use_ep(ep, UDC_EP_SEL);
2025                 stat = UDC_STAT_FLG_REG;
2026
2027                 /* NOTE: like the other controller drivers, this isn't
2028                  * currently reporting lost or damaged frames.
2029                  */
2030                 if (ep->bEndpointAddress & USB_DIR_IN) {
2031                         if (stat & UDC_MISS_IN)
2032                                 /* done(ep, req, -EPROTO) */;
2033                         else
2034                                 write_fifo(ep, req);
2035                 } else {
2036                         int     status = 0;
2037
2038                         if (stat & UDC_NO_RXPACKET)
2039                                 status = -EREMOTEIO;
2040                         else if (stat & UDC_ISO_ERR)
2041                                 status = -EILSEQ;
2042                         else if (stat & UDC_DATA_FLUSH)
2043                                 status = -ENOSR;
2044
2045                         if (status)
2046                                 /* done(ep, req, status) */;
2047                         else
2048                                 read_fifo(ep, req);
2049                 }
2050                 deselect_ep();
2051                 /* 6 wait states before next EP */
2052
2053                 ep->irqs++;
2054                 if (!list_empty(&ep->queue))
2055                         pending = 1;
2056         }
2057         if (!pending)
2058                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2059         UDC_IRQ_SRC_REG = UDC_SOF;
2060
2061         spin_unlock_irqrestore(&udc->lock, flags);
2062         return IRQ_HANDLED;
2063 }
2064 #endif
2065
2066 /*-------------------------------------------------------------------------*/
2067
2068 static inline int machine_without_vbus_sense(void)
2069 {
2070         return (machine_is_omap_innovator()
2071                 || machine_is_omap_osk()
2072                 || machine_is_omap_apollon()
2073 #ifndef CONFIG_MACH_OMAP_H4_OTG
2074                 || machine_is_omap_h4()
2075 #endif
2076                 || machine_is_sx1()
2077                 );
2078 }
2079
2080 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2081 {
2082         int             status = -ENODEV;
2083         struct omap_ep  *ep;
2084         unsigned long   flags;
2085
2086         /* basic sanity tests */
2087         if (!udc)
2088                 return -ENODEV;
2089         if (!driver
2090                         // FIXME if otg, check:  driver->is_otg
2091                         || driver->speed < USB_SPEED_FULL
2092                         || !driver->bind
2093                         || !driver->setup)
2094                 return -EINVAL;
2095
2096         spin_lock_irqsave(&udc->lock, flags);
2097         if (udc->driver) {
2098                 spin_unlock_irqrestore(&udc->lock, flags);
2099                 return -EBUSY;
2100         }
2101
2102         /* reset state */
2103         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2104                 ep->irqs = 0;
2105                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2106                         continue;
2107                 use_ep(ep, 0);
2108                 UDC_CTRL_REG = UDC_SET_HALT;
2109         }
2110         udc->ep0_pending = 0;
2111         udc->ep[0].irqs = 0;
2112         udc->softconnect = 1;
2113
2114         /* hook up the driver */
2115         driver->driver.bus = NULL;
2116         udc->driver = driver;
2117         udc->gadget.dev.driver = &driver->driver;
2118         spin_unlock_irqrestore(&udc->lock, flags);
2119
2120         if (udc->dc_clk != NULL)
2121                 omap_udc_enable_clock(1);
2122
2123         status = driver->bind (&udc->gadget);
2124         if (status) {
2125                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2126                 udc->gadget.dev.driver = NULL;
2127                 udc->driver = NULL;
2128                 goto done;
2129         }
2130         DBG("bound to driver %s\n", driver->driver.name);
2131
2132         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2133
2134         /* connect to bus through transceiver */
2135         if (udc->transceiver) {
2136                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2137                 if (status < 0) {
2138                         ERR("can't bind to transceiver\n");
2139                         if (driver->unbind) {
2140                                 driver->unbind (&udc->gadget);
2141                                 udc->gadget.dev.driver = NULL;
2142                                 udc->driver = NULL;
2143                         }
2144                         goto done;
2145                 }
2146         } else {
2147                 if (can_pullup(udc))
2148                         pullup_enable (udc);
2149                 else
2150                         pullup_disable (udc);
2151         }
2152
2153         /* boards that don't have VBUS sensing can't autogate 48MHz;
2154          * can't enter deep sleep while a gadget driver is active.
2155          */
2156         if (machine_without_vbus_sense())
2157                 omap_vbus_session(&udc->gadget, 1);
2158
2159 done:
2160         if (udc->dc_clk != NULL)
2161                 omap_udc_enable_clock(0);
2162         return status;
2163 }
2164 EXPORT_SYMBOL(usb_gadget_register_driver);
2165
2166 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2167 {
2168         unsigned long   flags;
2169         int             status = -ENODEV;
2170
2171         if (!udc)
2172                 return -ENODEV;
2173         if (!driver || driver != udc->driver || !driver->unbind)
2174                 return -EINVAL;
2175
2176         if (udc->dc_clk != NULL)
2177                 omap_udc_enable_clock(1);
2178
2179         if (machine_without_vbus_sense())
2180                 omap_vbus_session(&udc->gadget, 0);
2181
2182         if (udc->transceiver)
2183                 (void) otg_set_peripheral(udc->transceiver, NULL);
2184         else
2185                 pullup_disable(udc);
2186
2187         spin_lock_irqsave(&udc->lock, flags);
2188         udc_quiesce(udc);
2189         spin_unlock_irqrestore(&udc->lock, flags);
2190
2191         driver->unbind(&udc->gadget);
2192         udc->gadget.dev.driver = NULL;
2193         udc->driver = NULL;
2194
2195         if (udc->dc_clk != NULL)
2196                 omap_udc_enable_clock(0);
2197         DBG("unregistered driver '%s'\n", driver->driver.name);
2198         return status;
2199 }
2200 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2201
2202
2203 /*-------------------------------------------------------------------------*/
2204
2205 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2206
2207 #include <linux/seq_file.h>
2208
2209 static const char proc_filename[] = "driver/udc";
2210
2211 #define FOURBITS "%s%s%s%s"
2212 #define EIGHTBITS FOURBITS FOURBITS
2213
2214 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2215 {
2216         u16             stat_flg;
2217         struct omap_req *req;
2218         char            buf[20];
2219
2220         use_ep(ep, 0);
2221
2222         if (use_dma && ep->has_dma)
2223                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2224                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2225                         ep->dma_channel - 1, ep->lch);
2226         else
2227                 buf[0] = 0;
2228
2229         stat_flg = UDC_STAT_FLG_REG;
2230         seq_printf(s,
2231                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2232                 ep->name, buf,
2233                 ep->double_buf ? "dbuf " : "",
2234                 ({char *s; switch(ep->ackwait){
2235                 case 0: s = ""; break;
2236                 case 1: s = "(ackw) "; break;
2237                 case 2: s = "(ackw2) "; break;
2238                 default: s = "(?) "; break;
2239                 } s;}),
2240                 ep->irqs, stat_flg,
2241                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2242                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2243                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2244                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2245                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2246                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2247                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2248                 (stat_flg & UDC_STALL) ? "STALL " : "",
2249                 (stat_flg & UDC_NAK) ? "NAK " : "",
2250                 (stat_flg & UDC_ACK) ? "ACK " : "",
2251                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2252                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2253                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2254
2255         if (list_empty (&ep->queue))
2256                 seq_printf(s, "\t(queue empty)\n");
2257         else
2258                 list_for_each_entry (req, &ep->queue, queue) {
2259                         unsigned        length = req->req.actual;
2260
2261                         if (use_dma && buf[0]) {
2262                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2263                                                 ? dma_src_len : dma_dest_len)
2264                                         (ep, req->req.dma + length);
2265                                 buf[0] = 0;
2266                         }
2267                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2268                                         &req->req, length,
2269                                         req->req.length, req->req.buf);
2270                 }
2271 }
2272
2273 static char *trx_mode(unsigned m, int enabled)
2274 {
2275         switch (m) {
2276         case 0:         return enabled ? "*6wire" : "unused";
2277         case 1:         return "4wire";
2278         case 2:         return "3wire";
2279         case 3:         return "6wire";
2280         default:        return "unknown";
2281         }
2282 }
2283
2284 static int proc_otg_show(struct seq_file *s)
2285 {
2286         u32             tmp;
2287         u32             trans;
2288         char            *ctrl_name;
2289
2290         tmp = OTG_REV_REG;
2291         if (cpu_is_omap24xx()) {
2292                 /*
2293                  * REVISIT: Not clear how this works on OMAP2.  trans
2294                  * is ANDed to produce bits 7 and 8, which might make
2295                  * sense for USB_TRANSCEIVER_CTRL_REG on OMAP1,
2296                  * but with CONTROL_DEVCONF, these bits have something to
2297                  * do with the frame adjustment counter and McBSP2.
2298                  */
2299                 ctrl_name = "control_devconf";
2300                 trans = omap_ctrl_readb(OMAP2_CONTROL_DEVCONF0);
2301         } else {
2302                 ctrl_name = "tranceiver_ctrl";
2303                 trans = USB_TRANSCEIVER_CTRL_REG;
2304         }
2305         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2306                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2307         tmp = OTG_SYSCON_1_REG;
2308         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2309                         FOURBITS "\n", tmp,
2310                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2311                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2312                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2313                         ? "internal"
2314                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2315                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2316                 (tmp & HST_IDLE_EN) ? " !host" : "",
2317                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2318                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2319         tmp = OTG_SYSCON_2_REG;
2320         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2321                         " b_ase_brst=%d hmc=%d\n", tmp,
2322                 (tmp & OTG_EN) ? " otg_en" : "",
2323                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2324                 // much more SRP stuff
2325                 (tmp & SRP_DATA) ? " srp_data" : "",
2326                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2327                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2328                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2329                 (tmp & UHOST_EN) ? " uhost_en" : "",
2330                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2331                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2332                 B_ASE_BRST(tmp),
2333                 OTG_HMC(tmp));
2334         tmp = OTG_CTRL_REG;
2335         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2336                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2337                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2338                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2339                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2340                 (tmp & OTG_ID) ? " id" : "",
2341                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2342                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2343                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2344                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2345                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2346                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2347                 (tmp & OTG_PULLDOWN) ? " down" : "",
2348                 (tmp & OTG_PULLUP) ? " up" : "",
2349                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2350                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2351                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2352                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2353                 );
2354         tmp = OTG_IRQ_EN_REG;
2355         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2356         tmp = OTG_IRQ_SRC_REG;
2357         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2358         tmp = OTG_OUTCTRL_REG;
2359         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2360         tmp = OTG_TEST_REG;
2361         seq_printf(s, "otg_test    %04x" "\n", tmp);
2362         return 0;
2363 }
2364
2365 static int proc_udc_show(struct seq_file *s, void *_)
2366 {
2367         u32             tmp;
2368         struct omap_ep  *ep;
2369         unsigned long   flags;
2370
2371         spin_lock_irqsave(&udc->lock, flags);
2372
2373         seq_printf(s, "%s, version: " DRIVER_VERSION
2374 #ifdef  USE_ISO
2375                 " (iso)"
2376 #endif
2377                 "%s\n",
2378                 driver_desc,
2379                 use_dma ?  " (dma)" : "");
2380
2381         tmp = UDC_REV_REG & 0xff;
2382         seq_printf(s,
2383                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2384                 "hmc %d, transceiver %s\n",
2385                 tmp >> 4, tmp & 0xf,
2386                 fifo_mode,
2387                 udc->driver ? udc->driver->driver.name : "(none)",
2388                 HMC,
2389                 udc->transceiver
2390                         ? udc->transceiver->label
2391                         : ((cpu_is_omap1710() || cpu_is_omap24xx())
2392                                 ? "external" : "(none)"));
2393         if (cpu_class_is_omap1()) {
2394                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2395                         __REG16(ULPD_CLOCK_CTRL),
2396                         __REG16(ULPD_SOFT_REQ),
2397                         __REG16(ULPD_STATUS_REQ));
2398         }
2399
2400         /* OTG controller registers */
2401         if (!cpu_is_omap15xx())
2402                 proc_otg_show(s);
2403
2404         tmp = UDC_SYSCON1_REG;
2405         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2406                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2407                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2408                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2409                 (tmp & UDC_NAK_EN) ? " nak" : "",
2410                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2411                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2412                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2413                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2414         // syscon2 is write-only
2415
2416         /* UDC controller registers */
2417         if (!(tmp & UDC_PULLUP_EN)) {
2418                 seq_printf(s, "(suspended)\n");
2419                 spin_unlock_irqrestore(&udc->lock, flags);
2420                 return 0;
2421         }
2422
2423         tmp = UDC_DEVSTAT_REG;
2424         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2425                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2426                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2427                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2428                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2429                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2430                 (tmp & UDC_SUS) ? " SUS" : "",
2431                 (tmp & UDC_CFG) ? " CFG" : "",
2432                 (tmp & UDC_ADD) ? " ADD" : "",
2433                 (tmp & UDC_DEF) ? " DEF" : "",
2434                 (tmp & UDC_ATT) ? " ATT" : "");
2435         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2436         tmp = UDC_IRQ_EN_REG;
2437         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2438                 (tmp & UDC_SOF_IE) ? " sof" : "",
2439                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2440                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2441                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2442                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2443         tmp = UDC_IRQ_SRC_REG;
2444         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2445                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2446                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2447                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2448                 (tmp & UDC_SOF) ? " sof" : "",
2449                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2450                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2451                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2452                 (tmp & UDC_SETUP) ? " setup" : "",
2453                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2454                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2455         if (use_dma) {
2456                 unsigned i;
2457
2458                 tmp = UDC_DMA_IRQ_EN_REG;
2459                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2460                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2461                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2462                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2463
2464                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2465                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2466                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2467
2468                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2469                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2470                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2471
2472                 tmp = UDC_RXDMA_CFG_REG;
2473                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2474                 if (tmp) {
2475                         for (i = 0; i < 3; i++) {
2476                                 if ((tmp & (0x0f << (i * 4))) == 0)
2477                                         continue;
2478                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2479                                                 UDC_RXDMA_REG(i + 1));
2480                         }
2481                 }
2482                 tmp = UDC_TXDMA_CFG_REG;
2483                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2484                 if (tmp) {
2485                         for (i = 0; i < 3; i++) {
2486                                 if (!(tmp & (0x0f << (i * 4))))
2487                                         continue;
2488                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2489                                                 UDC_TXDMA_REG(i + 1));
2490                         }
2491                 }
2492         }
2493
2494         tmp = UDC_DEVSTAT_REG;
2495         if (tmp & UDC_ATT) {
2496                 proc_ep_show(s, &udc->ep[0]);
2497                 if (tmp & UDC_ADD) {
2498                         list_for_each_entry (ep, &udc->gadget.ep_list,
2499                                         ep.ep_list) {
2500                                 if (ep->desc)
2501                                         proc_ep_show(s, ep);
2502                         }
2503                 }
2504         }
2505         spin_unlock_irqrestore(&udc->lock, flags);
2506         return 0;
2507 }
2508
2509 static int proc_udc_open(struct inode *inode, struct file *file)
2510 {
2511         return single_open(file, proc_udc_show, NULL);
2512 }
2513
2514 static const struct file_operations proc_ops = {
2515         .owner          = THIS_MODULE,
2516         .open           = proc_udc_open,
2517         .read           = seq_read,
2518         .llseek         = seq_lseek,
2519         .release        = single_release,
2520 };
2521
2522 static void create_proc_file(void)
2523 {
2524         proc_create(proc_filename, 0, NULL, &proc_ops);
2525 }
2526
2527 static void remove_proc_file(void)
2528 {
2529         remove_proc_entry(proc_filename, NULL);
2530 }
2531
2532 #else
2533
2534 static inline void create_proc_file(void) {}
2535 static inline void remove_proc_file(void) {}
2536
2537 #endif
2538
2539 /*-------------------------------------------------------------------------*/
2540
2541 /* Before this controller can enumerate, we need to pick an endpoint
2542  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2543  * buffer space among the endpoints we'll be operating.
2544  *
2545  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2546  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2547  * capability yet though.
2548  */
2549 static unsigned __init
2550 omap_ep_setup(char *name, u8 addr, u8 type,
2551                 unsigned buf, unsigned maxp, int dbuf)
2552 {
2553         struct omap_ep  *ep;
2554         u16             epn_rxtx = 0;
2555
2556         /* OUT endpoints first, then IN */
2557         ep = &udc->ep[addr & 0xf];
2558         if (addr & USB_DIR_IN)
2559                 ep += 16;
2560
2561         /* in case of ep init table bugs */
2562         BUG_ON(ep->name[0]);
2563
2564         /* chip setup ... bit values are same for IN, OUT */
2565         if (type == USB_ENDPOINT_XFER_ISOC) {
2566                 switch (maxp) {
2567                 case 8:         epn_rxtx = 0 << 12; break;
2568                 case 16:        epn_rxtx = 1 << 12; break;
2569                 case 32:        epn_rxtx = 2 << 12; break;
2570                 case 64:        epn_rxtx = 3 << 12; break;
2571                 case 128:       epn_rxtx = 4 << 12; break;
2572                 case 256:       epn_rxtx = 5 << 12; break;
2573                 case 512:       epn_rxtx = 6 << 12; break;
2574                 default:        BUG();
2575                 }
2576                 epn_rxtx |= UDC_EPN_RX_ISO;
2577                 dbuf = 1;
2578         } else {
2579                 /* double-buffering "not supported" on 15xx,
2580                  * and ignored for PIO-IN on newer chips
2581                  * (for more reliable behavior)
2582                  */
2583                 if ((!use_dma && (addr & USB_DIR_IN))
2584                                 || machine_is_omap_apollon()
2585                                 || cpu_is_omap15xx())
2586                         dbuf = 0;
2587
2588                 switch (maxp) {
2589                 case 8:         epn_rxtx = 0 << 12; break;
2590                 case 16:        epn_rxtx = 1 << 12; break;
2591                 case 32:        epn_rxtx = 2 << 12; break;
2592                 case 64:        epn_rxtx = 3 << 12; break;
2593                 default:        BUG();
2594                 }
2595                 if (dbuf && addr)
2596                         epn_rxtx |= UDC_EPN_RX_DB;
2597                 init_timer(&ep->timer);
2598                 ep->timer.function = pio_out_timer;
2599                 ep->timer.data = (unsigned long) ep;
2600         }
2601         if (addr)
2602                 epn_rxtx |= UDC_EPN_RX_VALID;
2603         BUG_ON(buf & 0x07);
2604         epn_rxtx |= buf >> 3;
2605
2606         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2607                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2608
2609         if (addr & USB_DIR_IN)
2610                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2611         else
2612                 UDC_EP_RX_REG(addr) = epn_rxtx;
2613
2614         /* next endpoint's buffer starts after this one's */
2615         buf += maxp;
2616         if (dbuf)
2617                 buf += maxp;
2618         BUG_ON(buf > 2048);
2619
2620         /* set up driver data structures */
2621         BUG_ON(strlen(name) >= sizeof ep->name);
2622         strlcpy(ep->name, name, sizeof ep->name);
2623         INIT_LIST_HEAD(&ep->queue);
2624         INIT_LIST_HEAD(&ep->iso);
2625         ep->bEndpointAddress = addr;
2626         ep->bmAttributes = type;
2627         ep->double_buf = dbuf;
2628         ep->udc = udc;
2629
2630         ep->ep.name = ep->name;
2631         ep->ep.ops = &omap_ep_ops;
2632         ep->ep.maxpacket = ep->maxpacket = maxp;
2633         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2634
2635         return buf;
2636 }
2637
2638 static void omap_udc_release(struct device *dev)
2639 {
2640         complete(udc->done);
2641         kfree (udc);
2642         udc = NULL;
2643 }
2644
2645 static int __init
2646 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2647 {
2648         unsigned        tmp, buf;
2649
2650         /* abolish any previous hardware state */
2651         UDC_SYSCON1_REG = 0;
2652         UDC_IRQ_EN_REG = 0;
2653         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2654         UDC_DMA_IRQ_EN_REG = 0;
2655         UDC_RXDMA_CFG_REG = 0;
2656         UDC_TXDMA_CFG_REG = 0;
2657
2658         /* UDC_PULLUP_EN gates the chip clock */
2659         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2660
2661         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2662         if (!udc)
2663                 return -ENOMEM;
2664
2665         spin_lock_init (&udc->lock);
2666
2667         udc->gadget.ops = &omap_gadget_ops;
2668         udc->gadget.ep0 = &udc->ep[0].ep;
2669         INIT_LIST_HEAD(&udc->gadget.ep_list);
2670         INIT_LIST_HEAD(&udc->iso);
2671         udc->gadget.speed = USB_SPEED_UNKNOWN;
2672         udc->gadget.name = driver_name;
2673
2674         device_initialize(&udc->gadget.dev);
2675         strcpy (udc->gadget.dev.bus_id, "gadget");
2676         udc->gadget.dev.release = omap_udc_release;
2677         udc->gadget.dev.parent = &odev->dev;
2678         if (use_dma)
2679                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2680
2681         udc->transceiver = xceiv;
2682
2683         /* ep0 is special; put it right after the SETUP buffer */
2684         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2685                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2686         list_del_init(&udc->ep[0].ep.ep_list);
2687
2688         /* initially disable all non-ep0 endpoints */
2689         for (tmp = 1; tmp < 15; tmp++) {
2690                 UDC_EP_RX_REG(tmp) = 0;
2691                 UDC_EP_TX_REG(tmp) = 0;
2692         }
2693
2694 #define OMAP_BULK_EP(name,addr) \
2695         buf = omap_ep_setup(name "-bulk", addr, \
2696                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2697 #define OMAP_INT_EP(name,addr, maxp) \
2698         buf = omap_ep_setup(name "-int", addr, \
2699                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2700 #define OMAP_ISO_EP(name,addr, maxp) \
2701         buf = omap_ep_setup(name "-iso", addr, \
2702                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2703
2704         switch (fifo_mode) {
2705         case 0:
2706                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2707                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2708                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2709                 break;
2710         case 1:
2711                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2712                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2713                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2714
2715                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2716                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2717                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2718
2719                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2720                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2721                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2722
2723                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2724                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2725                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2726
2727                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2728                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2729                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2730                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2731
2732                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2733                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2734                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2735                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2736
2737                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2738                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2739
2740                 break;
2741
2742 #ifdef  USE_ISO
2743         case 2:                 /* mixed iso/bulk */
2744                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2745                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2746                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2747                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2748
2749                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2750
2751                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2752                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2753                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2754                 break;
2755         case 3:                 /* mixed bulk/iso */
2756                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2757                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2758                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2759
2760                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2761                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2762                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2763
2764                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2765                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2766                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2767                 break;
2768 #endif
2769
2770         /* add more modes as needed */
2771
2772         default:
2773                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2774                 return -ENODEV;
2775         }
2776         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2777         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2778         return 0;
2779 }
2780
2781 static int __init omap_udc_probe(struct platform_device *pdev)
2782 {
2783         int                     status = -ENODEV;
2784         int                     hmc;
2785         struct otg_transceiver  *xceiv = NULL;
2786         const char              *type = NULL;
2787         struct omap_usb_config  *config = pdev->dev.platform_data;
2788         struct clk              *dc_clk;
2789         struct clk              *hhc_clk;
2790
2791         /* NOTE:  "knows" the order of the resources! */
2792         if (!request_mem_region(pdev->resource[0].start,
2793                         pdev->resource[0].end - pdev->resource[0].start + 1,
2794                         driver_name)) {
2795                 DBG("request_mem_region failed\n");
2796                 return -EBUSY;
2797         }
2798
2799         if (cpu_is_omap16xx()) {
2800                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2801                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2802                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2803                 /* can't use omap_udc_enable_clock yet */
2804                 clk_enable(dc_clk);
2805                 clk_enable(hhc_clk);
2806                 udelay(100);
2807         }
2808
2809         if (cpu_is_omap24xx()) {
2810                 dc_clk = clk_get(&pdev->dev, "usb_fck");
2811                 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2812                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2813                 /* can't use omap_udc_enable_clock yet */
2814                 clk_enable(dc_clk);
2815                 clk_enable(hhc_clk);
2816                 udelay(100);
2817         }
2818
2819         INFO("OMAP UDC rev %d.%d%s\n",
2820                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2821                 config->otg ? ", Mini-AB" : "");
2822
2823         /* use the mode given to us by board init code */
2824         if (cpu_is_omap15xx()) {
2825                 hmc = HMC_1510;
2826                 type = "(unknown)";
2827
2828                 if (machine_without_vbus_sense()) {
2829                         /* just set up software VBUS detect, and then
2830                          * later rig it so we always report VBUS.
2831                          * FIXME without really sensing VBUS, we can't
2832                          * know when to turn PULLUP_EN on/off; and that
2833                          * means we always "need" the 48MHz clock.
2834                          */
2835                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2836
2837                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2838                         tmp |= VBUS_MODE_1510;
2839                         tmp &= ~VBUS_CTRL_1510;
2840                         FUNC_MUX_CTRL_0_REG = tmp;
2841                 }
2842         } else {
2843                 /* The transceiver may package some GPIO logic or handle
2844                  * loopback and/or transceiverless setup; if we find one,
2845                  * use it.  Except for OTG, we don't _need_ to talk to one;
2846                  * but not having one probably means no VBUS detection.
2847                  */
2848                 xceiv = otg_get_transceiver();
2849                 if (xceiv)
2850                         type = xceiv->label;
2851                 else if (config->otg) {
2852                         DBG("OTG requires external transceiver!\n");
2853                         goto cleanup0;
2854                 }
2855
2856                 hmc = HMC_1610;
2857
2858                 if (cpu_is_omap24xx()) {
2859                         /* this could be transceiverless in one of the
2860                          * "we don't need to know" modes.
2861                          */
2862                         type = "external";
2863                         goto known;
2864                 }
2865
2866                 switch (hmc) {
2867                 case 0:                 /* POWERUP DEFAULT == 0 */
2868                 case 4:
2869                 case 12:
2870                 case 20:
2871                         if (!cpu_is_omap1710()) {
2872                                 type = "integrated";
2873                                 break;
2874                         }
2875                         /* FALL THROUGH */
2876                 case 3:
2877                 case 11:
2878                 case 16:
2879                 case 19:
2880                 case 25:
2881                         if (!xceiv) {
2882                                 DBG("external transceiver not registered!\n");
2883                                 type = "unknown";
2884                         }
2885                         break;
2886                 case 21:                        /* internal loopback */
2887                         type = "loopback";
2888                         break;
2889                 case 14:                        /* transceiverless */
2890                         if (cpu_is_omap1710())
2891                                 goto bad_on_1710;
2892                         /* FALL THROUGH */
2893                 case 13:
2894                 case 15:
2895                         type = "no";
2896                         break;
2897
2898                 default:
2899 bad_on_1710:
2900                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2901                         goto cleanup0;
2902                 }
2903         }
2904 known:
2905         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2906
2907         /* a "gadget" abstracts/virtualizes the controller */
2908         status = omap_udc_setup(pdev, xceiv);
2909         if (status) {
2910                 goto cleanup0;
2911         }
2912         xceiv = NULL;
2913         // "udc" is now valid
2914         pullup_disable(udc);
2915 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2916         udc->gadget.is_otg = (config->otg != 0);
2917 #endif
2918
2919         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2920         if (UDC_REV_REG >= 0x61)
2921                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2922         else
2923                 udc->clr_halt = UDC_RESET_EP;
2924
2925         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2926         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2927                         IRQF_SAMPLE_RANDOM, driver_name, udc);
2928         if (status != 0) {
2929                 ERR("can't get irq %d, err %d\n",
2930                         (int) pdev->resource[1].start, status);
2931                 goto cleanup1;
2932         }
2933
2934         /* USB "non-iso" IRQ (PIO for all but ep0) */
2935         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2936                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2937         if (status != 0) {
2938                 ERR("can't get irq %d, err %d\n",
2939                         (int) pdev->resource[2].start, status);
2940                 goto cleanup2;
2941         }
2942 #ifdef  USE_ISO
2943         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2944                         IRQF_DISABLED, "omap_udc iso", udc);
2945         if (status != 0) {
2946                 ERR("can't get irq %d, err %d\n",
2947                         (int) pdev->resource[3].start, status);
2948                 goto cleanup3;
2949         }
2950 #endif
2951         if (cpu_is_omap16xx()) {
2952                 udc->dc_clk = dc_clk;
2953                 udc->hhc_clk = hhc_clk;
2954                 clk_disable(hhc_clk);
2955                 clk_disable(dc_clk);
2956         }
2957
2958         if (cpu_is_omap24xx()) {
2959                 udc->dc_clk = dc_clk;
2960                 udc->hhc_clk = hhc_clk;
2961                 /* FIXME OMAP2 don't release hhc & dc clock */
2962 #if 0
2963                 clk_disable(hhc_clk);
2964                 clk_disable(dc_clk);
2965 #endif
2966         }
2967
2968         create_proc_file();
2969         status = device_add(&udc->gadget.dev);
2970         if (!status)
2971                 return status;
2972         /* If fail, fall through */
2973 #ifdef  USE_ISO
2974 cleanup3:
2975         free_irq(pdev->resource[2].start, udc);
2976 #endif
2977
2978 cleanup2:
2979         free_irq(pdev->resource[1].start, udc);
2980
2981 cleanup1:
2982         kfree (udc);
2983         udc = NULL;
2984
2985 cleanup0:
2986         if (xceiv)
2987                 put_device(xceiv->dev);
2988
2989         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
2990                 clk_disable(hhc_clk);
2991                 clk_disable(dc_clk);
2992                 clk_put(hhc_clk);
2993                 clk_put(dc_clk);
2994         }
2995
2996         release_mem_region(pdev->resource[0].start,
2997                         pdev->resource[0].end - pdev->resource[0].start + 1);
2998
2999         return status;
3000 }
3001
3002 static int __exit omap_udc_remove(struct platform_device *pdev)
3003 {
3004         DECLARE_COMPLETION_ONSTACK(done);
3005
3006         if (!udc)
3007                 return -ENODEV;
3008         if (udc->driver)
3009                 return -EBUSY;
3010
3011         udc->done = &done;
3012
3013         pullup_disable(udc);
3014         if (udc->transceiver) {
3015                 put_device(udc->transceiver->dev);
3016                 udc->transceiver = NULL;
3017         }
3018         UDC_SYSCON1_REG = 0;
3019
3020         remove_proc_file();
3021
3022 #ifdef  USE_ISO
3023         free_irq(pdev->resource[3].start, udc);
3024 #endif
3025         free_irq(pdev->resource[2].start, udc);
3026         free_irq(pdev->resource[1].start, udc);
3027
3028         if (udc->dc_clk) {
3029                 if (udc->clk_requested)
3030                         omap_udc_enable_clock(0);
3031                 clk_put(udc->hhc_clk);
3032                 clk_put(udc->dc_clk);
3033         }
3034
3035         release_mem_region(pdev->resource[0].start,
3036                         pdev->resource[0].end - pdev->resource[0].start + 1);
3037
3038         device_unregister(&udc->gadget.dev);
3039         wait_for_completion(&done);
3040
3041         return 0;
3042 }
3043
3044 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3045  * system is forced into deep sleep
3046  *
3047  * REVISIT we should probably reject suspend requests when there's a host
3048  * session active, rather than disconnecting, at least on boards that can
3049  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
3050  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3051  * may involve talking to an external transceiver (e.g. isp1301).
3052  */
3053
3054 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3055 {
3056         u32     devstat;
3057
3058         devstat = UDC_DEVSTAT_REG;
3059
3060         /* we're requesting 48 MHz clock if the pullup is enabled
3061          * (== we're attached to the host) and we're not suspended,
3062          * which would prevent entry to deep sleep...
3063          */
3064         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3065                 WARN("session active; suspend requires disconnect\n");
3066                 omap_pullup(&udc->gadget, 0);
3067         }
3068
3069         return 0;
3070 }
3071
3072 static int omap_udc_resume(struct platform_device *dev)
3073 {
3074         DBG("resume + wakeup/SRP\n");
3075         omap_pullup(&udc->gadget, 1);
3076
3077         /* maybe the host would enumerate us if we nudged it */
3078         msleep(100);
3079         return omap_wakeup(&udc->gadget);
3080 }
3081
3082 /*-------------------------------------------------------------------------*/
3083
3084 static struct platform_driver udc_driver = {
3085         .probe          = omap_udc_probe,
3086         .remove         = __exit_p(omap_udc_remove),
3087         .suspend        = omap_udc_suspend,
3088         .resume         = omap_udc_resume,
3089         .driver         = {
3090                 .owner  = THIS_MODULE,
3091                 .name   = (char *) driver_name,
3092         },
3093 };
3094
3095 static int __init udc_init(void)
3096 {
3097         INFO("%s, version: " DRIVER_VERSION
3098 #ifdef  USE_ISO
3099                 " (iso)"
3100 #endif
3101                 "%s\n", driver_desc,
3102                 use_dma ?  " (dma)" : "");
3103         return platform_driver_register(&udc_driver);
3104 }
3105 module_init(udc_init);
3106
3107 static void __exit udc_exit(void)
3108 {
3109         platform_driver_unregister(&udc_driver);
3110 }
3111 module_exit(udc_exit);
3112
3113 MODULE_DESCRIPTION(DRIVER_DESC);
3114 MODULE_LICENSE("GPL");
3115 MODULE_ALIAS("platform:omap_udc");