drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #undef  DEBUG
  23 #undef  VERBOSE
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/ioport.h>
  28 #include <linux/types.h>
  29 #include <linux/errno.h>
  30 #include <linux/delay.h>
  31 #include <linux/slab.h>
  32 #include <linux/init.h>
  33 #include <linux/timer.h>
  34 #include <linux/list.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/proc_fs.h>
  37 #include <linux/mm.h>
  38 #include <linux/moduleparam.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/usb/ch9.h>
  41 #include <linux/usb/gadget.h>
  42 #include <linux/usb/otg.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/clk.h>
  45
  46 #include <asm/byteorder.h>
  47 #include <asm/io.h>
  48 #include <asm/irq.h>
  49 #include <asm/system.h>
  50 #include <asm/unaligned.h>
  51 #include <asm/mach-types.h>
  52
  53 #include <asm/arch/dma.h>
  54 #include <asm/arch/usb.h>
  55 #include <asm/arch/control.h>
  56
  57 #include "omap_udc.h"
  58
  59 #undef  USB_TRACE
  60
  61 /* bulk DMA seems to be behaving for both IN and OUT */
  62 #define USE_DMA
  63
  64 /* FIXME: OMAP2 currently has some problem in DMA mode */
  65 #ifdef CONFIG_ARCH_OMAP2
  66 #undef USE_DMA
  67 #endif
  68
  69 /* ISO too */
  70 #define USE_ISO
  71
  72 #define DRIVER_DESC     "OMAP UDC driver"
  73 #define DRIVER_VERSION  "4 October 2004"
  74
  75 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  76
  77
  78 /*
  79  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  80  * D+ pullup to allow enumeration.  That's too early for the gadget
  81  * framework to use from usb_endpoint_enable(), which happens after
  82  * enumeration as part of activating an interface.  (But if we add an
  83  * optional new "UDC not yet running" state to the gadget driver model,
  84  * even just during driver binding, the endpoint autoconfig logic is the
  85  * natural spot to manufacture new endpoints.)
  86  *
  87  * So instead of using endpoint enable calls to control the hardware setup,
  88  * this driver defines a "fifo mode" parameter.  It's used during driver
  89  * initialization to choose among a set of pre-defined endpoint configs.
  90  * See omap_udc_setup() for available modes, or to add others.  That code
  91  * lives in an init section, so use this driver as a module if you need
  92  * to change the fifo mode after the kernel boots.
  93  *
  94  * Gadget drivers normally ignore endpoints they don't care about, and
  95  * won't include them in configuration descriptors.  That means only
  96  * misbehaving hosts would even notice they exist.
  97  */
  98 #ifdef  USE_ISO
  99 static unsigned fifo_mode = 3;
 100 #else
 101 static unsigned fifo_mode = 0;
 102 #endif
 103
 104 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 105  * boot parameter "omap_udc:fifo_mode=42"
 106  */
 107 module_param (fifo_mode, uint, 0);
 108 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
 109
 110 #ifdef  USE_DMA
 111 static unsigned use_dma = 1;
 112
 113 /* "modprobe omap_udc use_dma=y", or else as a kernel
 114  * boot parameter "omap_udc:use_dma=y"
 115  */
 116 module_param (use_dma, bool, 0);
 117 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 118 #else   /* !USE_DMA */
 119
 120 /* save a bit of code */
 121 #define use_dma         0
 122 #endif  /* !USE_DMA */
 123
 124
 125 static const char driver_name [] = "omap_udc";
 126 static const char driver_desc [] = DRIVER_DESC;
 127
 128 /*-------------------------------------------------------------------------*/
 129
 130 /* there's a notion of "current endpoint" for modifying endpoint
 131  * state, and PIO access to its FIFO.
 132  */
 133
 134 static void use_ep(struct omap_ep *ep, u16 select)
 135 {
 136         u16     num = ep->bEndpointAddress & 0x0f;
 137
 138         if (ep->bEndpointAddress & USB_DIR_IN)
 139                 num |= UDC_EP_DIR;
 140         UDC_EP_NUM_REG = num | select;
 141         /* when select, MUST deselect later !! */
 142 }
 143
 144 static inline void deselect_ep(void)
 145 {
 146         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
 147         /* 6 wait states before TX will happen */
 148 }
 149
 150 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 151
 152 /*-------------------------------------------------------------------------*/
 153
 154 static int omap_ep_enable(struct usb_ep *_ep,
 155                 const struct usb_endpoint_descriptor *desc)
 156 {
 157         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 158         struct omap_udc *udc;
 159         unsigned long   flags;
 160         u16             maxp;
 161
 162         /* catch various bogus parameters */
 163         if (!_ep || !desc || ep->desc
 164                         || desc->bDescriptorType != USB_DT_ENDPOINT
 165                         || ep->bEndpointAddress != desc->bEndpointAddress
 166                         || ep->maxpacket < le16_to_cpu
 167                                                 (desc->wMaxPacketSize)) {
 168                 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
 169                 return -EINVAL;
 170         }
 171         maxp = le16_to_cpu (desc->wMaxPacketSize);
 172         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 173                                 && maxp != ep->maxpacket)
 174                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 175                         || !desc->wMaxPacketSize) {
 176                 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 177                 return -ERANGE;
 178         }
 179
 180 #ifdef  USE_ISO
 181         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 182                                 && desc->bInterval != 1)) {
 183                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 184                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 185                                 1 << (desc->bInterval - 1));
 186                 return -EDOM;
 187         }
 188 #else
 189         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 190                 DBG("%s, ISO nyet\n", _ep->name);
 191                 return -EDOM;
 192         }
 193 #endif
 194
 195         /* xfer types must match, except that interrupt ~= bulk */
 196         if (ep->bmAttributes != desc->bmAttributes
 197                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 198                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 199                 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 200                 return -EINVAL;
 201         }
 202
 203         udc = ep->udc;
 204         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 205                 DBG("%s, bogus device state\n", __FUNCTION__);
 206                 return -ESHUTDOWN;
 207         }
 208
 209         spin_lock_irqsave(&udc->lock, flags);
 210
 211         ep->desc = desc;
 212         ep->irqs = 0;
 213         ep->stopped = 0;
 214         ep->ep.maxpacket = maxp;
 215
 216         /* set endpoint to initial state */
 217         ep->dma_channel = 0;
 218         ep->has_dma = 0;
 219         ep->lch = -1;
 220         use_ep(ep, UDC_EP_SEL);
 221         UDC_CTRL_REG = udc->clr_halt;
 222         ep->ackwait = 0;
 223         deselect_ep();
 224
 225         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 226                 list_add(&ep->iso, &udc->iso);
 227
 228         /* maybe assign a DMA channel to this endpoint */
 229         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 230                 /* FIXME ISO can dma, but prefers first channel */
 231                 dma_channel_claim(ep, 0);
 232
 233         /* PIO OUT may RX packets */
 234         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 235                         && !ep->has_dma
 236                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 237                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 238                 ep->ackwait = 1 + ep->double_buf;
 239         }
 240
 241         spin_unlock_irqrestore(&udc->lock, flags);
 242         VDBG("%s enabled\n", _ep->name);
 243         return 0;
 244 }
 245
 246 static void nuke(struct omap_ep *, int status);
 247
 248 static int omap_ep_disable(struct usb_ep *_ep)
 249 {
 250         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 251         unsigned long   flags;
 252
 253         if (!_ep || !ep->desc) {
 254                 DBG("%s, %s not enabled\n", __FUNCTION__,
 255                         _ep ? ep->ep.name : NULL);
 256                 return -EINVAL;
 257         }
 258
 259         spin_lock_irqsave(&ep->udc->lock, flags);
 260         ep->desc = NULL;
 261         nuke (ep, -ESHUTDOWN);
 262         ep->ep.maxpacket = ep->maxpacket;
 263         ep->has_dma = 0;
 264         UDC_CTRL_REG = UDC_SET_HALT;
 265         list_del_init(&ep->iso);
 266         del_timer(&ep->timer);
 267
 268         spin_unlock_irqrestore(&ep->udc->lock, flags);
 269
 270         VDBG("%s disabled\n", _ep->name);
 271         return 0;
 272 }
 273
 274 /*-------------------------------------------------------------------------*/
 275
 276 static struct usb_request *
 277 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 278 {
 279         struct omap_req *req;
 280
 281         req = kzalloc(sizeof(*req), gfp_flags);
 282         if (req) {
 283                 req->req.dma = DMA_ADDR_INVALID;
 284                 INIT_LIST_HEAD (&req->queue);
 285         }
 286         return &req->req;
 287 }
 288
 289 static void
 290 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 291 {
 292         struct omap_req *req = container_of(_req, struct omap_req, req);
 293
 294         if (_req)
 295                 kfree (req);
 296 }
 297
 298 /*-------------------------------------------------------------------------*/
 299
 300 static void
 301 done(struct omap_ep *ep, struct omap_req *req, int status)
 302 {
 303         unsigned                stopped = ep->stopped;
 304
 305         list_del_init(&req->queue);
 306
 307         if (req->req.status == -EINPROGRESS)
 308                 req->req.status = status;
 309         else
 310                 status = req->req.status;
 311
 312         if (use_dma && ep->has_dma) {
 313                 if (req->mapped) {
 314                         dma_unmap_single(ep->udc->gadget.dev.parent,
 315                                 req->req.dma, req->req.length,
 316                                 (ep->bEndpointAddress & USB_DIR_IN)
 317                                         ? DMA_TO_DEVICE
 318                                         : DMA_FROM_DEVICE);
 319                         req->req.dma = DMA_ADDR_INVALID;
 320                         req->mapped = 0;
 321                 } else
 322                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 323                                 req->req.dma, req->req.length,
 324                                 (ep->bEndpointAddress & USB_DIR_IN)
 325                                         ? DMA_TO_DEVICE
 326                                         : DMA_FROM_DEVICE);
 327         }
 328
 329 #ifndef USB_TRACE
 330         if (status && status != -ESHUTDOWN)
 331 #endif
 332                 VDBG("complete %s req %p stat %d len %u/%u\n",
 333                         ep->ep.name, &req->req, status,
 334                         req->req.actual, req->req.length);
 335
 336         /* don't modify queue heads during completion callback */
 337         ep->stopped = 1;
 338         spin_unlock(&ep->udc->lock);
 339         req->req.complete(&ep->ep, &req->req);
 340         spin_lock(&ep->udc->lock);
 341         ep->stopped = stopped;
 342 }
 343
 344 /*-------------------------------------------------------------------------*/
 345
 346 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 347 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 348
 349 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 350 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 351
 352 static inline int
 353 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 354 {
 355         unsigned        len;
 356         u16             *wp;
 357
 358         len = min(req->req.length - req->req.actual, max);
 359         req->req.actual += len;
 360
 361         max = len;
 362         if (likely((((int)buf) & 1) == 0)) {
 363                 wp = (u16 *)buf;
 364                 while (max >= 2) {
 365                         UDC_DATA_REG = *wp++;
 366                         max -= 2;
 367                 }
 368                 buf = (u8 *)wp;
 369         }
 370         while (max--)
 371                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
 372         return len;
 373 }
 374
 375 // FIXME change r/w fifo calling convention
 376
 377
 378 // return:  0 = still running, 1 = completed, negative = errno
 379 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 380 {
 381         u8              *buf;
 382         unsigned        count;
 383         int             is_last;
 384         u16             ep_stat;
 385
 386         buf = req->req.buf + req->req.actual;
 387         prefetch(buf);
 388
 389         /* PIO-IN isn't double buffered except for iso */
 390         ep_stat = UDC_STAT_FLG_REG;
 391         if (ep_stat & UDC_FIFO_UNWRITABLE)
 392                 return 0;
 393
 394         count = ep->ep.maxpacket;
 395         count = write_packet(buf, req, count);
 396         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 397         ep->ackwait = 1;
 398
 399         /* last packet is often short (sometimes a zlp) */
 400         if (count != ep->ep.maxpacket)
 401                 is_last = 1;
 402         else if (req->req.length == req->req.actual
 403                         && !req->req.zero)
 404                 is_last = 1;
 405         else
 406                 is_last = 0;
 407
 408         /* NOTE:  requests complete when all IN data is in a
 409          * FIFO (or sometimes later, if a zlp was needed).
 410          * Use usb_ep_fifo_status() where needed.
 411          */
 412         if (is_last)
 413                 done(ep, req, 0);
 414         return is_last;
 415 }
 416
 417 static inline int
 418 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 419 {
 420         unsigned        len;
 421         u16             *wp;
 422
 423         len = min(req->req.length - req->req.actual, avail);
 424         req->req.actual += len;
 425         avail = len;
 426
 427         if (likely((((int)buf) & 1) == 0)) {
 428                 wp = (u16 *)buf;
 429                 while (avail >= 2) {
 430                         *wp++ = UDC_DATA_REG;
 431                         avail -= 2;
 432                 }
 433                 buf = (u8 *)wp;
 434         }
 435         while (avail--)
 436                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
 437         return len;
 438 }
 439
 440 // return:  0 = still running, 1 = queue empty, negative = errno
 441 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 442 {
 443         u8              *buf;
 444         unsigned        count, avail;
 445         int             is_last;
 446
 447         buf = req->req.buf + req->req.actual;
 448         prefetchw(buf);
 449
 450         for (;;) {
 451                 u16     ep_stat = UDC_STAT_FLG_REG;
 452
 453                 is_last = 0;
 454                 if (ep_stat & FIFO_EMPTY) {
 455                         if (!ep->double_buf)
 456                                 break;
 457                         ep->fnf = 1;
 458                 }
 459                 if (ep_stat & UDC_EP_HALTED)
 460                         break;
 461
 462                 if (ep_stat & UDC_FIFO_FULL)
 463                         avail = ep->ep.maxpacket;
 464                 else  {
 465                         avail = UDC_RXFSTAT_REG;
 466                         ep->fnf = ep->double_buf;
 467                 }
 468                 count = read_packet(buf, req, avail);
 469
 470                 /* partial packet reads may not be errors */
 471                 if (count < ep->ep.maxpacket) {
 472                         is_last = 1;
 473                         /* overflowed this request?  flush extra data */
 474                         if (count != avail) {
 475                                 req->req.status = -EOVERFLOW;
 476                                 avail -= count;
 477                                 while (avail--)
 478                                         (void) *(volatile u8 *)&UDC_DATA_REG;
 479                         }
 480                 } else if (req->req.length == req->req.actual)
 481                         is_last = 1;
 482                 else
 483                         is_last = 0;
 484
 485                 if (!ep->bEndpointAddress)
 486                         break;
 487                 if (is_last)
 488                         done(ep, req, 0);
 489                 break;
 490         }
 491         return is_last;
 492 }
 493
 494 /*-------------------------------------------------------------------------*/
 495
 496 static inline dma_addr_t dma_csac(unsigned lch)
 497 {
 498         dma_addr_t      csac;
 499
 500         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 501          * read before the DMA controller finished disabling the channel.
 502          */
 503         csac = OMAP_DMA_CSAC_REG(lch);
 504         if (csac == 0)
 505                 csac = OMAP_DMA_CSAC_REG(lch);
 506         return csac;
 507 }
 508
 509 static inline dma_addr_t dma_cdac(unsigned lch)
 510 {
 511         dma_addr_t      cdac;
 512
 513         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 514          * read before the DMA controller finished disabling the channel.
 515          */
 516         cdac = OMAP_DMA_CDAC_REG(lch);
 517         if (cdac == 0)
 518                 cdac = OMAP_DMA_CDAC_REG(lch);
 519         return cdac;
 520 }
 521
 522 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 523 {
 524         dma_addr_t      end;
 525
 526         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 527          * the last transfer's bytecount by more than a FIFO's worth.
 528          */
 529         if (cpu_is_omap15xx())
 530                 return 0;
 531
 532         end = dma_csac(ep->lch);
 533         if (end == ep->dma_counter)
 534                 return 0;
 535
 536         end |= start & (0xffff << 16);
 537         if (end < start)
 538                 end += 0x10000;
 539         return end - start;
 540 }
 541
 542 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
 543                 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
 544                 : dma_cdac(x))
 545
 546 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 547 {
 548         dma_addr_t      end;
 549
 550         end = DMA_DEST_LAST(ep->lch);
 551         if (end == ep->dma_counter)
 552                 return 0;
 553
 554         end |= start & (0xffff << 16);
 555         if (cpu_is_omap15xx())
 556                 end++;
 557         if (end < start)
 558                 end += 0x10000;
 559         return end - start;
 560 }
 561
 562
 563 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 564  * When DMA completion isn't request completion, the UDC continues with
 565  * the next DMA transfer for that USB transfer.
 566  */
 567
 568 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 569 {
 570         u16             txdma_ctrl;
 571         unsigned        length = req->req.length - req->req.actual;
 572         const int       sync_mode = cpu_is_omap15xx()
 573                                 ? OMAP_DMA_SYNC_FRAME
 574                                 : OMAP_DMA_SYNC_ELEMENT;
 575
 576         /* measure length in either bytes or packets */
 577         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 578                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 579                 txdma_ctrl = UDC_TXN_EOT | length;
 580                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 581                                 length, 1, sync_mode, 0, 0);
 582         } else {
 583                 length = min(length / ep->maxpacket,
 584                                 (unsigned) UDC_TXN_TSC + 1);
 585                 txdma_ctrl = length;
 586                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 587                                 ep->ep.maxpacket >> 1, length, sync_mode,
 588                                 0, 0);
 589                 length *= ep->maxpacket;
 590         }
 591         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 592                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 593                 0, 0);
 594
 595         omap_start_dma(ep->lch);
 596         ep->dma_counter = dma_csac(ep->lch);
 597         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
 598         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
 599         req->dma_bytes = length;
 600 }
 601
 602 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 603 {
 604         if (status == 0) {
 605                 req->req.actual += req->dma_bytes;
 606
 607                 /* return if this request needs to send data or zlp */
 608                 if (req->req.actual < req->req.length)
 609                         return;
 610                 if (req->req.zero
 611                                 && req->dma_bytes != 0
 612                                 && (req->req.actual % ep->maxpacket) == 0)
 613                         return;
 614         } else
 615                 req->req.actual += dma_src_len(ep, req->req.dma
 616                                                         + req->req.actual);
 617
 618         /* tx completion */
 619         omap_stop_dma(ep->lch);
 620         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
 621         done(ep, req, status);
 622 }
 623
 624 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 625 {
 626         unsigned packets;
 627
 628         /* NOTE:  we filtered out "short reads" before, so we know
 629          * the buffer has only whole numbers of packets.
 630          */
 631
 632         /* set up this DMA transfer, enable the fifo, start */
 633         packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
 634         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 635         req->dma_bytes = packets * ep->ep.maxpacket;
 636         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 637                         ep->ep.maxpacket >> 1, packets,
 638                         OMAP_DMA_SYNC_ELEMENT,
 639                         0, 0);
 640         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 641                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 642                 0, 0);
 643         ep->dma_counter = DMA_DEST_LAST(ep->lch);
 644
 645         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
 646         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
 647         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
 648         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 649
 650         omap_start_dma(ep->lch);
 651 }
 652
 653 static void
 654 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 655 {
 656         u16     count;
 657
 658         if (status == 0)
 659                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 660         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 661         count += req->req.actual;
 662         if (one)
 663                 count--;
 664         if (count <= req->req.length)
 665                 req->req.actual = count;
 666
 667         if (count != req->dma_bytes || status)
 668                 omap_stop_dma(ep->lch);
 669
 670         /* if this wasn't short, request may need another transfer */
 671         else if (req->req.actual < req->req.length)
 672                 return;
 673
 674         /* rx completion */
 675         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
 676         done(ep, req, status);
 677 }
 678
 679 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 680 {
 681         u16             dman_stat = UDC_DMAN_STAT_REG;
 682         struct omap_ep  *ep;
 683         struct omap_req *req;
 684
 685         /* IN dma: tx to host */
 686         if (irq_src & UDC_TXN_DONE) {
 687                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 688                 ep->irqs++;
 689                 /* can see TXN_DONE after dma abort */
 690                 if (!list_empty(&ep->queue)) {
 691                         req = container_of(ep->queue.next,
 692                                                 struct omap_req, queue);
 693                         finish_in_dma(ep, req, 0);
 694                 }
 695                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
 696
 697                 if (!list_empty (&ep->queue)) {
 698                         req = container_of(ep->queue.next,
 699                                         struct omap_req, queue);
 700                         next_in_dma(ep, req);
 701                 }
 702         }
 703
 704         /* OUT dma: rx from host */
 705         if (irq_src & UDC_RXN_EOT) {
 706                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 707                 ep->irqs++;
 708                 /* can see RXN_EOT after dma abort */
 709                 if (!list_empty(&ep->queue)) {
 710                         req = container_of(ep->queue.next,
 711                                         struct omap_req, queue);
 712                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 713                 }
 714                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
 715
 716                 if (!list_empty (&ep->queue)) {
 717                         req = container_of(ep->queue.next,
 718                                         struct omap_req, queue);
 719                         next_out_dma(ep, req);
 720                 }
 721         }
 722
 723         if (irq_src & UDC_RXN_CNT) {
 724                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 725                 ep->irqs++;
 726                 /* omap15xx does this unasked... */
 727                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 728                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
 729         }
 730 }
 731
 732 static void dma_error(int lch, u16 ch_status, void *data)
 733 {
 734         struct omap_ep  *ep = data;
 735
 736         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 737         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 738         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 739
 740         /* complete current transfer ... */
 741 }
 742
 743 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 744 {
 745         u16     reg;
 746         int     status, restart, is_in;
 747
 748         is_in = ep->bEndpointAddress & USB_DIR_IN;
 749         if (is_in)
 750                 reg = UDC_TXDMA_CFG_REG;
 751         else
 752                 reg = UDC_RXDMA_CFG_REG;
 753         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 754
 755         ep->dma_channel = 0;
 756         ep->lch = -1;
 757         if (channel == 0 || channel > 3) {
 758                 if ((reg & 0x0f00) == 0)
 759                         channel = 3;
 760                 else if ((reg & 0x00f0) == 0)
 761                         channel = 2;
 762                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 763                         channel = 1;
 764                 else {
 765                         status = -EMLINK;
 766                         goto just_restart;
 767                 }
 768         }
 769         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 770         ep->dma_channel = channel;
 771
 772         if (is_in) {
 773                 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
 774                         ep->ep.name, dma_error, ep, &ep->lch);
 775                 if (status == 0) {
 776                         UDC_TXDMA_CFG_REG = reg;
 777                         /* EMIFF */
 778                         omap_set_dma_src_burst_mode(ep->lch,
 779                                                 OMAP_DMA_DATA_BURST_4);
 780                         omap_set_dma_src_data_pack(ep->lch, 1);
 781                         /* TIPB */
 782                         omap_set_dma_dest_params(ep->lch,
 783                                 OMAP_DMA_PORT_TIPB,
 784                                 OMAP_DMA_AMODE_CONSTANT,
 785                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 786                                 0, 0);
 787                 }
 788         } else {
 789                 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
 790                         ep->ep.name, dma_error, ep, &ep->lch);
 791                 if (status == 0) {
 792                         UDC_RXDMA_CFG_REG = reg;
 793                         /* TIPB */
 794                         omap_set_dma_src_params(ep->lch,
 795                                 OMAP_DMA_PORT_TIPB,
 796                                 OMAP_DMA_AMODE_CONSTANT,
 797                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 798                                 0, 0);
 799                         /* EMIFF */
 800                         omap_set_dma_dest_burst_mode(ep->lch,
 801                                                 OMAP_DMA_DATA_BURST_4);
 802                         omap_set_dma_dest_data_pack(ep->lch, 1);
 803                 }
 804         }
 805         if (status)
 806                 ep->dma_channel = 0;
 807         else {
 808                 ep->has_dma = 1;
 809                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 810
 811                 /* channel type P: hw synch (fifo) */
 812                 if (!cpu_is_omap15xx())
 813                         OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
 814         }
 815
 816 just_restart:
 817         /* restart any queue, even if the claim failed  */
 818         restart = !ep->stopped && !list_empty(&ep->queue);
 819
 820         if (status)
 821                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 822                         restart ? " (restart)" : "");
 823         else
 824                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 825                         is_in ? 't' : 'r',
 826                         ep->dma_channel - 1, ep->lch,
 827                         restart ? " (restart)" : "");
 828
 829         if (restart) {
 830                 struct omap_req *req;
 831                 req = container_of(ep->queue.next, struct omap_req, queue);
 832                 if (ep->has_dma)
 833                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 834                 else {
 835                         use_ep(ep, UDC_EP_SEL);
 836                         (is_in ? write_fifo : read_fifo)(ep, req);
 837                         deselect_ep();
 838                         if (!is_in) {
 839                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 840                                 ep->ackwait = 1 + ep->double_buf;
 841                         }
 842                         /* IN: 6 wait states before it'll tx */
 843                 }
 844         }
 845 }
 846
 847 static void dma_channel_release(struct omap_ep *ep)
 848 {
 849         int             shift = 4 * (ep->dma_channel - 1);
 850         u16             mask = 0x0f << shift;
 851         struct omap_req *req;
 852         int             active;
 853
 854         /* abort any active usb transfer request */
 855         if (!list_empty(&ep->queue))
 856                 req = container_of(ep->queue.next, struct omap_req, queue);
 857         else
 858                 req = NULL;
 859
 860         active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
 861
 862         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 863                         active ? "active" : "idle",
 864                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 865                         ep->dma_channel - 1, req);
 866
 867         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 868          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 869          */
 870
 871         /* wait till current packet DMA finishes, and fifo empties */
 872         if (ep->bEndpointAddress & USB_DIR_IN) {
 873                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 874
 875                 if (req) {
 876                         finish_in_dma(ep, req, -ECONNRESET);
 877
 878                         /* clear FIFO; hosts probably won't empty it */
 879                         use_ep(ep, UDC_EP_SEL);
 880                         UDC_CTRL_REG = UDC_CLR_EP;
 881                         deselect_ep();
 882                 }
 883                 while (UDC_TXDMA_CFG_REG & mask)
 884                         udelay(10);
 885         } else {
 886                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 887
 888                 /* dma empties the fifo */
 889                 while (UDC_RXDMA_CFG_REG & mask)
 890                         udelay(10);
 891                 if (req)
 892                         finish_out_dma(ep, req, -ECONNRESET, 0);
 893         }
 894         omap_free_dma(ep->lch);
 895         ep->dma_channel = 0;
 896         ep->lch = -1;
 897         /* has_dma still set, till endpoint is fully quiesced */
 898 }
 899
 900
 901 /*-------------------------------------------------------------------------*/
 902
 903 static int
 904 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 905 {
 906         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 907         struct omap_req *req = container_of(_req, struct omap_req, req);
 908         struct omap_udc *udc;
 909         unsigned long   flags;
 910         int             is_iso = 0;
 911
 912         /* catch various bogus parameters */
 913         if (!_req || !req->req.complete || !req->req.buf
 914                         || !list_empty(&req->queue)) {
 915                 DBG("%s, bad params\n", __FUNCTION__);
 916                 return -EINVAL;
 917         }
 918         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 919                 DBG("%s, bad ep\n", __FUNCTION__);
 920                 return -EINVAL;
 921         }
 922         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 923                 if (req->req.length > ep->ep.maxpacket)
 924                         return -EMSGSIZE;
 925                 is_iso = 1;
 926         }
 927
 928         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 929          * have a hard time with partial packet reads...  reject it.
 930          */
 931         if (use_dma
 932                         && ep->has_dma
 933                         && ep->bEndpointAddress != 0
 934                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 935                         && (req->req.length % ep->ep.maxpacket) != 0) {
 936                 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
 937                 return -EMSGSIZE;
 938         }
 939
 940         udc = ep->udc;
 941         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 942                 return -ESHUTDOWN;
 943
 944         if (use_dma && ep->has_dma) {
 945                 if (req->req.dma == DMA_ADDR_INVALID) {
 946                         req->req.dma = dma_map_single(
 947                                 ep->udc->gadget.dev.parent,
 948                                 req->req.buf,
 949                                 req->req.length,
 950                                 (ep->bEndpointAddress & USB_DIR_IN)
 951                                         ? DMA_TO_DEVICE
 952                                         : DMA_FROM_DEVICE);
 953                         req->mapped = 1;
 954                 } else {
 955                         dma_sync_single_for_device(
 956                                 ep->udc->gadget.dev.parent,
 957                                 req->req.dma, req->req.length,
 958                                 (ep->bEndpointAddress & USB_DIR_IN)
 959                                         ? DMA_TO_DEVICE
 960                                         : DMA_FROM_DEVICE);
 961                         req->mapped = 0;
 962                 }
 963         }
 964
 965         VDBG("%s queue req %p, len %d buf %p\n",
 966                 ep->ep.name, _req, _req->length, _req->buf);
 967
 968         spin_lock_irqsave(&udc->lock, flags);
 969
 970         req->req.status = -EINPROGRESS;
 971         req->req.actual = 0;
 972
 973         /* maybe kickstart non-iso i/o queues */
 974         if (is_iso)
 975                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
 976         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
 977                 int     is_in;
 978
 979                 if (ep->bEndpointAddress == 0) {
 980                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
 981                                 spin_unlock_irqrestore(&udc->lock, flags);
 982                                 return -EL2HLT;
 983                         }
 984
 985                         /* empty DATA stage? */
 986                         is_in = udc->ep0_in;
 987                         if (!req->req.length) {
 988
 989                                 /* chip became CONFIGURED or ADDRESSED
 990                                  * earlier; drivers may already have queued
 991                                  * requests to non-control endpoints
 992                                  */
 993                                 if (udc->ep0_set_config) {
 994                                         u16     irq_en = UDC_IRQ_EN_REG;
 995
 996                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
 997                                         if (!udc->ep0_reset_config)
 998                                                 irq_en |= UDC_EPN_RX_IE
 999                                                         | UDC_EPN_TX_IE;
1000                                         UDC_IRQ_EN_REG = irq_en;
1001                                 }
1002
1003                                 /* STATUS for zero length DATA stages is
1004                                  * always an IN ... even for IN transfers,
1005                                  * a wierd case which seem to stall OMAP.
1006                                  */
1007                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1008                                 UDC_CTRL_REG = UDC_CLR_EP;
1009                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1010                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1011
1012                                 /* cleanup */
1013                                 udc->ep0_pending = 0;
1014                                 done(ep, req, 0);
1015                                 req = NULL;
1016
1017                         /* non-empty DATA stage */
1018                         } else if (is_in) {
1019                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1020                         } else {
1021                                 if (udc->ep0_setup)
1022                                         goto irq_wait;
1023                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1024                         }
1025                 } else {
1026                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1027                         if (!ep->has_dma)
1028                                 use_ep(ep, UDC_EP_SEL);
1029                         /* if ISO: SOF IRQs must be enabled/disabled! */
1030                 }
1031
1032                 if (ep->has_dma)
1033                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1034                 else if (req) {
1035                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1036                                 req = NULL;
1037                         deselect_ep();
1038                         if (!is_in) {
1039                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1040                                 ep->ackwait = 1 + ep->double_buf;
1041                         }
1042                         /* IN: 6 wait states before it'll tx */
1043                 }
1044         }
1045
1046 irq_wait:
1047         /* irq handler advances the queue */
1048         if (req != NULL)
1049                 list_add_tail(&req->queue, &ep->queue);
1050         spin_unlock_irqrestore(&udc->lock, flags);
1051
1052         return 0;
1053 }
1054
1055 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1056 {
1057         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1058         struct omap_req *req;
1059         unsigned long   flags;
1060
1061         if (!_ep || !_req)
1062                 return -EINVAL;
1063
1064         spin_lock_irqsave(&ep->udc->lock, flags);
1065
1066         /* make sure it's actually queued on this endpoint */
1067         list_for_each_entry (req, &ep->queue, queue) {
1068                 if (&req->req == _req)
1069                         break;
1070         }
1071         if (&req->req != _req) {
1072                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1073                 return -EINVAL;
1074         }
1075
1076         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1077                 int channel = ep->dma_channel;
1078
1079                 /* releasing the channel cancels the request,
1080                  * reclaiming the channel restarts the queue
1081                  */
1082                 dma_channel_release(ep);
1083                 dma_channel_claim(ep, channel);
1084         } else
1085                 done(ep, req, -ECONNRESET);
1086         spin_unlock_irqrestore(&ep->udc->lock, flags);
1087         return 0;
1088 }
1089
1090 /*-------------------------------------------------------------------------*/
1091
1092 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1093 {
1094         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1095         unsigned long   flags;
1096         int             status = -EOPNOTSUPP;
1097
1098         spin_lock_irqsave(&ep->udc->lock, flags);
1099
1100         /* just use protocol stalls for ep0; real halts are annoying */
1101         if (ep->bEndpointAddress == 0) {
1102                 if (!ep->udc->ep0_pending)
1103                         status = -EINVAL;
1104                 else if (value) {
1105                         if (ep->udc->ep0_set_config) {
1106                                 WARN("error changing config?\n");
1107                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1108                         }
1109                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1110                         ep->udc->ep0_pending = 0;
1111                         status = 0;
1112                 } else /* NOP */
1113                         status = 0;
1114
1115         /* otherwise, all active non-ISO endpoints can halt */
1116         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1117
1118                 /* IN endpoints must already be idle */
1119                 if ((ep->bEndpointAddress & USB_DIR_IN)
1120                                 && !list_empty(&ep->queue)) {
1121                         status = -EAGAIN;
1122                         goto done;
1123                 }
1124
1125                 if (value) {
1126                         int     channel;
1127
1128                         if (use_dma && ep->dma_channel
1129                                         && !list_empty(&ep->queue)) {
1130                                 channel = ep->dma_channel;
1131                                 dma_channel_release(ep);
1132                         } else
1133                                 channel = 0;
1134
1135                         use_ep(ep, UDC_EP_SEL);
1136                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1137                                 UDC_CTRL_REG = UDC_SET_HALT;
1138                                 status = 0;
1139                         } else
1140                                 status = -EAGAIN;
1141                         deselect_ep();
1142
1143                         if (channel)
1144                                 dma_channel_claim(ep, channel);
1145                 } else {
1146                         use_ep(ep, 0);
1147                         UDC_CTRL_REG = ep->udc->clr_halt;
1148                         ep->ackwait = 0;
1149                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1150                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1151                                 ep->ackwait = 1 + ep->double_buf;
1152                         }
1153                 }
1154         }
1155 done:
1156         VDBG("%s %s halt stat %d\n", ep->ep.name,
1157                 value ? "set" : "clear", status);
1158
1159         spin_unlock_irqrestore(&ep->udc->lock, flags);
1160         return status;
1161 }
1162
1163 static struct usb_ep_ops omap_ep_ops = {
1164         .enable         = omap_ep_enable,
1165         .disable        = omap_ep_disable,
1166
1167         .alloc_request  = omap_alloc_request,
1168         .free_request   = omap_free_request,
1169
1170         .queue          = omap_ep_queue,
1171         .dequeue        = omap_ep_dequeue,
1172
1173         .set_halt       = omap_ep_set_halt,
1174         // fifo_status ... report bytes in fifo
1175         // fifo_flush ... flush fifo
1176 };
1177
1178 /*-------------------------------------------------------------------------*/
1179
1180 static int omap_get_frame(struct usb_gadget *gadget)
1181 {
1182         u16     sof = UDC_SOF_REG;
1183         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1184 }
1185
1186 static int omap_wakeup(struct usb_gadget *gadget)
1187 {
1188         struct omap_udc *udc;
1189         unsigned long   flags;
1190         int             retval = -EHOSTUNREACH;
1191
1192         udc = container_of(gadget, struct omap_udc, gadget);
1193
1194         spin_lock_irqsave(&udc->lock, flags);
1195         if (udc->devstat & UDC_SUS) {
1196                 /* NOTE:  OTG spec erratum says that OTG devices may
1197                  * issue wakeups without host enable.
1198                  */
1199                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1200                         DBG("remote wakeup...\n");
1201                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1202                         retval = 0;
1203                 }
1204
1205         /* NOTE:  non-OTG systems may use SRP TOO... */
1206         } else if (!(udc->devstat & UDC_ATT)) {
1207                 if (udc->transceiver)
1208                         retval = otg_start_srp(udc->transceiver);
1209         }
1210         spin_unlock_irqrestore(&udc->lock, flags);
1211
1212         return retval;
1213 }
1214
1215 static int
1216 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1217 {
1218         struct omap_udc *udc;
1219         unsigned long   flags;
1220         u16             syscon1;
1221
1222         udc = container_of(gadget, struct omap_udc, gadget);
1223         spin_lock_irqsave(&udc->lock, flags);
1224         syscon1 = UDC_SYSCON1_REG;
1225         if (is_selfpowered)
1226                 syscon1 |= UDC_SELF_PWR;
1227         else
1228                 syscon1 &= ~UDC_SELF_PWR;
1229         UDC_SYSCON1_REG = syscon1;
1230         spin_unlock_irqrestore(&udc->lock, flags);
1231
1232         return 0;
1233 }
1234
1235 static int can_pullup(struct omap_udc *udc)
1236 {
1237         return udc->driver && udc->softconnect && udc->vbus_active;
1238 }
1239
1240 static void pullup_enable(struct omap_udc *udc)
1241 {
1242         udc->gadget.dev.parent->power.power_state = PMSG_ON;
1243         udc->gadget.dev.power.power_state = PMSG_ON;
1244         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1245         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1246                 OTG_CTRL_REG |= OTG_BSESSVLD;
1247         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1248 }
1249
1250 static void pullup_disable(struct omap_udc *udc)
1251 {
1252         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
1253                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1254         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1255         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1256 }
1257
1258 static struct omap_udc *udc;
1259
1260 static void omap_udc_enable_clock(int enable)
1261 {
1262         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1263                 return;
1264
1265         if (enable) {
1266                 clk_enable(udc->dc_clk);
1267                 clk_enable(udc->hhc_clk);
1268                 udelay(100);
1269         } else {
1270                 clk_disable(udc->hhc_clk);
1271                 clk_disable(udc->dc_clk);
1272         }
1273 }
1274
1275 /*
1276  * Called by whatever detects VBUS sessions:  external transceiver
1277  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1278  */
1279 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1280 {
1281         struct omap_udc *udc;
1282         unsigned long   flags;
1283
1284         udc = container_of(gadget, struct omap_udc, gadget);
1285         spin_lock_irqsave(&udc->lock, flags);
1286         VDBG("VBUS %s\n", is_active ? "on" : "off");
1287         udc->vbus_active = (is_active != 0);
1288         if (cpu_is_omap15xx()) {
1289                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1290                 if (is_active)
1291                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1292                 else
1293                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1294         }
1295         if (udc->dc_clk != NULL && is_active) {
1296                 if (!udc->clk_requested) {
1297                         omap_udc_enable_clock(1);
1298                         udc->clk_requested = 1;
1299                 }
1300         }
1301         if (can_pullup(udc))
1302                 pullup_enable(udc);
1303         else
1304                 pullup_disable(udc);
1305         if (udc->dc_clk != NULL && !is_active) {
1306                 if (udc->clk_requested) {
1307                         omap_udc_enable_clock(0);
1308                         udc->clk_requested = 0;
1309                 }
1310         }
1311         spin_unlock_irqrestore(&udc->lock, flags);
1312         return 0;
1313 }
1314
1315 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1316 {
1317         struct omap_udc *udc;
1318
1319         udc = container_of(gadget, struct omap_udc, gadget);
1320         if (udc->transceiver)
1321                 return otg_set_power(udc->transceiver, mA);
1322         return -EOPNOTSUPP;
1323 }
1324
1325 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1326 {
1327         struct omap_udc *udc;
1328         unsigned long   flags;
1329
1330         udc = container_of(gadget, struct omap_udc, gadget);
1331         spin_lock_irqsave(&udc->lock, flags);
1332         udc->softconnect = (is_on != 0);
1333         if (can_pullup(udc))
1334                 pullup_enable(udc);
1335         else
1336                 pullup_disable(udc);
1337         spin_unlock_irqrestore(&udc->lock, flags);
1338         return 0;
1339 }
1340
1341 static struct usb_gadget_ops omap_gadget_ops = {
1342         .get_frame              = omap_get_frame,
1343         .wakeup                 = omap_wakeup,
1344         .set_selfpowered        = omap_set_selfpowered,
1345         .vbus_session           = omap_vbus_session,
1346         .vbus_draw              = omap_vbus_draw,
1347         .pullup                 = omap_pullup,
1348 };
1349
1350 /*-------------------------------------------------------------------------*/
1351
1352 /* dequeue ALL requests; caller holds udc->lock */
1353 static void nuke(struct omap_ep *ep, int status)
1354 {
1355         struct omap_req *req;
1356
1357         ep->stopped = 1;
1358
1359         if (use_dma && ep->dma_channel)
1360                 dma_channel_release(ep);
1361
1362         use_ep(ep, 0);
1363         UDC_CTRL_REG = UDC_CLR_EP;
1364         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1365                 UDC_CTRL_REG = UDC_SET_HALT;
1366
1367         while (!list_empty(&ep->queue)) {
1368                 req = list_entry(ep->queue.next, struct omap_req, queue);
1369                 done(ep, req, status);
1370         }
1371 }
1372
1373 /* caller holds udc->lock */
1374 static void udc_quiesce(struct omap_udc *udc)
1375 {
1376         struct omap_ep  *ep;
1377
1378         udc->gadget.speed = USB_SPEED_UNKNOWN;
1379         nuke(&udc->ep[0], -ESHUTDOWN);
1380         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1381                 nuke(ep, -ESHUTDOWN);
1382 }
1383
1384 /*-------------------------------------------------------------------------*/
1385
1386 static void update_otg(struct omap_udc *udc)
1387 {
1388         u16     devstat;
1389
1390         if (!gadget_is_otg(&udc->gadget))
1391                 return;
1392
1393         if (OTG_CTRL_REG & OTG_ID)
1394                 devstat = UDC_DEVSTAT_REG;
1395         else
1396                 devstat = 0;
1397
1398         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1399         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1400         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1401
1402         /* Enable HNP early, avoiding races on suspend irq path.
1403          * ASSUMES OTG state machine B_BUS_REQ input is true.
1404          */
1405         if (udc->gadget.b_hnp_enable)
1406                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1407                                 & ~OTG_PULLUP;
1408 }
1409
1410 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1411 {
1412         struct omap_ep  *ep0 = &udc->ep[0];
1413         struct omap_req *req = NULL;
1414
1415         ep0->irqs++;
1416
1417         /* Clear any pending requests and then scrub any rx/tx state
1418          * before starting to handle the SETUP request.
1419          */
1420         if (irq_src & UDC_SETUP) {
1421                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1422
1423                 nuke(ep0, 0);
1424                 if (ack) {
1425                         UDC_IRQ_SRC_REG = ack;
1426                         irq_src = UDC_SETUP;
1427                 }
1428         }
1429
1430         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1431          * This driver uses only uses protocol stalls (ep0 never halts),
1432          * and if we got this far the gadget driver already had a
1433          * chance to stall.  Tries to be forgiving of host oddities.
1434          *
1435          * NOTE:  the last chance gadget drivers have to stall control
1436          * requests is during their request completion callback.
1437          */
1438         if (!list_empty(&ep0->queue))
1439                 req = container_of(ep0->queue.next, struct omap_req, queue);
1440
1441         /* IN == TX to host */
1442         if (irq_src & UDC_EP0_TX) {
1443                 int     stat;
1444
1445                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1446                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1447                 stat = UDC_STAT_FLG_REG;
1448                 if (stat & UDC_ACK) {
1449                         if (udc->ep0_in) {
1450                                 /* write next IN packet from response,
1451                                  * or set up the status stage.
1452                                  */
1453                                 if (req)
1454                                         stat = write_fifo(ep0, req);
1455                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1456                                 if (!req && udc->ep0_pending) {
1457                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1458                                         UDC_CTRL_REG = UDC_CLR_EP;
1459                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1460                                         UDC_EP_NUM_REG = 0;
1461                                         udc->ep0_pending = 0;
1462                                 } /* else:  6 wait states before it'll tx */
1463                         } else {
1464                                 /* ack status stage of OUT transfer */
1465                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1466                                 if (req)
1467                                         done(ep0, req, 0);
1468                         }
1469                         req = NULL;
1470                 } else if (stat & UDC_STALL) {
1471                         UDC_CTRL_REG = UDC_CLR_HALT;
1472                         UDC_EP_NUM_REG = UDC_EP_DIR;
1473                 } else {
1474                         UDC_EP_NUM_REG = UDC_EP_DIR;
1475                 }
1476         }
1477
1478         /* OUT == RX from host */
1479         if (irq_src & UDC_EP0_RX) {
1480                 int     stat;
1481
1482                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1483                 UDC_EP_NUM_REG = UDC_EP_SEL;
1484                 stat = UDC_STAT_FLG_REG;
1485                 if (stat & UDC_ACK) {
1486                         if (!udc->ep0_in) {
1487                                 stat = 0;
1488                                 /* read next OUT packet of request, maybe
1489                                  * reactiviting the fifo; stall on errors.
1490                                  */
1491                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1492                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1493                                         udc->ep0_pending = 0;
1494                                         stat = 0;
1495                                 } else if (stat == 0)
1496                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1497                                 UDC_EP_NUM_REG = 0;
1498
1499                                 /* activate status stage */
1500                                 if (stat == 1) {
1501                                         done(ep0, req, 0);
1502                                         /* that may have STALLed ep0... */
1503                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1504                                         UDC_CTRL_REG = UDC_CLR_EP;
1505                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1506                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1507                                         udc->ep0_pending = 0;
1508                                 }
1509                         } else {
1510                                 /* ack status stage of IN transfer */
1511                                 UDC_EP_NUM_REG = 0;
1512                                 if (req)
1513                                         done(ep0, req, 0);
1514                         }
1515                 } else if (stat & UDC_STALL) {
1516                         UDC_CTRL_REG = UDC_CLR_HALT;
1517                         UDC_EP_NUM_REG = 0;
1518                 } else {
1519                         UDC_EP_NUM_REG = 0;
1520                 }
1521         }
1522
1523         /* SETUP starts all control transfers */
1524         if (irq_src & UDC_SETUP) {
1525                 union u {
1526                         u16                     word[4];
1527                         struct usb_ctrlrequest  r;
1528                 } u;
1529                 int                     status = -EINVAL;
1530                 struct omap_ep          *ep;
1531
1532                 /* read the (latest) SETUP message */
1533                 do {
1534                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1535                         /* two bytes at a time */
1536                         u.word[0] = UDC_DATA_REG;
1537                         u.word[1] = UDC_DATA_REG;
1538                         u.word[2] = UDC_DATA_REG;
1539                         u.word[3] = UDC_DATA_REG;
1540                         UDC_EP_NUM_REG = 0;
1541                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1542
1543 #define w_value         le16_to_cpu(u.r.wValue)
1544 #define w_index         le16_to_cpu(u.r.wIndex)
1545 #define w_length        le16_to_cpu(u.r.wLength)
1546
1547                 /* Delegate almost all control requests to the gadget driver,
1548                  * except for a handful of ch9 status/feature requests that
1549                  * hardware doesn't autodecode _and_ the gadget API hides.
1550                  */
1551                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1552                 udc->ep0_set_config = 0;
1553                 udc->ep0_pending = 1;
1554                 ep0->stopped = 0;
1555                 ep0->ackwait = 0;
1556                 switch (u.r.bRequest) {
1557                 case USB_REQ_SET_CONFIGURATION:
1558                         /* udc needs to know when ep != 0 is valid */
1559                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1560                                 goto delegate;
1561                         if (w_length != 0)
1562                                 goto do_stall;
1563                         udc->ep0_set_config = 1;
1564                         udc->ep0_reset_config = (w_value == 0);
1565                         VDBG("set config %d\n", w_value);
1566
1567                         /* update udc NOW since gadget driver may start
1568                          * queueing requests immediately; clear config
1569                          * later if it fails the request.
1570                          */
1571                         if (udc->ep0_reset_config)
1572                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1573                         else
1574                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1575                         update_otg(udc);
1576                         goto delegate;
1577                 case USB_REQ_CLEAR_FEATURE:
1578                         /* clear endpoint halt */
1579                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1580                                 goto delegate;
1581                         if (w_value != USB_ENDPOINT_HALT
1582                                         || w_length != 0)
1583                                 goto do_stall;
1584                         ep = &udc->ep[w_index & 0xf];
1585                         if (ep != ep0) {
1586                                 if (w_index & USB_DIR_IN)
1587                                         ep += 16;
1588                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1589                                                 || !ep->desc)
1590                                         goto do_stall;
1591                                 use_ep(ep, 0);
1592                                 UDC_CTRL_REG = udc->clr_halt;
1593                                 ep->ackwait = 0;
1594                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1595                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1596                                         ep->ackwait = 1 + ep->double_buf;
1597                                 }
1598                                 /* NOTE:  assumes the host behaves sanely,
1599                                  * only clearing real halts.  Else we may
1600                                  * need to kill pending transfers and then
1601                                  * restart the queue... very messy for DMA!
1602                                  */
1603                         }
1604                         VDBG("%s halt cleared by host\n", ep->name);
1605                         goto ep0out_status_stage;
1606                 case USB_REQ_SET_FEATURE:
1607                         /* set endpoint halt */
1608                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1609                                 goto delegate;
1610                         if (w_value != USB_ENDPOINT_HALT
1611                                         || w_length != 0)
1612                                 goto do_stall;
1613                         ep = &udc->ep[w_index & 0xf];
1614                         if (w_index & USB_DIR_IN)
1615                                 ep += 16;
1616                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1617                                         || ep == ep0 || !ep->desc)
1618                                 goto do_stall;
1619                         if (use_dma && ep->has_dma) {
1620                                 /* this has rude side-effects (aborts) and
1621                                  * can't really work if DMA-IN is active
1622                                  */
1623                                 DBG("%s host set_halt, NYET \n", ep->name);
1624                                 goto do_stall;
1625                         }
1626                         use_ep(ep, 0);
1627                         /* can't halt if fifo isn't empty... */
1628                         UDC_CTRL_REG = UDC_CLR_EP;
1629                         UDC_CTRL_REG = UDC_SET_HALT;
1630                         VDBG("%s halted by host\n", ep->name);
1631 ep0out_status_stage:
1632                         status = 0;
1633                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1634                         UDC_CTRL_REG = UDC_CLR_EP;
1635                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1636                         UDC_EP_NUM_REG = UDC_EP_DIR;
1637                         udc->ep0_pending = 0;
1638                         break;
1639                 case USB_REQ_GET_STATUS:
1640                         /* USB_ENDPOINT_HALT status? */
1641                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1642                                 goto intf_status;
1643
1644                         /* ep0 never stalls */
1645                         if (!(w_index & 0xf))
1646                                 goto zero_status;
1647
1648                         /* only active endpoints count */
1649                         ep = &udc->ep[w_index & 0xf];
1650                         if (w_index & USB_DIR_IN)
1651                                 ep += 16;
1652                         if (!ep->desc)
1653                                 goto do_stall;
1654
1655                         /* iso never stalls */
1656                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1657                                 goto zero_status;
1658
1659                         /* FIXME don't assume non-halted endpoints!! */
1660                         ERR("%s status, can't report\n", ep->ep.name);
1661                         goto do_stall;
1662
1663 intf_status:
1664                         /* return interface status.  if we were pedantic,
1665                          * we'd detect non-existent interfaces, and stall.
1666                          */
1667                         if (u.r.bRequestType
1668                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1669                                 goto delegate;
1670
1671 zero_status:
1672                         /* return two zero bytes */
1673                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1674                         UDC_DATA_REG = 0;
1675                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1676                         UDC_EP_NUM_REG = UDC_EP_DIR;
1677                         status = 0;
1678                         VDBG("GET_STATUS, interface %d\n", w_index);
1679                         /* next, status stage */
1680                         break;
1681                 default:
1682 delegate:
1683                         /* activate the ep0out fifo right away */
1684                         if (!udc->ep0_in && w_length) {
1685                                 UDC_EP_NUM_REG = 0;
1686                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1687                         }
1688
1689                         /* gadget drivers see class/vendor specific requests,
1690                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1691                          * and more
1692                          */
1693                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1694                                 u.r.bRequestType, u.r.bRequest,
1695                                 w_value, w_index, w_length);
1696
1697 #undef  w_value
1698 #undef  w_index
1699 #undef  w_length
1700
1701                         /* The gadget driver may return an error here,
1702                          * causing an immediate protocol stall.
1703                          *
1704                          * Else it must issue a response, either queueing a
1705                          * response buffer for the DATA stage, or halting ep0
1706                          * (causing a protocol stall, not a real halt).  A
1707                          * zero length buffer means no DATA stage.
1708                          *
1709                          * It's fine to issue that response after the setup()
1710                          * call returns, and this IRQ was handled.
1711                          */
1712                         udc->ep0_setup = 1;
1713                         spin_unlock(&udc->lock);
1714                         status = udc->driver->setup (&udc->gadget, &u.r);
1715                         spin_lock(&udc->lock);
1716                         udc->ep0_setup = 0;
1717                 }
1718
1719                 if (status < 0) {
1720 do_stall:
1721                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1722                                         u.r.bRequestType, u.r.bRequest, status);
1723                         if (udc->ep0_set_config) {
1724                                 if (udc->ep0_reset_config)
1725                                         WARN("error resetting config?\n");
1726                                 else
1727                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1728                         }
1729                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1730                         udc->ep0_pending = 0;
1731                 }
1732         }
1733 }
1734
1735 /*-------------------------------------------------------------------------*/
1736
1737 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1738
1739 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1740 {
1741         u16     devstat, change;
1742
1743         devstat = UDC_DEVSTAT_REG;
1744         change = devstat ^ udc->devstat;
1745         udc->devstat = devstat;
1746
1747         if (change & (UDC_USB_RESET|UDC_ATT)) {
1748                 udc_quiesce(udc);
1749
1750                 if (change & UDC_ATT) {
1751                         /* driver for any external transceiver will
1752                          * have called omap_vbus_session() already
1753                          */
1754                         if (devstat & UDC_ATT) {
1755                                 udc->gadget.speed = USB_SPEED_FULL;
1756                                 VDBG("connect\n");
1757                                 if (!udc->transceiver)
1758                                         pullup_enable(udc);
1759                                 // if (driver->connect) call it
1760                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1761                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1762                                 if (!udc->transceiver)
1763                                         pullup_disable(udc);
1764                                 DBG("disconnect, gadget %s\n",
1765                                         udc->driver->driver.name);
1766                                 if (udc->driver->disconnect) {
1767                                         spin_unlock(&udc->lock);
1768                                         udc->driver->disconnect(&udc->gadget);
1769                                         spin_lock(&udc->lock);
1770                                 }
1771                         }
1772                         change &= ~UDC_ATT;
1773                 }
1774
1775                 if (change & UDC_USB_RESET) {
1776                         if (devstat & UDC_USB_RESET) {
1777                                 VDBG("RESET=1\n");
1778                         } else {
1779                                 udc->gadget.speed = USB_SPEED_FULL;
1780                                 INFO("USB reset done, gadget %s\n",
1781                                         udc->driver->driver.name);
1782                                 /* ep0 traffic is legal from now on */
1783                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1784                         }
1785                         change &= ~UDC_USB_RESET;
1786                 }
1787         }
1788         if (change & UDC_SUS) {
1789                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1790                         // FIXME tell isp1301 to suspend/resume (?)
1791                         if (devstat & UDC_SUS) {
1792                                 VDBG("suspend\n");
1793                                 update_otg(udc);
1794                                 /* HNP could be under way already */
1795                                 if (udc->gadget.speed == USB_SPEED_FULL
1796                                                 && udc->driver->suspend) {
1797                                         spin_unlock(&udc->lock);
1798                                         udc->driver->suspend(&udc->gadget);
1799                                         spin_lock(&udc->lock);
1800                                 }
1801                                 if (udc->transceiver)
1802                                         otg_set_suspend(udc->transceiver, 1);
1803                         } else {
1804                                 VDBG("resume\n");
1805                                 if (udc->transceiver)
1806                                         otg_set_suspend(udc->transceiver, 0);
1807                                 if (udc->gadget.speed == USB_SPEED_FULL
1808                                                 && udc->driver->resume) {
1809                                         spin_unlock(&udc->lock);
1810                                         udc->driver->resume(&udc->gadget);
1811                                         spin_lock(&udc->lock);
1812                                 }
1813                         }
1814                 }
1815                 change &= ~UDC_SUS;
1816         }
1817         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1818                 update_otg(udc);
1819                 change &= ~OTG_FLAGS;
1820         }
1821
1822         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1823         if (change)
1824                 VDBG("devstat %03x, ignore change %03x\n",
1825                         devstat,  change);
1826
1827         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1828 }
1829
1830 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1831 {
1832         struct omap_udc *udc = _udc;
1833         u16             irq_src;
1834         irqreturn_t     status = IRQ_NONE;
1835         unsigned long   flags;
1836
1837         spin_lock_irqsave(&udc->lock, flags);
1838         irq_src = UDC_IRQ_SRC_REG;
1839
1840         /* Device state change (usb ch9 stuff) */
1841         if (irq_src & UDC_DS_CHG) {
1842                 devstate_irq(_udc, irq_src);
1843                 status = IRQ_HANDLED;
1844                 irq_src &= ~UDC_DS_CHG;
1845         }
1846
1847         /* EP0 control transfers */
1848         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1849                 ep0_irq(_udc, irq_src);
1850                 status = IRQ_HANDLED;
1851                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1852         }
1853
1854         /* DMA transfer completion */
1855         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1856                 dma_irq(_udc, irq_src);
1857                 status = IRQ_HANDLED;
1858                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1859         }
1860
1861         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1862         if (irq_src)
1863                 DBG("udc_irq, unhandled %03x\n", irq_src);
1864         spin_unlock_irqrestore(&udc->lock, flags);
1865
1866         return status;
1867 }
1868
1869 /* workaround for seemingly-lost IRQs for RX ACKs... */
1870 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1871 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1872
1873 static void pio_out_timer(unsigned long _ep)
1874 {
1875         struct omap_ep  *ep = (void *) _ep;
1876         unsigned long   flags;
1877         u16             stat_flg;
1878
1879         spin_lock_irqsave(&ep->udc->lock, flags);
1880         if (!list_empty(&ep->queue) && ep->ackwait) {
1881                 use_ep(ep, UDC_EP_SEL);
1882                 stat_flg = UDC_STAT_FLG_REG;
1883
1884                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1885                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1886                         struct omap_req *req;
1887
1888                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1889                         req = container_of(ep->queue.next,
1890                                         struct omap_req, queue);
1891                         (void) read_fifo(ep, req);
1892                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1893                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1894                         ep->ackwait = 1 + ep->double_buf;
1895                 } else
1896                         deselect_ep();
1897         }
1898         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1899         spin_unlock_irqrestore(&ep->udc->lock, flags);
1900 }
1901
1902 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1903 {
1904         u16             epn_stat, irq_src;
1905         irqreturn_t     status = IRQ_NONE;
1906         struct omap_ep  *ep;
1907         int             epnum;
1908         struct omap_udc *udc = _dev;
1909         struct omap_req *req;
1910         unsigned long   flags;
1911
1912         spin_lock_irqsave(&udc->lock, flags);
1913         epn_stat = UDC_EPN_STAT_REG;
1914         irq_src = UDC_IRQ_SRC_REG;
1915
1916         /* handle OUT first, to avoid some wasteful NAKs */
1917         if (irq_src & UDC_EPN_RX) {
1918                 epnum = (epn_stat >> 8) & 0x0f;
1919                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1920                 status = IRQ_HANDLED;
1921                 ep = &udc->ep[epnum];
1922                 ep->irqs++;
1923
1924                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1925                 ep->fnf = 0;
1926                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1927                         ep->ackwait--;
1928                         if (!list_empty(&ep->queue)) {
1929                                 int stat;
1930                                 req = container_of(ep->queue.next,
1931                                                 struct omap_req, queue);
1932                                 stat = read_fifo(ep, req);
1933                                 if (!ep->double_buf)
1934                                         ep->fnf = 1;
1935                         }
1936                 }
1937                 /* min 6 clock delay before clearing EP_SEL ... */
1938                 epn_stat = UDC_EPN_STAT_REG;
1939                 epn_stat = UDC_EPN_STAT_REG;
1940                 UDC_EP_NUM_REG = epnum;
1941
1942                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1943                  * reduces lossage; timer still needed though (sigh).
1944                  */
1945                 if (ep->fnf) {
1946                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1947                         ep->ackwait = 1 + ep->double_buf;
1948                 }
1949                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1950         }
1951
1952         /* then IN transfers */
1953         else if (irq_src & UDC_EPN_TX) {
1954                 epnum = epn_stat & 0x0f;
1955                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1956                 status = IRQ_HANDLED;
1957                 ep = &udc->ep[16 + epnum];
1958                 ep->irqs++;
1959
1960                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1961                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1962                         ep->ackwait = 0;
1963                         if (!list_empty(&ep->queue)) {
1964                                 req = container_of(ep->queue.next,
1965                                                 struct omap_req, queue);
1966                                 (void) write_fifo(ep, req);
1967                         }
1968                 }
1969                 /* min 6 clock delay before clearing EP_SEL ... */
1970                 epn_stat = UDC_EPN_STAT_REG;
1971                 epn_stat = UDC_EPN_STAT_REG;
1972                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
1973                 /* then 6 clocks before it'd tx */
1974         }
1975
1976         spin_unlock_irqrestore(&udc->lock, flags);
1977         return status;
1978 }
1979
1980 #ifdef  USE_ISO
1981 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1982 {
1983         struct omap_udc *udc = _dev;
1984         struct omap_ep  *ep;
1985         int             pending = 0;
1986         unsigned long   flags;
1987
1988         spin_lock_irqsave(&udc->lock, flags);
1989
1990         /* handle all non-DMA ISO transfers */
1991         list_for_each_entry (ep, &udc->iso, iso) {
1992                 u16             stat;
1993                 struct omap_req *req;
1994
1995                 if (ep->has_dma || list_empty(&ep->queue))
1996                         continue;
1997                 req = list_entry(ep->queue.next, struct omap_req, queue);
1998
1999                 use_ep(ep, UDC_EP_SEL);
2000                 stat = UDC_STAT_FLG_REG;
2001
2002                 /* NOTE: like the other controller drivers, this isn't
2003                  * currently reporting lost or damaged frames.
2004                  */
2005                 if (ep->bEndpointAddress & USB_DIR_IN) {
2006                         if (stat & UDC_MISS_IN)
2007                                 /* done(ep, req, -EPROTO) */;
2008                         else
2009                                 write_fifo(ep, req);
2010                 } else {
2011                         int     status = 0;
2012
2013                         if (stat & UDC_NO_RXPACKET)
2014                                 status = -EREMOTEIO;
2015                         else if (stat & UDC_ISO_ERR)
2016                                 status = -EILSEQ;
2017                         else if (stat & UDC_DATA_FLUSH)
2018                                 status = -ENOSR;
2019
2020                         if (status)
2021                                 /* done(ep, req, status) */;
2022                         else
2023                                 read_fifo(ep, req);
2024                 }
2025                 deselect_ep();
2026                 /* 6 wait states before next EP */
2027
2028                 ep->irqs++;
2029                 if (!list_empty(&ep->queue))
2030                         pending = 1;
2031         }
2032         if (!pending)
2033                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2034         UDC_IRQ_SRC_REG = UDC_SOF;
2035
2036         spin_unlock_irqrestore(&udc->lock, flags);
2037         return IRQ_HANDLED;
2038 }
2039 #endif
2040
2041 /*-------------------------------------------------------------------------*/
2042
2043 static inline int machine_without_vbus_sense(void)
2044 {
2045         return (machine_is_omap_innovator()
2046                 || machine_is_omap_osk()
2047                 || machine_is_omap_apollon()
2048 #ifndef CONFIG_MACH_OMAP_H4_OTG
2049                 || machine_is_omap_h4()
2050 #endif
2051                 || machine_is_sx1()
2052                 );
2053 }
2054
2055 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2056 {
2057         int             status = -ENODEV;
2058         struct omap_ep  *ep;
2059         unsigned long   flags;
2060
2061         /* basic sanity tests */
2062         if (!udc)
2063                 return -ENODEV;
2064         if (!driver
2065                         // FIXME if otg, check:  driver->is_otg
2066                         || driver->speed < USB_SPEED_FULL
2067                         || !driver->bind
2068                         || !driver->setup)
2069                 return -EINVAL;
2070
2071         spin_lock_irqsave(&udc->lock, flags);
2072         if (udc->driver) {
2073                 spin_unlock_irqrestore(&udc->lock, flags);
2074                 return -EBUSY;
2075         }
2076
2077         /* reset state */
2078         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2079                 ep->irqs = 0;
2080                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2081                         continue;
2082                 use_ep(ep, 0);
2083                 UDC_CTRL_REG = UDC_SET_HALT;
2084         }
2085         udc->ep0_pending = 0;
2086         udc->ep[0].irqs = 0;
2087         udc->softconnect = 1;
2088
2089         /* hook up the driver */
2090         driver->driver.bus = NULL;
2091         udc->driver = driver;
2092         udc->gadget.dev.driver = &driver->driver;
2093         spin_unlock_irqrestore(&udc->lock, flags);
2094
2095         if (udc->dc_clk != NULL)
2096                 omap_udc_enable_clock(1);
2097
2098         status = driver->bind (&udc->gadget);
2099         if (status) {
2100                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2101                 udc->gadget.dev.driver = NULL;
2102                 udc->driver = NULL;
2103                 goto done;
2104         }
2105         DBG("bound to driver %s\n", driver->driver.name);
2106
2107         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2108
2109         /* connect to bus through transceiver */
2110         if (udc->transceiver) {
2111                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2112                 if (status < 0) {
2113                         ERR("can't bind to transceiver\n");
2114                         if (driver->unbind) {
2115                                 driver->unbind (&udc->gadget);
2116                                 udc->gadget.dev.driver = NULL;
2117                                 udc->driver = NULL;
2118                         }
2119                         goto done;
2120                 }
2121         } else {
2122                 if (can_pullup(udc))
2123                         pullup_enable (udc);
2124                 else
2125                         pullup_disable (udc);
2126         }
2127
2128         /* boards that don't have VBUS sensing can't autogate 48MHz;
2129          * can't enter deep sleep while a gadget driver is active.
2130          */
2131         if (machine_without_vbus_sense())
2132                 omap_vbus_session(&udc->gadget, 1);
2133
2134 done:
2135         if (udc->dc_clk != NULL)
2136                 omap_udc_enable_clock(0);
2137         return status;
2138 }
2139 EXPORT_SYMBOL(usb_gadget_register_driver);
2140
2141 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2142 {
2143         unsigned long   flags;
2144         int             status = -ENODEV;
2145
2146         if (!udc)
2147                 return -ENODEV;
2148         if (!driver || driver != udc->driver || !driver->unbind)
2149                 return -EINVAL;
2150
2151         if (udc->dc_clk != NULL)
2152                 omap_udc_enable_clock(1);
2153
2154         if (machine_without_vbus_sense())
2155                 omap_vbus_session(&udc->gadget, 0);
2156
2157         if (udc->transceiver)
2158                 (void) otg_set_peripheral(udc->transceiver, NULL);
2159         else
2160                 pullup_disable(udc);
2161
2162         spin_lock_irqsave(&udc->lock, flags);
2163         udc_quiesce(udc);
2164         spin_unlock_irqrestore(&udc->lock, flags);
2165
2166         driver->unbind(&udc->gadget);
2167         udc->gadget.dev.driver = NULL;
2168         udc->driver = NULL;
2169
2170         if (udc->dc_clk != NULL)
2171                 omap_udc_enable_clock(0);
2172         DBG("unregistered driver '%s'\n", driver->driver.name);
2173         return status;
2174 }
2175 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2176
2177
2178 /*-------------------------------------------------------------------------*/
2179
2180 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2181
2182 #include <linux/seq_file.h>
2183
2184 static const char proc_filename[] = "driver/udc";
2185
2186 #define FOURBITS "%s%s%s%s"
2187 #define EIGHTBITS FOURBITS FOURBITS
2188
2189 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2190 {
2191         u16             stat_flg;
2192         struct omap_req *req;
2193         char            buf[20];
2194
2195         use_ep(ep, 0);
2196
2197         if (use_dma && ep->has_dma)
2198                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2199                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2200                         ep->dma_channel - 1, ep->lch);
2201         else
2202                 buf[0] = 0;
2203
2204         stat_flg = UDC_STAT_FLG_REG;
2205         seq_printf(s,
2206                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2207                 ep->name, buf,
2208                 ep->double_buf ? "dbuf " : "",
2209                 ({char *s; switch(ep->ackwait){
2210                 case 0: s = ""; break;
2211                 case 1: s = "(ackw) "; break;
2212                 case 2: s = "(ackw2) "; break;
2213                 default: s = "(?) "; break;
2214                 } s;}),
2215                 ep->irqs, stat_flg,
2216                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2217                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2218                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2219                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2220                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2221                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2222                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2223                 (stat_flg & UDC_STALL) ? "STALL " : "",
2224                 (stat_flg & UDC_NAK) ? "NAK " : "",
2225                 (stat_flg & UDC_ACK) ? "ACK " : "",
2226                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2227                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2228                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2229
2230         if (list_empty (&ep->queue))
2231                 seq_printf(s, "\t(queue empty)\n");
2232         else
2233                 list_for_each_entry (req, &ep->queue, queue) {
2234                         unsigned        length = req->req.actual;
2235
2236                         if (use_dma && buf[0]) {
2237                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2238                                                 ? dma_src_len : dma_dest_len)
2239                                         (ep, req->req.dma + length);
2240                                 buf[0] = 0;
2241                         }
2242                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2243                                         &req->req, length,
2244                                         req->req.length, req->req.buf);
2245                 }
2246 }
2247
2248 static char *trx_mode(unsigned m, int enabled)
2249 {
2250         switch (m) {
2251         case 0:         return enabled ? "*6wire" : "unused";
2252         case 1:         return "4wire";
2253         case 2:         return "3wire";
2254         case 3:         return "6wire";
2255         default:        return "unknown";
2256         }
2257 }
2258
2259 static int proc_otg_show(struct seq_file *s)
2260 {
2261         u32             tmp;
2262         u32             trans;
2263         char            *ctrl_name;
2264
2265         tmp = OTG_REV_REG;
2266         if (cpu_is_omap24xx()) {
2267                 /*
2268                  * REVISIT: Not clear how this works on OMAP2.  trans
2269                  * is ANDed to produce bits 7 and 8, which might make
2270                  * sense for USB_TRANSCEIVER_CTRL_REG on OMAP1,
2271                  * but with CONTROL_DEVCONF, these bits have something to
2272                  * do with the frame adjustment counter and McBSP2.
2273                  */
2274                 ctrl_name = "control_devconf";
2275                 trans = ctrl_read_reg(CONTROL_DEVCONF0);
2276         } else {
2277                 ctrl_name = "tranceiver_ctrl";
2278                 trans = USB_TRANSCEIVER_CTRL_REG;
2279         }
2280         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2281                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2282         tmp = OTG_SYSCON_1_REG;
2283         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2284                         FOURBITS "\n", tmp,
2285                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2286                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2287                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2288                         ? "internal"
2289                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2290                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2291                 (tmp & HST_IDLE_EN) ? " !host" : "",
2292                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2293                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2294         tmp = OTG_SYSCON_2_REG;
2295         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2296                         " b_ase_brst=%d hmc=%d\n", tmp,
2297                 (tmp & OTG_EN) ? " otg_en" : "",
2298                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2299                 // much more SRP stuff
2300                 (tmp & SRP_DATA) ? " srp_data" : "",
2301                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2302                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2303                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2304                 (tmp & UHOST_EN) ? " uhost_en" : "",
2305                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2306                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2307                 B_ASE_BRST(tmp),
2308                 OTG_HMC(tmp));
2309         tmp = OTG_CTRL_REG;
2310         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2311                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2312                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2313                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2314                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2315                 (tmp & OTG_ID) ? " id" : "",
2316                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2317                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2318                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2319                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2320                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2321                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2322                 (tmp & OTG_PULLDOWN) ? " down" : "",
2323                 (tmp & OTG_PULLUP) ? " up" : "",
2324                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2325                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2326                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2327                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2328                 );
2329         tmp = OTG_IRQ_EN_REG;
2330         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2331         tmp = OTG_IRQ_SRC_REG;
2332         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2333         tmp = OTG_OUTCTRL_REG;
2334         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2335         tmp = OTG_TEST_REG;
2336         seq_printf(s, "otg_test    %04x" "\n", tmp);
2337         return 0;
2338 }
2339
2340 static int proc_udc_show(struct seq_file *s, void *_)
2341 {
2342         u32             tmp;
2343         struct omap_ep  *ep;
2344         unsigned long   flags;
2345
2346         spin_lock_irqsave(&udc->lock, flags);
2347
2348         seq_printf(s, "%s, version: " DRIVER_VERSION
2349 #ifdef  USE_ISO
2350                 " (iso)"
2351 #endif
2352                 "%s\n",
2353                 driver_desc,
2354                 use_dma ?  " (dma)" : "");
2355
2356         tmp = UDC_REV_REG & 0xff;
2357         seq_printf(s,
2358                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2359                 "hmc %d, transceiver %s\n",
2360                 tmp >> 4, tmp & 0xf,
2361                 fifo_mode,
2362                 udc->driver ? udc->driver->driver.name : "(none)",
2363                 HMC,
2364                 udc->transceiver
2365                         ? udc->transceiver->label
2366                         : ((cpu_is_omap1710() || cpu_is_omap24xx())
2367                                 ? "external" : "(none)"));
2368         if (cpu_class_is_omap1()) {
2369                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2370                         __REG16(ULPD_CLOCK_CTRL),
2371                         __REG16(ULPD_SOFT_REQ),
2372                         __REG16(ULPD_STATUS_REQ));
2373         }
2374
2375         /* OTG controller registers */
2376         if (!cpu_is_omap15xx())
2377                 proc_otg_show(s);
2378
2379         tmp = UDC_SYSCON1_REG;
2380         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2381                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2382                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2383                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2384                 (tmp & UDC_NAK_EN) ? " nak" : "",
2385                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2386                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2387                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2388                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2389         // syscon2 is write-only
2390
2391         /* UDC controller registers */
2392         if (!(tmp & UDC_PULLUP_EN)) {
2393                 seq_printf(s, "(suspended)\n");
2394                 spin_unlock_irqrestore(&udc->lock, flags);
2395                 return 0;
2396         }
2397
2398         tmp = UDC_DEVSTAT_REG;
2399         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2400                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2401                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2402                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2403                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2404                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2405                 (tmp & UDC_SUS) ? " SUS" : "",
2406                 (tmp & UDC_CFG) ? " CFG" : "",
2407                 (tmp & UDC_ADD) ? " ADD" : "",
2408                 (tmp & UDC_DEF) ? " DEF" : "",
2409                 (tmp & UDC_ATT) ? " ATT" : "");
2410         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2411         tmp = UDC_IRQ_EN_REG;
2412         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2413                 (tmp & UDC_SOF_IE) ? " sof" : "",
2414                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2415                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2416                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2417                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2418         tmp = UDC_IRQ_SRC_REG;
2419         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2420                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2421                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2422                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2423                 (tmp & UDC_SOF) ? " sof" : "",
2424                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2425                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2426                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2427                 (tmp & UDC_SETUP) ? " setup" : "",
2428                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2429                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2430         if (use_dma) {
2431                 unsigned i;
2432
2433                 tmp = UDC_DMA_IRQ_EN_REG;
2434                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2435                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2436                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2437                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2438
2439                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2440                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2441                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2442
2443                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2444                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2445                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2446
2447                 tmp = UDC_RXDMA_CFG_REG;
2448                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2449                 if (tmp) {
2450                         for (i = 0; i < 3; i++) {
2451                                 if ((tmp & (0x0f << (i * 4))) == 0)
2452                                         continue;
2453                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2454                                                 UDC_RXDMA_REG(i + 1));
2455                         }
2456                 }
2457                 tmp = UDC_TXDMA_CFG_REG;
2458                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2459                 if (tmp) {
2460                         for (i = 0; i < 3; i++) {
2461                                 if (!(tmp & (0x0f << (i * 4))))
2462                                         continue;
2463                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2464                                                 UDC_TXDMA_REG(i + 1));
2465                         }
2466                 }
2467         }
2468
2469         tmp = UDC_DEVSTAT_REG;
2470         if (tmp & UDC_ATT) {
2471                 proc_ep_show(s, &udc->ep[0]);
2472                 if (tmp & UDC_ADD) {
2473                         list_for_each_entry (ep, &udc->gadget.ep_list,
2474                                         ep.ep_list) {
2475                                 if (ep->desc)
2476                                         proc_ep_show(s, ep);
2477                         }
2478                 }
2479         }
2480         spin_unlock_irqrestore(&udc->lock, flags);
2481         return 0;
2482 }
2483
2484 static int proc_udc_open(struct inode *inode, struct file *file)
2485 {
2486         return single_open(file, proc_udc_show, NULL);
2487 }
2488
2489 static const struct file_operations proc_ops = {
2490         .open           = proc_udc_open,
2491         .read           = seq_read,
2492         .llseek         = seq_lseek,
2493         .release        = single_release,
2494 };
2495
2496 static void create_proc_file(void)
2497 {
2498         struct proc_dir_entry *pde;
2499
2500         pde = create_proc_entry (proc_filename, 0, NULL);
2501         if (pde)
2502                 pde->proc_fops = &proc_ops;
2503 }
2504
2505 static void remove_proc_file(void)
2506 {
2507         remove_proc_entry(proc_filename, NULL);
2508 }
2509
2510 #else
2511
2512 static inline void create_proc_file(void) {}
2513 static inline void remove_proc_file(void) {}
2514
2515 #endif
2516
2517 /*-------------------------------------------------------------------------*/
2518
2519 /* Before this controller can enumerate, we need to pick an endpoint
2520  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2521  * buffer space among the endpoints we'll be operating.
2522  *
2523  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2524  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2525  * capability yet though.
2526  */
2527 static unsigned __init
2528 omap_ep_setup(char *name, u8 addr, u8 type,
2529                 unsigned buf, unsigned maxp, int dbuf)
2530 {
2531         struct omap_ep  *ep;
2532         u16             epn_rxtx = 0;
2533
2534         /* OUT endpoints first, then IN */
2535         ep = &udc->ep[addr & 0xf];
2536         if (addr & USB_DIR_IN)
2537                 ep += 16;
2538
2539         /* in case of ep init table bugs */
2540         BUG_ON(ep->name[0]);
2541
2542         /* chip setup ... bit values are same for IN, OUT */
2543         if (type == USB_ENDPOINT_XFER_ISOC) {
2544                 switch (maxp) {
2545                 case 8:         epn_rxtx = 0 << 12; break;
2546                 case 16:        epn_rxtx = 1 << 12; break;
2547                 case 32:        epn_rxtx = 2 << 12; break;
2548                 case 64:        epn_rxtx = 3 << 12; break;
2549                 case 128:       epn_rxtx = 4 << 12; break;
2550                 case 256:       epn_rxtx = 5 << 12; break;
2551                 case 512:       epn_rxtx = 6 << 12; break;
2552                 default:        BUG();
2553                 }
2554                 epn_rxtx |= UDC_EPN_RX_ISO;
2555                 dbuf = 1;
2556         } else {
2557                 /* double-buffering "not supported" on 15xx,
2558                  * and ignored for PIO-IN on newer chips
2559                  * (for more reliable behavior)
2560                  */
2561                 if ((!use_dma && (addr & USB_DIR_IN))
2562                                 || machine_is_omap_apollon()
2563                                 || cpu_is_omap15xx())
2564                         dbuf = 0;
2565
2566                 switch (maxp) {
2567                 case 8:         epn_rxtx = 0 << 12; break;
2568                 case 16:        epn_rxtx = 1 << 12; break;
2569                 case 32:        epn_rxtx = 2 << 12; break;
2570                 case 64:        epn_rxtx = 3 << 12; break;
2571                 default:        BUG();
2572                 }
2573                 if (dbuf && addr)
2574                         epn_rxtx |= UDC_EPN_RX_DB;
2575                 init_timer(&ep->timer);
2576                 ep->timer.function = pio_out_timer;
2577                 ep->timer.data = (unsigned long) ep;
2578         }
2579         if (addr)
2580                 epn_rxtx |= UDC_EPN_RX_VALID;
2581         BUG_ON(buf & 0x07);
2582         epn_rxtx |= buf >> 3;
2583
2584         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2585                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2586
2587         if (addr & USB_DIR_IN)
2588                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2589         else
2590                 UDC_EP_RX_REG(addr) = epn_rxtx;
2591
2592         /* next endpoint's buffer starts after this one's */
2593         buf += maxp;
2594         if (dbuf)
2595                 buf += maxp;
2596         BUG_ON(buf > 2048);
2597
2598         /* set up driver data structures */
2599         BUG_ON(strlen(name) >= sizeof ep->name);
2600         strlcpy(ep->name, name, sizeof ep->name);
2601         INIT_LIST_HEAD(&ep->queue);
2602         INIT_LIST_HEAD(&ep->iso);
2603         ep->bEndpointAddress = addr;
2604         ep->bmAttributes = type;
2605         ep->double_buf = dbuf;
2606         ep->udc = udc;
2607
2608         ep->ep.name = ep->name;
2609         ep->ep.ops = &omap_ep_ops;
2610         ep->ep.maxpacket = ep->maxpacket = maxp;
2611         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2612
2613         return buf;
2614 }
2615
2616 static void omap_udc_release(struct device *dev)
2617 {
2618         complete(udc->done);
2619         kfree (udc);
2620         udc = NULL;
2621 }
2622
2623 static int __init
2624 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2625 {
2626         unsigned        tmp, buf;
2627
2628         /* abolish any previous hardware state */
2629         UDC_SYSCON1_REG = 0;
2630         UDC_IRQ_EN_REG = 0;
2631         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2632         UDC_DMA_IRQ_EN_REG = 0;
2633         UDC_RXDMA_CFG_REG = 0;
2634         UDC_TXDMA_CFG_REG = 0;
2635
2636         /* UDC_PULLUP_EN gates the chip clock */
2637         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2638
2639         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2640         if (!udc)
2641                 return -ENOMEM;
2642
2643         spin_lock_init (&udc->lock);
2644
2645         udc->gadget.ops = &omap_gadget_ops;
2646         udc->gadget.ep0 = &udc->ep[0].ep;
2647         INIT_LIST_HEAD(&udc->gadget.ep_list);
2648         INIT_LIST_HEAD(&udc->iso);
2649         udc->gadget.speed = USB_SPEED_UNKNOWN;
2650         udc->gadget.name = driver_name;
2651
2652         device_initialize(&udc->gadget.dev);
2653         strcpy (udc->gadget.dev.bus_id, "gadget");
2654         udc->gadget.dev.release = omap_udc_release;
2655         udc->gadget.dev.parent = &odev->dev;
2656         if (use_dma)
2657                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2658
2659         udc->transceiver = xceiv;
2660
2661         /* ep0 is special; put it right after the SETUP buffer */
2662         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2663                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2664         list_del_init(&udc->ep[0].ep.ep_list);
2665
2666         /* initially disable all non-ep0 endpoints */
2667         for (tmp = 1; tmp < 15; tmp++) {
2668                 UDC_EP_RX_REG(tmp) = 0;
2669                 UDC_EP_TX_REG(tmp) = 0;
2670         }
2671
2672 #define OMAP_BULK_EP(name,addr) \
2673         buf = omap_ep_setup(name "-bulk", addr, \
2674                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2675 #define OMAP_INT_EP(name,addr, maxp) \
2676         buf = omap_ep_setup(name "-int", addr, \
2677                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2678 #define OMAP_ISO_EP(name,addr, maxp) \
2679         buf = omap_ep_setup(name "-iso", addr, \
2680                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2681
2682         switch (fifo_mode) {
2683         case 0:
2684                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2685                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2686                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2687                 break;
2688         case 1:
2689                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2690                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2691                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2692
2693                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2694                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2695                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2696
2697                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2698                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2699                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2700
2701                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2702                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2703                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2704
2705                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2706                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2707                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2708                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2709
2710                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2711                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2712                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2713                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2714
2715                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2716                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2717
2718                 break;
2719
2720 #ifdef  USE_ISO
2721         case 2:                 /* mixed iso/bulk */
2722                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2723                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2724                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2725                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2726
2727                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2728
2729                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2730                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2731                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2732                 break;
2733         case 3:                 /* mixed bulk/iso */
2734                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2735                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2736                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2737
2738                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2739                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2740                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2741
2742                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2743                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2744                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2745                 break;
2746 #endif
2747
2748         /* add more modes as needed */
2749
2750         default:
2751                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2752                 return -ENODEV;
2753         }
2754         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2755         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2756         return 0;
2757 }
2758
2759 static int __init omap_udc_probe(struct platform_device *pdev)
2760 {
2761         int                     status = -ENODEV;
2762         int                     hmc;
2763         struct otg_transceiver  *xceiv = NULL;
2764         const char              *type = NULL;
2765         struct omap_usb_config  *config = pdev->dev.platform_data;
2766         struct clk              *dc_clk;
2767         struct clk              *hhc_clk;
2768
2769         /* NOTE:  "knows" the order of the resources! */
2770         if (!request_mem_region(pdev->resource[0].start,
2771                         pdev->resource[0].end - pdev->resource[0].start + 1,
2772                         driver_name)) {
2773                 DBG("request_mem_region failed\n");
2774                 return -EBUSY;
2775         }
2776
2777         if (cpu_is_omap16xx()) {
2778                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2779                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2780                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2781                 /* can't use omap_udc_enable_clock yet */
2782                 clk_enable(dc_clk);
2783                 clk_enable(hhc_clk);
2784                 udelay(100);
2785         }
2786
2787         if (cpu_is_omap24xx()) {
2788                 dc_clk = clk_get(&pdev->dev, "usb_fck");
2789                 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2790                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2791                 /* can't use omap_udc_enable_clock yet */
2792                 clk_enable(dc_clk);
2793                 clk_enable(hhc_clk);
2794                 udelay(100);
2795         }
2796
2797         INFO("OMAP UDC rev %d.%d%s\n",
2798                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2799                 config->otg ? ", Mini-AB" : "");
2800
2801         /* use the mode given to us by board init code */
2802         if (cpu_is_omap15xx()) {
2803                 hmc = HMC_1510;
2804                 type = "(unknown)";
2805
2806                 if (machine_without_vbus_sense()) {
2807                         /* just set up software VBUS detect, and then
2808                          * later rig it so we always report VBUS.
2809                          * FIXME without really sensing VBUS, we can't
2810                          * know when to turn PULLUP_EN on/off; and that
2811                          * means we always "need" the 48MHz clock.
2812                          */
2813                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2814
2815                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2816                         tmp |= VBUS_MODE_1510;
2817                         tmp &= ~VBUS_CTRL_1510;
2818                         FUNC_MUX_CTRL_0_REG = tmp;
2819                 }
2820         } else {
2821                 /* The transceiver may package some GPIO logic or handle
2822                  * loopback and/or transceiverless setup; if we find one,
2823                  * use it.  Except for OTG, we don't _need_ to talk to one;
2824                  * but not having one probably means no VBUS detection.
2825                  */
2826                 xceiv = otg_get_transceiver();
2827                 if (xceiv)
2828                         type = xceiv->label;
2829                 else if (config->otg) {
2830                         DBG("OTG requires external transceiver!\n");
2831                         goto cleanup0;
2832                 }
2833
2834                 hmc = HMC_1610;
2835
2836                 if (cpu_is_omap24xx()) {
2837                         /* this could be transceiverless in one of the
2838                          * "we don't need to know" modes.
2839                          */
2840                         type = "external";
2841                         goto known;
2842                 }
2843
2844                 switch (hmc) {
2845                 case 0:                 /* POWERUP DEFAULT == 0 */
2846                 case 4:
2847                 case 12:
2848                 case 20:
2849                         if (!cpu_is_omap1710()) {
2850                                 type = "integrated";
2851                                 break;
2852                         }
2853                         /* FALL THROUGH */
2854                 case 3:
2855                 case 11:
2856                 case 16:
2857                 case 19:
2858                 case 25:
2859                         if (!xceiv) {
2860                                 DBG("external transceiver not registered!\n");
2861                                 type = "unknown";
2862                         }
2863                         break;
2864                 case 21:                        /* internal loopback */
2865                         type = "loopback";
2866                         break;
2867                 case 14:                        /* transceiverless */
2868                         if (cpu_is_omap1710())
2869                                 goto bad_on_1710;
2870                         /* FALL THROUGH */
2871                 case 13:
2872                 case 15:
2873                         type = "no";
2874                         break;
2875
2876                 default:
2877 bad_on_1710:
2878                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2879                         goto cleanup0;
2880                 }
2881         }
2882 known:
2883         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2884
2885         /* a "gadget" abstracts/virtualizes the controller */
2886         status = omap_udc_setup(pdev, xceiv);
2887         if (status) {
2888                 goto cleanup0;
2889         }
2890         xceiv = NULL;
2891         // "udc" is now valid
2892         pullup_disable(udc);
2893 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2894         udc->gadget.is_otg = (config->otg != 0);
2895 #endif
2896
2897         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2898         if (UDC_REV_REG >= 0x61)
2899                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2900         else
2901                 udc->clr_halt = UDC_RESET_EP;
2902
2903         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2904         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2905                         IRQF_SAMPLE_RANDOM, driver_name, udc);
2906         if (status != 0) {
2907                 ERR("can't get irq %d, err %d\n",
2908                         (int) pdev->resource[1].start, status);
2909                 goto cleanup1;
2910         }
2911
2912         /* USB "non-iso" IRQ (PIO for all but ep0) */
2913         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2914                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2915         if (status != 0) {
2916                 ERR("can't get irq %d, err %d\n",
2917                         (int) pdev->resource[2].start, status);
2918                 goto cleanup2;
2919         }
2920 #ifdef  USE_ISO
2921         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2922                         IRQF_DISABLED, "omap_udc iso", udc);
2923         if (status != 0) {
2924                 ERR("can't get irq %d, err %d\n",
2925                         (int) pdev->resource[3].start, status);
2926                 goto cleanup3;
2927         }
2928 #endif
2929         if (cpu_is_omap16xx()) {
2930                 udc->dc_clk = dc_clk;
2931                 udc->hhc_clk = hhc_clk;
2932                 clk_disable(hhc_clk);
2933                 clk_disable(dc_clk);
2934         }
2935
2936         if (cpu_is_omap24xx()) {
2937                 udc->dc_clk = dc_clk;
2938                 udc->hhc_clk = hhc_clk;
2939                 /* FIXME OMAP2 don't release hhc & dc clock */
2940 #if 0
2941                 clk_disable(hhc_clk);
2942                 clk_disable(dc_clk);
2943 #endif
2944         }
2945
2946         create_proc_file();
2947         status = device_add(&udc->gadget.dev);
2948         if (!status)
2949                 return status;
2950         /* If fail, fall through */
2951 #ifdef  USE_ISO
2952 cleanup3:
2953         free_irq(pdev->resource[2].start, udc);
2954 #endif
2955
2956 cleanup2:
2957         free_irq(pdev->resource[1].start, udc);
2958
2959 cleanup1:
2960         kfree (udc);
2961         udc = NULL;
2962
2963 cleanup0:
2964         if (xceiv)
2965                 put_device(xceiv->dev);
2966
2967         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
2968                 clk_disable(hhc_clk);
2969                 clk_disable(dc_clk);
2970                 clk_put(hhc_clk);
2971                 clk_put(dc_clk);
2972         }
2973
2974         release_mem_region(pdev->resource[0].start,
2975                         pdev->resource[0].end - pdev->resource[0].start + 1);
2976
2977         return status;
2978 }
2979
2980 static int __exit omap_udc_remove(struct platform_device *pdev)
2981 {
2982         DECLARE_COMPLETION_ONSTACK(done);
2983
2984         if (!udc)
2985                 return -ENODEV;
2986         if (udc->driver)
2987                 return -EBUSY;
2988
2989         udc->done = &done;
2990
2991         pullup_disable(udc);
2992         if (udc->transceiver) {
2993                 put_device(udc->transceiver->dev);
2994                 udc->transceiver = NULL;
2995         }
2996         UDC_SYSCON1_REG = 0;
2997
2998         remove_proc_file();
2999
3000 #ifdef  USE_ISO
3001         free_irq(pdev->resource[3].start, udc);
3002 #endif
3003         free_irq(pdev->resource[2].start, udc);
3004         free_irq(pdev->resource[1].start, udc);
3005
3006         if (udc->dc_clk) {
3007                 if (udc->clk_requested)
3008                         omap_udc_enable_clock(0);
3009                 clk_put(udc->hhc_clk);
3010                 clk_put(udc->dc_clk);
3011         }
3012
3013         release_mem_region(pdev->resource[0].start,
3014                         pdev->resource[0].end - pdev->resource[0].start + 1);
3015
3016         device_unregister(&udc->gadget.dev);
3017         wait_for_completion(&done);
3018
3019         return 0;
3020 }
3021
3022 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3023  * system is forced into deep sleep
3024  *
3025  * REVISIT we should probably reject suspend requests when there's a host
3026  * session active, rather than disconnecting, at least on boards that can
3027  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
3028  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3029  * may involve talking to an external transceiver (e.g. isp1301).
3030  */
3031
3032 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3033 {
3034         u32     devstat;
3035
3036         devstat = UDC_DEVSTAT_REG;
3037
3038         /* we're requesting 48 MHz clock if the pullup is enabled
3039          * (== we're attached to the host) and we're not suspended,
3040          * which would prevent entry to deep sleep...
3041          */
3042         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3043                 WARN("session active; suspend requires disconnect\n");
3044                 omap_pullup(&udc->gadget, 0);
3045         }
3046
3047         udc->gadget.dev.power.power_state = PMSG_SUSPEND;
3048         udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
3049         return 0;
3050 }
3051
3052 static int omap_udc_resume(struct platform_device *dev)
3053 {
3054         DBG("resume + wakeup/SRP\n");
3055         omap_pullup(&udc->gadget, 1);
3056
3057         /* maybe the host would enumerate us if we nudged it */
3058         msleep(100);
3059         return omap_wakeup(&udc->gadget);
3060 }
3061
3062 /*-------------------------------------------------------------------------*/
3063
3064 static struct platform_driver udc_driver = {
3065         .probe          = omap_udc_probe,
3066         .remove         = __exit_p(omap_udc_remove),
3067         .suspend        = omap_udc_suspend,
3068         .resume         = omap_udc_resume,
3069         .driver         = {
3070                 .owner  = THIS_MODULE,
3071                 .name   = (char *) driver_name,
3072         },
3073 };
3074
3075 static int __init udc_init(void)
3076 {
3077         INFO("%s, version: " DRIVER_VERSION
3078 #ifdef  USE_ISO
3079                 " (iso)"
3080 #endif
3081                 "%s\n", driver_desc,
3082                 use_dma ?  " (dma)" : "");
3083         return platform_driver_register(&udc_driver);
3084 }
3085 module_init(udc_init);
3086
3087 static void __exit udc_exit(void)
3088 {
3089         platform_driver_unregister(&udc_driver);
3090 }
3091 module_exit(udc_exit);
3092
3093 MODULE_DESCRIPTION(DRIVER_DESC);
3094 MODULE_LICENSE("GPL");
3095