drivers/staging/winbond/wbhal_s.h

   1 #ifndef __WINBOND_WBHAL_S_H
   2 #define __WINBOND_WBHAL_S_H
   3
   4 #include <linux/types.h>
   5 #include <linux/if_ether.h> /* for ETH_ALEN */
   6
   7 #include "common.h"
   8
   9 //[20040722 WK]
  10 #define HAL_LED_SET_MASK                0x001c  //20060901 Extend
  11 #define HAL_LED_SET_SHIFT               2
  12
  13 //supported RF type
  14 #define RF_MAXIM_2825           0
  15 #define RF_MAXIM_2827           1
  16 #define RF_MAXIM_2828           2
  17 #define RF_MAXIM_2829           3
  18 #define RF_MAXIM_V1                     15
  19 #define RF_AIROHA_2230          16
  20 #define RF_AIROHA_7230          17
  21 #define RF_AIROHA_2230S         18      // 20060420 Add this
  22 // #define RF_RFMD_2959         32      // 20060626 Remove all about RFMD
  23 #define RF_WB_242                       33
  24 #define RF_WB_242_1                     34      // 20060619.5 Add
  25 #define RF_DECIDE_BY_INF        255
  26
  27 //----------------------------------------------------------------
  28 // The follow define connect to upper layer
  29 //      User must modify for connection between HAL and upper layer
  30 //----------------------------------------------------------------
  31
  32
  33
  34
  35 /////////////////////////////////////////////////////////////////////////////////////////////////////
  36 //================================================================================================
  37 // Common define
  38 //================================================================================================
  39 #define HAL_USB_MODE_BURST( _H )        (_H->SoftwareSet & 0x20 ) // Bit 5 20060901 Modify
  40
  41 // Scan interval
  42 #define SCAN_MAX_CHNL_TIME                              (50)
  43
  44 // For TxL2 Frame typr recognise
  45 #define FRAME_TYPE_802_3_DATA                   0
  46 #define FRAME_TYPE_802_11_MANAGEMENT            1
  47 #define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE  2
  48 #define FRAME_TYPE_802_11_CONTROL               3
  49 #define FRAME_TYPE_802_11_DATA                  4
  50 #define FRAME_TYPE_PROMISCUOUS                  5
  51
  52 // The follow definition is used for convert the frame--------------------
  53 #define DOT_11_SEQUENCE_OFFSET          22 //Sequence control offset
  54 #define DOT_3_TYPE_OFFSET                       12
  55 #define DOT_11_MAC_HEADER_SIZE          24
  56 #define DOT_11_SNAP_SIZE                        6
  57 #define DOT_11_TYPE_OFFSET                      30 //The start offset of 802.11 Frame. Type encapsulatuin.
  58 #define DEFAULT_SIFSTIME                        10
  59 #define DEFAULT_FRAGMENT_THRESHOLD              2346 // No fragment
  60 #define DEFAULT_MSDU_LIFE_TIME                  0xffff
  61
  62 #define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME                                              (144+48)
  63 #define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME                                     (72+24)
  64 #define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION                               (16+4+6)
  65 #define Tsym 4
  66
  67 //  Frame Type of Bits (2, 3)---------------------------------------------
  68 #define MAC_TYPE_MANAGEMENT                     0x00
  69 #define MAC_TYPE_CONTROL                        0x04
  70 #define MAC_TYPE_DATA                           0x08
  71 #define MASK_FRAGMENT_NUMBER            0x000F
  72 #define SEQUENCE_NUMBER_SHIFT           4
  73
  74 #define  HAL_WOL_TYPE_WAKEUP_FRAME              0x01
  75 #define  HAL_WOL_TYPE_MAGIC_PACKET              0x02
  76
  77 // 20040106 ADDED
  78 #define HAL_KEYTYPE_WEP40                       0
  79 #define HAL_KEYTYPE_WEP104                      1
  80 #define HAL_KEYTYPE_TKIP                        2 // 128 bit key
  81 #define HAL_KEYTYPE_AES_CCMP                    3 // 128 bit key
  82
  83 // For VM state
  84 enum {
  85         VM_STOP = 0,
  86         VM_RUNNING,
  87         VM_COMPLETED
  88 };
  89
  90 // Be used for 802.11 mac header
  91 typedef struct _MAC_FRAME_CONTROL {
  92         u8      mac_frame_info; // this is a combination of the protovl version, type and subtype
  93         u8      to_ds:1;
  94         u8      from_ds:1;
  95         u8      more_frag:1;
  96         u8      retry:1;
  97         u8      pwr_mgt:1;
  98         u8      more_data:1;
  99         u8      WEP:1;
 100         u8      order:1;
 101 } MAC_FRAME_CONTROL, *PMAC_FRAME_CONTROL;
 102
 103 //-----------------------------------------------------
 104 // Normal Key table format
 105 //-----------------------------------------------------
 106 // The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX
 107 #define MAX_KEY_TABLE                           24      // 24 entry for storing key data
 108 #define GROUP_KEY_START_INDEX           4
 109 #define MAPPING_KEY_START_INDEX         8
 110 typedef struct _KEY_TABLE
 111 {
 112         u32     DW0_Valid:1;
 113         u32     DW0_NullKey:1;
 114         u32     DW0_Security_Mode:2;//0:WEP 40 bit 1:WEP 104 bit 2:TKIP 128 bit 3:CCMP 128 bit
 115         u32     DW0_WEPON:1;
 116         u32     DW0_RESERVED:11;
 117         u32     DW0_Address1:16;
 118
 119         u32     DW1_Address2;
 120
 121         u32     DW2_RxSequenceCount1;
 122
 123         u32     DW3_RxSequenceCount2:16;
 124         u32     DW3_RESERVED:16;
 125
 126         u32     DW4_TxSequenceCount1;
 127
 128         u32     DW5_TxSequenceCount2:16;
 129         u32     DW5_RESERVED:16;
 130
 131 } KEY_TABLE, *PKEY_TABLE;
 132
 133 //--------------------------------------------------------
 134 //                       Descriptor
 135 //--------------------------------------------------------
 136 #define MAX_DESCRIPTOR_BUFFER_INDEX     8       // Have to multiple of 2
 137 //#define FLAG_ERROR_TX_MASK                    cpu_to_le32(0x000000bf) //20061009 marked by anson's endian
 138 #define FLAG_ERROR_TX_MASK                      0x000000bf  //20061009 anson's endian
 139 //#define FLAG_ERROR_RX_MASK                    0x00000c3f
 140 //#define FLAG_ERROR_RX_MASK                    cpu_to_le32(0x0000083f) //20061009 marked by anson's endian
 141                                                                         //Don't care replay error,
 142                                                                                                 //it is handled by S/W
 143 #define FLAG_ERROR_RX_MASK                      0x0000083f      //20060926 anson's endian
 144
 145 #define FLAG_BAND_RX_MASK                       0x10000000      //Bit 28
 146
 147 typedef struct _R00_DESCRIPTOR
 148 {
 149         union
 150         {
 151                 u32     value;
 152                 #ifdef _BIG_ENDIAN_  //20060926 anson's endian
 153                 struct
 154                 {
 155                         u32     R00_packet_or_buffer_status:1;
 156                         u32     R00_packet_in_fifo:1;
 157                         u32     R00_RESERVED:2;
 158                         u32     R00_receive_byte_count:12;
 159                         u32     R00_receive_time_index:16;
 160                 };
 161                 #else
 162                 struct
 163                 {
 164                         u32     R00_receive_time_index:16;
 165                         u32     R00_receive_byte_count:12;
 166                         u32     R00_RESERVED:2;
 167                         u32     R00_packet_in_fifo:1;
 168                         u32     R00_packet_or_buffer_status:1;
 169                 };
 170                 #endif
 171         };
 172 } R00_DESCRIPTOR, *PR00_DESCRIPTOR;
 173
 174 typedef struct _T00_DESCRIPTOR
 175 {
 176         union
 177         {
 178                 u32     value;
 179                 #ifdef _BIG_ENDIAN_  //20061009 anson's endian
 180                 struct
 181                 {
 182                         u32     T00_first_mpdu:1; // for hardware use
 183                         u32     T00_last_mpdu:1; // for hardware use
 184                         u32     T00_IsLastMpdu:1;// 0: not   1:Yes for software used
 185                         u32     T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
 186                         u32     T00_RESERVED_ID:2;//3 bit ID reserved
 187                         u32     T00_tx_packet_id:4;//930519.4.e 930810.3.c
 188                         u32     T00_RESERVED:4;
 189                         u32     T00_header_length:6;
 190                         u32     T00_frame_length:12;
 191                 };
 192                 #else
 193                 struct
 194                 {
 195                         u32     T00_frame_length:12;
 196                         u32     T00_header_length:6;
 197                         u32     T00_RESERVED:4;
 198                         u32     T00_tx_packet_id:4;//930519.4.e 930810.3.c
 199                         u32     T00_RESERVED_ID:2;//3 bit ID reserved
 200                         u32     T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
 201                         u32     T00_IsLastMpdu:1;// 0: not   1:Yes for software used
 202                         u32     T00_last_mpdu:1; // for hardware use
 203                         u32     T00_first_mpdu:1; // for hardware use
 204                 };
 205                 #endif
 206         };
 207 } T00_DESCRIPTOR, *PT00_DESCRIPTOR;
 208
 209 typedef struct _R01_DESCRIPTOR
 210 {
 211         union
 212         {
 213                 u32     value;
 214                 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
 215                 struct
 216                 {
 217                         u32     R01_RESERVED:3;
 218                         u32     R01_mod_type:1;
 219                         u32     R01_pre_type:1;
 220                         u32     R01_data_rate:3;
 221                         u32     R01_AGC_state:8;
 222                         u32     R01_LNA_state:2;
 223                         u32     R01_decryption_method:2;
 224                         u32     R01_mic_error:1;
 225                         u32     R01_replay:1;
 226                         u32     R01_broadcast_frame:1;
 227                         u32     R01_multicast_frame:1;
 228                         u32     R01_directed_frame:1;
 229                         u32     R01_receive_frame_antenna_selection:1;
 230                         u32     R01_frame_receive_during_atim_window:1;
 231                         u32     R01_protocol_version_error:1;
 232                         u32     R01_authentication_frame_icv_error:1;
 233                         u32     R01_null_key_to_authentication_frame:1;
 234                         u32     R01_icv_error:1;
 235                         u32     R01_crc_error:1;
 236                 };
 237                 #else
 238                 struct
 239                 {
 240                         u32     R01_crc_error:1;
 241                         u32     R01_icv_error:1;
 242                         u32     R01_null_key_to_authentication_frame:1;
 243                         u32     R01_authentication_frame_icv_error:1;
 244                         u32     R01_protocol_version_error:1;
 245                         u32     R01_frame_receive_during_atim_window:1;
 246                         u32     R01_receive_frame_antenna_selection:1;
 247                         u32     R01_directed_frame:1;
 248                         u32     R01_multicast_frame:1;
 249                         u32     R01_broadcast_frame:1;
 250                         u32     R01_replay:1;
 251                         u32     R01_mic_error:1;
 252                         u32     R01_decryption_method:2;
 253                         u32     R01_LNA_state:2;
 254                         u32     R01_AGC_state:8;
 255                         u32     R01_data_rate:3;
 256                         u32     R01_pre_type:1;
 257                         u32     R01_mod_type:1;
 258                         u32     R01_RESERVED:3;
 259                 };
 260                 #endif
 261         };
 262 } R01_DESCRIPTOR, *PR01_DESCRIPTOR;
 263
 264 typedef struct _T01_DESCRIPTOR
 265 {
 266         union
 267         {
 268                 u32     value;
 269                 #ifdef _BIG_ENDIAN_ //20061009 anson's endian
 270                 struct
 271                 {
 272                         u32     T01_rts_cts_duration:16;
 273                         u32     T01_fall_back_rate:3;
 274                         u32     T01_add_rts:1;
 275                         u32     T01_add_cts:1;
 276                         u32     T01_modulation_type:1;
 277                         u32     T01_plcp_header_length:1;
 278                         u32     T01_transmit_rate:3;
 279                         u32     T01_wep_id:2;
 280                         u32     T01_add_challenge_text:1;
 281                         u32     T01_inhibit_crc:1;
 282                         u32     T01_loop_back_wep_mode:1;
 283                         u32     T01_retry_abort_ebable:1;
 284                 };
 285                 #else
 286                 struct
 287                 {
 288                         u32     T01_retry_abort_ebable:1;
 289                         u32     T01_loop_back_wep_mode:1;
 290                         u32     T01_inhibit_crc:1;
 291                         u32     T01_add_challenge_text:1;
 292                         u32     T01_wep_id:2;
 293                         u32     T01_transmit_rate:3;
 294                         u32     T01_plcp_header_length:1;
 295                         u32     T01_modulation_type:1;
 296                         u32     T01_add_cts:1;
 297                         u32     T01_add_rts:1;
 298                         u32     T01_fall_back_rate:3;
 299                         u32     T01_rts_cts_duration:16;
 300                 };
 301                 #endif
 302         };
 303 } T01_DESCRIPTOR, *PT01_DESCRIPTOR;
 304
 305 typedef struct _T02_DESCRIPTOR
 306 {
 307         union
 308         {
 309                 u32     value;
 310                 #ifdef _BIG_ENDIAN_  //20061009 add by anson's endian
 311                 struct
 312                 {
 313                         u32     T02_IsLastMpdu:1;// The same mechanism with T00 setting
 314                         u32     T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
 315                         u32     T02_RESERVED_ID:2;// The same mechanism with T00 setting
 316                         u32     T02_Tx_PktID:4;
 317                         u32     T02_MPDU_Cnt:4;
 318                         u32     T02_RTS_Cnt:4;
 319                         u32     T02_RESERVED:7;
 320                         u32     T02_transmit_complete:1;
 321                         u32     T02_transmit_abort_due_to_TBTT:1;
 322                         u32     T02_effective_transmission_rate:1;
 323                         u32     T02_transmit_without_encryption_due_to_wep_on_false:1;
 324                         u32     T02_discard_due_to_null_wep_key:1;
 325                         u32     T02_RESERVED_1:1;
 326                         u32     T02_out_of_MaxTxMSDULiftTime:1;
 327                         u32     T02_transmit_abort:1;
 328                         u32     T02_transmit_fail:1;
 329                 };
 330                 #else
 331                 struct
 332                 {
 333                         u32     T02_transmit_fail:1;
 334                         u32     T02_transmit_abort:1;
 335                         u32     T02_out_of_MaxTxMSDULiftTime:1;
 336                         u32     T02_RESERVED_1:1;
 337                         u32     T02_discard_due_to_null_wep_key:1;
 338                         u32     T02_transmit_without_encryption_due_to_wep_on_false:1;
 339                         u32     T02_effective_transmission_rate:1;
 340                         u32     T02_transmit_abort_due_to_TBTT:1;
 341                         u32     T02_transmit_complete:1;
 342                         u32     T02_RESERVED:7;
 343                         u32     T02_RTS_Cnt:4;
 344                         u32     T02_MPDU_Cnt:4;
 345                         u32     T02_Tx_PktID:4;
 346                         u32     T02_RESERVED_ID:2;// The same mechanism with T00 setting
 347                         u32     T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
 348                         u32     T02_IsLastMpdu:1;// The same mechanism with T00 setting
 349                 };
 350                 #endif
 351         };
 352 } T02_DESCRIPTOR, *PT02_DESCRIPTOR;
 353
 354 typedef struct _DESCRIPTOR {            // Skip length = 8 DWORD
 355         // ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition
 356         u8      Descriptor_ID;
 357         //----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------
 358         u8      RESERVED[3];
 359
 360         u16     FragmentThreshold;
 361         u8      InternalUsed;//Only can be used by operation of descriptor definition
 362         u8      Type;// 0: 802.3        1:802.11 data frame     2:802.11 management frame
 363
 364         u8      PreambleMode;// 0: short 1:long
 365         u8      TxRate;
 366         u8      FragmentCount;
 367         u8      EapFix; // For speed up key install
 368
 369         // For R00 and T00 ----------------------------------------------
 370         union
 371         {
 372                 R00_DESCRIPTOR  R00;
 373                 T00_DESCRIPTOR  T00;
 374         };
 375
 376         // For R01 and T01 ----------------------------------------------
 377         union
 378         {
 379                 R01_DESCRIPTOR  R01;
 380                 T01_DESCRIPTOR  T01;
 381         };
 382
 383         // For R02 and T02 ----------------------------------------------
 384         union
 385         {
 386                 u32                     R02;
 387                 T02_DESCRIPTOR  T02;
 388         };
 389
 390         // For R03 and T03 ----------------------------------------------
 391         // For software used
 392         union
 393         {
 394                 u32     R03;
 395                 u32     T03;
 396                 struct
 397                 {
 398                         u8      buffer_number;
 399                         u8      buffer_start_index;
 400                         u16     buffer_total_size;
 401                 };
 402         };
 403
 404         // For storing the buffer
 405         u16     buffer_size[ MAX_DESCRIPTOR_BUFFER_INDEX ];
 406         void*   buffer_address[ MAX_DESCRIPTOR_BUFFER_INDEX ];//931130.4.q
 407
 408 } DESCRIPTOR, *PDESCRIPTOR;
 409
 410
 411 #define DEFAULT_NULL_PACKET_COUNT               180000  //20060828.1 Add. 180 seconds
 412
 413 #define MAX_TXVGA_EEPROM        9       //How many word(u16) of EEPROM will be used for TxVGA
 414 #define MAX_RF_PARAMETER        32
 415
 416 typedef struct _TXVGA_FOR_50 {
 417         u8      ChanNo;
 418         u8      TxVgaValue;
 419 } TXVGA_FOR_50;
 420
 421
 422 //=====================================================================
 423 // Device related include
 424 //=====================================================================
 425
 426 #include "wbusb_s.h"
 427 #include "wb35reg_s.h"
 428 #include "wb35tx_s.h"
 429 #include "wb35rx_s.h"
 430
 431 // For Hal using ==================================================================
 432 typedef struct _HW_DATA_T
 433 {
 434         // For compatible with 33
 435         u32     revision;
 436         u32     BB3c_cal; // The value for Tx calibration comes from EEPROM
 437         u32     BB54_cal; // The value for Rx calibration comes from EEPROM
 438
 439
 440         // For surprise remove
 441         u32     SurpriseRemove; // 0: Normal 1: Surprise remove
 442         u8      InitialResource;
 443         u8      IsKeyPreSet;
 444         u8      CalOneTime; // 20060630.1
 445
 446         u8      VCO_trim;
 447
 448         // For Fix 1'st DMA bug
 449         u32     FragCount;
 450         u32     DMAFix; //V1_DMA_FIX The variable can be removed if driver want to save mem space for V2.
 451
 452         //===============================================
 453         // Definition for MAC address
 454         //===============================================
 455         u8              PermanentMacAddress[ETH_ALEN + 2]; // The Enthernet addr that are stored in EEPROM.  + 2 to 8-byte alignment
 456         u8              CurrentMacAddress[ETH_ALEN + 2]; // The Enthernet addr that are in used.  + 2 to 8-byte alignment
 457
 458         //=====================================================================
 459         // Definition for 802.11
 460         //=====================================================================
 461         u8      *bssid_pointer; // Used by hal_get_bssid for return value
 462         u8      bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer
 463         u8      ssid[32];// maximum ssid length is 32 byte
 464
 465         u16     AID;
 466         u8      ssid_length;
 467         u8      Channel;
 468
 469         u16     ListenInterval;
 470         u16     CapabilityInformation;
 471
 472         u16     BeaconPeriod;
 473         u16     ProbeDelay;
 474
 475         u8      bss_type;// 0: IBSS_NET or 1:ESS_NET
 476         u8      preamble;// 0: short preamble, 1: long preamble
 477         u8      slot_time_select;// 9 or 20 value
 478         u8      phy_type;// Phy select
 479
 480         u32     phy_para[MAX_RF_PARAMETER];
 481         u32     phy_number;
 482
 483         u32     CurrentRadioSw; // 20060320.2 0:On 1:Off
 484         u32     CurrentRadioHw; // 20060825 0:On 1:Off
 485
 486         u8      *power_save_point;  // Used by hal_get_power_save_mode for return value
 487         u8      cwmin;
 488         u8      desired_power_save;
 489         u8      dtim;// Is running dtim
 490         u8      mapping_key_replace_index;//In Key table, the next index be replaced 931130.4.r
 491
 492         u16     MaxReceiveLifeTime;
 493         u16     FragmentThreshold;
 494         u16     FragmentThreshold_tmp;
 495         u16     cwmax;
 496
 497         u8      Key_slot[MAX_KEY_TABLE][8]; //Ownership record for key slot. For Alignment
 498         u32     Key_content[MAX_KEY_TABLE][12]; // 10DW for each entry + 2 for burst command( Off and On valid bit)
 499         u8      CurrentDefaultKeyIndex;
 500         u32     CurrentDefaultKeyLength;
 501
 502         //========================================================================
 503         // Variable for each module
 504         //========================================================================
 505         WBUSB           WbUsb; // Need WbUsb.h
 506         struct wb35_reg reg; // Need Wb35Reg.h
 507         WB35TX          Wb35Tx; // Need Wb35Tx.h
 508         WB35RX          Wb35Rx; // Need Wb35Rx.h
 509
 510         struct timer_list       LEDTimer;// For LED
 511
 512         u32             LEDpoint;// For LED
 513
 514     u32         dto_tx_retry_count;         // LA20040210_DTO kevin
 515     u32         dto_tx_frag_count;          // LA20040210_DTO kevin
 516     u32         rx_ok_count[13];    // index=0: total rx ok
 517     //u32         rx_ok_bytes[13];    // index=0, total rx ok bytes
 518     u32         rx_err_count[13];   // index=0: total rx err
 519
 520         //for Tx debug
 521         u32                     tx_TBTT_start_count;
 522         u32                     tx_ETR_count;
 523         u32                     tx_WepOn_false_count;
 524         u32                     tx_Null_key_count;
 525         u32                     tx_retry_count[8];
 526
 527         u8              PowerIndexFromEEPROM; // For 2412MHz
 528         u8              power_index;
 529         u8              IsWaitJoinComplete;     // TRUE: set join request
 530         u8              band;
 531
 532         u16             SoftwareSet;
 533         u16             Reserved_s;
 534
 535         u32             IsInitOK; // 0: Driver starting   1: Driver init OK
 536
 537         // For Phy calibration
 538     s32         iq_rsdl_gain_tx_d2;
 539     s32         iq_rsdl_phase_tx_d2;
 540         u32             txvga_setting_for_cal; // 20060703.1 Add
 541
 542         u8              TxVgaSettingInEEPROM[ (((MAX_TXVGA_EEPROM*2)+3) & ~0x03) ]; // 20060621 For backup EEPROM value
 543         u8              TxVgaFor24[16]; // Max is 14, 2 for alignment
 544         TXVGA_FOR_50    TxVgaFor50[36]; // 35 channels in 5G. 35x2 = 70 byte. 2 for alignments
 545
 546         u16             Scan_Interval;
 547         u16             RESERVED6;
 548
 549         // LED control
 550         u32             LED_control;
 551                 // LED_control 4 byte: Gray_Led_1[3]            Gray_Led_0[2]           Led[1]                  Led[0]
 552                 // Gray_Led
 553                 //              For Led gray setting
 554                 // Led
 555                 //              0: normal control, LED behavior will decide by EEPROM setting
 556                 //              1: Turn off specific LED
 557                 //              2: Always on specific LED
 558                 //              3: slow blinking specific LED
 559                 //              4: fast blinking specific LED
 560                 //              5: WPS led control is set. Led0 is Red, Led1 id Green
 561                 //                      Led[1] is parameter for WPS LED mode
 562                 //                               // 1:InProgress  2: Error 3: Session overlap 4: Success 20061108 control
 563
 564         u32             LED_LinkOn;             //Turn LED on control
 565         u32             LED_Scanning;   // Let LED in scan process control
 566         u32             LED_Blinking; // Temp variable for shining
 567         u32             RxByteCountLast;
 568         u32             TxByteCountLast;
 569
 570         atomic_t        SurpriseRemoveCount;
 571
 572         // For global timer
 573         u32             time_count;//TICK_TIME_100ms 1 = 100ms
 574
 575         // For error recover
 576         u32             HwStop;
 577
 578         // 20060828.1 for avoid AP disconnect
 579         u32             NullPacketCount;
 580
 581 } hw_data_t, *phw_data_t;
 582
 583 // The mapping of Rx and Tx descriptor field
 584 typedef struct _HAL_RATE
 585 {
 586         // DSSS
 587         u32     RESERVED_0;
 588         u32   NumRate2MS;
 589         u32   NumRate55MS;
 590         u32   NumRate11MS;
 591
 592         u32     RESERVED_1[4];
 593
 594         u32   NumRate1M;
 595         u32   NumRate2ML;
 596         u32   NumRate55ML;
 597         u32   NumRate11ML;
 598
 599         u32     RESERVED_2[4];
 600
 601         // OFDM
 602         u32   NumRate6M;
 603         u32   NumRate9M;
 604         u32   NumRate12M;
 605         u32   NumRate18M;
 606         u32   NumRate24M;
 607         u32   NumRate36M;
 608         u32   NumRate48M;
 609         u32   NumRate54M;
 610 } HAL_RATE, *PHAL_RATE;
 611
 612 #endif