1 //=======================================================================================
5 ========================================
6 |Uxx| |Dxx| |Mxx| |BB| |RF|
7 ========================================
9 Wb35Reg_Read Wb35Reg_Write
11 ----------------------------------------
12 WbUsb_CallUSBDASync supplied By WbUsb module
14 //=======================================================================================
16 #define GetBit( dwData, i) ( dwData & (0x00000001 << i))
17 #define SetBit( dwData, i) ( dwData | (0x00000001 << i))
18 #define ClearBit( dwData, i) ( dwData & ~(0x00000001 << i))
20 #define IGNORE_INCREMENT 0
21 #define AUTO_INCREMENT 0
22 #define NO_INCREMENT 1
23 #define REG_DIRECTION(_x,_y) ((_y)->DIRECT ==0 ? usb_rcvctrlpipe(_x,0) : usb_sndctrlpipe(_x,0))
24 #define REG_BUF_SIZE(_x) ((_x)->bRequest== 0x04 ? cpu_to_le16((_x)->wLength) : 4)
26 // 20060613.2 Add the follow definition
27 #define BB48_DEFAULT_AL2230_11B 0x0033447c
28 #define BB4C_DEFAULT_AL2230_11B 0x0A00FEFF
29 #define BB48_DEFAULT_AL2230_11G 0x00332C1B
30 #define BB4C_DEFAULT_AL2230_11G 0x0A00FEFF
33 #define BB48_DEFAULT_WB242_11B 0x00292315 //backoff 2dB
34 #define BB4C_DEFAULT_WB242_11B 0x0800FEFF //backoff 2dB
35 //#define BB48_DEFAULT_WB242_11B 0x00201B11 //backoff 4dB
36 //#define BB4C_DEFAULT_WB242_11B 0x0600FF00 //backoff 4dB
37 #define BB48_DEFAULT_WB242_11G 0x00453B24
38 #define BB4C_DEFAULT_WB242_11G 0x0E00FEFF
40 //====================================
41 // Default setting for Mxx
42 //====================================
43 #define DEFAULT_CWMIN 31 //(M2C) CWmin. Its value is in the range 0-31.
44 #define DEFAULT_CWMAX 1023 //(M2C) CWmax. Its value is in the range 0-1023.
45 #define DEFAULT_AID 1 //(M34) AID. Its value is in the range 1-2007.
47 #ifdef _USE_FALLBACK_RATE_
48 #define DEFAULT_RATE_RETRY_LIMIT 2 //(M38) as named
50 #define DEFAULT_RATE_RETRY_LIMIT 7 //(M38) as named
53 #define DEFAULT_LONG_RETRY_LIMIT 7 //(M38) LongRetryLimit. Its value is in the range 0-15.
54 #define DEFAULT_SHORT_RETRY_LIMIT 7 //(M38) ShortRetryLimit. Its value is in the range 0-15.
55 #define DEFAULT_PIFST 25 //(M3C) PIFS Time. Its value is in the range 0-65535.
56 #define DEFAULT_EIFST 354 //(M3C) EIFS Time. Its value is in the range 0-1048575.
57 #define DEFAULT_DIFST 45 //(M3C) DIFS Time. Its value is in the range 0-65535.
58 #define DEFAULT_SIFST 5 //(M3C) SIFS Time. Its value is in the range 0-65535.
59 #define DEFAULT_OSIFST 10 //(M3C) Original SIFS Time. Its value is in the range 0-15.
60 #define DEFAULT_ATIMWD 0 //(M40) ATIM Window. Its value is in the range 0-65535.
61 #define DEFAULT_SLOT_TIME 20 //(M40) ($) SlotTime. Its value is in the range 0-255.
62 #define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 //(M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295.
63 #define DEFAULT_BEACON_INTERVAL 500 //(M48) Beacon Interval. Its value is in the range 0-65535.
64 #define DEFAULT_PROBE_DELAY_TIME 200 //(M48) Probe Delay Time. Its value is in the range 0-65535.
65 #define DEFAULT_PROTOCOL_VERSION 0 //(M4C)
66 #define DEFAULT_MAC_POWER_STATE 2 //(M4C) 2: MAC at power active
67 #define DEFAULT_DTIM_ALERT_TIME 0
70 typedef struct _REG_QUEUE
80 u8 RESERVED[4];// space reserved for communication
82 u16 INDEX; // For storing the register index
83 u8 RESERVED_VALID; //Indicate whether the RESERVED space is valid at this command.
84 u8 DIRECT; // 0:In 1:Out
86 } REG_QUEUE, *PREG_QUEUE;
88 //====================================
89 // Internal variable for module
90 //====================================
91 #define MAX_SQ3_FILTER_SIZE 5
92 typedef struct _WB35REG
94 //============================
95 // Register Bank backup
96 //============================
97 u32 U1B0; //bit16 record the h/w radio on/off status
98 u32 U1BC_LEDConfigure;
103 u32 M04_MulticastAddress1;
104 u32 M08_MulticastAddress2;
106 u8 Multicast[8]; // contents of card multicast registers
113 u32 M3C_MacControl; // 20060214 backup only
115 u32 M44_MacControl; // 20060214 backup only
116 u32 M48_MacControl; // 20060214 backup only
118 u32 M60_MacControl; // 20060214 backup only
119 u32 M68_MacControl; // 20060214 backup only
120 u32 M70_MacControl; // 20060214 backup only
121 u32 M74_MacControl; // 20060214 backup only
122 u32 M78_ERPInformation;//930206.2.b
123 u32 M7C_MacControl; // 20060214 backup only
124 u32 M80_MacControl; // 20060214 backup only
125 u32 M84_MacControl; // 20060214 backup only
126 u32 M88_MacControl; // 20060214 backup only
127 u32 M98_MacControl; // 20060214 backup only
131 u32 BB0C; // Used for LNA calculation
133 u32 BB30; //11b acquisition control register
135 u32 BB48; // 20051221.1.a 20060613.1 Fix OBW issue of 11b/11g rate
136 u32 BB4C; // 20060613.1 Fix OBW issue of 11b/11g rate
137 u32 BB50; //mode control register
140 u32 BB5C; // For test
141 u32 BB60; // for WTO read value
143 //-------------------
145 //-------------------
146 OS_SPIN_LOCK EP0VM_spin_lock; // 4B
147 u32 EP0VM_status;//$$
148 PREG_QUEUE pRegFirst;
150 OS_ATOMIC RegFireCount;
155 u8 EEPROMPhyType; // 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829),
156 // 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230)
158 // 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step)
159 // 48 ~ 255 ARE RESERVED.
160 u8 EEPROMRegion; //Region setting in EEPROM
162 u32 SyncIoPause; // If user use the Sync Io to access Hw, then pause the async access
164 u8 LNAValue[4]; //Table for speed up running
165 u32 SQ3_filter[MAX_SQ3_FILTER_SIZE];
168 } WB35REG, *PWB35REG;