drivers/staging/sxg/sxghif.h

   1 /*
   2  * Copyright © 1997-2007 Alacritech, Inc. All rights reserved
   3  *
   4  * $Id: sxghif.h,v 1.5 2008/07/24 19:18:22 chris Exp $
   5  *
   6  * sxghif.h:
   7  *
   8  * This file contains structures and definitions for the
   9  * Alacritech Sahara host interface
  10  */
  11
  12 /*******************************************************************************
  13  * UCODE Registers
  14  *******************************************************************************/
  15 typedef struct _SXG_UCODE_REGS {
  16         // Address 0 - 0x3F = Command codes 0-15 for TCB 0.  Excode 0
  17         u32 Icr;                // Code = 0 (extended), ExCode = 0 - Int control
  18         u32 RsvdReg1;           // Code = 1 - TOE -NA
  19         u32 RsvdReg2;           // Code = 2 - TOE -NA
  20         u32 RsvdReg3;           // Code = 3 - TOE -NA
  21         u32 RsvdReg4;           // Code = 4 - TOE -NA
  22         u32 RsvdReg5;           // Code = 5 - TOE -NA
  23         u32 CardUp;             // Code = 6 - Microcode initialized when 1
  24         u32 RsvdReg7;           // Code = 7 - TOE -NA
  25         u32 CodeNotUsed[8];     // Codes 8-15 not used.  ExCode = 0
  26         // This brings us to ExCode 1 at address 0x40 = Interrupt status pointer
  27         u32 Isp;                // Code = 0 (extended), ExCode = 1
  28         u32 PadEx1[15];         // Codes 1-15 not used with extended codes
  29         // ExCode 2 = Interrupt Status Register
  30         u32 Isr;                // Code = 0 (extended), ExCode = 2
  31         u32 PadEx2[15];
  32         // ExCode 3 = Event base register.  Location of event rings
  33         u32 EventBase;          // Code = 0 (extended), ExCode = 3
  34         u32 PadEx3[15];
  35         // ExCode 4 = Event ring size
  36         u32 EventSize;          // Code = 0 (extended), ExCode = 4
  37         u32 PadEx4[15];
  38         // ExCode 5 = TCB Buffers base address
  39         u32 TcbBase;            // Code = 0 (extended), ExCode = 5
  40         u32 PadEx5[15];
  41         // ExCode 6 = TCB Composite Buffers base address
  42         u32 TcbCompBase;        // Code = 0 (extended), ExCode = 6
  43         u32 PadEx6[15];
  44         // ExCode 7 = Transmit ring base address
  45         u32 XmtBase;            // Code = 0 (extended), ExCode = 7
  46         u32 PadEx7[15];
  47         // ExCode 8 = Transmit ring size
  48         u32 XmtSize;            // Code = 0 (extended), ExCode = 8
  49         u32 PadEx8[15];
  50         // ExCode 9 = Receive ring base address
  51         u32 RcvBase;            // Code = 0 (extended), ExCode = 9
  52         u32 PadEx9[15];
  53         // ExCode 10 = Receive ring size
  54         u32 RcvSize;            // Code = 0 (extended), ExCode = 10
  55         u32 PadEx10[15];
  56         // ExCode 11 = Read EEPROM Config
  57         u32 Config;             // Code = 0 (extended), ExCode = 11
  58         u32 PadEx11[15];
  59         // ExCode 12 = Multicast bits 31:0
  60         u32 McastLow;           // Code = 0 (extended), ExCode = 12
  61         u32 PadEx12[15];
  62         // ExCode 13 = Multicast bits 63:32
  63         u32 McastHigh;          // Code = 0 (extended), ExCode = 13
  64         u32 PadEx13[15];
  65         // ExCode 14 = Ping
  66         u32 Ping;               // Code = 0 (extended), ExCode = 14
  67         u32 PadEx14[15];
  68         // ExCode 15 = Link MTU
  69         u32 LinkMtu;            // Code = 0 (extended), ExCode = 15
  70         u32 PadEx15[15];
  71         // ExCode 16 = Download synchronization
  72         u32 LoadSync;           // Code = 0 (extended), ExCode = 16
  73         u32 PadEx16[15];
  74         // ExCode 17 = Upper DRAM address bits on 32-bit systems
  75         u32 Upper;              // Code = 0 (extended), ExCode = 17
  76         u32 PadEx17[15];
  77         // ExCode 18 = Slowpath Send Index Address
  78         u32 SPSendIndex;        // Code = 0 (extended), ExCode = 18
  79         u32 PadEx18[15];
  80         u32 RsvdXF;             // Code = 0 (extended), ExCode = 19
  81         u32 PadEx19[15];
  82         // ExCode 20 = Aggregation
  83         u32 Aggregation;        // Code = 0 (extended), ExCode = 20
  84         u32 PadEx20[15];
  85         // ExCode 21 = Receive MDL push timer
  86         u32 PushTicks;          // Code = 0 (extended), ExCode = 21
  87         u32 PadEx21[15];
  88         // ExCode 22 = TOE NA
  89         u32 AckFrequency;       // Code = 0 (extended), ExCode = 22
  90         u32 PadEx22[15];
  91         // ExCode 23 = TOE NA
  92         u32 RsvdReg23;
  93         u32 PadEx23[15];
  94         // ExCode 24 = TOE NA
  95         u32 RsvdReg24;
  96         u32 PadEx24[15];
  97         // ExCode 25 = TOE NA
  98         u32 RsvdReg25;          // Code = 0 (extended), ExCode = 25
  99         u32 PadEx25[15];
 100         // ExCode 26 = Receive checksum requirements
 101         u32 ReceiveChecksum;    // Code = 0 (extended), ExCode = 26
 102         u32 PadEx26[15];
 103         // ExCode 27 = RSS Requirements
 104         u32 Rss;                // Code = 0 (extended), ExCode = 27
 105         u32 PadEx27[15];
 106         // ExCode 28 = RSS Table
 107         u32 RssTable;           // Code = 0 (extended), ExCode = 28
 108         u32 PadEx28[15];
 109         // ExCode 29 = Event ring release entries
 110         u32 EventRelease;       // Code = 0 (extended), ExCode = 29
 111         u32 PadEx29[15];
 112         // ExCode 30 = Number of receive bufferlist commands on ring 0
 113         u32 RcvCmd;             // Code = 0 (extended), ExCode = 30
 114         u32 PadEx30[15];
 115         // ExCode 31 = slowpath transmit command - Data[31:0] = 1
 116         u32 XmtCmd;             // Code = 0 (extended), ExCode = 31
 117         u32 PadEx31[15];
 118         // ExCode 32 = Dump command
 119         u32 DumpCmd;            // Code = 0 (extended), ExCode = 32
 120         u32 PadEx32[15];
 121         // ExCode 33 = Debug command
 122         u32 DebugCmd;           // Code = 0 (extended), ExCode = 33
 123         u32 PadEx33[15];
 124         // There are 128 possible extended commands - each of account for 16
 125         // words (including the non-relevent base command codes 1-15).
 126         // Pad for the remainder of these here to bring us to the next CPU
 127         // base.  As extended codes are added, reduce the first array value in
 128         // the following field
 129         u32 PadToNextCpu[94][16];       // 94 = 128 - 34 (34 = Excodes 0 - 33)
 130 } SXG_UCODE_REGS, *PSXG_UCODE_REGS;
 131
 132 // Interrupt control register (0) values
 133 #define SXG_ICR_DISABLE                                 0x00000000
 134 #define SXG_ICR_ENABLE                                  0x00000001
 135 #define SXG_ICR_MASK                                    0x00000002
 136 #define SXG_ICR_MSGID_MASK                              0xFFFF0000
 137 #define SXG_ICR_MSGID_SHIFT                     16
 138 #define SXG_ICR(_MessageId, _Data)      \
 139         ((((_MessageId) << SXG_ICR_MSGID_SHIFT) &       \
 140           SXG_ICR_MSGID_MASK) | (_Data))
 141
 142 // The Microcode supports up to 16 RSS queues
 143 #define SXG_MAX_RSS                             16
 144 #define SXG_MAX_RSS_TABLE_SIZE  256     // 256-byte max
 145
 146 #define SXG_RSS_TCP6                            0x00000001      // RSS TCP over IPv6
 147 #define SXG_RSS_TCP4                            0x00000002      // RSS TCP over IPv4
 148 #define SXG_RSS_LEGACY                          0x00000004      // Line-base interrupts
 149 #define SXG_RSS_TABLE_SIZE                      0x0000FF00      // Table size mask
 150 #define SXG_RSS_TABLE_SHIFT                     8
 151 #define SXG_RSS_BASE_CPU                        0x00FF0000      // Base CPU (not used)
 152 #define SXG_RSS_BASE_SHIFT                      16
 153
 154 #define SXG_RCV_IP_CSUM_ENABLED         0x00000001      // ExCode 26 (ReceiveChecksum)
 155 #define SXG_RCV_TCP_CSUM_ENABLED        0x00000002      // ExCode 26 (ReceiveChecksum)
 156
 157 #define SXG_XMT_CPUID_SHIFT                     16
 158
 159 #if VPCI
 160 #define SXG_CHECK_FOR_HANG_TIME         3000
 161 #else
 162 #define SXG_CHECK_FOR_HANG_TIME         5
 163 #endif
 164
 165 /*
 166  * TCB registers - This is really the same register memory area as UCODE_REGS
 167  * above, but defined differently.  Bits 17:06 of the address define the TCB,
 168  * which means each TCB area occupies 0x40 (64) bytes, or 16 u32S.  What really
 169  * is happening is that these registers occupy the "PadEx[15]" areas in the
 170  * SXG_UCODE_REGS definition above
 171  */
 172 typedef struct _SXG_TCB_REGS {
 173         u32 ExCode;             /* Extended codes - see SXG_UCODE_REGS */
 174         u32 Xmt;                /* Code = 1 - # of Xmt descriptors added to ring */
 175         u32 Rcv;                /* Code = 2 - # of Rcv descriptors added to ring */
 176         u32 Rsvd1;              /* Code = 3 - TOE NA */
 177         u32 Rsvd2;              /* Code = 4 - TOE NA */
 178         u32 Rsvd3;              /* Code = 5 - TOE NA */
 179         u32 Invalid;            /* Code = 6 - Reserved for "CardUp" see above */
 180         u32 Rsvd4;              /* Code = 7 - TOE NA */
 181         u32 Rsvd5;              /* Code = 8 - TOE NA */
 182         u32 Pad[7];             /* Codes 8-15 - Not used. */
 183 } SXG_TCB_REGS, *PSXG_TCB_REGS;
 184
 185 /***************************************************************************
 186  * ISR Format
 187  *                31                                      0
 188  *                 _______________________________________
 189  *                |    |    |    |    |    |    |    |    |
 190  *                |____|____|____|____|____|____|____|____|
 191  *                 ^^^^ ^^^^ ^^^^ ^^^^ \                 /
 192  *           ERR --|||| |||| |||| ||||  -----------------
 193  *         EVENT ---||| |||| |||| ||||          |
 194  *               ----|| |||| |||| ||||          |-- Crash Address
 195  *           UPC -----| |||| |||| ||||
 196  *        LEVENT -------|||| |||| ||||
 197  *          PDQF --------||| |||| ||||
 198  *         RMISS ---------|| |||| ||||
 199  *         BREAK ----------| |||| ||||
 200  *       HBEATOK ------------|||| ||||
 201  *       NOHBEAT -------------||| ||||
 202  *        ERFULL --------------|| ||||
 203  *         XDROP ---------------| ||||
 204  *               -----------------||||
 205  *               -----------------||||--\
 206  *                                 ||---|-CpuId of crash
 207  *                                 |----/
 208  ***************************************************************************/
 209 #define SXG_ISR_ERR             0x80000000      // Error
 210 #define SXG_ISR_EVENT           0x40000000      // Event ring event
 211 #define SXG_ISR_NONE1           0x20000000      // Not used
 212 #define SXG_ISR_UPC             0x10000000      // Dump/debug command complete
 213 #define SXG_ISR_LINK            0x08000000      // Link event
 214 #define SXG_ISR_PDQF            0x04000000      // Processed data queue full
 215 #define SXG_ISR_RMISS           0x02000000      // Drop - no host buf
 216 #define SXG_ISR_BREAK           0x01000000      // Breakpoint hit
 217 #define SXG_ISR_PING            0x00800000      // Heartbeat response
 218 #define SXG_ISR_DEAD            0x00400000      // Card crash
 219 #define SXG_ISR_ERFULL          0x00200000      // Event ring full
 220 #define SXG_ISR_XDROP           0x00100000      // XMT Drop - no DRAM bufs or XMT err
 221 #define SXG_ISR_SPSEND          0x00080000      // Slow send complete
 222 #define SXG_ISR_CPU             0x00070000      // Dead CPU mask
 223 #define SXG_ISR_CPU_SHIFT               16      // Dead CPU shift
 224 #define SXG_ISR_CRASH           0x0000FFFF      // Crash address mask
 225
 226 /***************************************************************************
 227  *
 228  * Event Ring entry
 229  *
 230  ***************************************************************************/
 231 /*
 232  *  31                  15                 0
 233  *  .___________________.___________________.
 234  *  |<------------    Pad 0    ------------>|
 235  *  |_________|_________|_________|_________|0          0x00
 236  *  |<------------    Pad 1    ------------>|
 237  *  |_________|_________|_________|_________|4          0x04
 238  *  |<------------    Pad 2    ------------>|
 239  *  |_________|_________|_________|_________|8          0x08
 240  *  |<----------- Event Word 0 ------------>|
 241  *  |_________|_________|_________|_________|12         0x0c
 242  *  |<----------- Event Word 1 ------------>|
 243  *  |_________|_________|_________|_________|16         0x10
 244  *  |<------------- Toeplitz   ------------>|
 245  *  |_________|_________|_________|_________|20         0x14
 246  *  |<----- Length ---->|<------ TCB Id --->|
 247  *  |_________|_________|_________|_________|24         0x18
 248  *  |<----- Status ---->|Evnt Code|Flsh Code|
 249  *  |_________|_________|_________|_________|28         0x1c
 250  *   ^                   ^^^^ ^^^^
 251  *   |- VALID            |||| ||||- RBUFC
 252  *                       |||| |||-- SLOWR
 253  *                       |||| ||--- UNUSED
 254  *                       |||| |---- FASTC
 255  *                       ||||------ FASTR
 256  *                       |||-------
 257  *                       ||--------
 258  *                       |---------
 259  *
 260  * Slowpath status:
 261  *   _______________________________________
 262  *  |<----- Status ---->|Evnt Code|Flsh Code|
 263  *  |_________|Cmd Index|_________|_________|28         0x1c
 264  *    ^^^ ^^^^
 265  *    ||| ||||- ISTCPIP6
 266  *    ||| |||-- IPONLY
 267  *    ||| ||--- RCVERR
 268  *    ||| |---- IPCBAD
 269  *    |||------ TCPCBAD
 270  *    ||------- ISTCPIP
 271  *    |-------- SCERR
 272  *
 273  */
 274 #pragma pack(push, 1)
 275 typedef struct _SXG_EVENT {
 276         u32 Pad[1];             // not used
 277         u32 SndUna;             // SndUna value
 278         u32 Resid;              // receive MDL resid
 279         union {
 280                 void *HostHandle;       // Receive host handle
 281                 u32 Rsvd1;      // TOE NA
 282                 struct {
 283                         u32 NotUsed;
 284                         u32 Rsvd2;      // TOE NA
 285                 } Flush;
 286         };
 287         u32 Toeplitz;           // RSS Toeplitz hash
 288         union {
 289                 ushort Rsvd3;   // TOE NA
 290                 ushort HdrOffset;       // Slowpath
 291         };
 292         ushort Length;          //
 293         unsigned char Rsvd4;    // TOE NA
 294         unsigned char Code;     // Event code
 295         unsigned char CommandIndex;     // New ring index
 296         unsigned char Status;   // Event status
 297 } SXG_EVENT, *PSXG_EVENT;
 298 #pragma pack(pop)
 299
 300 // Event code definitions
 301 #define EVENT_CODE_BUFFERS      0x01    // Receive buffer list command (ring 0)
 302 #define EVENT_CODE_SLOWRCV      0x02    // Slowpath receive
 303 #define EVENT_CODE_UNUSED       0x04    // Was slowpath commands complete
 304
 305 // Status values
 306 #define EVENT_STATUS_VALID      0x80    // Entry valid
 307
 308 // Slowpath status
 309 #define EVENT_STATUS_ERROR      0x40    // Completed with error. Index in next byte
 310 #define EVENT_STATUS_TCPIP4     0x20    // TCPIPv4 frame
 311 #define EVENT_STATUS_TCPBAD     0x10    // Bad TCP checksum
 312 #define EVENT_STATUS_IPBAD      0x08    // Bad IP checksum
 313 #define EVENT_STATUS_RCVERR     0x04    // Slowpath receive error
 314 #define EVENT_STATUS_IPONLY     0x02    // IP frame
 315 #define EVENT_STATUS_TCPIP6     0x01    // TCPIPv6 frame
 316 #define EVENT_STATUS_TCPIP      0x21    // Combination of v4 and v6
 317
 318 // Event ring
 319 // Size must be power of 2, between 128 and 16k
 320 #define EVENT_RING_SIZE         4096    // ??
 321 #define EVENT_RING_BATCH        16      // Hand entries back 16 at a time.
 322 #define EVENT_BATCH_LIMIT       256     // Stop processing events after 256 (16 * 16)
 323
 324 typedef struct _SXG_EVENT_RING {
 325         SXG_EVENT Ring[EVENT_RING_SIZE];
 326 } SXG_EVENT_RING, *PSXG_EVENT_RING;
 327
 328 /***************************************************************************
 329  *
 330  * TCB Buffers
 331  *
 332  ***************************************************************************/
 333 // Maximum number of TCBS supported by hardware/microcode
 334 #define SXG_MAX_TCB             4096
 335 // Minimum TCBs before we fail initialization
 336 #define SXG_MIN_TCB             512
 337 // TCB Hash
 338 // The bucket is determined by bits 11:4 of the toeplitz if we support 4k
 339 // offloaded connections, 10:4 if we support 2k and so on.
 340 #define SXG_TCB_BUCKET_SHIFT    4
 341 #define SXG_TCB_PER_BUCKET              16
 342 #define SXG_TCB_BUCKET_MASK             0xFF0   // Bucket portion of TCB ID
 343 #define SXG_TCB_ELEMENT_MASK    0x00F   // Element within bucket
 344 #define SXG_TCB_BUCKETS                 256     // 256 * 16 = 4k
 345
 346 #define SXG_TCB_BUFFER_SIZE     512     // ASSERT format is correct
 347
 348 #define SXG_TCB_RCVQ_SIZE               736
 349
 350 #define SXG_TCB_COMPOSITE_BUFFER_SIZE   1024
 351
 352 #define SXG_LOCATE_TCP_FRAME_HDR(_TcpObject, _IPv6)                                                     \
 353         (((_TcpObject)->VlanId) ?                                                                                               \
 354          ((_IPv6) ?             /* Vlan frame header = yes */                                                   \
 355           &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.SxgTcp                        :       \
 356           &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.SxgTcp)                        :       \
 357          ((_IPv6) ?             /* Vlan frame header = No */                                                    \
 358           &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.SxgTcp                         :       \
 359           &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp.SxgTcp))
 360
 361 #define SXG_LOCATE_IP_FRAME_HDR(_TcpObject)                                                                     \
 362         (_TcpObject)->VlanId ?                                                                                                  \
 363         &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.Ip                               :               \
 364         &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp.Ip
 365
 366 #define SXG_LOCATE_IP6_FRAME_HDR(_TcpObject)                                                            \
 367         (_TcpObject)->VlanId ?                                                                                                  \
 368         &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip                              :               \
 369         &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.Ip
 370
 371 #if DBG
 372 // Horrible kludge to distinguish dumb-nic, slowpath, and
 373 // fastpath traffic.  Decrement the HopLimit by one
 374 // for slowpath, two for fastpath.  This assumes the limit is measurably
 375 // greater than two, which I think is reasonable.
 376 // Obviously this is DBG only.  Maybe remove later, or #if 0 so we
 377 // can set it when needed
 378 #define SXG_DBG_HOP_LIMIT(_TcpObject, _FastPath) {                                                              \
 379         PIPV6_HDR               _Ip6FrameHdr;                                                                                           \
 380         if((_TcpObject)->IPv6) {                                                                                                        \
 381                 _Ip6FrameHdr = SXG_LOCATE_IP6_FRAME_HDR((_TcpObject));                                  \
 382                 if(_FastPath) {                                                                                                                 \
 383                         _Ip6FrameHdr->HopLimit = (_TcpObject)->Cached.TtlOrHopLimit - 2;        \
 384                 } else {                                                                                                                                \
 385                         _Ip6FrameHdr->HopLimit = (_TcpObject)->Cached.TtlOrHopLimit - 1;        \
 386                 }                                                                                                                                               \
 387         }                                                                                                                                                       \
 388 }
 389 #else
 390 // Do nothing with free build
 391 #define SXG_DBG_HOP_LIMIT(_TcpObject, _FastPath)
 392 #endif
 393
 394 /***************************************************************************
 395  * Receive and transmit rings
 396  ***************************************************************************/
 397 #define SXG_MAX_RING_SIZE       256
 398 #define SXG_XMT_RING_SIZE       128     // Start with 128
 399 #define SXG_RCV_RING_SIZE       128     // Start with 128
 400 #define SXG_MAX_ENTRIES     4096
 401
 402 // Structure and macros to manage a ring
 403 typedef struct _SXG_RING_INFO {
 404         unsigned char Head;     // Where we add entries - Note unsigned char:RING_SIZE
 405         unsigned char Tail;     // Where we pull off completed entries
 406         ushort Size;            // Ring size - Must be multiple of 2
 407         void *Context[SXG_MAX_RING_SIZE];       // Shadow ring
 408 } SXG_RING_INFO, *PSXG_RING_INFO;
 409
 410 #define SXG_INITIALIZE_RING(_ring, _size) {                                                     \
 411         (_ring).Head = 0;                                                                                               \
 412         (_ring).Tail = 0;                                                                                               \
 413         (_ring).Size = (_size);                                                                                 \
 414 }
 415 #define SXG_ADVANCE_INDEX(_index, _size) ((_index) = ((_index) + 1) & ((_size) - 1))
 416 #define SXG_PREVIOUS_INDEX(_index, _size) (((_index) - 1) &((_size) - 1))
 417 #define SXG_RING_EMPTY(_ring) ((_ring)->Head == (_ring)->Tail)
 418 #define SXG_RING_FULL(_ring) ((((_ring)->Head + 1) & ((_ring)->Size - 1)) == (_ring)->Tail)
 419 #define SXG_RING_ADVANCE_HEAD(_ring) SXG_ADVANCE_INDEX((_ring)->Head, ((_ring)->Size))
 420 #define SXG_RING_RETREAT_HEAD(_ring) ((_ring)->Head =                           \
 421                                                                           SXG_PREVIOUS_INDEX((_ring)->Head, (_ring)->Size))
 422 #define SXG_RING_ADVANCE_TAIL(_ring) {                                                          \
 423         ASSERT((_ring)->Tail != (_ring)->Head);                                                 \
 424         SXG_ADVANCE_INDEX((_ring)->Tail, ((_ring)->Size));                              \
 425 }
 426 // Set cmd to the next available ring entry, set the shadow context
 427 // entry and advance the ring.
 428 // The appropriate lock must be held when calling this macro
 429 #define SXG_GET_CMD(_ring, _ringinfo, _cmd, _context) {                         \
 430         if(SXG_RING_FULL(_ringinfo)) {                                                                  \
 431                 (_cmd) = NULL;                                                                                          \
 432         } else {                                                                                                                \
 433                 (_cmd) = &(_ring)->Descriptors[(_ringinfo)->Head];                      \
 434                 (_ringinfo)->Context[(_ringinfo)->Head] = (void *)(_context);\
 435                 SXG_RING_ADVANCE_HEAD(_ringinfo);                                                       \
 436         }                                                                                                                               \
 437 }
 438
 439 // Abort the previously allocated command by retreating the head.
 440 // NOTE - The appopriate lock MUST NOT BE DROPPED between the SXG_GET_CMD
 441 // and SXG_ABORT_CMD calls.
 442 #define SXG_ABORT_CMD(_ringinfo) {                                                                      \
 443         ASSERT(!(SXG_RING_EMPTY(_ringinfo)));                                                   \
 444         SXG_RING_RETREAT_HEAD(_ringinfo);                                                               \
 445         (_ringinfo)->Context[(_ringinfo)->Head] = NULL;                                 \
 446 }
 447
 448 // For the given ring, return a pointer to the tail cmd and context,
 449 // clear the context and advance the tail
 450 #define SXG_RETURN_CMD(_ring, _ringinfo, _cmd, _context) {                      \
 451         (_cmd) = &(_ring)->Descriptors[(_ringinfo)->Tail];                              \
 452         (_context) = (_ringinfo)->Context[(_ringinfo)->Tail];           \
 453         (_ringinfo)->Context[(_ringinfo)->Tail] = NULL;                                 \
 454         SXG_RING_ADVANCE_TAIL(_ringinfo);                                                               \
 455 }
 456
 457 /***************************************************************************
 458  *
 459  * Host Command Buffer - commands to INIC via the Cmd Rings
 460  *
 461  ***************************************************************************/
 462 /*
 463  *  31                  15                 0
 464  *  .___________________.___________________.
 465  *  |<-------------- Sgl Low -------------->|
 466  *  |_________|_________|_________|_________|0          0x00
 467  *  |<-------------- Sgl High ------------->|
 468  *  |_________|_________|_________|_________|4          0x04
 469  *  |<-------------  Sge 0 Low  ----------->|
 470  *  |_________|_________|_________|_________|8          0x08
 471  *  |<-------------  Sge 0 High ----------->|
 472  *  |_________|_________|_________|_________|12         0x0c
 473  *  |<------------  Sge 0 Length ---------->|
 474  *  |_________|_________|_________|_________|16         0x10
 475  *  |<----------- Window Update ----------->|
 476  *  |<-------- SP 1st SGE offset ---------->|
 477  *  |_________|_________|_________|_________|20         0x14
 478  *  |<----------- Total Length ------------>|
 479  *  |_________|_________|_________|_________|24         0x18
 480  *  |<----- LCnt ------>|<----- Flags ----->|
 481  *  |_________|_________|_________|_________|28         0x1c
 482  */
 483 #pragma pack(push, 1)
 484 typedef struct _SXG_CMD {
 485         dma_addr_t Sgl;         // Physical address of SGL
 486         union {
 487                 struct {
 488                         dma64_addr_t FirstSgeAddress;   // Address of first SGE
 489                         u32 FirstSgeLength;     // Length of first SGE
 490                         union {
 491                                 u32 Rsvd1;      // TOE NA
 492                                 u32 SgeOffset;  // Slowpath - 2nd SGE offset
 493                                 u32 Resid;      // MDL completion - clobbers update
 494                         };
 495                         union {
 496                                 u32 TotalLength;        // Total transfer length
 497                                 u32 Mss;        // LSO MSS
 498                         };
 499                 } Buffer;
 500         };
 501         union {
 502                 struct {
 503                         unsigned char Flags:4;  // slowpath flags
 504                         unsigned char IpHl:4;   // Ip header length (>>2)
 505                         unsigned char MacLen;   // Mac header len
 506                 } CsumFlags;
 507                 struct {
 508                         ushort Flags:4; // slowpath flags
 509                         ushort TcpHdrOff:7;     // TCP
 510                         ushort MacLen:5;        // Mac header len
 511                 } LsoFlags;
 512                 ushort Flags;   // flags
 513         };
 514         union {
 515                 ushort SgEntries;       // SG entry count including first sge
 516                 struct {
 517                         unsigned char Status;   // Copied from event status
 518                         unsigned char NotUsed;
 519                 } Status;
 520         };
 521 } SXG_CMD, *PSXG_CMD;
 522 #pragma pack(pop)
 523
 524 #pragma pack(push, 1)
 525 typedef struct _VLAN_HDR {
 526         ushort VlanTci;
 527         ushort VlanTpid;
 528 } VLAN_HDR, *PVLAN_HDR;
 529 #pragma pack(pop)
 530
 531 /*
 532  * Slowpath Flags:
 533  *
 534  *
 535  * LSS Flags:
 536  *                                        .---
 537  *                                       /.--- TCP Large segment send
 538  *                                      //.---
 539  *                                     ///.---
 540  *  3                   1     1       ////
 541  *  1                   5     0      ||||
 542  *  .___________________.____________vvvv.
 543  *  |                   |MAC |  TCP |    |
 544  *  |      LCnt         |hlen|hdroff|Flgs|
 545  *  |___________________|||||||||||||____|
 546  *
 547  *
 548  * Checksum Flags
 549  *
 550  *                                           .---
 551  *                                          /.---
 552  *                                         //.--- Checksum TCP
 553  *                                        ///.--- Checksum IP
 554  *  3                   1                //// No bits - normal send
 555  *  1                   5          7    ||||
 556  *  .___________________._______________vvvv.
 557  *  |                   | Offload | IP |    |
 558  *  |      LCnt         |MAC hlen |Hlen|Flgs|
 559  *  |___________________|____|____|____|____|
 560  *
 561  */
 562 // Slowpath CMD flags
 563 #define SXG_SLOWCMD_CSUM_IP                     0x01    // Checksum IP
 564 #define SXG_SLOWCMD_CSUM_TCP            0x02    // Checksum TCP
 565 #define SXG_SLOWCMD_LSO                         0x04    // Large segment send
 566
 567 typedef struct _SXG_XMT_RING {
 568         SXG_CMD Descriptors[SXG_XMT_RING_SIZE];
 569 } SXG_XMT_RING, *PSXG_XMT_RING;
 570
 571 typedef struct _SXG_RCV_RING {
 572         SXG_CMD Descriptors[SXG_RCV_RING_SIZE];
 573 } SXG_RCV_RING, *PSXG_RCV_RING;
 574
 575 /***************************************************************************
 576  * Share memory buffer types - Used to identify asynchronous
 577  * shared memory allocation
 578  ***************************************************************************/
 579 typedef enum {
 580         SXG_BUFFER_TYPE_RCV,    // Receive buffer
 581         SXG_BUFFER_TYPE_SGL     // SGL buffer
 582 } SXG_BUFFER_TYPE;
 583
 584 // State for SXG buffers
 585 #define SXG_BUFFER_FREE         0x01
 586 #define SXG_BUFFER_BUSY         0x02
 587 #define SXG_BUFFER_ONCARD       0x04
 588 #define SXG_BUFFER_UPSTREAM     0x08
 589
 590 /***************************************************************************
 591  * Receive data buffers
 592  *
 593  * Receive data buffers are given to the Sahara card 128 at a time.
 594  * This is accomplished by filling in a "receive descriptor block"
 595  * with 128 "receive descriptors".  Each descriptor consists of
 596  * a physical address, which the card uses as the address to
 597  * DMA data into, and a virtual address, which is given back
 598  * to the host in the "HostHandle" portion of an event.
 599  * The receive descriptor data structure is defined below
 600  * as SXG_RCV_DATA_DESCRIPTOR, and the corresponding block
 601  * is defined as SXG_RCV_DESCRIPTOR_BLOCK.
 602  *
 603  * This receive descriptor block is given to the card by filling
 604  * in the Sgl field of a SXG_CMD entry from pAdapt->RcvRings[0]
 605  * with the physical address of the receive descriptor block.
 606  *
 607  * Both the receive buffers and the receive descriptor blocks
 608  * require additional data structures to maintain them
 609  * on a free queue and contain other information associated with them.
 610  * Those data structures are defined as the SXG_RCV_DATA_BUFFER_HDR
 611  * and SXG_RCV_DESCRIPTOR_BLOCK_HDR respectively.
 612  *
 613  * Since both the receive buffers and the receive descriptor block
 614  * must be accessible by the card, both must be allocated out of
 615  * shared memory.  To ensure that we always have a descriptor
 616  * block available for every 128 buffers, we allocate all of
 617  * these resources together in a single block.  This entire
 618  * block is managed by a SXG_RCV_BLOCK_HDR, who's sole purpose
 619  * is to maintain address information so that the entire block
 620  * can be free later.
 621  *
 622  * Further complicating matters is the fact that the receive
 623  * buffers must be variable in length in order to accomodate
 624  * jumbo frame configurations.  We configure the buffer
 625  * length so that the buffer and it's corresponding SXG_RCV_DATA_BUFFER_HDR
 626  * structure add up to an even boundary.  Then we place the
 627  * remaining data structures after 128 of them as shown in
 628  * the following diagram:
 629  *
 630  *  _________________________________________
 631  * |                                         |
 632  * |    Variable length receive buffer #1    |
 633  * |_________________________________________|
 634  * |                                         |
 635  * |       SXG_RCV_DATA_BUFFER_HDR #1        |
 636  * |_________________________________________| <== Even 2k or 10k boundary
 637  * |                                         |
 638  * |         ... repeat 2-128 ..             |
 639  * |_________________________________________|
 640  * |                                         |
 641  * |      SXG_RCV_DESCRIPTOR_BLOCK           |
 642  * |  Contains SXG_RCV_DATA_DESCRIPTOR * 128 |
 643  * |_________________________________________|
 644  * |                                         |
 645  * |      SXG_RCV_DESCRIPTOR_BLOCK_HDR       |
 646  * |_________________________________________|
 647  * |                                         |
 648  * |          SXG_RCV_BLOCK_HDR              |
 649  * |_________________________________________|
 650  *
 651  * Memory consumption:
 652  *        Non-jumbo:
 653  *      Buffers and SXG_RCV_DATA_BUFFER_HDR = 2k * 128 = 256k
 654  *    + SXG_RCV_DESCRIPTOR_BLOCK = 2k
 655  *    + SXG_RCV_DESCRIPTOR_BLOCK_HDR = ~32
 656  *    + SXG_RCV_BLOCK_HDR = ~32
 657  *    => Total = ~258k/block
 658  *
 659  *        Jumbo:
 660  *      Buffers and SXG_RCV_DATA_BUFFER_HDR = 10k * 128 = 1280k
 661  *    + SXG_RCV_DESCRIPTOR_BLOCK = 2k
 662  *    + SXG_RCV_DESCRIPTOR_BLOCK_HDR = ~32
 663  *    + SXG_RCV_BLOCK_HDR = ~32
 664  *    => Total = ~1282k/block
 665  *
 666  ***************************************************************************/
 667 #define SXG_RCV_DATA_BUFFERS                    4096    // Amount to give to the card
 668 #define SXG_INITIAL_RCV_DATA_BUFFERS    8192    // Initial pool of buffers
 669 #define SXG_MIN_RCV_DATA_BUFFERS                2048    // Minimum amount and when to get more
 670 #define SXG_MAX_RCV_BLOCKS                              128     // = 16384 receive buffers
 671
 672 // Receive buffer header
 673 typedef struct _SXG_RCV_DATA_BUFFER_HDR {
 674         dma_addr_t PhysicalAddress;     // Buffer physical address
 675         // Note - DO NOT USE the VirtualAddress field to locate data.
 676         // Use the sxg.h:SXG_RECEIVE_DATA_LOCATION macro instead.
 677         void *VirtualAddress;   // Start of buffer
 678         LIST_ENTRY FreeList;    // Free queue of buffers
 679         struct _SXG_RCV_DATA_BUFFER_HDR *Next;  // Fastpath data buffer queue
 680         u32 Size;               // Buffer size
 681         u32 ByteOffset;         // See SXG_RESTORE_MDL_OFFSET
 682         unsigned char State;    // See SXG_BUFFER state above
 683         unsigned char Status;   // Event status (to log PUSH)
 684         struct sk_buff *skb;    // Double mapped (nbl and pkt)
 685 } SXG_RCV_DATA_BUFFER_HDR, *PSXG_RCV_DATA_BUFFER_HDR;
 686
 687 // SxgSlowReceive uses the PACKET (skb) contained
 688 // in the SXG_RCV_DATA_BUFFER_HDR when indicating dumb-nic data
 689 #define SxgDumbRcvPacket                skb
 690
 691 #define SXG_RCV_DATA_HDR_SIZE                   256     // Space for SXG_RCV_DATA_BUFFER_HDR
 692 #define SXG_RCV_DATA_BUFFER_SIZE                2048    // Non jumbo = 2k including HDR
 693 #define SXG_RCV_JUMBO_BUFFER_SIZE               10240   // jumbo = 10k including HDR
 694
 695 // Receive data descriptor
 696 typedef struct _SXG_RCV_DATA_DESCRIPTOR {
 697         union {
 698                 struct sk_buff *VirtualAddress; // Host handle
 699                 u64 ForceTo8Bytes;      // Force x86 to 8-byte boundary
 700         };
 701         dma_addr_t PhysicalAddress;
 702 } SXG_RCV_DATA_DESCRIPTOR, *PSXG_RCV_DATA_DESCRIPTOR;
 703
 704 // Receive descriptor block
 705 #define SXG_RCV_DESCRIPTORS_PER_BLOCK           128
 706 #define SXG_RCV_DESCRIPTOR_BLOCK_SIZE           2048    // For sanity check
 707 typedef struct _SXG_RCV_DESCRIPTOR_BLOCK {
 708         SXG_RCV_DATA_DESCRIPTOR Descriptors[SXG_RCV_DESCRIPTORS_PER_BLOCK];
 709 } SXG_RCV_DESCRIPTOR_BLOCK, *PSXG_RCV_DESCRIPTOR_BLOCK;
 710
 711 // Receive descriptor block header
 712 typedef struct _SXG_RCV_DESCRIPTOR_BLOCK_HDR {
 713         void *VirtualAddress;   // Start of 2k buffer
 714         dma_addr_t PhysicalAddress;     // ..and it's physical address
 715         LIST_ENTRY FreeList;    // Free queue of descriptor blocks
 716         unsigned char State;    // See SXG_BUFFER state above
 717 } SXG_RCV_DESCRIPTOR_BLOCK_HDR, *PSXG_RCV_DESCRIPTOR_BLOCK_HDR;
 718
 719 // Receive block header
 720 typedef struct _SXG_RCV_BLOCK_HDR {
 721         void *VirtualAddress;   // Start of virtual memory
 722         dma_addr_t PhysicalAddress;     // ..and it's physical address
 723         LIST_ENTRY AllList;     // Queue of all SXG_RCV_BLOCKS
 724 } SXG_RCV_BLOCK_HDR, *PSXG_RCV_BLOCK_HDR;
 725
 726 // Macros to determine data structure offsets into receive block
 727 #define SXG_RCV_BLOCK_SIZE(_Buffersize)                                         \
 728         (((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) +              \
 729          (sizeof(SXG_RCV_DESCRIPTOR_BLOCK))              +              \
 730          (sizeof(SXG_RCV_DESCRIPTOR_BLOCK_HDR))          +              \
 731          (sizeof(SXG_RCV_BLOCK_HDR)))
 732 #define SXG_RCV_BUFFER_DATA_SIZE(_Buffersize)                           \
 733         ((_Buffersize) - SXG_RCV_DATA_HDR_SIZE)
 734 #define SXG_RCV_DATA_BUFFER_HDR_OFFSET(_Buffersize)                     \
 735         ((_Buffersize) - SXG_RCV_DATA_HDR_SIZE)
 736 #define SXG_RCV_DESCRIPTOR_BLOCK_OFFSET(_Buffersize)            \
 737         ((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK)
 738 #define SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET(_Buffersize)        \
 739         (((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) +              \
 740          (sizeof(SXG_RCV_DESCRIPTOR_BLOCK)))
 741 #define SXG_RCV_BLOCK_HDR_OFFSET(_Buffersize)                           \
 742         (((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) +              \
 743          (sizeof(SXG_RCV_DESCRIPTOR_BLOCK))              +              \
 744          (sizeof(SXG_RCV_DESCRIPTOR_BLOCK_HDR)))
 745
 746 // Use the miniport reserved portion of the NBL to locate
 747 // our SXG_RCV_DATA_BUFFER_HDR structure.
 748 typedef struct _SXG_RCV_NBL_RESERVED {
 749         PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr;
 750         void *Available;
 751 } SXG_RCV_NBL_RESERVED, *PSXG_RCV_NBL_RESERVED;
 752
 753 #define SXG_RCV_NBL_BUFFER_HDR(_NBL) (((PSXG_RCV_NBL_RESERVED)NET_BUFFER_LIST_MINIPORT_RESERVED(_NBL))->RcvDataBufferHdr)
 754
 755 /***************************************************************************
 756  * Scatter gather list buffer
 757  ***************************************************************************/
 758 #define SXG_INITIAL_SGL_BUFFERS         8192    // Initial pool of SGL buffers
 759 #define SXG_MIN_SGL_BUFFERS                     2048    // Minimum amount and when to get more
 760 #define SXG_MAX_SGL_BUFFERS                     16384   // Maximum to allocate (note ADAPT:ushort)
 761
 762 // Self identifying structure type
 763 typedef enum _SXG_SGL_TYPE {
 764         SXG_SGL_DUMB,           // Dumb NIC SGL
 765         SXG_SGL_SLOW,           // Slowpath protocol header - see below
 766         SXG_SGL_CHIMNEY         // Chimney offload SGL
 767 } SXG_SGL_TYPE, PSXG_SGL_TYPE;
 768
 769 // Note - the description below is Microsoft specific
 770 //
 771 // The following definition specifies the amount of shared memory to allocate
 772 // for the SCATTER_GATHER_LIST portion of the SXG_SCATTER_GATHER data structure.
 773 // The following considerations apply when setting this value:
 774 // - First, the Sahara card is designed to read the Microsoft SGL structure
 775 //       straight out of host memory.  This means that the SGL must reside in
 776 //       shared memory.  If the length here is smaller than the SGL for the
 777 //       NET_BUFFER, then NDIS will allocate its own buffer.  The buffer
 778 //       that NDIS allocates is not in shared memory, so when this happens,
 779 //       the SGL will need to be copied to a set of SXG_SCATTER_GATHER buffers.
 780 //       In other words.. we don't want this value to be too small.
 781 // - On the other hand.. we're allocating up to 16k of these things.  If
 782 //       we make this too big, we start to consume a ton of memory..
 783 // At the moment, I'm going to limit the number of SG entries to 150.
 784 // If each entry maps roughly 4k, then this should cover roughly 600kB
 785 // NET_BUFFERs.  Furthermore, since each entry is 24 bytes, the total
 786 // SGE portion of the structure consumes 3600 bytes, which should allow
 787 // the entire SXG_SCATTER_GATHER structure to reside comfortably within
 788 // a 4k block, providing the remaining fields stay under 500 bytes.
 789 //
 790 // So with 150 entries, the SXG_SCATTER_GATHER structure becomes roughly
 791 // 4k.  At 16k of them, that amounts to 64M of shared memory.  A ton, but
 792 // manageable.
 793 #define SXG_SGL_ENTRIES         150
 794
 795 // The ucode expects an NDIS SGL structure that
 796 // is formatted for an x64 system.  When running
 797 // on an x64 system, we can simply hand the NDIS SGL
 798 // to the card directly.  For x86 systems we must reconstruct
 799 // the SGL.  The following structure defines an x64
 800 // formatted SGL entry
 801 typedef struct _SXG_X64_SGE {
 802         dma64_addr_t Address;   // same as wdm.h
 803         u32 Length;             // same as wdm.h
 804         u32 CompilerPad;        // The compiler pads to 8-bytes
 805         u64 Reserved;           // u32 * in wdm.h.  Force to 8 bytes
 806 } SXG_X64_SGE, *PSXG_X64_SGE;
 807
 808 typedef struct _SCATTER_GATHER_ELEMENT {
 809         dma64_addr_t Address;   // same as wdm.h
 810         u32 Length;             // same as wdm.h
 811         u32 CompilerPad;        // The compiler pads to 8-bytes
 812         u64 Reserved;           // u32 * in wdm.h.  Force to 8 bytes
 813 } SCATTER_GATHER_ELEMENT, *PSCATTER_GATHER_ELEMENT;
 814
 815 typedef struct _SCATTER_GATHER_LIST {
 816         u32 NumberOfElements;
 817         u32 *Reserved;
 818         SCATTER_GATHER_ELEMENT Elements[];
 819 } SCATTER_GATHER_LIST, *PSCATTER_GATHER_LIST;
 820
 821 // The card doesn't care about anything except elements, so
 822 // we can leave the u32 * reserved field alone in the following
 823 // SGL structure.  But redefine from wdm.h:SCATTER_GATHER_LIST so
 824 // we can specify SXG_X64_SGE and define a fixed number of elements
 825 typedef struct _SXG_X64_SGL {
 826         u32 NumberOfElements;
 827         u32 *Reserved;
 828         SXG_X64_SGE Elements[SXG_SGL_ENTRIES];
 829 } SXG_X64_SGL, *PSXG_X64_SGL;
 830
 831 typedef struct _SXG_SCATTER_GATHER {
 832         SXG_SGL_TYPE Type;      // FIRST! Dumb-nic or offload
 833         void *adapter;          // Back pointer to adapter
 834         LIST_ENTRY FreeList;    // Free SXG_SCATTER_GATHER blocks
 835         LIST_ENTRY AllList;     // All SXG_SCATTER_GATHER blocks
 836         dma_addr_t PhysicalAddress;     // physical address
 837         unsigned char State;    // See SXG_BUFFER state above
 838         unsigned char CmdIndex; // Command ring index
 839         struct sk_buff *DumbPacket;     // Associated Packet
 840         u32 Direction;          // For asynchronous completions
 841         u32 CurOffset;          // Current SGL offset
 842         u32 SglRef;             // SGL reference count
 843         VLAN_HDR VlanTag;       // VLAN tag to be inserted into SGL
 844         PSCATTER_GATHER_LIST pSgl;      // SGL Addr. Possibly &Sgl
 845         SXG_X64_SGL Sgl;        // SGL handed to card
 846 } SXG_SCATTER_GATHER, *PSXG_SCATTER_GATHER;
 847
 848 #if defined(CONFIG_X86_64)
 849 #define SXG_SGL_BUFFER(_SxgSgl)         (&_SxgSgl->Sgl)
 850 #define SXG_SGL_BUF_SIZE                        sizeof(SXG_X64_SGL)
 851 #elif defined(CONFIG_X86)
 852 // Force NDIS to give us it's own buffer so we can reformat to our own
 853 #define SXG_SGL_BUFFER(_SxgSgl)         NULL
 854 #define SXG_SGL_BUF_SIZE                        0
 855 #else
 856 Stop Compilation;
 857 #endif