1 /**************************************************************************
3 * Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
5 * $Id: slichw.h,v 1.3 2008/03/17 19:27:26 chris Exp $
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
22 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * The views and conclusions contained in the software and documentation
32 * are those of the authors and should not be interpreted as representing
33 * official policies, either expressed or implied, of Alacritech, Inc.
35 **************************************************************************/
40 * This header file contains definitions that are common to our hardware.
45 #define PCI_VENDOR_ID_ALACRITECH 0x139A
46 #define SLIC_1GB_DEVICE_ID 0x0005
47 #define SLIC_2GB_DEVICE_ID 0x0007 /*Oasis Device ID */
49 #define SLIC_1GB_CICADA_SUBSYS_ID 0x0008
51 #define SLIC_NBR_MACS 4
53 #define SLIC_RCVBUF_SIZE 2048
54 #define SLIC_RCVBUF_HEADSIZE 34
55 #define SLIC_RCVBUF_TAILSIZE 0
56 #define SLIC_RCVBUF_DATASIZE (SLIC_RCVBUF_SIZE - (SLIC_RCVBUF_HEADSIZE +\
57 SLIC_RCVBUF_TAILSIZE))
59 #define VGBSTAT_XPERR 0x40000000
60 #define VGBSTAT_XERRSHFT 25
61 #define VGBSTAT_XCSERR 0x23
62 #define VGBSTAT_XUFLOW 0x22
63 #define VGBSTAT_XHLEN 0x20
64 #define VGBSTAT_NETERR 0x01000000
65 #define VGBSTAT_NERRSHFT 16
66 #define VGBSTAT_NERRMSK 0x1ff
67 #define VGBSTAT_NCSERR 0x103
68 #define VGBSTAT_NUFLOW 0x102
69 #define VGBSTAT_NHLEN 0x100
70 #define VGBSTAT_LNKERR 0x00000080
71 #define VGBSTAT_LERRMSK 0xff
72 #define VGBSTAT_LDEARLY 0x86
73 #define VGBSTAT_LBOFLO 0x85
74 #define VGBSTAT_LCODERR 0x84
75 #define VGBSTAT_LDBLNBL 0x83
76 #define VGBSTAT_LCRCERR 0x82
77 #define VGBSTAT_LOFLO 0x81
78 #define VGBSTAT_LUFLO 0x80
79 #define IRHDDR_FLEN_MSK 0x0000ffff
80 #define IRHDDR_SVALID 0x80000000
81 #define IRHDDR_ERR 0x10000000
82 #define VRHSTAT_802OE 0x80000000
83 #define VRHSTAT_TPOFLO 0x10000000
84 #define VRHSTATB_802UE 0x80000000
85 #define VRHSTATB_RCVE 0x40000000
86 #define VRHSTATB_BUFF 0x20000000
87 #define VRHSTATB_CARRE 0x08000000
88 #define VRHSTATB_LONGE 0x02000000
89 #define VRHSTATB_PREA 0x01000000
90 #define VRHSTATB_CRC 0x00800000
91 #define VRHSTATB_DRBL 0x00400000
92 #define VRHSTATB_CODE 0x00200000
93 #define VRHSTATB_TPCSUM 0x00100000
94 #define VRHSTATB_TPHLEN 0x00080000
95 #define VRHSTATB_IPCSUM 0x00040000
96 #define VRHSTATB_IPLERR 0x00020000
97 #define VRHSTATB_IPHERR 0x00010000
98 #define SLIC_MAX64_BCNT 23
99 #define SLIC_MAX32_BCNT 26
100 #define IHCMD_XMT_REQ 0x01
101 #define IHFLG_IFSHFT 2
102 #define SLIC_RSPBUF_SIZE 32
104 #define SLIC_RESET_MAGIC 0xDEAD
105 #define ICR_INT_OFF 0
107 #define ICR_INT_MASK 2
109 #define ISR_ERR 0x80000000
110 #define ISR_RCV 0x40000000
111 #define ISR_CMD 0x20000000
112 #define ISR_IO 0x60000000
113 #define ISR_UPC 0x10000000
114 #define ISR_LEVENT 0x08000000
115 #define ISR_RMISS 0x02000000
116 #define ISR_UPCERR 0x01000000
117 #define ISR_XDROP 0x00800000
118 #define ISR_UPCBSY 0x00020000
119 #define ISR_EVMSK 0xffff0000
120 #define ISR_PINGMASK 0x00700000
121 #define ISR_PINGDSMASK 0x00710000
122 #define ISR_UPCMASK 0x11000000
123 #define SLIC_WCS_START 0x80000000
124 #define SLIC_WCS_COMPARE 0x40000000
125 #define SLIC_RCVWCS_BEGIN 0x40000000
126 #define SLIC_RCVWCS_FINISH 0x80000000
127 #define SLIC_PM_MAXPATTERNS 6
128 #define SLIC_PM_PATTERNSIZE 128
129 #define SLIC_PMCAPS_WAKEONLAN 0x00000001
130 #define MIICR_REG_PCR 0x00000000
131 #define MIICR_REG_4 0x00040000
132 #define MIICR_REG_9 0x00090000
133 #define MIICR_REG_16 0x00100000
134 #define PCR_RESET 0x8000
135 #define PCR_POWERDOWN 0x0800
136 #define PCR_SPEED_100 0x2000
137 #define PCR_SPEED_1000 0x0040
138 #define PCR_AUTONEG 0x1000
139 #define PCR_AUTONEG_RST 0x0200
140 #define PCR_DUPLEX_FULL 0x0100
141 #define PSR_LINKUP 0x0004
143 #define PAR_ADV100FD 0x0100
144 #define PAR_ADV100HD 0x0080
145 #define PAR_ADV10FD 0x0040
146 #define PAR_ADV10HD 0x0020
147 #define PAR_ASYMPAUSE 0x0C00
148 #define PAR_802_3 0x0001
150 #define PAR_ADV1000XFD 0x0020
151 #define PAR_ADV1000XHD 0x0040
152 #define PAR_ASYMPAUSE_FIBER 0x0180
154 #define PGC_ADV1000FD 0x0200
155 #define PGC_ADV1000HD 0x0100
156 #define SEEQ_LINKFAIL 0x4000
157 #define SEEQ_SPEED 0x0080
158 #define SEEQ_DUPLEX 0x0040
159 #define TDK_DUPLEX 0x0800
160 #define TDK_SPEED 0x0400
161 #define MRV_REG16_XOVERON 0x0068
162 #define MRV_REG16_XOVEROFF 0x0008
163 #define MRV_SPEED_1000 0x8000
164 #define MRV_SPEED_100 0x4000
165 #define MRV_SPEED_10 0x0000
166 #define MRV_FULLDUPLEX 0x2000
167 #define MRV_LINKUP 0x0400
169 #define GIG_LINKUP 0x0001
170 #define GIG_FULLDUPLEX 0x0002
171 #define GIG_SPEED_MASK 0x000C
172 #define GIG_SPEED_1000 0x0008
173 #define GIG_SPEED_100 0x0004
174 #define GIG_SPEED_10 0x0000
176 #define MCR_RESET 0x80000000
177 #define MCR_CRCEN 0x40000000
178 #define MCR_FULLD 0x10000000
179 #define MCR_PAD 0x02000000
180 #define MCR_RETRYLATE 0x01000000
181 #define MCR_BOL_SHIFT 21
182 #define MCR_IPG1_SHIFT 14
183 #define MCR_IPG2_SHIFT 7
184 #define MCR_IPG3_SHIFT 0
185 #define GMCR_RESET 0x80000000
186 #define GMCR_GBIT 0x20000000
187 #define GMCR_FULLD 0x10000000
188 #define GMCR_GAPBB_SHIFT 14
189 #define GMCR_GAPR1_SHIFT 7
190 #define GMCR_GAPR2_SHIFT 0
191 #define GMCR_GAPBB_1000 0x60
192 #define GMCR_GAPR1_1000 0x2C
193 #define GMCR_GAPR2_1000 0x40
194 #define GMCR_GAPBB_100 0x70
195 #define GMCR_GAPR1_100 0x2C
196 #define GMCR_GAPR2_100 0x40
197 #define XCR_RESET 0x80000000
198 #define XCR_XMTEN 0x40000000
199 #define XCR_PAUSEEN 0x20000000
200 #define XCR_LOADRNG 0x10000000
201 #define RCR_RESET 0x80000000
202 #define RCR_RCVEN 0x40000000
203 #define RCR_RCVALL 0x20000000
204 #define RCR_RCVBAD 0x10000000
205 #define RCR_CTLEN 0x08000000
206 #define RCR_ADDRAEN 0x02000000
207 #define GXCR_RESET 0x80000000
208 #define GXCR_XMTEN 0x40000000
209 #define GXCR_PAUSEEN 0x20000000
210 #define GRCR_RESET 0x80000000
211 #define GRCR_RCVEN 0x40000000
212 #define GRCR_RCVALL 0x20000000
213 #define GRCR_RCVBAD 0x10000000
214 #define GRCR_CTLEN 0x08000000
215 #define GRCR_ADDRAEN 0x02000000
216 #define GRCR_HASHSIZE_SHIFT 17
217 #define GRCR_HASHSIZE 14
219 #define SLIC_EEPROM_ID 0xA5A5
220 #define SLIC_SRAM_SIZE2GB (64 * 1024)
221 #define SLIC_SRAM_SIZE1GB (32 * 1024)
222 #define SLIC_HOSTID_DEFAULT 0xFFFF /* uninitialized hostid */
223 #define SLIC_NBR_MACS 4
239 typedef struct _slic_rcvbuf_t {
249 uchar data[SLIC_RCVBUF_DATASIZE];
250 } slic_rcvbuf_t, *p_slic_rcvbuf_t;
252 typedef struct _slic_hddr_wds {
255 ulong32 frame_status;
256 ulong32 frame_status_b;
261 ulong32 frame_status;
269 } slic_hddr_wds_t, *p_slic_hddr_wds;
271 #define frame_status14 u0.hdrs_14port.frame_status
272 #define frame_status_b14 u0.hdrs_14port.frame_status_b
273 #define frame_statusGB u0.hdrs_gbit.frame_status
275 typedef struct _slic_host64sg_t {
279 } slic_host64sg_t, *p_slic_host64sg_t;
281 typedef struct _slic_host64_cmd_t {
293 slic_host64sg_t bufs[SLIC_MAX64_BCNT];
297 } slic_host64_cmd_t, *p_slic_host64_cmd_t;
299 typedef struct _slic_rspbuf_t {
306 } slic_rspbuf_t, *p_slic_rspbuf_t;
308 typedef ulong32 SLIC_REG;
311 typedef struct _slic_regs_t {
312 ULONG slic_reset; /* Reset Register */
315 ULONG slic_icr; /* Interrupt Control Register */
317 #define SLIC_ICR 0x0008
319 ULONG slic_isp; /* Interrupt status pointer */
321 #define SLIC_ISP 0x0010
323 ULONG slic_isr; /* Interrupt status */
325 #define SLIC_ISR 0x0018
327 SLIC_REG slic_hbar; /* Header buffer address reg */
329 /* 31-8 - phy addr of set of contiguous hdr buffers
330 7-0 - number of buffers passed
331 Buffers are 256 bytes long on 256-byte boundaries. */
332 #define SLIC_HBAR 0x0020
333 #define SLIC_HBAR_CNT_MSK 0x000000FF
335 SLIC_REG slic_dbar; /* Data buffer handle & address reg */
338 /* 4 sets of registers; Buffers are 2K bytes long 2 per 4K page. */
339 #define SLIC_DBAR 0x0028
340 #define SLIC_DBAR_SIZE 2048
342 SLIC_REG slic_cbar; /* Xmt Cmd buf addr regs.*/
343 /* 1 per XMT interface
344 31-5 - phy addr of host command buffer
345 4-0 - length of cmd in multiples of 32 bytes
346 Buffers are 32 bytes up to 512 bytes long */
347 #define SLIC_CBAR 0x0030
348 #define SLIC_CBAR_LEN_MSK 0x0000001F
349 #define SLIC_CBAR_ALIGN 0x00000020
351 SLIC_REG slic_wcs; /* write control store*/
352 #define SLIC_WCS 0x0034
353 #define SLIC_WCS_START 0x80000000 /*Start the SLIC (Jump to WCS)*/
354 #define SLIC_WCS_COMPARE 0x40000000 /* Compare with value in WCS*/
356 SLIC_REG slic_rbar; /* Response buffer address reg.*/
358 /*31-8 - phy addr of set of contiguous response buffers
359 7-0 - number of buffers passed
360 Buffers are 32 bytes long on 32-byte boundaries.*/
361 #define SLIC_RBAR 0x0038
362 #define SLIC_RBAR_CNT_MSK 0x000000FF
363 #define SLIC_RBAR_SIZE 32
365 SLIC_REG slic_stats; /* read statistics (UPR) */
367 #define SLIC_RSTAT 0x0040
369 SLIC_REG slic_rlsr; /* read link status */
371 #define SLIC_LSTAT 0x0048
373 SLIC_REG slic_wmcfg; /* Write Mac Config */
375 #define SLIC_WMCFG 0x0050
377 SLIC_REG slic_wphy; /* Write phy register */
379 #define SLIC_WPHY 0x0058
381 SLIC_REG slic_rcbar; /*Rcv Cmd buf addr reg*/
383 #define SLIC_RCBAR 0x0060
385 SLIC_REG slic_rconfig; /* Read SLIC Config*/
387 #define SLIC_RCONFIG 0x0068
389 SLIC_REG slic_intagg; /* Interrupt aggregation time*/
391 #define SLIC_INTAGG 0x0070
393 SLIC_REG slic_wxcfg; /* Write XMIT config reg*/
395 #define SLIC_WXCFG 0x0078
397 SLIC_REG slic_wrcfg; /* Write RCV config reg*/
399 #define SLIC_WRCFG 0x0080
401 SLIC_REG slic_wraddral; /* Write rcv addr a low*/
403 #define SLIC_WRADDRAL 0x0088
405 SLIC_REG slic_wraddrah; /* Write rcv addr a high*/
407 #define SLIC_WRADDRAH 0x0090
409 SLIC_REG slic_wraddrbl; /* Write rcv addr b low*/
411 #define SLIC_WRADDRBL 0x0098
413 SLIC_REG slic_wraddrbh; /* Write rcv addr b high*/
415 #define SLIC_WRADDRBH 0x00a0
417 SLIC_REG slic_mcastlow; /* Low bits of mcast mask*/
419 #define SLIC_MCASTLOW 0x00a8
421 SLIC_REG slic_mcasthigh; /* High bits of mcast mask*/
423 #define SLIC_MCASTHIGH 0x00b0
425 SLIC_REG slic_ping; /* Ping the card*/
427 #define SLIC_PING 0x00b8
429 SLIC_REG slic_dump_cmd; /* Dump command */
431 #define SLIC_DUMP_CMD 0x00c0
433 SLIC_REG slic_dump_data; /* Dump data pointer */
435 #define SLIC_DUMP_DATA 0x00c8
437 SLIC_REG slic_pcistatus; /* Read card's pci_status register */
439 #define SLIC_PCISTATUS 0x00d0
441 SLIC_REG slic_wrhostid; /* Write hostid field */
443 #define SLIC_WRHOSTID 0x00d8
444 #define SLIC_RDHOSTID_1GB 0x1554
445 #define SLIC_RDHOSTID_2GB 0x1554
447 SLIC_REG slic_low_power; /* Put card in a low power state */
449 #define SLIC_LOW_POWER 0x00e0
451 SLIC_REG slic_quiesce; /* force slic into quiescent state
454 #define SLIC_QUIESCE 0x00e8
456 SLIC_REG slic_reset_iface; /* reset interface queues */
458 #define SLIC_RESET_IFACE 0x00f0
460 SLIC_REG slic_addr_upper; /* Bits 63-32 for host i/f addrs */
462 #define SLIC_ADDR_UPPER 0x00f8 /*Register is only written when it has changed*/
464 SLIC_REG slic_hbar64; /* 64 bit Header buffer address reg */
466 #define SLIC_HBAR64 0x0100
468 SLIC_REG slic_dbar64; /* 64 bit Data buffer handle & address reg */
470 #define SLIC_DBAR64 0x0108
472 SLIC_REG slic_cbar64; /* 64 bit Xmt Cmd buf addr regs. */
474 #define SLIC_CBAR64 0x0110
476 SLIC_REG slic_rbar64; /* 64 bit Response buffer address reg.*/
478 #define SLIC_RBAR64 0x0118
480 SLIC_REG slic_rcbar64; /* 64 bit Rcv Cmd buf addr reg*/
482 #define SLIC_RCBAR64 0x0120
484 SLIC_REG slic_stats64; /*read statistics (64 bit UPR)*/
486 #define SLIC_RSTAT64 0x0128
488 SLIC_REG slic_rcv_wcs; /*Download Gigabit RCV sequencer ucode*/
490 #define SLIC_RCV_WCS 0x0130
491 #define SLIC_RCVWCS_BEGIN 0x40000000
492 #define SLIC_RCVWCS_FINISH 0x80000000
494 SLIC_REG slic_wrvlanid; /* Write VlanId field */
496 #define SLIC_WRVLANID 0x0138
498 SLIC_REG slic_read_xf_info; /* Read Transformer info */
500 #define SLIC_READ_XF_INFO 0x0140
502 SLIC_REG slic_write_xf_info; /* Write Transformer info */
504 #define SLIC_WRITE_XF_INFO 0x0148
506 SLIC_REG RSVD1; /* TOE Only */
509 SLIC_REG RSVD2; /* TOE Only */
512 SLIC_REG RSVD3; /* TOE Only */
515 SLIC_REG RSVD4; /* TOE Only */
518 SLIC_REG slic_ticks_per_sec; /* Write card ticks per second */
520 #define SLIC_TICKS_PER_SEC 0x0170
522 } __iomem slic_regs_t, *p_slic_regs_t, SLIC_REGS, *PSLIC_REGS;
524 typedef enum _UPR_REQUEST {
537 typedef struct _inicpm_wakepattern {
538 ulong32 patternlength;
539 uchar pattern[SLIC_PM_PATTERNSIZE];
540 uchar mask[SLIC_PM_PATTERNSIZE];
541 } inicpm_wakepattern_t, *p_inicpm_wakepattern_t;
543 typedef struct _inicpm_state {
546 ulong32 wake_linkstatus;
547 ulong32 wake_magicpacket;
548 ulong32 wake_framepattern;
549 inicpm_wakepattern_t wakepattern[SLIC_PM_MAXPATTERNS];
550 } inicpm_state_t, *p_inicpm_state_t;
552 typedef struct _slicpm_packet_pattern {
556 ulong32 patternoffset;
558 ulong32 patternflags;
559 } slicpm_packet_pattern_t, *p_slicpm_packet_pattern_t;
561 typedef enum _slicpm_power_state {
562 slicpm_state_unspecified = 0,
568 } slicpm_state_t, *p_slicpm_state_t;
570 typedef struct _slicpm_wakeup_capabilities {
571 slicpm_state_t min_magic_packet_wakeup;
572 slicpm_state_t min_pattern_wakeup;
573 slicpm_state_t min_link_change_wakeup;
574 } slicpm_wakeup_capabilities_t, *p_slicpm_wakeup_capabilities_t;
577 typedef struct _slic_pnp_capabilities {
579 slicpm_wakeup_capabilities_t wakeup_capabilities;
580 } slic_pnp_capabilities_t, *p_slic_pnp_capabilities_t;
582 typedef struct _xmt_stats_t {
583 ulong32 xmit_tcp_bytes;
584 ulong32 xmit_tcp_segs;
586 ulong32 xmit_collisions;
587 ulong32 xmit_unicasts;
588 ulong32 xmit_other_error;
589 ulong32 xmit_excess_collisions;
592 typedef struct _rcv_stats_t {
593 ulong32 rcv_tcp_bytes;
594 ulong32 rcv_tcp_segs;
596 ulong32 rcv_unicasts;
597 ulong32 rcv_other_error;
601 typedef struct _xmt_statsgb_t {
602 ulong64 xmit_tcp_bytes;
603 ulong64 xmit_tcp_segs;
605 ulong64 xmit_collisions;
606 ulong64 xmit_unicasts;
607 ulong64 xmit_other_error;
608 ulong64 xmit_excess_collisions;
611 typedef struct _rcv_statsgb_t {
612 ulong64 rcv_tcp_bytes;
613 ulong64 rcv_tcp_segs;
615 ulong64 rcv_unicasts;
620 typedef struct _slic_stats {
623 xmt_stats100_t xmt100;
624 rcv_stats100_t rcv100;
631 } slic_stats_t, *p_slic_stats_t;
633 #define xmit_tcp_segs100 u.stats_100.xmt100.xmit_tcp_segs
634 #define xmit_tcp_bytes100 u.stats_100.xmt100.xmit_tcp_bytes
635 #define xmit_bytes100 u.stats_100.xmt100.xmit_bytes
636 #define xmit_collisions100 u.stats_100.xmt100.xmit_collisions
637 #define xmit_unicasts100 u.stats_100.xmt100.xmit_unicasts
638 #define xmit_other_error100 u.stats_100.xmt100.xmit_other_error
639 #define xmit_excess_collisions100 u.stats_100.xmt100.xmit_excess_collisions
640 #define rcv_tcp_segs100 u.stats_100.rcv100.rcv_tcp_segs
641 #define rcv_tcp_bytes100 u.stats_100.rcv100.rcv_tcp_bytes
642 #define rcv_bytes100 u.stats_100.rcv100.rcv_bytes
643 #define rcv_unicasts100 u.stats_100.rcv100.rcv_unicasts
644 #define rcv_other_error100 u.stats_100.rcv100.rcv_other_error
645 #define rcv_drops100 u.stats_100.rcv100.rcv_drops
646 #define xmit_tcp_segs_gb u.stats_GB.xmtGB.xmit_tcp_segs
647 #define xmit_tcp_bytes_gb u.stats_GB.xmtGB.xmit_tcp_bytes
648 #define xmit_bytes_gb u.stats_GB.xmtGB.xmit_bytes
649 #define xmit_collisions_gb u.stats_GB.xmtGB.xmit_collisions
650 #define xmit_unicasts_gb u.stats_GB.xmtGB.xmit_unicasts
651 #define xmit_other_error_gb u.stats_GB.xmtGB.xmit_other_error
652 #define xmit_excess_collisions_gb u.stats_GB.xmtGB.xmit_excess_collisions
654 #define rcv_tcp_segs_gb u.stats_GB.rcvGB.rcv_tcp_segs
655 #define rcv_tcp_bytes_gb u.stats_GB.rcvGB.rcv_tcp_bytes
656 #define rcv_bytes_gb u.stats_GB.rcvGB.rcv_bytes
657 #define rcv_unicasts_gb u.stats_GB.rcvGB.rcv_unicasts
658 #define rcv_other_error_gb u.stats_GB.rcvGB.rcv_other_error
659 #define rcv_drops_gb u.stats_GB.rcvGB.rcv_drops
661 typedef struct _slic_config_mac_t {
664 } slic_config_mac_t, *pslic_config_mac_t;
666 #define ATK_FRU_FORMAT 0x00
667 #define VENDOR1_FRU_FORMAT 0x01
668 #define VENDOR2_FRU_FORMAT 0x02
669 #define VENDOR3_FRU_FORMAT 0x03
670 #define VENDOR4_FRU_FORMAT 0x04
671 #define NO_FRU_FORMAT 0xFF
673 typedef struct _atk_fru_t {
678 } atk_fru_t, *patk_fru_t;
680 typedef struct _vendor1_fru_t {
688 } vendor1_fru_t, *pvendor1_fru_t;
690 typedef struct _vendor2_fru_t {
696 } vendor2_fru_t, *pvendor2_fru_t;
698 typedef struct _vendor3_fru_t {
703 } vendor3_fru_t, *pvendor3_fru_t;
705 typedef struct _vendor4_fru_t {
710 } vendor4_fru_t, *pvendor4_fru_t;
712 typedef union _oemfru_t {
713 vendor1_fru_t vendor1_fru;
714 vendor2_fru_t vendor2_fru;
715 vendor3_fru_t vendor3_fru;
716 vendor4_fru_t vendor4_fru;
717 } oemfru_t, *poemfru_t;
720 SLIC EEPROM structure for Mojave
722 typedef struct _slic_eeprom {
723 ushort Id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/
724 ushort EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
725 ushort FlashSize; /* 02 Flash size */
726 ushort EepromSize; /* 03 EEPROM Size */
727 ushort VendorId; /* 04 Vendor ID */
728 ushort DeviceId; /* 05 Device ID */
729 uchar RevisionId; /* 06 Revision ID */
730 uchar ClassCode[3]; /* 07 Class Code */
731 uchar DbgIntPin; /* 08 Debug Interrupt pin */
732 uchar NetIntPin0; /* Network Interrupt Pin */
733 uchar MinGrant; /* 09 Minimum grant */
734 uchar MaxLat; /* Maximum Latency */
735 ushort PciStatus; /* 10 PCI Status */
736 ushort SubSysVId; /* 11 Subsystem Vendor Id */
737 ushort SubSysId; /* 12 Subsystem ID */
738 ushort DbgDevId; /* 13 Debug Device Id */
739 ushort DramRomFn; /* 14 Dram/Rom function */
740 ushort DSize2Pci; /* 15 DRAM size to PCI (bytes * 64K) */
741 ushort RSize2Pci; /* 16 ROM extension size to PCI (bytes * 4k) */
742 uchar NetIntPin1; /* 17 Network Interface Pin 1 (simba/leone only) */
743 uchar NetIntPin2; /* Network Interface Pin 2 (simba/leone only) */
745 uchar NetIntPin3;/* 18 Network Interface Pin 3 (simba only) */
746 uchar FreeTime;/* FreeTime setting (leone/mojave only) */
748 uchar TBIctl; /* 10-bit interface control (Mojave only) */
749 ushort DramSize; /* 19 DRAM size (bytes * 64k) */
752 /* Mac Interface Specific portions */
753 slic_config_mac_t MacInfo[SLIC_NBR_MACS];
754 } mac; /* MAC access for all boards */
756 /* use above struct for MAC access */
757 slic_config_mac_t pad[SLIC_NBR_MACS - 1];
758 ushort DeviceId2; /* Device ID for 2nd
760 uchar IntPin2; /* Interrupt pin for
762 uchar ClassCode2[3]; /* Class Code for 2nd
764 } mojave; /* 2nd function access for gigabit board */
766 ushort CfgByte6; /* Config Byte 6 */
767 ushort PMECapab; /* Power Mgment capabilities */
768 ushort NwClkCtrls; /* NetworkClockControls */
769 uchar FruFormat; /* Alacritech FRU format type */
770 atk_fru_t AtkFru; /* Alacritech FRU information */
771 uchar OemFruFormat; /* optional OEM FRU format type */
772 oemfru_t OemFru; /* optional OEM FRU information */
773 uchar Pad[4]; /* Pad to 128 bytes - includes 2 cksum bytes
774 *(if OEM FRU info exists) and two unusable
775 * bytes at the end */
776 } slic_eeprom_t, *pslic_eeprom_t;
778 /* SLIC EEPROM structure for Oasis */
779 typedef struct _oslic_eeprom_t {
780 ushort Id; /* 00 EEPROM/FLASH Magic code 'A5A5' */
781 ushort EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
782 ushort FlashConfig0; /* 02 Flash Config for SPI device 0 */
783 ushort FlashConfig1; /* 03 Flash Config for SPI device 1 */
784 ushort VendorId; /* 04 Vendor ID */
785 ushort DeviceId; /* 05 Device ID (function 0) */
786 uchar RevisionId; /* 06 Revision ID */
787 uchar ClassCode[3]; /* 07 Class Code for PCI function 0 */
788 uchar IntPin1; /* 08 Interrupt pin for PCI function 1*/
789 uchar ClassCode2[3]; /* 09 Class Code for PCI function 1 */
790 uchar IntPin2; /* 10 Interrupt pin for PCI function 2*/
791 uchar IntPin0; /* Interrupt pin for PCI function 0*/
792 uchar MinGrant; /* 11 Minimum grant */
793 uchar MaxLat; /* Maximum Latency */
794 ushort SubSysVId; /* 12 Subsystem Vendor Id */
795 ushort SubSysId; /* 13 Subsystem ID */
796 ushort FlashSize; /* 14 Flash size (bytes / 4K) */
797 ushort DSize2Pci; /* 15 DRAM size to PCI (bytes / 64K) */
798 ushort RSize2Pci; /* 16 Flash (ROM extension) size to
800 ushort DeviceId1; /* 17 Device Id (function 1) */
801 ushort DeviceId2; /* 18 Device Id (function 2) */
802 ushort CfgByte6; /* 19 Device Status Config Bytes 6-7 */
803 ushort PMECapab; /* 20 Power Mgment capabilities */
804 uchar MSICapab; /* 21 MSI capabilities */
805 uchar ClockDivider; /* Clock divider */
806 ushort PciStatusLow; /* 22 PCI Status bits 15:0 */
807 ushort PciStatusHigh; /* 23 PCI Status bits 31:16 */
808 ushort DramConfigLow; /* 24 DRAM Configuration bits 15:0 */
809 ushort DramConfigHigh; /* 25 DRAM Configuration bits 31:16 */
810 ushort DramSize; /* 26 DRAM size (bytes / 64K) */
811 ushort GpioTbiCtl;/* 27 GPIO/TBI controls for functions 1/0 */
812 ushort EepromSize; /* 28 EEPROM Size */
813 slic_config_mac_t MacInfo[2]; /* 29 MAC addresses (2 ports) */
814 uchar FruFormat; /* 35 Alacritech FRU format type */
815 atk_fru_t AtkFru; /* Alacritech FRU information */
816 uchar OemFruFormat; /* optional OEM FRU format type */
817 oemfru_t OemFru; /* optional OEM FRU information */
818 uchar Pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes
819 * (if OEM FRU info exists) and two unusable
822 } oslic_eeprom_t, *poslic_eeprom_t;
824 #define MAX_EECODE_SIZE sizeof(slic_eeprom_t)
825 #define MIN_EECODE_SIZE 0x62 /* code size without optional OEM FRU stuff */
827 /* SLIC CONFIG structure
829 This structure lives in the CARD structure and is valid for all
830 board types. It is filled in from the appropriate EEPROM structure
831 by SlicGetConfigData().
833 typedef struct _slic_config_t {
834 boolean EepromValid; /* Valid EEPROM flag (checksum good?) */
835 ushort DramSize; /* DRAM size (bytes / 64K) */
836 slic_config_mac_t MacInfo[SLIC_NBR_MACS]; /* MAC addresses */
837 uchar FruFormat; /* Alacritech FRU format type */
838 atk_fru_t AtkFru; /* Alacritech FRU information */
839 uchar OemFruFormat; /* optional OEM FRU format type */
841 vendor1_fru_t vendor1_fru;
842 vendor2_fru_t vendor2_fru;
843 vendor3_fru_t vendor3_fru;
844 vendor4_fru_t vendor4_fru;
846 } slic_config_t, *pslic_config_t;