2 * $Id: slicdump.h,v 1.2 2006/03/27 15:09:57 mook Exp $
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32 * ALACRITECH PATENTS INCLUDING BUT NOT LIMITED TO U.S. PATENT NOS. 6,226,680,
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45 #define DEBUG_SUCCESS 0
47 /***********************************************************************
49 * Utility processor register locations
51 **********************************************************************/
52 #define UTILITY_RESET 0x0
53 #define UTILITY_ISP_ADDR 0x4 /* Interrupt status Pointer */
54 #define UTILITY_ISR_ADDR 0x8 /* Interrupt status Register */
55 #define UTILITY_ICR_ADDR 0xc /* Interrupt Control Register */
56 #define UTILITY_CPR_ADDR 0x10 /* Command Pointer Register */
57 #define UTILITY_DPR_ADDR 0x14 /* Data Pointer Register */
58 #define UTILITY_DMP_TRQ 0x18 /* Dump queue onto ALU for analyser */
59 #define UTILITY_UPP_ADDR 0x1c /* Bits 63-32 of cmd/data pointer */
61 /***********************************************************************
63 * INIC status register bits
65 ***********************************************************************/
66 #define SLIC_ISR_CC 0x10000000 /* Command complete - synchronous */
67 #define SLIC_ISR_ERR 0x01000000 /* Command Error - synchronous */
68 #define SLIC_ISR_CMD_MASK 0x11000000 /* Command status mask */
69 #define SLIC_ISR_TPH 0x00080000 /* Transmit processor halted - async */
70 #define SLIC_ISR_RPH 0x00040000 /* Receive processor halted - async */
72 /***********************************************************************
74 * INIC Control register values
76 ***********************************************************************/
77 #define SLIC_ICR_OFF 0 /* Interrupts disabled */
78 #define SLIC_ICR_ON 1 /* Interrupts enabled */
79 #define SLIC_ICR_MASK 2 /* Interrupts masked */
81 #define WRITE_DREG(reg, value, flush) \
83 writel((value), (reg)); \
89 /************************************************************************
93 * Each command contains a command byte which is defined as follows:
96 * ----------------------------------------------
97 * command Alt. Proc Processor
99 ************************************************************************/
102 * Macro to create the command byte given the command, Alt. Proc, and
103 * Processor values. Note that the macro assumes that the values are
104 * preshifted. That is, the values for alt. proc are 0 for transmit and
107 #define COMMAND_BYTE(command, alt_proc, proc) ((command) | (alt_proc) | (proc))
112 #define CMD_HALT 0x0 /* Send a halt to the INIC */
113 #define CMD_RUN 0x8 /* Start the halted INIC */
114 #define CMD_STEP 0x10 /* Single step the inic */
115 #define CMD_BREAK 0x18 /* Set a breakpoint - 8 byte command */
116 #define CMD_RESET_BREAK 0x20 /* Reset a breakpoint - 8 byte cmd */
117 #define CMD_DUMP 0x28 /* Dump INIC memory - 8 byte command */
118 #define CMD_LOAD 0x30 /* Load INIC memory - 8 byte command */
119 #define CMD_MAP 0x38 /* Map out a ROM instruction - 8 BC */
120 #define CMD_CAM_OPS 0x38 /* perform ops on specific CAM */
121 #define CMD_XMT 0x40 /* Transmit frame */
122 #define CMD_RCV 0x48 /* Receive frame */
127 * When the proc value is set to the utility processor, the Alt. Proc
128 * specifies which processor handles the debugging.
130 #define ALT_PROC_TRANSMIT 0x0
131 #define ALT_PROC_RECEIVE 0x4
136 #define PROC_INVALID 0x0
137 #define PROC_NONE 0x0 /* Gigabit use */
138 #define PROC_TRANSMIT 0x1
139 #define PROC_RECEIVE 0x2
140 #define PROC_UTILITY 0x3
142 /******************************************************************
144 * 8 byte command structure definitions
146 ******************************************************************/
149 * Break and Reset Break command structure
151 typedef struct _BREAK {
152 uchar command; /* Command word defined above */
154 ushort count; /* Number of executions before break */
155 ulong32 addr; /* Address of break point */
159 * Dump and Load command structure
161 typedef struct _dump_cmd {
162 uchar cmd; /* Command word defined above */
163 uchar desc; /* Descriptor values - defined below */
164 ushort count; /* number of 4 byte words to be transferred */
165 ulong32 addr; /* start address of dump or load */
166 } dump_cmd_t, *pdump_cmd_t;
169 * Receive or Transmit a frame.
171 typedef struct _RCV_OR_XMT_FRAME {
172 uchar command; /* Command word defined above */
173 uchar MacId; /* Mac ID of interface - transmit only */
174 ushort count; /* Length of frame in bytes */
175 ulong32 pad; /* not used */
176 } RCV_OR_XMT_FRAME, *PRCV_OR_XMT_FRAME;
179 * Values of desc field in DUMP_OR_LOAD structure
181 #define DESC_RFILE 0x0 /* Register file */
182 #define DESC_SRAM 0x1 /* SRAM */
183 #define DESC_DRAM 0x2 /* DRAM */
184 #define DESC_QUEUE 0x3 /* queues */
185 #define DESC_REG 0x4 /* General registers (pc, status, etc) */
186 #define DESC_SENSE 0x5 /* Sense register */
188 /* Descriptor field definitions for CMD_DUMP_CAM */
190 #define DUMP_CAM_B 1 /* unused at present */
193 #define SEARCH_CAM_A 4
194 #define SEARCH_CAM_C 5
197 * Map command to replace a command in ROM with a command in WCS
199 typedef struct _MAP {
200 uchar command; /* Command word defined above */
202 ushort map_to; /* Instruction address in WCS */
203 ushort map_out; /* Instruction address in ROM */
209 #define SLIC_MAX_QUEUE 32 /* Total # of queues on the INIC (0-31)*/
210 #define SLIC_4MAX_REG 512 /* Total # of 4-port file-registers */
211 #define SLIC_1MAX_REG 384 /* Total # of file-registers */
212 #define SLIC_GBMAX_REG 1024 /* Total # of Gbit file-registers */
213 #define SLIC_NUM_REG 32 /* non-file-registers = NUM_REG in tm-simba.h */
214 #define SLIC_GB_CAMA_SZE 32
215 #define SLIC_GB_CAMB_SZE 16
216 #define SLIC_GB_CAMAB_SZE 32
217 #define SLIC_GB_CAMC_SZE 16
218 #define SLIC_GB_CAMD_SZE 16
219 #define SLIC_GB_CAMCD_SZE 32
222 * Coredump header structure
224 typedef struct _CORE_Q {
225 ulong32 queueOff; /* Offset of queue */
226 ulong32 queuesize; /* size of queue */
229 #define DRIVER_NAME_SIZE 32
231 typedef struct _sliccore_hdr_t {
232 uchar driver_version[DRIVER_NAME_SIZE]; /* Driver version string */
233 ulong32 RcvRegOff; /* Offset of receive registers */
234 ulong32 RcvRegsize; /* size of receive registers */
235 ulong32 XmtRegOff; /* Offset of transmit registers */
236 ulong32 XmtRegsize; /* size of transmit registers */
237 ulong32 FileRegOff; /* Offset of register file */
238 ulong32 FileRegsize; /* size of register file */
239 ulong32 SramOff; /* Offset of Sram */
240 ulong32 Sramsize; /* size of Sram */
241 ulong32 DramOff; /* Offset of Dram */
242 ulong32 Dramsize; /* size of Dram */
243 CORE_Q queues[SLIC_MAX_QUEUE]; /* size and offsets of queues */
244 ulong32 CamAMOff; /* Offset of CAM A contents */
245 ulong32 CamASize; /* Size of Cam A */
246 ulong32 CamBMOff; /* Offset of CAM B contents */
247 ulong32 CamBSize; /* Size of Cam B */
248 ulong32 CamCMOff; /* Offset of CAM C contents */
249 ulong32 CamCSize; /* Size of Cam C */
250 ulong32 CamDMOff; /* Offset of CAM D contents */
251 ulong32 CamDSize; /* Size of Cam D */
252 } sliccore_hdr_t, *p_sliccore_hdr_t;
255 * definitions needed for our kernel-mode gdb stub.
257 /***********************************************************************
259 * Definitions & Typedefs
261 **********************************************************************/
262 #define BUFMAX 0x20000 /* 128k - size of input/output buffer */
263 #define BUFMAXP2 5 /* 2**5 (32) 4K pages */
265 #define IOCTL_SIMBA_BREAK _IOW('s', 0, unsigned long)
266 /* #define IOCTL_SIMBA_INIT _IOW('s', 1, unsigned long) */
267 #define IOCTL_SIMBA_KILL_TGT_PROC _IOW('s', 2, unsigned long)
269 /***********************************************************************
273 ***********************************************************************/
275 #define THREADRECEIVE 1 /* bit 0 of StoppedThreads */
276 #define THREADTRANSMIT 2 /* bit 1 of StoppedThreads */
277 #define THREADBOTH 3 /* bit 0 and 1.. */
279 #endif /* _SLIC_DUMP_H */