1 /* linux/drivers/spi/spi_s3c24xx.c
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright (c) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/spinlock.h>
15 #include <linux/workqueue.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/platform_device.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spi/spi_bitbang.h>
28 #include <asm/hardware.h>
30 #include <asm/arch/regs-gpio.h>
31 #include <asm/plat-s3c24xx/regs-spi.h>
32 #include <asm/arch/spi.h>
35 /* bitbang has to be first */
36 struct spi_bitbang bitbang;
37 struct completion done;
44 void (*set_cs)(struct s3c2410_spi_info *spi,
48 const unsigned char *tx;
52 struct resource *ioarea;
53 struct spi_master *master;
54 struct spi_device *curdev;
56 struct s3c2410_spi_info *pdata;
59 #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
60 #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
62 static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
64 return spi_master_get_devdata(sdev->master);
67 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
69 s3c2410_gpio_setpin(spi->pin_cs, pol);
72 static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
74 struct s3c24xx_spi *hw = to_hw(spi);
75 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
79 case BITBANG_CS_INACTIVE:
80 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
83 case BITBANG_CS_ACTIVE:
84 spcon = readb(hw->regs + S3C2410_SPCON);
86 if (spi->mode & SPI_CPHA)
87 spcon |= S3C2410_SPCON_CPHA_FMTB;
89 spcon &= ~S3C2410_SPCON_CPHA_FMTB;
91 if (spi->mode & SPI_CPOL)
92 spcon |= S3C2410_SPCON_CPOL_HIGH;
94 spcon &= ~S3C2410_SPCON_CPOL_HIGH;
96 spcon |= S3C2410_SPCON_ENSCK;
98 /* write new configration */
100 writeb(spcon, hw->regs + S3C2410_SPCON);
101 hw->set_cs(hw->pdata, spi->chip_select, cspol);
107 static int s3c24xx_spi_setupxfer(struct spi_device *spi,
108 struct spi_transfer *t)
110 struct s3c24xx_spi *hw = to_hw(spi);
115 bpw = t ? t->bits_per_word : spi->bits_per_word;
116 hz = t ? t->speed_hz : spi->max_speed_hz;
119 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
123 div = clk_get_rate(hw->clk) / hz;
125 /* is clk = pclk / (2 * (pre+1)), or is it
126 * clk = (pclk * 2) / ( pre + 1) */
136 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
137 writeb(div, hw->regs + S3C2410_SPPRE);
139 spin_lock(&hw->bitbang.lock);
140 if (!hw->bitbang.busy) {
141 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
142 /* need to ndelay for 0.5 clocktick ? */
144 spin_unlock(&hw->bitbang.lock);
149 /* the spi->mode bits understood by this driver: */
150 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
152 static int s3c24xx_spi_setup(struct spi_device *spi)
156 if (!spi->bits_per_word)
157 spi->bits_per_word = 8;
159 if (spi->mode & ~MODEBITS) {
160 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
161 spi->mode & ~MODEBITS);
165 ret = s3c24xx_spi_setupxfer(spi, NULL);
167 dev_err(&spi->dev, "setupxfer returned %d\n", ret);
171 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n",
172 __func__, spi->mode, spi->bits_per_word,
178 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
180 return hw->tx ? hw->tx[count] : 0;
183 static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
185 struct s3c24xx_spi *hw = to_hw(spi);
187 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
188 t->tx_buf, t->rx_buf, t->len);
195 init_completion(&hw->done);
197 /* send the first byte */
198 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
200 wait_for_completion(&hw->done);
205 static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
207 struct s3c24xx_spi *hw = dev;
208 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
209 unsigned int count = hw->count;
211 if (spsta & S3C2410_SPSTA_DCOL) {
212 dev_dbg(hw->dev, "data-collision\n");
217 if (!(spsta & S3C2410_SPSTA_READY)) {
218 dev_dbg(hw->dev, "spi not ready for tx?\n");
226 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
231 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
239 static int __init s3c24xx_spi_probe(struct platform_device *pdev)
241 struct s3c2410_spi_info *pdata;
242 struct s3c24xx_spi *hw;
243 struct spi_master *master;
244 struct resource *res;
247 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
248 if (master == NULL) {
249 dev_err(&pdev->dev, "No memory for spi_master\n");
254 hw = spi_master_get_devdata(master);
255 memset(hw, 0, sizeof(struct s3c24xx_spi));
257 hw->master = spi_master_get(master);
258 hw->pdata = pdata = pdev->dev.platform_data;
259 hw->dev = &pdev->dev;
262 dev_err(&pdev->dev, "No platform data supplied\n");
267 platform_set_drvdata(pdev, hw);
268 init_completion(&hw->done);
270 /* setup the master state. */
272 master->num_chipselect = hw->pdata->num_cs;
273 master->bus_num = pdata->bus_num;
275 /* setup the state for the bitbang driver */
277 hw->bitbang.master = hw->master;
278 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
279 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
280 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
281 hw->bitbang.master->setup = s3c24xx_spi_setup;
283 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
285 /* find and map our resources */
287 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
289 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
294 hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
297 if (hw->ioarea == NULL) {
298 dev_err(&pdev->dev, "Cannot reserve region\n");
303 hw->regs = ioremap(res->start, (res->end - res->start)+1);
304 if (hw->regs == NULL) {
305 dev_err(&pdev->dev, "Cannot map IO\n");
310 hw->irq = platform_get_irq(pdev, 0);
312 dev_err(&pdev->dev, "No IRQ specified\n");
317 err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
319 dev_err(&pdev->dev, "Cannot claim IRQ\n");
323 hw->clk = clk_get(&pdev->dev, "spi");
324 if (IS_ERR(hw->clk)) {
325 dev_err(&pdev->dev, "No clock for device\n");
326 err = PTR_ERR(hw->clk);
330 /* for the moment, permanently enable the clock */
334 /* program defaults into the registers */
336 writeb(0xff, hw->regs + S3C2410_SPPRE);
337 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
338 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
340 /* setup any gpio we can */
342 if (!pdata->set_cs) {
343 hw->set_cs = s3c24xx_spi_gpiocs;
345 s3c2410_gpio_setpin(pdata->pin_cs, 1);
346 s3c2410_gpio_cfgpin(pdata->pin_cs, S3C2410_GPIO_OUTPUT);
348 hw->set_cs = pdata->set_cs;
350 /* register our spi controller */
352 err = spi_bitbang_start(&hw->bitbang);
354 dev_err(&pdev->dev, "Failed to register SPI master\n");
361 clk_disable(hw->clk);
365 free_irq(hw->irq, hw);
371 release_resource(hw->ioarea);
376 spi_master_put(hw->master);;
382 static int __exit s3c24xx_spi_remove(struct platform_device *dev)
384 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
386 platform_set_drvdata(dev, NULL);
388 spi_unregister_master(hw->master);
390 clk_disable(hw->clk);
393 free_irq(hw->irq, hw);
396 release_resource(hw->ioarea);
399 spi_master_put(hw->master);
406 static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
408 struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
410 clk_disable(hw->clk);
414 static int s3c24xx_spi_resume(struct platform_device *pdev)
416 struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
423 #define s3c24xx_spi_suspend NULL
424 #define s3c24xx_spi_resume NULL
427 MODULE_ALIAS("platform:s3c2410-spi");
428 static struct platform_driver s3c24xx_spidrv = {
429 .remove = __exit_p(s3c24xx_spi_remove),
430 .suspend = s3c24xx_spi_suspend,
431 .resume = s3c24xx_spi_resume,
433 .name = "s3c2410-spi",
434 .owner = THIS_MODULE,
438 static int __init s3c24xx_spi_init(void)
440 return platform_driver_probe(&s3c24xx_spidrv, s3c24xx_spi_probe);
443 static void __exit s3c24xx_spi_exit(void)
445 platform_driver_unregister(&s3c24xx_spidrv);
448 module_init(s3c24xx_spi_init);
449 module_exit(s3c24xx_spi_exit);
451 MODULE_DESCRIPTION("S3C24XX SPI Driver");
452 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
453 MODULE_LICENSE("GPL");