2 * MPC83xx SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/completion.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
20 #include <linux/irq.h>
21 #include <linux/device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/spi_bitbang.h>
24 #include <linux/platform_device.h>
25 #include <linux/fsl_devices.h>
30 /* SPI Controller registers */
31 struct mpc83xx_spi_reg {
41 /* SPI Controller mode register definitions */
42 #define SPMODE_LOOP (1 << 30)
43 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
44 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
45 #define SPMODE_DIV16 (1 << 27)
46 #define SPMODE_REV (1 << 26)
47 #define SPMODE_MS (1 << 25)
48 #define SPMODE_ENABLE (1 << 24)
49 #define SPMODE_LEN(x) ((x) << 20)
50 #define SPMODE_PM(x) ((x) << 16)
51 #define SPMODE_OP (1 << 14)
52 #define SPMODE_CG(x) ((x) << 7)
55 * Default for SPI Mode:
56 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
58 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
59 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
61 /* SPIE register values */
62 #define SPIE_NE 0x00000200 /* Not empty */
63 #define SPIE_NF 0x00000100 /* Not full */
65 /* SPIM register values */
66 #define SPIM_NE 0x00000200 /* Not empty */
67 #define SPIM_NF 0x00000100 /* Not full */
69 /* SPI Controller driver's private data. */
71 struct mpc83xx_spi_reg __iomem *base;
73 /* rx & tx bufs from the spi_transfer */
77 /* functions to deal with different sized buffers */
78 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
79 u32(*get_tx) (struct mpc83xx_spi *);
84 unsigned nsecs; /* (clock cycle time)/2 */
86 u32 spibrg; /* SPIBRG input clock */
87 u32 rx_shift; /* RX data reg shift when in qe mode */
88 u32 tx_shift; /* TX data reg shift when in qe mode */
94 struct workqueue_struct *workqueue;
95 struct work_struct work;
97 struct list_head queue;
100 struct completion done;
103 struct spi_mpc83xx_cs {
104 /* functions to deal with different sized buffers */
105 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
106 u32 (*get_tx) (struct mpc83xx_spi *);
107 u32 rx_shift; /* RX data reg shift when in qe mode */
108 u32 tx_shift; /* TX data reg shift when in qe mode */
109 u32 hw_mode; /* Holds HW mode register settings */
112 static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
117 static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
122 #define MPC83XX_SPI_RX_BUF(type) \
124 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
126 type * rx = mpc83xx_spi->rx; \
127 *rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
128 mpc83xx_spi->rx = rx; \
131 #define MPC83XX_SPI_TX_BUF(type) \
133 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
136 const type * tx = mpc83xx_spi->tx; \
139 data = *tx++ << mpc83xx_spi->tx_shift; \
140 mpc83xx_spi->tx = tx; \
144 MPC83XX_SPI_RX_BUF(u8)
145 MPC83XX_SPI_RX_BUF(u16)
146 MPC83XX_SPI_RX_BUF(u32)
147 MPC83XX_SPI_TX_BUF(u8)
148 MPC83XX_SPI_TX_BUF(u16)
149 MPC83XX_SPI_TX_BUF(u32)
151 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
153 struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
154 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
155 bool pol = spi->mode & SPI_CS_HIGH;
156 struct spi_mpc83xx_cs *cs = spi->controller_state;
158 if (value == BITBANG_CS_INACTIVE) {
159 if (pdata->cs_control)
160 pdata->cs_control(spi, !pol);
163 if (value == BITBANG_CS_ACTIVE) {
164 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
166 mpc83xx_spi->rx_shift = cs->rx_shift;
167 mpc83xx_spi->tx_shift = cs->tx_shift;
168 mpc83xx_spi->get_rx = cs->get_rx;
169 mpc83xx_spi->get_tx = cs->get_tx;
171 if (cs->hw_mode != regval) {
173 __be32 __iomem *mode = &mpc83xx_spi->base->mode;
175 regval = cs->hw_mode;
176 /* Turn off IRQs locally to minimize time that
179 local_irq_save(flags);
180 /* Turn off SPI unit prior changing mode */
181 mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
182 mpc83xx_spi_write_reg(mode, regval);
183 local_irq_restore(flags);
185 if (pdata->cs_control)
186 pdata->cs_control(spi, pol);
191 int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
193 struct mpc83xx_spi *mpc83xx_spi;
195 u8 bits_per_word, pm;
197 struct spi_mpc83xx_cs *cs = spi->controller_state;
199 mpc83xx_spi = spi_master_get_devdata(spi->master);
202 bits_per_word = t->bits_per_word;
209 /* spi_transfer level calls that work per-word */
211 bits_per_word = spi->bits_per_word;
213 /* Make sure its a bit width we support [4..16, 32] */
214 if ((bits_per_word < 4)
215 || ((bits_per_word > 16) && (bits_per_word != 32)))
219 hz = spi->max_speed_hz;
223 if (bits_per_word <= 8) {
224 cs->get_rx = mpc83xx_spi_rx_buf_u8;
225 cs->get_tx = mpc83xx_spi_tx_buf_u8;
226 if (mpc83xx_spi->qe_mode) {
230 } else if (bits_per_word <= 16) {
231 cs->get_rx = mpc83xx_spi_rx_buf_u16;
232 cs->get_tx = mpc83xx_spi_tx_buf_u16;
233 if (mpc83xx_spi->qe_mode) {
237 } else if (bits_per_word <= 32) {
238 cs->get_rx = mpc83xx_spi_rx_buf_u32;
239 cs->get_tx = mpc83xx_spi_tx_buf_u32;
243 if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
245 if (bits_per_word <= 8)
251 mpc83xx_spi->rx_shift = cs->rx_shift;
252 mpc83xx_spi->tx_shift = cs->tx_shift;
253 mpc83xx_spi->get_rx = cs->get_rx;
254 mpc83xx_spi->get_tx = cs->get_tx;
256 if (bits_per_word == 32)
259 bits_per_word = bits_per_word - 1;
261 /* mask out bits we are going to set */
262 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
265 cs->hw_mode |= SPMODE_LEN(bits_per_word);
267 if ((mpc83xx_spi->spibrg / hz) > 64) {
268 cs->hw_mode |= SPMODE_DIV16;
269 pm = mpc83xx_spi->spibrg / (hz * 64);
271 dev_err(&spi->dev, "Requested speed is too "
272 "low: %d Hz. Will use %d Hz instead.\n",
273 hz, mpc83xx_spi->spibrg / 1024);
277 pm = mpc83xx_spi->spibrg / (hz * 4);
281 cs->hw_mode |= SPMODE_PM(pm);
282 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
283 if (cs->hw_mode != regval) {
285 __be32 __iomem *mode = &mpc83xx_spi->base->mode;
287 regval = cs->hw_mode;
288 /* Turn off IRQs locally to minimize time
289 * that SPI is disabled
291 local_irq_save(flags);
292 /* Turn off SPI unit prior changing mode */
293 mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
294 mpc83xx_spi_write_reg(mode, regval);
295 local_irq_restore(flags);
300 static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
302 struct mpc83xx_spi *mpc83xx_spi;
303 u32 word, len, bits_per_word;
305 mpc83xx_spi = spi_master_get_devdata(spi->master);
307 mpc83xx_spi->tx = t->tx_buf;
308 mpc83xx_spi->rx = t->rx_buf;
309 bits_per_word = spi->bits_per_word;
310 if (t->bits_per_word)
311 bits_per_word = t->bits_per_word;
313 if (bits_per_word > 8) {
314 /* invalid length? */
319 if (bits_per_word > 16) {
320 /* invalid length? */
325 mpc83xx_spi->count = len;
327 INIT_COMPLETION(mpc83xx_spi->done);
330 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
333 word = mpc83xx_spi->get_tx(mpc83xx_spi);
334 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
336 wait_for_completion(&mpc83xx_spi->done);
338 /* disable rx ints */
339 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
341 return mpc83xx_spi->count;
344 static void mpc83xx_spi_work(struct work_struct *work)
346 struct mpc83xx_spi *mpc83xx_spi =
347 container_of(work, struct mpc83xx_spi, work);
349 spin_lock_irq(&mpc83xx_spi->lock);
350 mpc83xx_spi->busy = 1;
351 while (!list_empty(&mpc83xx_spi->queue)) {
352 struct spi_message *m;
353 struct spi_device *spi;
354 struct spi_transfer *t = NULL;
356 int status, nsecs = 50;
358 m = container_of(mpc83xx_spi->queue.next,
359 struct spi_message, queue);
360 list_del_init(&m->queue);
361 spin_unlock_irq(&mpc83xx_spi->lock);
366 list_for_each_entry(t, &m->transfers, transfer_list) {
367 if (t->bits_per_word || t->speed_hz) {
368 /* Don't allow changes if CS is active */
372 status = mpc83xx_spi_setup_transfer(spi, t);
378 mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
379 cs_change = t->cs_change;
381 status = mpc83xx_spi_bufs(spi, t);
386 m->actual_length += t->len;
389 udelay(t->delay_usecs);
393 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
399 m->complete(m->context);
401 if (status || !cs_change) {
403 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
406 mpc83xx_spi_setup_transfer(spi, NULL);
408 spin_lock_irq(&mpc83xx_spi->lock);
410 mpc83xx_spi->busy = 0;
411 spin_unlock_irq(&mpc83xx_spi->lock);
414 /* the spi->mode bits understood by this driver: */
415 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
416 | SPI_LSB_FIRST | SPI_LOOP)
418 static int mpc83xx_spi_setup(struct spi_device *spi)
420 struct mpc83xx_spi *mpc83xx_spi;
423 struct spi_mpc83xx_cs *cs = spi->controller_state;
425 if (spi->mode & ~MODEBITS) {
426 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
427 spi->mode & ~MODEBITS);
431 if (!spi->max_speed_hz)
435 cs = kzalloc(sizeof *cs, GFP_KERNEL);
438 spi->controller_state = cs;
440 mpc83xx_spi = spi_master_get_devdata(spi->master);
442 if (!spi->bits_per_word)
443 spi->bits_per_word = 8;
445 hw_mode = cs->hw_mode; /* Save orginal settings */
446 cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
447 /* mask out bits we are going to set */
448 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
449 | SPMODE_REV | SPMODE_LOOP);
451 if (spi->mode & SPI_CPHA)
452 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
453 if (spi->mode & SPI_CPOL)
454 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
455 if (!(spi->mode & SPI_LSB_FIRST))
456 cs->hw_mode |= SPMODE_REV;
457 if (spi->mode & SPI_LOOP)
458 cs->hw_mode |= SPMODE_LOOP;
460 retval = mpc83xx_spi_setup_transfer(spi, NULL);
462 cs->hw_mode = hw_mode; /* Restore settings */
466 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n",
467 __func__, spi->mode & (SPI_CPOL | SPI_CPHA),
468 spi->bits_per_word, spi->max_speed_hz);
469 #if 0 /* Don't think this is needed */
470 /* NOTE we _need_ to call chipselect() early, ideally with adapter
471 * setup, unless the hardware defaults cooperate to avoid confusion
472 * between normal (active low) and inverted chipselects.
475 /* deselect chip (low or high) */
476 spin_lock(&mpc83xx_spi->lock);
477 if (!mpc83xx_spi->busy)
478 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
479 spin_unlock(&mpc83xx_spi->lock);
484 static irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
486 struct mpc83xx_spi *mpc83xx_spi = context_data;
488 irqreturn_t ret = IRQ_NONE;
490 /* Get interrupt events(tx/rx) */
491 event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
493 /* We need handle RX first */
494 if (event & SPIE_NE) {
495 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
498 mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
503 if ((event & SPIE_NF) == 0)
504 /* spin until TX is done */
506 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
510 mpc83xx_spi->count -= 1;
511 if (mpc83xx_spi->count) {
512 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
513 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
515 complete(&mpc83xx_spi->done);
518 /* Clear the events */
519 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
523 static int mpc83xx_spi_transfer(struct spi_device *spi,
524 struct spi_message *m)
526 struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
529 m->actual_length = 0;
530 m->status = -EINPROGRESS;
532 spin_lock_irqsave(&mpc83xx_spi->lock, flags);
533 list_add_tail(&m->queue, &mpc83xx_spi->queue);
534 queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
535 spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
541 static void mpc83xx_spi_cleanup(struct spi_device *spi)
543 kfree(spi->controller_state);
546 static int __init mpc83xx_spi_probe(struct platform_device *dev)
548 struct spi_master *master;
549 struct mpc83xx_spi *mpc83xx_spi;
550 struct fsl_spi_platform_data *pdata;
555 /* Get resources(memory, IRQ) associated with the device */
556 master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
558 if (master == NULL) {
563 platform_set_drvdata(dev, master);
564 pdata = dev->dev.platform_data;
571 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
576 master->setup = mpc83xx_spi_setup;
577 master->transfer = mpc83xx_spi_transfer;
578 master->cleanup = mpc83xx_spi_cleanup;
580 mpc83xx_spi = spi_master_get_devdata(master);
581 mpc83xx_spi->qe_mode = pdata->qe_mode;
582 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
583 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
584 mpc83xx_spi->spibrg = pdata->sysclk;
586 mpc83xx_spi->rx_shift = 0;
587 mpc83xx_spi->tx_shift = 0;
588 if (mpc83xx_spi->qe_mode) {
589 mpc83xx_spi->rx_shift = 16;
590 mpc83xx_spi->tx_shift = 24;
593 init_completion(&mpc83xx_spi->done);
595 mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
596 if (mpc83xx_spi->base == NULL) {
601 mpc83xx_spi->irq = platform_get_irq(dev, 0);
603 if (mpc83xx_spi->irq < 0) {
608 /* Register for SPI Interrupt */
609 ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
610 0, "mpc83xx_spi", mpc83xx_spi);
615 master->bus_num = pdata->bus_num;
616 master->num_chipselect = pdata->max_chipselect;
618 /* SPI controller initializations */
619 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
620 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
621 mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
622 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
624 /* Enable SPI interface */
625 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
629 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
630 spin_lock_init(&mpc83xx_spi->lock);
631 init_completion(&mpc83xx_spi->done);
632 INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
633 INIT_LIST_HEAD(&mpc83xx_spi->queue);
635 mpc83xx_spi->workqueue = create_singlethread_workqueue(
636 dev_name(master->dev.parent));
637 if (mpc83xx_spi->workqueue == NULL) {
642 ret = spi_register_master(master);
647 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
648 dev_name(&dev->dev), mpc83xx_spi->base, mpc83xx_spi->irq);
653 destroy_workqueue(mpc83xx_spi->workqueue);
655 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
657 iounmap(mpc83xx_spi->base);
659 spi_master_put(master);
666 static int __exit mpc83xx_spi_remove(struct platform_device *dev)
668 struct mpc83xx_spi *mpc83xx_spi;
669 struct spi_master *master;
671 master = platform_get_drvdata(dev);
672 mpc83xx_spi = spi_master_get_devdata(master);
674 flush_workqueue(mpc83xx_spi->workqueue);
675 destroy_workqueue(mpc83xx_spi->workqueue);
676 spi_unregister_master(master);
678 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
679 iounmap(mpc83xx_spi->base);
684 MODULE_ALIAS("platform:mpc83xx_spi");
685 static struct platform_driver mpc83xx_spi_driver = {
686 .remove = __exit_p(mpc83xx_spi_remove),
688 .name = "mpc83xx_spi",
689 .owner = THIS_MODULE,
693 static int __init mpc83xx_spi_init(void)
695 return platform_driver_probe(&mpc83xx_spi_driver, mpc83xx_spi_probe);
698 static void __exit mpc83xx_spi_exit(void)
700 platform_driver_unregister(&mpc83xx_spi_driver);
703 module_init(mpc83xx_spi_init);
704 module_exit(mpc83xx_spi_exit);
706 MODULE_AUTHOR("Kumar Gala");
707 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
708 MODULE_LICENSE("GPL");