2 * File: drivers/spi/bfin5xx_spi.c
4 * Bryan Wu <bryan.wu@analog.com>
6 * Luke Yang (Analog Devices Inc.)
8 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
16 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
19 * Copyright 2004-2007 Analog Devices Inc.
21 * This program is free software ; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation ; either version 2, or (at your option)
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program ; see the file COPYING.
33 * If not, write to the Free Software Foundation,
34 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
37 #include <linux/init.h>
38 #include <linux/module.h>
39 #include <linux/delay.h>
40 #include <linux/device.h>
42 #include <linux/ioport.h>
43 #include <linux/irq.h>
44 #include <linux/errno.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/spi/spi.h>
49 #include <linux/workqueue.h>
52 #include <asm/portmux.h>
53 #include <asm/bfin5xx_spi.h>
55 #define DRV_NAME "bfin-spi"
56 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
57 #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
58 #define DRV_VERSION "1.0"
60 MODULE_AUTHOR(DRV_AUTHOR);
61 MODULE_DESCRIPTION(DRV_DESC);
62 MODULE_LICENSE("GPL");
64 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
66 #define START_STATE ((void *)0)
67 #define RUNNING_STATE ((void *)1)
68 #define DONE_STATE ((void *)2)
69 #define ERROR_STATE ((void *)-1)
70 #define QUEUE_RUNNING 0
71 #define QUEUE_STOPPED 1
74 /* Driver model hookup */
75 struct platform_device *pdev;
77 /* SPI framework hookup */
78 struct spi_master *master;
80 /* Regs base of SPI controller */
81 void __iomem *regs_base;
83 /* Pin request list */
87 struct bfin5xx_spi_master *master_info;
89 /* Driver message queue */
90 struct workqueue_struct *workqueue;
91 struct work_struct pump_messages;
93 struct list_head queue;
97 /* Message Transfer pump */
98 struct tasklet_struct pump_transfers;
100 /* Current message transfer state info */
101 struct spi_message *cur_msg;
102 struct spi_transfer *cur_transfer;
103 struct chip_data *cur_chip;
122 void (*write) (struct driver_data *);
123 void (*read) (struct driver_data *);
124 void (*duplex) (struct driver_data *);
134 u8 width; /* 0 or 1 */
136 u8 bits_per_word; /* 8 or 16 */
137 u8 cs_change_per_word;
138 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
139 void (*write) (struct driver_data *);
140 void (*read) (struct driver_data *);
141 void (*duplex) (struct driver_data *);
144 #define DEFINE_SPI_REG(reg, off) \
145 static inline u16 read_##reg(struct driver_data *drv_data) \
146 { return bfin_read16(drv_data->regs_base + off); } \
147 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
148 { bfin_write16(drv_data->regs_base + off, v); }
150 DEFINE_SPI_REG(CTRL, 0x00)
151 DEFINE_SPI_REG(FLAG, 0x04)
152 DEFINE_SPI_REG(STAT, 0x08)
153 DEFINE_SPI_REG(TDBR, 0x0C)
154 DEFINE_SPI_REG(RDBR, 0x10)
155 DEFINE_SPI_REG(BAUD, 0x14)
156 DEFINE_SPI_REG(SHAW, 0x18)
158 static void bfin_spi_enable(struct driver_data *drv_data)
162 cr = read_CTRL(drv_data);
163 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
166 static void bfin_spi_disable(struct driver_data *drv_data)
170 cr = read_CTRL(drv_data);
171 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
174 /* Caculate the SPI_BAUD register value based on input HZ */
175 static u16 hz_to_spi_baud(u32 speed_hz)
177 u_long sclk = get_sclk();
178 u16 spi_baud = (sclk / (2 * speed_hz));
180 if ((sclk % (2 * speed_hz)) > 0)
186 static int flush(struct driver_data *drv_data)
188 unsigned long limit = loops_per_jiffy << 1;
190 /* wait for stop and clear stat */
191 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
194 write_STAT(drv_data, BIT_STAT_CLR);
199 /* Chip select operation functions for cs_change flag */
200 static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
202 u16 flag = read_FLAG(drv_data);
205 flag &= ~(chip->flag << 8);
207 write_FLAG(drv_data, flag);
210 static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
212 u16 flag = read_FLAG(drv_data);
214 flag |= (chip->flag << 8);
216 write_FLAG(drv_data, flag);
218 /* Move delay here for consistency */
219 if (chip->cs_chg_udelay)
220 udelay(chip->cs_chg_udelay);
223 #define MAX_SPI_SSEL 7
225 /* stop controller and re-config current chip*/
226 static void restore_state(struct driver_data *drv_data)
228 struct chip_data *chip = drv_data->cur_chip;
230 /* Clear status and disable clock */
231 write_STAT(drv_data, BIT_STAT_CLR);
232 bfin_spi_disable(drv_data);
233 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
235 /* Load the registers */
236 write_CTRL(drv_data, chip->ctl_reg);
237 write_BAUD(drv_data, chip->baud);
239 bfin_spi_enable(drv_data);
240 cs_active(drv_data, chip);
243 /* used to kick off transfer in rx mode */
244 static unsigned short dummy_read(struct driver_data *drv_data)
247 tmp = read_RDBR(drv_data);
251 static void null_writer(struct driver_data *drv_data)
253 u8 n_bytes = drv_data->n_bytes;
255 while (drv_data->tx < drv_data->tx_end) {
256 write_TDBR(drv_data, 0);
257 while ((read_STAT(drv_data) & BIT_STAT_TXS))
259 drv_data->tx += n_bytes;
263 static void null_reader(struct driver_data *drv_data)
265 u8 n_bytes = drv_data->n_bytes;
266 dummy_read(drv_data);
268 while (drv_data->rx < drv_data->rx_end) {
269 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
271 dummy_read(drv_data);
272 drv_data->rx += n_bytes;
276 static void u8_writer(struct driver_data *drv_data)
278 dev_dbg(&drv_data->pdev->dev,
279 "cr8-s is 0x%x\n", read_STAT(drv_data));
281 /* poll for SPI completion before start */
282 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
285 while (drv_data->tx < drv_data->tx_end) {
286 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
287 while (read_STAT(drv_data) & BIT_STAT_TXS)
293 static void u8_cs_chg_writer(struct driver_data *drv_data)
295 struct chip_data *chip = drv_data->cur_chip;
297 while (drv_data->tx < drv_data->tx_end) {
298 cs_active(drv_data, chip);
300 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
301 while (read_STAT(drv_data) & BIT_STAT_TXS)
303 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
306 cs_deactive(drv_data, chip);
312 static void u8_reader(struct driver_data *drv_data)
314 dev_dbg(&drv_data->pdev->dev,
315 "cr-8 is 0x%x\n", read_STAT(drv_data));
317 /* poll for SPI completion before start */
318 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
321 /* clear TDBR buffer before read(else it will be shifted out) */
322 write_TDBR(drv_data, 0xFFFF);
324 dummy_read(drv_data);
326 while (drv_data->rx < drv_data->rx_end - 1) {
327 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
329 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
333 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
335 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
339 static void u8_cs_chg_reader(struct driver_data *drv_data)
341 struct chip_data *chip = drv_data->cur_chip;
343 while (drv_data->rx < drv_data->rx_end) {
344 cs_active(drv_data, chip);
345 read_RDBR(drv_data); /* kick off */
347 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
349 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
352 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
353 cs_deactive(drv_data, chip);
359 static void u8_duplex(struct driver_data *drv_data)
361 /* poll for SPI completion before start */
362 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
365 /* in duplex mode, clk is triggered by writing of TDBR */
366 while (drv_data->rx < drv_data->rx_end) {
367 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
368 while (read_STAT(drv_data) & BIT_STAT_TXS)
370 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
372 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
378 static void u8_cs_chg_duplex(struct driver_data *drv_data)
380 struct chip_data *chip = drv_data->cur_chip;
382 while (drv_data->rx < drv_data->rx_end) {
383 cs_active(drv_data, chip);
385 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
387 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
389 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
391 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
393 cs_deactive(drv_data, chip);
400 static void u16_writer(struct driver_data *drv_data)
402 dev_dbg(&drv_data->pdev->dev,
403 "cr16 is 0x%x\n", read_STAT(drv_data));
405 /* poll for SPI completion before start */
406 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
409 while (drv_data->tx < drv_data->tx_end) {
410 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
411 while ((read_STAT(drv_data) & BIT_STAT_TXS))
417 static void u16_cs_chg_writer(struct driver_data *drv_data)
419 struct chip_data *chip = drv_data->cur_chip;
421 /* poll for SPI completion before start */
422 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
425 while (drv_data->tx < drv_data->tx_end) {
426 cs_active(drv_data, chip);
428 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
429 while ((read_STAT(drv_data) & BIT_STAT_TXS))
432 cs_deactive(drv_data, chip);
438 static void u16_reader(struct driver_data *drv_data)
440 dev_dbg(&drv_data->pdev->dev,
441 "cr-16 is 0x%x\n", read_STAT(drv_data));
443 /* poll for SPI completion before start */
444 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
447 /* clear TDBR buffer before read(else it will be shifted out) */
448 write_TDBR(drv_data, 0xFFFF);
450 dummy_read(drv_data);
452 while (drv_data->rx < (drv_data->rx_end - 2)) {
453 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
455 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
459 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
461 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
465 static void u16_cs_chg_reader(struct driver_data *drv_data)
467 struct chip_data *chip = drv_data->cur_chip;
469 /* poll for SPI completion before start */
470 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
473 /* clear TDBR buffer before read(else it will be shifted out) */
474 write_TDBR(drv_data, 0xFFFF);
476 cs_active(drv_data, chip);
477 dummy_read(drv_data);
479 while (drv_data->rx < drv_data->rx_end - 2) {
480 cs_deactive(drv_data, chip);
482 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
484 cs_active(drv_data, chip);
485 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
488 cs_deactive(drv_data, chip);
490 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
492 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
496 static void u16_duplex(struct driver_data *drv_data)
498 /* poll for SPI completion before start */
499 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
502 /* in duplex mode, clk is triggered by writing of TDBR */
503 while (drv_data->tx < drv_data->tx_end) {
504 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
505 while (read_STAT(drv_data) & BIT_STAT_TXS)
507 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
509 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
515 static void u16_cs_chg_duplex(struct driver_data *drv_data)
517 struct chip_data *chip = drv_data->cur_chip;
519 /* poll for SPI completion before start */
520 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
523 while (drv_data->tx < drv_data->tx_end) {
524 cs_active(drv_data, chip);
526 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
527 while (read_STAT(drv_data) & BIT_STAT_TXS)
529 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
531 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
533 cs_deactive(drv_data, chip);
540 /* test if ther is more transfer to be done */
541 static void *next_transfer(struct driver_data *drv_data)
543 struct spi_message *msg = drv_data->cur_msg;
544 struct spi_transfer *trans = drv_data->cur_transfer;
546 /* Move to next transfer */
547 if (trans->transfer_list.next != &msg->transfers) {
548 drv_data->cur_transfer =
549 list_entry(trans->transfer_list.next,
550 struct spi_transfer, transfer_list);
551 return RUNNING_STATE;
557 * caller already set message->status;
558 * dma and pio irqs are blocked give finished message back
560 static void giveback(struct driver_data *drv_data)
562 struct chip_data *chip = drv_data->cur_chip;
563 struct spi_transfer *last_transfer;
565 struct spi_message *msg;
567 spin_lock_irqsave(&drv_data->lock, flags);
568 msg = drv_data->cur_msg;
569 drv_data->cur_msg = NULL;
570 drv_data->cur_transfer = NULL;
571 drv_data->cur_chip = NULL;
572 queue_work(drv_data->workqueue, &drv_data->pump_messages);
573 spin_unlock_irqrestore(&drv_data->lock, flags);
575 last_transfer = list_entry(msg->transfers.prev,
576 struct spi_transfer, transfer_list);
580 /* disable chip select signal. And not stop spi in autobuffer mode */
581 if (drv_data->tx_dma != 0xFFFF) {
582 cs_deactive(drv_data, chip);
583 bfin_spi_disable(drv_data);
586 if (!drv_data->cs_change)
587 cs_deactive(drv_data, chip);
590 msg->complete(msg->context);
593 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
595 struct driver_data *drv_data = dev_id;
596 struct chip_data *chip = drv_data->cur_chip;
597 struct spi_message *msg = drv_data->cur_msg;
599 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
600 clear_dma_irqstat(drv_data->dma_channel);
602 /* Wait for DMA to complete */
603 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
607 * wait for the last transaction shifted out. HRM states:
608 * at this point there may still be data in the SPI DMA FIFO waiting
609 * to be transmitted ... software needs to poll TXS in the SPI_STAT
610 * register until it goes low for 2 successive reads
612 if (drv_data->tx != NULL) {
613 while ((read_STAT(drv_data) & TXS) ||
614 (read_STAT(drv_data) & TXS))
618 while (!(read_STAT(drv_data) & SPIF))
621 msg->actual_length += drv_data->len_in_bytes;
623 if (drv_data->cs_change)
624 cs_deactive(drv_data, chip);
626 /* Move to next transfer */
627 msg->state = next_transfer(drv_data);
629 /* Schedule transfer tasklet */
630 tasklet_schedule(&drv_data->pump_transfers);
632 /* free the irq handler before next transfer */
633 dev_dbg(&drv_data->pdev->dev,
634 "disable dma channel irq%d\n",
635 drv_data->dma_channel);
636 dma_disable_irq(drv_data->dma_channel);
641 static void pump_transfers(unsigned long data)
643 struct driver_data *drv_data = (struct driver_data *)data;
644 struct spi_message *message = NULL;
645 struct spi_transfer *transfer = NULL;
646 struct spi_transfer *previous = NULL;
647 struct chip_data *chip = NULL;
649 u16 cr, dma_width, dma_config;
650 u32 tranf_success = 1;
652 /* Get current state information */
653 message = drv_data->cur_msg;
654 transfer = drv_data->cur_transfer;
655 chip = drv_data->cur_chip;
658 * if msg is error or done, report it back using complete() callback
661 /* Handle for abort */
662 if (message->state == ERROR_STATE) {
663 message->status = -EIO;
668 /* Handle end of message */
669 if (message->state == DONE_STATE) {
675 /* Delay if requested at end of transfer */
676 if (message->state == RUNNING_STATE) {
677 previous = list_entry(transfer->transfer_list.prev,
678 struct spi_transfer, transfer_list);
679 if (previous->delay_usecs)
680 udelay(previous->delay_usecs);
683 /* Setup the transfer state based on the type of transfer */
684 if (flush(drv_data) == 0) {
685 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
686 message->status = -EIO;
691 if (transfer->tx_buf != NULL) {
692 drv_data->tx = (void *)transfer->tx_buf;
693 drv_data->tx_end = drv_data->tx + transfer->len;
694 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
695 transfer->tx_buf, drv_data->tx_end);
700 if (transfer->rx_buf != NULL) {
701 drv_data->rx = transfer->rx_buf;
702 drv_data->rx_end = drv_data->rx + transfer->len;
703 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
704 transfer->rx_buf, drv_data->rx_end);
709 drv_data->rx_dma = transfer->rx_dma;
710 drv_data->tx_dma = transfer->tx_dma;
711 drv_data->len_in_bytes = transfer->len;
712 drv_data->cs_change = transfer->cs_change;
714 /* Bits per word setup */
715 switch (transfer->bits_per_word) {
717 drv_data->n_bytes = 1;
718 width = CFG_SPI_WORDSIZE8;
719 drv_data->read = chip->cs_change_per_word ?
720 u8_cs_chg_reader : u8_reader;
721 drv_data->write = chip->cs_change_per_word ?
722 u8_cs_chg_writer : u8_writer;
723 drv_data->duplex = chip->cs_change_per_word ?
724 u8_cs_chg_duplex : u8_duplex;
728 drv_data->n_bytes = 2;
729 width = CFG_SPI_WORDSIZE16;
730 drv_data->read = chip->cs_change_per_word ?
731 u16_cs_chg_reader : u16_reader;
732 drv_data->write = chip->cs_change_per_word ?
733 u16_cs_chg_writer : u16_writer;
734 drv_data->duplex = chip->cs_change_per_word ?
735 u16_cs_chg_duplex : u16_duplex;
739 /* No change, the same as default setting */
740 drv_data->n_bytes = chip->n_bytes;
742 drv_data->write = drv_data->tx ? chip->write : null_writer;
743 drv_data->read = drv_data->rx ? chip->read : null_reader;
744 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
747 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
749 write_CTRL(drv_data, cr);
751 if (width == CFG_SPI_WORDSIZE16) {
752 drv_data->len = (transfer->len) >> 1;
754 drv_data->len = transfer->len;
756 dev_dbg(&drv_data->pdev->dev, "transfer: ",
757 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
758 drv_data->write, chip->write, null_writer);
760 /* speed and width has been set on per message */
761 message->state = RUNNING_STATE;
764 /* Speed setup (surely valid because already checked) */
765 if (transfer->speed_hz)
766 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
768 write_BAUD(drv_data, chip->baud);
770 write_STAT(drv_data, BIT_STAT_CLR);
771 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
772 cs_active(drv_data, chip);
774 dev_dbg(&drv_data->pdev->dev,
775 "now pumping a transfer: width is %d, len is %d\n",
776 width, transfer->len);
779 * Try to map dma buffer and do a dma transfer if
780 * successful use different way to r/w according to
781 * drv_data->cur_chip->enable_dma
783 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
785 disable_dma(drv_data->dma_channel);
786 clear_dma_irqstat(drv_data->dma_channel);
787 bfin_spi_disable(drv_data);
789 /* config dma channel */
790 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
791 if (width == CFG_SPI_WORDSIZE16) {
792 set_dma_x_count(drv_data->dma_channel, drv_data->len);
793 set_dma_x_modify(drv_data->dma_channel, 2);
794 dma_width = WDSIZE_16;
796 set_dma_x_count(drv_data->dma_channel, drv_data->len);
797 set_dma_x_modify(drv_data->dma_channel, 1);
798 dma_width = WDSIZE_8;
801 /* poll for SPI completion before start */
802 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
805 /* dirty hack for autobuffer DMA mode */
806 if (drv_data->tx_dma == 0xFFFF) {
807 dev_dbg(&drv_data->pdev->dev,
808 "doing autobuffer DMA out.\n");
810 /* no irq in autobuffer mode */
812 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
813 set_dma_config(drv_data->dma_channel, dma_config);
814 set_dma_start_addr(drv_data->dma_channel,
815 (unsigned long)drv_data->tx);
816 enable_dma(drv_data->dma_channel);
818 /* start SPI transfer */
820 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
822 /* just return here, there can only be one transfer
830 /* In dma mode, rx or tx must be NULL in one transfer */
831 if (drv_data->rx != NULL) {
832 /* set transfer mode, and enable SPI */
833 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
835 /* clear tx reg soformer data is not shifted out */
836 write_TDBR(drv_data, 0xFFFF);
838 set_dma_x_count(drv_data->dma_channel, drv_data->len);
841 dma_enable_irq(drv_data->dma_channel);
842 dma_config = (WNR | RESTART | dma_width | DI_EN);
843 set_dma_config(drv_data->dma_channel, dma_config);
844 set_dma_start_addr(drv_data->dma_channel,
845 (unsigned long)drv_data->rx);
846 enable_dma(drv_data->dma_channel);
848 /* start SPI transfer */
850 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
852 } else if (drv_data->tx != NULL) {
853 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
856 dma_enable_irq(drv_data->dma_channel);
857 dma_config = (RESTART | dma_width | DI_EN);
858 set_dma_config(drv_data->dma_channel, dma_config);
859 set_dma_start_addr(drv_data->dma_channel,
860 (unsigned long)drv_data->tx);
861 enable_dma(drv_data->dma_channel);
863 /* start SPI transfer */
865 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
868 /* IO mode write then read */
869 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
871 if (drv_data->tx != NULL && drv_data->rx != NULL) {
872 /* full duplex mode */
873 BUG_ON((drv_data->tx_end - drv_data->tx) !=
874 (drv_data->rx_end - drv_data->rx));
875 dev_dbg(&drv_data->pdev->dev,
876 "IO duplex: cr is 0x%x\n", cr);
878 /* set SPI transfer mode */
879 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
881 drv_data->duplex(drv_data);
883 if (drv_data->tx != drv_data->tx_end)
885 } else if (drv_data->tx != NULL) {
886 /* write only half duplex */
887 dev_dbg(&drv_data->pdev->dev,
888 "IO write: cr is 0x%x\n", cr);
890 /* set SPI transfer mode */
891 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
893 drv_data->write(drv_data);
895 if (drv_data->tx != drv_data->tx_end)
897 } else if (drv_data->rx != NULL) {
898 /* read only half duplex */
899 dev_dbg(&drv_data->pdev->dev,
900 "IO read: cr is 0x%x\n", cr);
902 /* set SPI transfer mode */
903 write_CTRL(drv_data, (cr | CFG_SPI_READ));
905 drv_data->read(drv_data);
906 if (drv_data->rx != drv_data->rx_end)
910 if (!tranf_success) {
911 dev_dbg(&drv_data->pdev->dev,
912 "IO write error!\n");
913 message->state = ERROR_STATE;
915 /* Update total byte transfered */
916 message->actual_length += drv_data->len;
918 /* Move to next transfer of this msg */
919 message->state = next_transfer(drv_data);
922 /* Schedule next transfer tasklet */
923 tasklet_schedule(&drv_data->pump_transfers);
928 /* pop a msg from queue and kick off real transfer */
929 static void pump_messages(struct work_struct *work)
931 struct driver_data *drv_data;
934 drv_data = container_of(work, struct driver_data, pump_messages);
936 /* Lock queue and check for queue work */
937 spin_lock_irqsave(&drv_data->lock, flags);
938 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
939 /* pumper kicked off but no work to do */
941 spin_unlock_irqrestore(&drv_data->lock, flags);
945 /* Make sure we are not already running a message */
946 if (drv_data->cur_msg) {
947 spin_unlock_irqrestore(&drv_data->lock, flags);
951 /* Extract head of queue */
952 drv_data->cur_msg = list_entry(drv_data->queue.next,
953 struct spi_message, queue);
955 /* Setup the SSP using the per chip configuration */
956 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
957 restore_state(drv_data);
959 list_del_init(&drv_data->cur_msg->queue);
961 /* Initial message state */
962 drv_data->cur_msg->state = START_STATE;
963 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
964 struct spi_transfer, transfer_list);
966 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
967 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
968 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
969 drv_data->cur_chip->ctl_reg);
971 dev_dbg(&drv_data->pdev->dev,
972 "the first transfer len is %d\n",
973 drv_data->cur_transfer->len);
975 /* Mark as busy and launch transfers */
976 tasklet_schedule(&drv_data->pump_transfers);
979 spin_unlock_irqrestore(&drv_data->lock, flags);
983 * got a msg to transfer, queue it in drv_data->queue.
984 * And kick off message pumper
986 static int transfer(struct spi_device *spi, struct spi_message *msg)
988 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
991 spin_lock_irqsave(&drv_data->lock, flags);
993 if (drv_data->run == QUEUE_STOPPED) {
994 spin_unlock_irqrestore(&drv_data->lock, flags);
998 msg->actual_length = 0;
999 msg->status = -EINPROGRESS;
1000 msg->state = START_STATE;
1002 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
1003 list_add_tail(&msg->queue, &drv_data->queue);
1005 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1006 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1008 spin_unlock_irqrestore(&drv_data->lock, flags);
1013 #define MAX_SPI_SSEL 7
1015 static u16 ssel[3][MAX_SPI_SSEL] = {
1016 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1017 P_SPI0_SSEL4, P_SPI0_SSEL5,
1018 P_SPI0_SSEL6, P_SPI0_SSEL7},
1020 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1021 P_SPI1_SSEL4, P_SPI1_SSEL5,
1022 P_SPI1_SSEL6, P_SPI1_SSEL7},
1024 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1025 P_SPI2_SSEL4, P_SPI2_SSEL5,
1026 P_SPI2_SSEL6, P_SPI2_SSEL7},
1029 /* first setup for new devices */
1030 static int setup(struct spi_device *spi)
1032 struct bfin5xx_spi_chip *chip_info = NULL;
1033 struct chip_data *chip;
1034 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1037 /* Abort device setup if requested features are not supported */
1038 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1039 dev_err(&spi->dev, "requested mode not fully supported\n");
1043 /* Zero (the default) here means 8 bits */
1044 if (!spi->bits_per_word)
1045 spi->bits_per_word = 8;
1047 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1050 /* Only alloc (or use chip_info) on first setup */
1051 chip = spi_get_ctldata(spi);
1053 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1057 chip->enable_dma = 0;
1058 chip_info = spi->controller_data;
1061 /* chip_info isn't always needed */
1063 /* Make sure people stop trying to set fields via ctl_reg
1064 * when they should actually be using common SPI framework.
1065 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1066 * Not sure if a user actually needs/uses any of these,
1067 * but let's assume (for now) they do.
1069 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1070 dev_err(&spi->dev, "do not set bits in ctl_reg "
1071 "that the SPI framework manages\n");
1075 chip->enable_dma = chip_info->enable_dma != 0
1076 && drv_data->master_info->enable_dma;
1077 chip->ctl_reg = chip_info->ctl_reg;
1078 chip->bits_per_word = chip_info->bits_per_word;
1079 chip->cs_change_per_word = chip_info->cs_change_per_word;
1080 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1083 /* translate common spi framework into our register */
1084 if (spi->mode & SPI_CPOL)
1085 chip->ctl_reg |= CPOL;
1086 if (spi->mode & SPI_CPHA)
1087 chip->ctl_reg |= CPHA;
1088 if (spi->mode & SPI_LSB_FIRST)
1089 chip->ctl_reg |= LSBF;
1090 /* we dont support running in slave mode (yet?) */
1091 chip->ctl_reg |= MSTR;
1094 * if any one SPI chip is registered and wants DMA, request the
1095 * DMA channel for it
1097 if (chip->enable_dma && !drv_data->dma_requested) {
1098 /* register dma irq handler */
1099 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
1101 "Unable to request BlackFin SPI DMA channel\n");
1104 if (set_dma_callback(drv_data->dma_channel,
1105 (void *)dma_irq_handler, drv_data) < 0) {
1106 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1109 dma_disable_irq(drv_data->dma_channel);
1110 drv_data->dma_requested = 1;
1114 * Notice: for blackfin, the speed_hz is the value of register
1115 * SPI_BAUD, not the real baudrate
1117 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1118 spi_flg = ~(1 << (spi->chip_select));
1119 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1120 chip->chip_select_num = spi->chip_select;
1122 switch (chip->bits_per_word) {
1125 chip->width = CFG_SPI_WORDSIZE8;
1126 chip->read = chip->cs_change_per_word ?
1127 u8_cs_chg_reader : u8_reader;
1128 chip->write = chip->cs_change_per_word ?
1129 u8_cs_chg_writer : u8_writer;
1130 chip->duplex = chip->cs_change_per_word ?
1131 u8_cs_chg_duplex : u8_duplex;
1136 chip->width = CFG_SPI_WORDSIZE16;
1137 chip->read = chip->cs_change_per_word ?
1138 u16_cs_chg_reader : u16_reader;
1139 chip->write = chip->cs_change_per_word ?
1140 u16_cs_chg_writer : u16_writer;
1141 chip->duplex = chip->cs_change_per_word ?
1142 u16_cs_chg_duplex : u16_duplex;
1146 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1147 chip->bits_per_word);
1152 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1153 spi->modalias, chip->width, chip->enable_dma);
1154 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1155 chip->ctl_reg, chip->flag);
1157 spi_set_ctldata(spi, chip);
1159 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1160 if ((chip->chip_select_num > 0)
1161 && (chip->chip_select_num <= spi->master->num_chipselect))
1162 peripheral_request(ssel[spi->master->bus_num]
1163 [chip->chip_select_num-1], spi->modalias);
1165 cs_deactive(drv_data, chip);
1171 * callback for spi framework.
1172 * clean driver specific data
1174 static void cleanup(struct spi_device *spi)
1176 struct chip_data *chip = spi_get_ctldata(spi);
1178 if ((chip->chip_select_num > 0)
1179 && (chip->chip_select_num <= spi->master->num_chipselect))
1180 peripheral_free(ssel[spi->master->bus_num]
1181 [chip->chip_select_num-1]);
1186 static inline int init_queue(struct driver_data *drv_data)
1188 INIT_LIST_HEAD(&drv_data->queue);
1189 spin_lock_init(&drv_data->lock);
1191 drv_data->run = QUEUE_STOPPED;
1194 /* init transfer tasklet */
1195 tasklet_init(&drv_data->pump_transfers,
1196 pump_transfers, (unsigned long)drv_data);
1198 /* init messages workqueue */
1199 INIT_WORK(&drv_data->pump_messages, pump_messages);
1200 drv_data->workqueue =
1201 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
1202 if (drv_data->workqueue == NULL)
1208 static inline int start_queue(struct driver_data *drv_data)
1210 unsigned long flags;
1212 spin_lock_irqsave(&drv_data->lock, flags);
1214 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1215 spin_unlock_irqrestore(&drv_data->lock, flags);
1219 drv_data->run = QUEUE_RUNNING;
1220 drv_data->cur_msg = NULL;
1221 drv_data->cur_transfer = NULL;
1222 drv_data->cur_chip = NULL;
1223 spin_unlock_irqrestore(&drv_data->lock, flags);
1225 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1230 static inline int stop_queue(struct driver_data *drv_data)
1232 unsigned long flags;
1233 unsigned limit = 500;
1236 spin_lock_irqsave(&drv_data->lock, flags);
1239 * This is a bit lame, but is optimized for the common execution path.
1240 * A wait_queue on the drv_data->busy could be used, but then the common
1241 * execution path (pump_messages) would be required to call wake_up or
1242 * friends on every SPI message. Do this instead
1244 drv_data->run = QUEUE_STOPPED;
1245 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1246 spin_unlock_irqrestore(&drv_data->lock, flags);
1248 spin_lock_irqsave(&drv_data->lock, flags);
1251 if (!list_empty(&drv_data->queue) || drv_data->busy)
1254 spin_unlock_irqrestore(&drv_data->lock, flags);
1259 static inline int destroy_queue(struct driver_data *drv_data)
1263 status = stop_queue(drv_data);
1267 destroy_workqueue(drv_data->workqueue);
1272 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1274 struct device *dev = &pdev->dev;
1275 struct bfin5xx_spi_master *platform_info;
1276 struct spi_master *master;
1277 struct driver_data *drv_data = 0;
1278 struct resource *res;
1281 platform_info = dev->platform_data;
1283 /* Allocate master with space for drv_data */
1284 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1286 dev_err(&pdev->dev, "can not alloc spi_master\n");
1290 drv_data = spi_master_get_devdata(master);
1291 drv_data->master = master;
1292 drv_data->master_info = platform_info;
1293 drv_data->pdev = pdev;
1294 drv_data->pin_req = platform_info->pin_req;
1296 master->bus_num = pdev->id;
1297 master->num_chipselect = platform_info->num_chipselect;
1298 master->cleanup = cleanup;
1299 master->setup = setup;
1300 master->transfer = transfer;
1302 /* Find and map our resources */
1303 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1305 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1307 goto out_error_get_res;
1310 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1311 if (drv_data->regs_base == NULL) {
1312 dev_err(dev, "Cannot map IO\n");
1314 goto out_error_ioremap;
1317 drv_data->dma_channel = platform_get_irq(pdev, 0);
1318 if (drv_data->dma_channel < 0) {
1319 dev_err(dev, "No DMA channel specified\n");
1321 goto out_error_no_dma_ch;
1324 /* Initial and start queue */
1325 status = init_queue(drv_data);
1327 dev_err(dev, "problem initializing queue\n");
1328 goto out_error_queue_alloc;
1331 status = start_queue(drv_data);
1333 dev_err(dev, "problem starting queue\n");
1334 goto out_error_queue_alloc;
1337 /* Register with the SPI framework */
1338 platform_set_drvdata(pdev, drv_data);
1339 status = spi_register_master(master);
1341 dev_err(dev, "problem registering spi master\n");
1342 goto out_error_queue_alloc;
1345 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1347 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1351 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1352 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1353 drv_data->dma_channel);
1356 out_error_queue_alloc:
1357 destroy_queue(drv_data);
1358 out_error_no_dma_ch:
1359 iounmap((void *) drv_data->regs_base);
1363 spi_master_put(master);
1368 /* stop hardware and remove the driver */
1369 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1371 struct driver_data *drv_data = platform_get_drvdata(pdev);
1377 /* Remove the queue */
1378 status = destroy_queue(drv_data);
1382 /* Disable the SSP at the peripheral and SOC level */
1383 bfin_spi_disable(drv_data);
1386 if (drv_data->master_info->enable_dma) {
1387 if (dma_channel_active(drv_data->dma_channel))
1388 free_dma(drv_data->dma_channel);
1391 /* Disconnect from the SPI framework */
1392 spi_unregister_master(drv_data->master);
1394 peripheral_free_list(drv_data->pin_req);
1396 /* Prevent double remove */
1397 platform_set_drvdata(pdev, NULL);
1403 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1405 struct driver_data *drv_data = platform_get_drvdata(pdev);
1408 status = stop_queue(drv_data);
1413 bfin_spi_disable(drv_data);
1418 static int bfin5xx_spi_resume(struct platform_device *pdev)
1420 struct driver_data *drv_data = platform_get_drvdata(pdev);
1423 /* Enable the SPI interface */
1424 bfin_spi_enable(drv_data);
1426 /* Start the queue running */
1427 status = start_queue(drv_data);
1429 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1436 #define bfin5xx_spi_suspend NULL
1437 #define bfin5xx_spi_resume NULL
1438 #endif /* CONFIG_PM */
1440 MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
1441 static struct platform_driver bfin5xx_spi_driver = {
1444 .owner = THIS_MODULE,
1446 .suspend = bfin5xx_spi_suspend,
1447 .resume = bfin5xx_spi_resume,
1448 .remove = __devexit_p(bfin5xx_spi_remove),
1451 static int __init bfin5xx_spi_init(void)
1453 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1455 module_init(bfin5xx_spi_init);
1457 static void __exit bfin5xx_spi_exit(void)
1459 platform_driver_unregister(&bfin5xx_spi_driver);
1461 module_exit(bfin5xx_spi_exit);