drivers/spi/spi_bfin5xx.c

   1 /*
   2  * File:        drivers/spi/bfin5xx_spi.c
   3  * Maintainer:
   4  *              Bryan Wu <bryan.wu@analog.com>
   5  * Original Author:
   6  *              Luke Yang (Analog Devices Inc.)
   7  *
   8  * Created:     March. 10th 2006
   9  * Description: SPI controller driver for Blackfin BF5xx
  10  * Bugs:        Enter bugs at http://blackfin.uclinux.org/
  11  *
  12  * Modified:
  13  *      March 10, 2006  bfin5xx_spi.c Created. (Luke Yang)
  14  *      August 7, 2006  added full duplex mode (Axel Weiss & Luke Yang)
  15  *      July  17, 2007  add support for BF54x SPI0 controller (Bryan Wu)
  16  *
  17  * Copyright 2004-2007 Analog Devices Inc.
  18  *
  19  * This program is free software ;  you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation ;  either version 2, or (at your option)
  22  * any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY ;  without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program ;  see the file COPYING.
  31  * If not, write to the Free Software Foundation,
  32  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  33  */
  34
  35 #include <linux/init.h>
  36 #include <linux/module.h>
  37 #include <linux/delay.h>
  38 #include <linux/device.h>
  39 #include <linux/io.h>
  40 #include <linux/ioport.h>
  41 #include <linux/irq.h>
  42 #include <linux/errno.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/spi/spi.h>
  47 #include <linux/workqueue.h>
  48
  49 #include <asm/dma.h>
  50 #include <asm/portmux.h>
  51 #include <asm/bfin5xx_spi.h>
  52
  53 MODULE_AUTHOR("Bryan Wu, Luke Yang");
  54 MODULE_DESCRIPTION("Blackfin BF5xx SPI Contoller Driver");
  55 MODULE_LICENSE("GPL");
  56
  57 #define DRV_NAME        "bfin-spi-master"
  58 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
  59
  60 #define DEFINE_SPI_REG(reg, off) \
  61 static inline u16 read_##reg(void) \
  62             { return *(volatile unsigned short*)(SPI0_REGBASE + off); } \
  63 static inline void write_##reg(u16 v) \
  64             {*(volatile unsigned short*)(SPI0_REGBASE + off) = v;\
  65              SSYNC();}
  66
  67 DEFINE_SPI_REG(CTRL, 0x00)
  68 DEFINE_SPI_REG(FLAG, 0x04)
  69 DEFINE_SPI_REG(STAT, 0x08)
  70 DEFINE_SPI_REG(TDBR, 0x0C)
  71 DEFINE_SPI_REG(RDBR, 0x10)
  72 DEFINE_SPI_REG(BAUD, 0x14)
  73 DEFINE_SPI_REG(SHAW, 0x18)
  74 #define START_STATE ((void*)0)
  75 #define RUNNING_STATE ((void*)1)
  76 #define DONE_STATE ((void*)2)
  77 #define ERROR_STATE ((void*)-1)
  78 #define QUEUE_RUNNING 0
  79 #define QUEUE_STOPPED 1
  80 int dma_requested;
  81
  82 struct driver_data {
  83         /* Driver model hookup */
  84         struct platform_device *pdev;
  85
  86         /* SPI framework hookup */
  87         struct spi_master *master;
  88
  89         /* BFIN hookup */
  90         struct bfin5xx_spi_master *master_info;
  91
  92         /* Driver message queue */
  93         struct workqueue_struct *workqueue;
  94         struct work_struct pump_messages;
  95         spinlock_t lock;
  96         struct list_head queue;
  97         int busy;
  98         int run;
  99
 100         /* Message Transfer pump */
 101         struct tasklet_struct pump_transfers;
 102
 103         /* Current message transfer state info */
 104         struct spi_message *cur_msg;
 105         struct spi_transfer *cur_transfer;
 106         struct chip_data *cur_chip;
 107         size_t len_in_bytes;
 108         size_t len;
 109         void *tx;
 110         void *tx_end;
 111         void *rx;
 112         void *rx_end;
 113         int dma_mapped;
 114         dma_addr_t rx_dma;
 115         dma_addr_t tx_dma;
 116         size_t rx_map_len;
 117         size_t tx_map_len;
 118         u8 n_bytes;
 119         void (*write) (struct driver_data *);
 120         void (*read) (struct driver_data *);
 121         void (*duplex) (struct driver_data *);
 122 };
 123
 124 struct chip_data {
 125         u16 ctl_reg;
 126         u16 baud;
 127         u16 flag;
 128
 129         u8 chip_select_num;
 130         u8 chip_select_requested;
 131         u8 n_bytes;
 132         u8 width;               /* 0 or 1 */
 133         u8 enable_dma;
 134         u8 bits_per_word;       /* 8 or 16 */
 135         u8 cs_change_per_word;
 136         u8 cs_chg_udelay;
 137         void (*write) (struct driver_data *);
 138         void (*read) (struct driver_data *);
 139         void (*duplex) (struct driver_data *);
 140 };
 141
 142 static void bfin_spi_enable(struct driver_data *drv_data)
 143 {
 144         u16 cr;
 145
 146         cr = read_CTRL();
 147         write_CTRL(cr | BIT_CTL_ENABLE);
 148         SSYNC();
 149 }
 150
 151 static void bfin_spi_disable(struct driver_data *drv_data)
 152 {
 153         u16 cr;
 154
 155         cr = read_CTRL();
 156         write_CTRL(cr & (~BIT_CTL_ENABLE));
 157         SSYNC();
 158 }
 159
 160 /* Caculate the SPI_BAUD register value based on input HZ */
 161 static u16 hz_to_spi_baud(u32 speed_hz)
 162 {
 163         u_long sclk = get_sclk();
 164         u16 spi_baud = (sclk / (2 * speed_hz));
 165
 166         if ((sclk % (2 * speed_hz)) > 0)
 167                 spi_baud++;
 168
 169         return spi_baud;
 170 }
 171
 172 static int flush(struct driver_data *drv_data)
 173 {
 174         unsigned long limit = loops_per_jiffy << 1;
 175
 176         /* wait for stop and clear stat */
 177         while (!(read_STAT() & BIT_STAT_SPIF) && limit--)
 178                 continue;
 179
 180         write_STAT(BIT_STAT_CLR);
 181
 182         return limit;
 183 }
 184
 185 /* stop controller and re-config current chip*/
 186 static void restore_state(struct driver_data *drv_data)
 187 {
 188         struct chip_data *chip = drv_data->cur_chip;
 189
 190         /* Clear status and disable clock */
 191         write_STAT(BIT_STAT_CLR);
 192         bfin_spi_disable(drv_data);
 193         dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
 194
 195         if (!chip->chip_select_requested) {
 196
 197                 dev_dbg(&drv_data->pdev->dev,
 198                 "chip select number is %d\n", chip->chip_select_num);
 199
 200                 switch (chip->chip_select_num) {
 201                 case 1:
 202                         peripheral_request(P_SPI0_SSEL1, DRV_NAME);
 203                         break;
 204                 case 2:
 205                         peripheral_request(P_SPI0_SSEL2, DRV_NAME);
 206                         break;
 207                 case 3:
 208                         peripheral_request(P_SPI0_SSEL3, DRV_NAME);
 209                         break;
 210                 case 4:
 211                         peripheral_request(P_SPI0_SSEL4, DRV_NAME);
 212                         break;
 213                 case 5:
 214                         peripheral_request(P_SPI0_SSEL5, DRV_NAME);
 215                         break;
 216                 case 6:
 217                         peripheral_request(P_SPI0_SSEL6, DRV_NAME);
 218                         break;
 219                 case 7:
 220                         peripheral_request(P_SPI0_SSEL7, DRV_NAME);
 221                         break;
 222                 }
 223
 224                 chip->chip_select_requested = 1;
 225         }
 226
 227         /* Load the registers */
 228         write_CTRL(chip->ctl_reg);
 229         write_BAUD(chip->baud);
 230         write_FLAG(chip->flag);
 231 }
 232
 233 /* used to kick off transfer in rx mode */
 234 static unsigned short dummy_read(void)
 235 {
 236         unsigned short tmp;
 237         tmp = read_RDBR();
 238         return tmp;
 239 }
 240
 241 static void null_writer(struct driver_data *drv_data)
 242 {
 243         u8 n_bytes = drv_data->n_bytes;
 244
 245         while (drv_data->tx < drv_data->tx_end) {
 246                 write_TDBR(0);
 247                 while ((read_STAT() & BIT_STAT_TXS))
 248                         continue;
 249                 drv_data->tx += n_bytes;
 250         }
 251 }
 252
 253 static void null_reader(struct driver_data *drv_data)
 254 {
 255         u8 n_bytes = drv_data->n_bytes;
 256         dummy_read();
 257
 258         while (drv_data->rx < drv_data->rx_end) {
 259                 while (!(read_STAT() & BIT_STAT_RXS))
 260                         continue;
 261                 dummy_read();
 262                 drv_data->rx += n_bytes;
 263         }
 264 }
 265
 266 static void u8_writer(struct driver_data *drv_data)
 267 {
 268         dev_dbg(&drv_data->pdev->dev,
 269                 "cr8-s is 0x%x\n", read_STAT());
 270         while (drv_data->tx < drv_data->tx_end) {
 271                 write_TDBR(*(u8 *) (drv_data->tx));
 272                 while (read_STAT() & BIT_STAT_TXS)
 273                         continue;
 274                 ++drv_data->tx;
 275         }
 276
 277         /* poll for SPI completion before returning */
 278         while (!(read_STAT() & BIT_STAT_SPIF))
 279                 continue;
 280 }
 281
 282 static void u8_cs_chg_writer(struct driver_data *drv_data)
 283 {
 284         struct chip_data *chip = drv_data->cur_chip;
 285
 286         while (drv_data->tx < drv_data->tx_end) {
 287                 write_FLAG(chip->flag);
 288                 SSYNC();
 289
 290                 write_TDBR(*(u8 *) (drv_data->tx));
 291                 while (read_STAT() & BIT_STAT_TXS)
 292                         continue;
 293                 while (!(read_STAT() & BIT_STAT_SPIF))
 294                         continue;
 295                 write_FLAG(0xFF00 | chip->flag);
 296                 SSYNC();
 297                 if (chip->cs_chg_udelay)
 298                         udelay(chip->cs_chg_udelay);
 299                 ++drv_data->tx;
 300         }
 301         write_FLAG(0xFF00);
 302         SSYNC();
 303 }
 304
 305 static void u8_reader(struct driver_data *drv_data)
 306 {
 307         dev_dbg(&drv_data->pdev->dev,
 308                 "cr-8 is 0x%x\n", read_STAT());
 309
 310         /* clear TDBR buffer before read(else it will be shifted out) */
 311         write_TDBR(0xFFFF);
 312
 313         dummy_read();
 314
 315         while (drv_data->rx < drv_data->rx_end - 1) {
 316                 while (!(read_STAT() & BIT_STAT_RXS))
 317                         continue;
 318                 *(u8 *) (drv_data->rx) = read_RDBR();
 319                 ++drv_data->rx;
 320         }
 321
 322         while (!(read_STAT() & BIT_STAT_RXS))
 323                 continue;
 324         *(u8 *) (drv_data->rx) = read_SHAW();
 325         ++drv_data->rx;
 326 }
 327
 328 static void u8_cs_chg_reader(struct driver_data *drv_data)
 329 {
 330         struct chip_data *chip = drv_data->cur_chip;
 331
 332         while (drv_data->rx < drv_data->rx_end) {
 333                 write_FLAG(chip->flag);
 334                 SSYNC();
 335
 336                 read_RDBR();    /* kick off */
 337                 while (!(read_STAT() & BIT_STAT_RXS))
 338                         continue;
 339                 while (!(read_STAT() & BIT_STAT_SPIF))
 340                         continue;
 341                 *(u8 *) (drv_data->rx) = read_SHAW();
 342                 write_FLAG(0xFF00 | chip->flag);
 343                 SSYNC();
 344                 if (chip->cs_chg_udelay)
 345                         udelay(chip->cs_chg_udelay);
 346                 ++drv_data->rx;
 347         }
 348         write_FLAG(0xFF00);
 349         SSYNC();
 350 }
 351
 352 static void u8_duplex(struct driver_data *drv_data)
 353 {
 354         /* in duplex mode, clk is triggered by writing of TDBR */
 355         while (drv_data->rx < drv_data->rx_end) {
 356                 write_TDBR(*(u8 *) (drv_data->tx));
 357                 while (!(read_STAT() & BIT_STAT_SPIF))
 358                         continue;
 359                 while (!(read_STAT() & BIT_STAT_RXS))
 360                         continue;
 361                 *(u8 *) (drv_data->rx) = read_RDBR();
 362                 ++drv_data->rx;
 363                 ++drv_data->tx;
 364         }
 365 }
 366
 367 static void u8_cs_chg_duplex(struct driver_data *drv_data)
 368 {
 369         struct chip_data *chip = drv_data->cur_chip;
 370
 371         while (drv_data->rx < drv_data->rx_end) {
 372                 write_FLAG(chip->flag);
 373                 SSYNC();
 374
 375                 write_TDBR(*(u8 *) (drv_data->tx));
 376                 while (!(read_STAT() & BIT_STAT_SPIF))
 377                         continue;
 378                 while (!(read_STAT() & BIT_STAT_RXS))
 379                         continue;
 380                 *(u8 *) (drv_data->rx) = read_RDBR();
 381                 write_FLAG(0xFF00 | chip->flag);
 382                 SSYNC();
 383                 if (chip->cs_chg_udelay)
 384                         udelay(chip->cs_chg_udelay);
 385                 ++drv_data->rx;
 386                 ++drv_data->tx;
 387         }
 388         write_FLAG(0xFF00);
 389         SSYNC();
 390 }
 391
 392 static void u16_writer(struct driver_data *drv_data)
 393 {
 394         dev_dbg(&drv_data->pdev->dev,
 395                 "cr16 is 0x%x\n", read_STAT());
 396
 397         while (drv_data->tx < drv_data->tx_end) {
 398                 write_TDBR(*(u16 *) (drv_data->tx));
 399                 while ((read_STAT() & BIT_STAT_TXS))
 400                         continue;
 401                 drv_data->tx += 2;
 402         }
 403
 404         /* poll for SPI completion before returning */
 405         while (!(read_STAT() & BIT_STAT_SPIF))
 406                 continue;
 407 }
 408
 409 static void u16_cs_chg_writer(struct driver_data *drv_data)
 410 {
 411         struct chip_data *chip = drv_data->cur_chip;
 412
 413         while (drv_data->tx < drv_data->tx_end) {
 414                 write_FLAG(chip->flag);
 415                 SSYNC();
 416
 417                 write_TDBR(*(u16 *) (drv_data->tx));
 418                 while ((read_STAT() & BIT_STAT_TXS))
 419                         continue;
 420                 while (!(read_STAT() & BIT_STAT_SPIF))
 421                         continue;
 422                 write_FLAG(0xFF00 | chip->flag);
 423                 SSYNC();
 424                 if (chip->cs_chg_udelay)
 425                         udelay(chip->cs_chg_udelay);
 426                 drv_data->tx += 2;
 427         }
 428         write_FLAG(0xFF00);
 429         SSYNC();
 430 }
 431
 432 static void u16_reader(struct driver_data *drv_data)
 433 {
 434         dev_dbg(&drv_data->pdev->dev,
 435                 "cr-16 is 0x%x\n", read_STAT());
 436         dummy_read();
 437
 438         while (drv_data->rx < (drv_data->rx_end - 2)) {
 439                 while (!(read_STAT() & BIT_STAT_RXS))
 440                         continue;
 441                 *(u16 *) (drv_data->rx) = read_RDBR();
 442                 drv_data->rx += 2;
 443         }
 444
 445         while (!(read_STAT() & BIT_STAT_RXS))
 446                 continue;
 447         *(u16 *) (drv_data->rx) = read_SHAW();
 448         drv_data->rx += 2;
 449 }
 450
 451 static void u16_cs_chg_reader(struct driver_data *drv_data)
 452 {
 453         struct chip_data *chip = drv_data->cur_chip;
 454
 455         while (drv_data->rx < drv_data->rx_end) {
 456                 write_FLAG(chip->flag);
 457                 SSYNC();
 458
 459                 read_RDBR();    /* kick off */
 460                 while (!(read_STAT() & BIT_STAT_RXS))
 461                         continue;
 462                 while (!(read_STAT() & BIT_STAT_SPIF))
 463                         continue;
 464                 *(u16 *) (drv_data->rx) = read_SHAW();
 465                 write_FLAG(0xFF00 | chip->flag);
 466                 SSYNC();
 467                 if (chip->cs_chg_udelay)
 468                         udelay(chip->cs_chg_udelay);
 469                 drv_data->rx += 2;
 470         }
 471         write_FLAG(0xFF00);
 472         SSYNC();
 473 }
 474
 475 static void u16_duplex(struct driver_data *drv_data)
 476 {
 477         /* in duplex mode, clk is triggered by writing of TDBR */
 478         while (drv_data->tx < drv_data->tx_end) {
 479                 write_TDBR(*(u16 *) (drv_data->tx));
 480                 while (!(read_STAT() & BIT_STAT_SPIF))
 481                         continue;
 482                 while (!(read_STAT() & BIT_STAT_RXS))
 483                         continue;
 484                 *(u16 *) (drv_data->rx) = read_RDBR();
 485                 drv_data->rx += 2;
 486                 drv_data->tx += 2;
 487         }
 488 }
 489
 490 static void u16_cs_chg_duplex(struct driver_data *drv_data)
 491 {
 492         struct chip_data *chip = drv_data->cur_chip;
 493
 494         while (drv_data->tx < drv_data->tx_end) {
 495                 write_FLAG(chip->flag);
 496                 SSYNC();
 497
 498                 write_TDBR(*(u16 *) (drv_data->tx));
 499                 while (!(read_STAT() & BIT_STAT_SPIF))
 500                         continue;
 501                 while (!(read_STAT() & BIT_STAT_RXS))
 502                         continue;
 503                 *(u16 *) (drv_data->rx) = read_RDBR();
 504                 write_FLAG(0xFF00 | chip->flag);
 505                 SSYNC();
 506                 if (chip->cs_chg_udelay)
 507                         udelay(chip->cs_chg_udelay);
 508                 drv_data->rx += 2;
 509                 drv_data->tx += 2;
 510         }
 511         write_FLAG(0xFF00);
 512         SSYNC();
 513 }
 514
 515 /* test if ther is more transfer to be done */
 516 static void *next_transfer(struct driver_data *drv_data)
 517 {
 518         struct spi_message *msg = drv_data->cur_msg;
 519         struct spi_transfer *trans = drv_data->cur_transfer;
 520
 521         /* Move to next transfer */
 522         if (trans->transfer_list.next != &msg->transfers) {
 523                 drv_data->cur_transfer =
 524                     list_entry(trans->transfer_list.next,
 525                                struct spi_transfer, transfer_list);
 526                 return RUNNING_STATE;
 527         } else
 528                 return DONE_STATE;
 529 }
 530
 531 /*
 532  * caller already set message->status;
 533  * dma and pio irqs are blocked give finished message back
 534  */
 535 static void giveback(struct driver_data *drv_data)
 536 {
 537         struct spi_transfer *last_transfer;
 538         unsigned long flags;
 539         struct spi_message *msg;
 540
 541         spin_lock_irqsave(&drv_data->lock, flags);
 542         msg = drv_data->cur_msg;
 543         drv_data->cur_msg = NULL;
 544         drv_data->cur_transfer = NULL;
 545         drv_data->cur_chip = NULL;
 546         queue_work(drv_data->workqueue, &drv_data->pump_messages);
 547         spin_unlock_irqrestore(&drv_data->lock, flags);
 548
 549         last_transfer = list_entry(msg->transfers.prev,
 550                                    struct spi_transfer, transfer_list);
 551
 552         msg->state = NULL;
 553
 554         /* disable chip select signal. And not stop spi in autobuffer mode */
 555         if (drv_data->tx_dma != 0xFFFF) {
 556                 write_FLAG(0xFF00);
 557                 bfin_spi_disable(drv_data);
 558         }
 559
 560         if (msg->complete)
 561                 msg->complete(msg->context);
 562 }
 563
 564 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 565 {
 566         struct driver_data *drv_data = (struct driver_data *)dev_id;
 567         struct spi_message *msg = drv_data->cur_msg;
 568
 569         dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
 570         clear_dma_irqstat(CH_SPI);
 571
 572         /* Wait for DMA to complete */
 573         while (get_dma_curr_irqstat(CH_SPI) & DMA_RUN)
 574                 continue;
 575
 576         /*
 577          * wait for the last transaction shifted out.  HRM states:
 578          * at this point there may still be data in the SPI DMA FIFO waiting
 579          * to be transmitted ... software needs to poll TXS in the SPI_STAT
 580          * register until it goes low for 2 successive reads
 581          */
 582         if (drv_data->tx != NULL) {
 583                 while ((bfin_read_SPI_STAT() & TXS) ||
 584                        (bfin_read_SPI_STAT() & TXS))
 585                         continue;
 586         }
 587
 588         while (!(bfin_read_SPI_STAT() & SPIF))
 589                 continue;
 590
 591         bfin_spi_disable(drv_data);
 592
 593         msg->actual_length += drv_data->len_in_bytes;
 594
 595         /* Move to next transfer */
 596         msg->state = next_transfer(drv_data);
 597
 598         /* Schedule transfer tasklet */
 599         tasklet_schedule(&drv_data->pump_transfers);
 600
 601         /* free the irq handler before next transfer */
 602         dev_dbg(&drv_data->pdev->dev,
 603                 "disable dma channel irq%d\n",
 604                 CH_SPI);
 605         dma_disable_irq(CH_SPI);
 606
 607         return IRQ_HANDLED;
 608 }
 609
 610 static void pump_transfers(unsigned long data)
 611 {
 612         struct driver_data *drv_data = (struct driver_data *)data;
 613         struct spi_message *message = NULL;
 614         struct spi_transfer *transfer = NULL;
 615         struct spi_transfer *previous = NULL;
 616         struct chip_data *chip = NULL;
 617         u8 width;
 618         u16 cr, dma_width, dma_config;
 619         u32 tranf_success = 1;
 620
 621         /* Get current state information */
 622         message = drv_data->cur_msg;
 623         transfer = drv_data->cur_transfer;
 624         chip = drv_data->cur_chip;
 625
 626         /*
 627          * if msg is error or done, report it back using complete() callback
 628          */
 629
 630          /* Handle for abort */
 631         if (message->state == ERROR_STATE) {
 632                 message->status = -EIO;
 633                 giveback(drv_data);
 634                 return;
 635         }
 636
 637         /* Handle end of message */
 638         if (message->state == DONE_STATE) {
 639                 message->status = 0;
 640                 giveback(drv_data);
 641                 return;
 642         }
 643
 644         /* Delay if requested at end of transfer */
 645         if (message->state == RUNNING_STATE) {
 646                 previous = list_entry(transfer->transfer_list.prev,
 647                                       struct spi_transfer, transfer_list);
 648                 if (previous->delay_usecs)
 649                         udelay(previous->delay_usecs);
 650         }
 651
 652         /* Setup the transfer state based on the type of transfer */
 653         if (flush(drv_data) == 0) {
 654                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 655                 message->status = -EIO;
 656                 giveback(drv_data);
 657                 return;
 658         }
 659
 660         if (transfer->tx_buf != NULL) {
 661                 drv_data->tx = (void *)transfer->tx_buf;
 662                 drv_data->tx_end = drv_data->tx + transfer->len;
 663                 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
 664                         transfer->tx_buf, drv_data->tx_end);
 665         } else {
 666                 drv_data->tx = NULL;
 667         }
 668
 669         if (transfer->rx_buf != NULL) {
 670                 drv_data->rx = transfer->rx_buf;
 671                 drv_data->rx_end = drv_data->rx + transfer->len;
 672                 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
 673                         transfer->rx_buf, drv_data->rx_end);
 674         } else {
 675                 drv_data->rx = NULL;
 676         }
 677
 678         drv_data->rx_dma = transfer->rx_dma;
 679         drv_data->tx_dma = transfer->tx_dma;
 680         drv_data->len_in_bytes = transfer->len;
 681
 682         width = chip->width;
 683         if (width == CFG_SPI_WORDSIZE16) {
 684                 drv_data->len = (transfer->len) >> 1;
 685         } else {
 686                 drv_data->len = transfer->len;
 687         }
 688         drv_data->write = drv_data->tx ? chip->write : null_writer;
 689         drv_data->read = drv_data->rx ? chip->read : null_reader;
 690         drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
 691         dev_dbg(&drv_data->pdev->dev, "transfer: ",
 692                 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
 693                 drv_data->write, chip->write, null_writer);
 694
 695         /* speed and width has been set on per message */
 696         message->state = RUNNING_STATE;
 697         dma_config = 0;
 698
 699         /* restore spi status for each spi transfer */
 700         if (transfer->speed_hz) {
 701                 write_BAUD(hz_to_spi_baud(transfer->speed_hz));
 702         } else {
 703                 write_BAUD(chip->baud);
 704         }
 705         write_FLAG(chip->flag);
 706
 707         dev_dbg(&drv_data->pdev->dev,
 708                 "now pumping a transfer: width is %d, len is %d\n",
 709                 width, transfer->len);
 710
 711         /*
 712          * Try to map dma buffer and do a dma transfer if
 713          * successful use different way to r/w according to
 714          * drv_data->cur_chip->enable_dma
 715          */
 716         if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
 717
 718                 write_STAT(BIT_STAT_CLR);
 719                 disable_dma(CH_SPI);
 720                 clear_dma_irqstat(CH_SPI);
 721                 bfin_spi_disable(drv_data);
 722
 723                 /* config dma channel */
 724                 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
 725                 if (width == CFG_SPI_WORDSIZE16) {
 726                         set_dma_x_count(CH_SPI, drv_data->len);
 727                         set_dma_x_modify(CH_SPI, 2);
 728                         dma_width = WDSIZE_16;
 729                 } else {
 730                         set_dma_x_count(CH_SPI, drv_data->len);
 731                         set_dma_x_modify(CH_SPI, 1);
 732                         dma_width = WDSIZE_8;
 733                 }
 734
 735                 /* set transfer width,direction. And enable spi */
 736                 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 737
 738                 /* dirty hack for autobuffer DMA mode */
 739                 if (drv_data->tx_dma == 0xFFFF) {
 740                         dev_dbg(&drv_data->pdev->dev,
 741                                 "doing autobuffer DMA out.\n");
 742
 743                         /* no irq in autobuffer mode */
 744                         dma_config =
 745                             (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
 746                         set_dma_config(CH_SPI, dma_config);
 747                         set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx);
 748                         enable_dma(CH_SPI);
 749                         write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
 750                                    (CFG_SPI_ENABLE << 14));
 751
 752                         /* just return here, there can only be one transfer in this mode */
 753                         message->status = 0;
 754                         giveback(drv_data);
 755                         return;
 756                 }
 757
 758                 /* In dma mode, rx or tx must be NULL in one transfer */
 759                 if (drv_data->rx != NULL) {
 760                         /* set transfer mode, and enable SPI */
 761                         dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
 762
 763                         /* disable SPI before write to TDBR */
 764                         write_CTRL(cr & ~BIT_CTL_ENABLE);
 765
 766                         /* clear tx reg soformer data is not shifted out */
 767                         write_TDBR(0xFF);
 768
 769                         set_dma_x_count(CH_SPI, drv_data->len);
 770
 771                         /* start dma */
 772                         dma_enable_irq(CH_SPI);
 773                         dma_config = (WNR | RESTART | dma_width | DI_EN);
 774                         set_dma_config(CH_SPI, dma_config);
 775                         set_dma_start_addr(CH_SPI, (unsigned long)drv_data->rx);
 776                         enable_dma(CH_SPI);
 777
 778                         cr |=
 779                             CFG_SPI_DMAREAD | (width << 8) | (CFG_SPI_ENABLE <<
 780                                                               14);
 781                         /* set transfer mode, and enable SPI */
 782                         write_CTRL(cr);
 783                 } else if (drv_data->tx != NULL) {
 784                         dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
 785
 786                         /* start dma */
 787                         dma_enable_irq(CH_SPI);
 788                         dma_config = (RESTART | dma_width | DI_EN);
 789                         set_dma_config(CH_SPI, dma_config);
 790                         set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx);
 791                         enable_dma(CH_SPI);
 792
 793                         write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
 794                                    (CFG_SPI_ENABLE << 14));
 795
 796                 }
 797         } else {
 798                 /* IO mode write then read */
 799                 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
 800
 801                 write_STAT(BIT_STAT_CLR);
 802
 803                 if (drv_data->tx != NULL && drv_data->rx != NULL) {
 804                         /* full duplex mode */
 805                         BUG_ON((drv_data->tx_end - drv_data->tx) !=
 806                                (drv_data->rx_end - drv_data->rx));
 807                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 808                         cr |= CFG_SPI_WRITE | (width << 8) |
 809                                 (CFG_SPI_ENABLE << 14);
 810                         dev_dbg(&drv_data->pdev->dev,
 811                                 "IO duplex: cr is 0x%x\n", cr);
 812
 813                         write_CTRL(cr);
 814                         SSYNC();
 815
 816                         drv_data->duplex(drv_data);
 817
 818                         if (drv_data->tx != drv_data->tx_end)
 819                                 tranf_success = 0;
 820                 } else if (drv_data->tx != NULL) {
 821                         /* write only half duplex */
 822                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 823                         cr |= CFG_SPI_WRITE | (width << 8) |
 824                                 (CFG_SPI_ENABLE << 14);
 825                         dev_dbg(&drv_data->pdev->dev,
 826                                 "IO write: cr is 0x%x\n", cr);
 827
 828                         write_CTRL(cr);
 829                         SSYNC();
 830
 831                         drv_data->write(drv_data);
 832
 833                         if (drv_data->tx != drv_data->tx_end)
 834                                 tranf_success = 0;
 835                 } else if (drv_data->rx != NULL) {
 836                         /* read only half duplex */
 837                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 838                         cr |= CFG_SPI_READ | (width << 8) |
 839                                 (CFG_SPI_ENABLE << 14);
 840                         dev_dbg(&drv_data->pdev->dev,
 841                                 "IO read: cr is 0x%x\n", cr);
 842
 843                         write_CTRL(cr);
 844                         SSYNC();
 845
 846                         drv_data->read(drv_data);
 847                         if (drv_data->rx != drv_data->rx_end)
 848                                 tranf_success = 0;
 849                 }
 850
 851                 if (!tranf_success) {
 852                         dev_dbg(&drv_data->pdev->dev,
 853                                 "IO write error!\n");
 854                         message->state = ERROR_STATE;
 855                 } else {
 856                         /* Update total byte transfered */
 857                         message->actual_length += drv_data->len;
 858
 859                         /* Move to next transfer of this msg */
 860                         message->state = next_transfer(drv_data);
 861                 }
 862
 863                 /* Schedule next transfer tasklet */
 864                 tasklet_schedule(&drv_data->pump_transfers);
 865
 866         }
 867 }
 868
 869 /* pop a msg from queue and kick off real transfer */
 870 static void pump_messages(struct work_struct *work)
 871 {
 872         struct driver_data *drv_data;
 873         unsigned long flags;
 874
 875         drv_data = container_of(work, struct driver_data, pump_messages);
 876
 877         /* Lock queue and check for queue work */
 878         spin_lock_irqsave(&drv_data->lock, flags);
 879         if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
 880                 /* pumper kicked off but no work to do */
 881                 drv_data->busy = 0;
 882                 spin_unlock_irqrestore(&drv_data->lock, flags);
 883                 return;
 884         }
 885
 886         /* Make sure we are not already running a message */
 887         if (drv_data->cur_msg) {
 888                 spin_unlock_irqrestore(&drv_data->lock, flags);
 889                 return;
 890         }
 891
 892         /* Extract head of queue */
 893         drv_data->cur_msg = list_entry(drv_data->queue.next,
 894                                        struct spi_message, queue);
 895         list_del_init(&drv_data->cur_msg->queue);
 896
 897         /* Initial message state */
 898         drv_data->cur_msg->state = START_STATE;
 899         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 900                                             struct spi_transfer, transfer_list);
 901
 902         /* Setup the SSP using the per chip configuration */
 903         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 904         restore_state(drv_data);
 905         dev_dbg(&drv_data->pdev->dev,
 906                 "got a message to pump, state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
 907                 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
 908                 drv_data->cur_chip->ctl_reg);
 909
 910         dev_dbg(&drv_data->pdev->dev,
 911                 "the first transfer len is %d\n",
 912                 drv_data->cur_transfer->len);
 913
 914         /* Mark as busy and launch transfers */
 915         tasklet_schedule(&drv_data->pump_transfers);
 916
 917         drv_data->busy = 1;
 918         spin_unlock_irqrestore(&drv_data->lock, flags);
 919 }
 920
 921 /*
 922  * got a msg to transfer, queue it in drv_data->queue.
 923  * And kick off message pumper
 924  */
 925 static int transfer(struct spi_device *spi, struct spi_message *msg)
 926 {
 927         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 928         unsigned long flags;
 929
 930         spin_lock_irqsave(&drv_data->lock, flags);
 931
 932         if (drv_data->run == QUEUE_STOPPED) {
 933                 spin_unlock_irqrestore(&drv_data->lock, flags);
 934                 return -ESHUTDOWN;
 935         }
 936
 937         msg->actual_length = 0;
 938         msg->status = -EINPROGRESS;
 939         msg->state = START_STATE;
 940
 941         dev_dbg(&spi->dev, "adding an msg in transfer() \n");
 942         list_add_tail(&msg->queue, &drv_data->queue);
 943
 944         if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
 945                 queue_work(drv_data->workqueue, &drv_data->pump_messages);
 946
 947         spin_unlock_irqrestore(&drv_data->lock, flags);
 948
 949         return 0;
 950 }
 951
 952 /* first setup for new devices */
 953 static int setup(struct spi_device *spi)
 954 {
 955         struct bfin5xx_spi_chip *chip_info = NULL;
 956         struct chip_data *chip;
 957         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 958         u8 spi_flg;
 959
 960         /* Abort device setup if requested features are not supported */
 961         if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
 962                 dev_err(&spi->dev, "requested mode not fully supported\n");
 963                 return -EINVAL;
 964         }
 965
 966         /* Zero (the default) here means 8 bits */
 967         if (!spi->bits_per_word)
 968                 spi->bits_per_word = 8;
 969
 970         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 971                 return -EINVAL;
 972
 973         /* Only alloc (or use chip_info) on first setup */
 974         chip = spi_get_ctldata(spi);
 975         if (chip == NULL) {
 976                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 977                 if (!chip)
 978                         return -ENOMEM;
 979
 980                 chip->enable_dma = 0;
 981                 chip_info = spi->controller_data;
 982         }
 983
 984         /* chip_info isn't always needed */
 985         if (chip_info) {
 986                 chip->enable_dma = chip_info->enable_dma != 0
 987                     && drv_data->master_info->enable_dma;
 988                 chip->ctl_reg = chip_info->ctl_reg;
 989                 chip->bits_per_word = chip_info->bits_per_word;
 990                 chip->cs_change_per_word = chip_info->cs_change_per_word;
 991                 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
 992         }
 993
 994         /* translate common spi framework into our register */
 995         if (spi->mode & SPI_CPOL)
 996                 chip->ctl_reg |= CPOL;
 997         if (spi->mode & SPI_CPHA)
 998                 chip->ctl_reg |= CPHA;
 999         if (spi->mode & SPI_LSB_FIRST)
1000                 chip->ctl_reg |= LSBF;
1001         /* we dont support running in slave mode (yet?) */
1002         chip->ctl_reg |= MSTR;
1003
1004         /*
1005          * if any one SPI chip is registered and wants DMA, request the
1006          * DMA channel for it
1007          */
1008         if (chip->enable_dma && !dma_requested) {
1009                 /* register dma irq handler */
1010                 if (request_dma(CH_SPI, "BF53x_SPI_DMA") < 0) {
1011                         dev_dbg(&spi->dev,
1012                                 "Unable to request BlackFin SPI DMA channel\n");
1013                         return -ENODEV;
1014                 }
1015                 if (set_dma_callback(CH_SPI, (void *)dma_irq_handler, drv_data)
1016                     < 0) {
1017                         dev_dbg(&spi->dev, "Unable to set dma callback\n");
1018                         return -EPERM;
1019                 }
1020                 dma_disable_irq(CH_SPI);
1021                 dma_requested = 1;
1022         }
1023
1024         /*
1025          * Notice: for blackfin, the speed_hz is the value of register
1026          * SPI_BAUD, not the real baudrate
1027          */
1028         chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1029         spi_flg = ~(1 << (spi->chip_select));
1030         chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1031         chip->chip_select_num = spi->chip_select;
1032
1033         switch (chip->bits_per_word) {
1034         case 8:
1035                 chip->n_bytes = 1;
1036                 chip->width = CFG_SPI_WORDSIZE8;
1037                 chip->read = chip->cs_change_per_word ?
1038                         u8_cs_chg_reader : u8_reader;
1039                 chip->write = chip->cs_change_per_word ?
1040                         u8_cs_chg_writer : u8_writer;
1041                 chip->duplex = chip->cs_change_per_word ?
1042                         u8_cs_chg_duplex : u8_duplex;
1043                 break;
1044
1045         case 16:
1046                 chip->n_bytes = 2;
1047                 chip->width = CFG_SPI_WORDSIZE16;
1048                 chip->read = chip->cs_change_per_word ?
1049                         u16_cs_chg_reader : u16_reader;
1050                 chip->write = chip->cs_change_per_word ?
1051                         u16_cs_chg_writer : u16_writer;
1052                 chip->duplex = chip->cs_change_per_word ?
1053                         u16_cs_chg_duplex : u16_duplex;
1054                 break;
1055
1056         default:
1057                 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1058                                 chip->bits_per_word);
1059                 kfree(chip);
1060                 return -ENODEV;
1061         }
1062
1063         dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1064                         spi->modalias, chip->width, chip->enable_dma);
1065         dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1066                         chip->ctl_reg, chip->flag);
1067
1068         spi_set_ctldata(spi, chip);
1069
1070         return 0;
1071 }
1072
1073 /*
1074  * callback for spi framework.
1075  * clean driver specific data
1076  */
1077 static void cleanup(struct spi_device *spi)
1078 {
1079         struct chip_data *chip = spi_get_ctldata(spi);
1080
1081         kfree(chip);
1082 }
1083
1084 static inline int init_queue(struct driver_data *drv_data)
1085 {
1086         INIT_LIST_HEAD(&drv_data->queue);
1087         spin_lock_init(&drv_data->lock);
1088
1089         drv_data->run = QUEUE_STOPPED;
1090         drv_data->busy = 0;
1091
1092         /* init transfer tasklet */
1093         tasklet_init(&drv_data->pump_transfers,
1094                      pump_transfers, (unsigned long)drv_data);
1095
1096         /* init messages workqueue */
1097         INIT_WORK(&drv_data->pump_messages, pump_messages);
1098         drv_data->workqueue =
1099             create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
1100         if (drv_data->workqueue == NULL)
1101                 return -EBUSY;
1102
1103         return 0;
1104 }
1105
1106 static inline int start_queue(struct driver_data *drv_data)
1107 {
1108         unsigned long flags;
1109
1110         spin_lock_irqsave(&drv_data->lock, flags);
1111
1112         if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1113                 spin_unlock_irqrestore(&drv_data->lock, flags);
1114                 return -EBUSY;
1115         }
1116
1117         drv_data->run = QUEUE_RUNNING;
1118         drv_data->cur_msg = NULL;
1119         drv_data->cur_transfer = NULL;
1120         drv_data->cur_chip = NULL;
1121         spin_unlock_irqrestore(&drv_data->lock, flags);
1122
1123         queue_work(drv_data->workqueue, &drv_data->pump_messages);
1124
1125         return 0;
1126 }
1127
1128 static inline int stop_queue(struct driver_data *drv_data)
1129 {
1130         unsigned long flags;
1131         unsigned limit = 500;
1132         int status = 0;
1133
1134         spin_lock_irqsave(&drv_data->lock, flags);
1135
1136         /*
1137          * This is a bit lame, but is optimized for the common execution path.
1138          * A wait_queue on the drv_data->busy could be used, but then the common
1139          * execution path (pump_messages) would be required to call wake_up or
1140          * friends on every SPI message. Do this instead
1141          */
1142         drv_data->run = QUEUE_STOPPED;
1143         while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1144                 spin_unlock_irqrestore(&drv_data->lock, flags);
1145                 msleep(10);
1146                 spin_lock_irqsave(&drv_data->lock, flags);
1147         }
1148
1149         if (!list_empty(&drv_data->queue) || drv_data->busy)
1150                 status = -EBUSY;
1151
1152         spin_unlock_irqrestore(&drv_data->lock, flags);
1153
1154         return status;
1155 }
1156
1157 static inline int destroy_queue(struct driver_data *drv_data)
1158 {
1159         int status;
1160
1161         status = stop_queue(drv_data);
1162         if (status != 0)
1163                 return status;
1164
1165         destroy_workqueue(drv_data->workqueue);
1166
1167         return 0;
1168 }
1169
1170 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1171 {
1172         struct device *dev = &pdev->dev;
1173         struct bfin5xx_spi_master *platform_info;
1174         struct spi_master *master;
1175         struct driver_data *drv_data = 0;
1176         int status = 0;
1177
1178         platform_info = dev->platform_data;
1179
1180         /* Allocate master with space for drv_data */
1181         master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1182         if (!master) {
1183                 dev_err(&pdev->dev, "can not alloc spi_master\n");
1184                 return -ENOMEM;
1185         }
1186
1187         if (peripheral_request(P_SPI0_SCK, DRV_NAME) ||
1188                  peripheral_request(P_SPI0_MISO, DRV_NAME) ||
1189                  peripheral_request(P_SPI0_MOSI, DRV_NAME)) {
1190
1191                 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1192                 goto out_error_queue_alloc;
1193         }
1194
1195         drv_data = spi_master_get_devdata(master);
1196         drv_data->master = master;
1197         drv_data->master_info = platform_info;
1198         drv_data->pdev = pdev;
1199
1200         master->bus_num = pdev->id;
1201         master->num_chipselect = platform_info->num_chipselect;
1202         master->cleanup = cleanup;
1203         master->setup = setup;
1204         master->transfer = transfer;
1205
1206         /* Initial and start queue */
1207         status = init_queue(drv_data);
1208         if (status != 0) {
1209                 dev_err(&pdev->dev, "problem initializing queue\n");
1210                 goto out_error_queue_alloc;
1211         }
1212         status = start_queue(drv_data);
1213         if (status != 0) {
1214                 dev_err(&pdev->dev, "problem starting queue\n");
1215                 goto out_error_queue_alloc;
1216         }
1217
1218         /* Register with the SPI framework */
1219         platform_set_drvdata(pdev, drv_data);
1220         status = spi_register_master(master);
1221         if (status != 0) {
1222                 dev_err(&pdev->dev, "problem registering spi master\n");
1223                 goto out_error_queue_alloc;
1224         }
1225         dev_dbg(&pdev->dev, "controller probe successfully\n");
1226         return status;
1227
1228       out_error_queue_alloc:
1229         destroy_queue(drv_data);
1230         spi_master_put(master);
1231         return status;
1232 }
1233
1234 /* stop hardware and remove the driver */
1235 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1236 {
1237         struct driver_data *drv_data = platform_get_drvdata(pdev);
1238         int status = 0;
1239
1240         if (!drv_data)
1241                 return 0;
1242
1243         /* Remove the queue */
1244         status = destroy_queue(drv_data);
1245         if (status != 0)
1246                 return status;
1247
1248         /* Disable the SSP at the peripheral and SOC level */
1249         bfin_spi_disable(drv_data);
1250
1251         /* Release DMA */
1252         if (drv_data->master_info->enable_dma) {
1253                 if (dma_channel_active(CH_SPI))
1254                         free_dma(CH_SPI);
1255         }
1256
1257         /* Disconnect from the SPI framework */
1258         spi_unregister_master(drv_data->master);
1259
1260         /* Prevent double remove */
1261         platform_set_drvdata(pdev, NULL);
1262
1263         return 0;
1264 }
1265
1266 #ifdef CONFIG_PM
1267 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1268 {
1269         struct driver_data *drv_data = platform_get_drvdata(pdev);
1270         int status = 0;
1271
1272         status = stop_queue(drv_data);
1273         if (status != 0)
1274                 return status;
1275
1276         /* stop hardware */
1277         bfin_spi_disable(drv_data);
1278
1279         return 0;
1280 }
1281
1282 static int bfin5xx_spi_resume(struct platform_device *pdev)
1283 {
1284         struct driver_data *drv_data = platform_get_drvdata(pdev);
1285         int status = 0;
1286
1287         /* Enable the SPI interface */
1288         bfin_spi_enable(drv_data);
1289
1290         /* Start the queue running */
1291         status = start_queue(drv_data);
1292         if (status != 0) {
1293                 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1294                 return status;
1295         }
1296
1297         return 0;
1298 }
1299 #else
1300 #define bfin5xx_spi_suspend NULL
1301 #define bfin5xx_spi_resume NULL
1302 #endif                          /* CONFIG_PM */
1303
1304 MODULE_ALIAS("bfin-spi-master");        /* for platform bus hotplug */
1305 static struct platform_driver bfin5xx_spi_driver = {
1306         .driver = {
1307                 .name   = "bfin-spi-master",
1308                 .owner  = THIS_MODULE,
1309         },
1310         .suspend        = bfin5xx_spi_suspend,
1311         .resume         = bfin5xx_spi_resume,
1312         .remove         = __devexit_p(bfin5xx_spi_remove),
1313 };
1314
1315 static int __init bfin5xx_spi_init(void)
1316 {
1317         return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1318 }
1319 module_init(bfin5xx_spi_init);
1320
1321 static void __exit bfin5xx_spi_exit(void)
1322 {
1323         platform_driver_unregister(&bfin5xx_spi_driver);
1324 }
1325 module_exit(bfin5xx_spi_exit);