drivers/spi/omap2_mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *         Juha Yrjölä <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34
  35 #include <linux/spi/spi.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/arch/dma.h>
  39 #include <asm/arch/mcspi.h>
  40
  41 #define OMAP2_MCSPI_MAX_FREQ            48000000
  42
  43 #define OMAP2_MCSPI_REVISION            0x00
  44 #define OMAP2_MCSPI_SYSCONFIG           0x10
  45 #define OMAP2_MCSPI_SYSSTATUS           0x14
  46 #define OMAP2_MCSPI_IRQSTATUS           0x18
  47 #define OMAP2_MCSPI_IRQENABLE           0x1c
  48 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  49 #define OMAP2_MCSPI_SYST                0x24
  50 #define OMAP2_MCSPI_MODULCTRL           0x28
  51 #define OMAP2_MCSPI_CHCONF0             0x2c
  52 #define OMAP2_MCSPI_CHSTAT0             0x30
  53 #define OMAP2_MCSPI_CHCTRL0             0x34
  54 #define OMAP2_MCSPI_TX0                 0x38
  55 #define OMAP2_MCSPI_RX0                 0x3c
  56
  57 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
  58
  59 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
  60
  61 #define OMAP2_MCSPI_MODULCTRL_SINGLE    (1 << 0)
  62 #define OMAP2_MCSPI_MODULCTRL_MS        (1 << 2)
  63 #define OMAP2_MCSPI_MODULCTRL_STEST     (1 << 3)
  64
  65 #define OMAP2_MCSPI_CHCONF_PHA          (1 << 0)
  66 #define OMAP2_MCSPI_CHCONF_POL          (1 << 1)
  67 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  68 #define OMAP2_MCSPI_CHCONF_EPOL         (1 << 6)
  69 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  70 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  (0x01 << 12)
  71 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  (0x02 << 12)
  72 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  73 #define OMAP2_MCSPI_CHCONF_DMAW         (1 << 14)
  74 #define OMAP2_MCSPI_CHCONF_DMAR         (1 << 15)
  75 #define OMAP2_MCSPI_CHCONF_DPE0         (1 << 16)
  76 #define OMAP2_MCSPI_CHCONF_DPE1         (1 << 17)
  77 #define OMAP2_MCSPI_CHCONF_IS           (1 << 18)
  78 #define OMAP2_MCSPI_CHCONF_TURBO        (1 << 19)
  79 #define OMAP2_MCSPI_CHCONF_FORCE        (1 << 20)
  80
  81
  82 #define OMAP2_MCSPI_CHSTAT_RXS          (1 << 0)
  83 #define OMAP2_MCSPI_CHSTAT_TXS          (1 << 1)
  84 #define OMAP2_MCSPI_CHSTAT_EOT          (1 << 2)
  85
  86 #define OMAP2_MCSPI_CHCTRL_EN           (1 << 0)
  87
  88 /* We have 2 DMA channels per CS, one for RX and one for TX */
  89 struct omap2_mcspi_dma {
  90         int dma_tx_channel;
  91         int dma_rx_channel;
  92
  93         int dma_tx_sync_dev;
  94         int dma_rx_sync_dev;
  95
  96         struct completion dma_tx_completion;
  97         struct completion dma_rx_completion;
  98 };
  99
 100 struct omap2_mcspi {
 101         struct work_struct      work;
 102         spinlock_t              lock;
 103         struct list_head        msg_queue;
 104         struct spi_master       *master;
 105         struct clk              *ick;
 106         struct clk              *fck;
 107         /* Virtual base address of the controller */
 108         unsigned long           base;
 109         /* SPI1 has 4 channels, while SPI2 has 2 */
 110         struct omap2_mcspi_dma  *dma_channels;
 111 };
 112
 113 struct omap2_mcspi_cs {
 114         u8 transmit_mode;
 115         int word_len;
 116 };
 117
 118 static struct workqueue_struct * omap2_mcspi_wq;
 119
 120 #define MOD_REG_BIT(val, mask, set) do { \
 121         if (set) \
 122                 val |= mask; \
 123         else \
 124                 val &= ~mask; \
 125 } while(0)
 126
 127 static inline void mcspi_write_reg(struct spi_master *master,
 128                                    int idx, u32 val)
 129 {
 130         struct omap2_mcspi * mcspi = class_get_devdata(&master->cdev);
 131
 132         __raw_writel(val, mcspi->base + idx);
 133 }
 134
 135 static inline u32 mcspi_read_reg(struct spi_master *master,
 136                                  int idx)
 137 {
 138         struct omap2_mcspi * mcspi = class_get_devdata(&master->cdev);
 139
 140         return __raw_readl(mcspi->base + idx);
 141 }
 142
 143 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 144                                       int idx, u32 val)
 145 {
 146         struct omap2_mcspi * mcspi = class_get_devdata(&spi->master->cdev);
 147
 148         __raw_writel(val, mcspi->base + spi->chip_select * 0x14 + idx);
 149 }
 150
 151 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi,
 152                                     int idx)
 153 {
 154         struct omap2_mcspi * mcspi = class_get_devdata(&spi->master->cdev);
 155
 156         return __raw_readl(mcspi->base + spi->chip_select * 0x14 + idx);
 157 }
 158
 159 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 160                                     int is_read, int enable)
 161 {
 162         u32 l, rw;
 163
 164         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 165
 166         if (is_read) /* 1 is read, 0 write */
 167                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 168         else
 169                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 170
 171         MOD_REG_BIT(l, rw, enable);
 172         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 173 }
 174
 175 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 176 {
 177         u32 l;
 178
 179         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 180         MOD_REG_BIT(l, OMAP2_MCSPI_CHCTRL_EN, enable);
 181         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 182 }
 183
 184 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 185 {
 186         u32 l;
 187
 188         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 189         MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
 190         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 191 }
 192
 193 static void omap2_mcspi_set_master_mode(struct spi_device *spi, int single_channel)
 194 {
 195         u32 l;
 196
 197         /* Need reset when switching from slave mode */
 198         l = mcspi_read_reg(spi->master, OMAP2_MCSPI_MODULCTRL);
 199         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
 200         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
 201         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, single_channel);
 202         mcspi_write_reg(spi->master, OMAP2_MCSPI_MODULCTRL, l);
 203 }
 204
 205 static void omap2_mcspi_txrx_dma(struct spi_device *spi,
 206                                  struct spi_transfer *xfer)
 207 {
 208         struct omap2_mcspi      * mcspi;
 209         struct omap2_mcspi_cs   * cs = spi->controller_state;
 210         struct omap2_mcspi_dma  * mcspi_dma;
 211         unsigned int            count, c;
 212         unsigned long           base, tx_reg, rx_reg;
 213         int                     word_len, data_type, element_count;
 214         u8                      * rx;
 215         const u8                * tx;
 216         u32                     l;
 217
 218         mcspi = class_get_devdata(&spi->master->cdev);
 219         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 220
 221         count = xfer->len;
 222         c = count;
 223         word_len = cs->word_len;
 224
 225         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 226         l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 227         if (xfer->tx_buf == NULL)
 228                 l |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 229         else if (xfer->rx_buf == NULL)
 230                 l |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 231         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 232
 233         omap2_mcspi_set_enable(spi, 1);
 234
 235         base = io_v2p(mcspi->base) + spi->chip_select * 0x14;
 236         tx_reg = base + OMAP2_MCSPI_TX0;
 237         rx_reg = base + OMAP2_MCSPI_RX0;
 238         rx = xfer->rx_buf;
 239         tx = xfer->tx_buf;
 240
 241         if (word_len <= 8) {
 242                 data_type = OMAP_DMA_DATA_TYPE_S8;
 243                 element_count = count;
 244         } else if (word_len <= 16) {
 245                 data_type = OMAP_DMA_DATA_TYPE_S16;
 246                 element_count = count >> 1;
 247         } else if (word_len <= 32) {
 248                 data_type = OMAP_DMA_DATA_TYPE_S32;
 249                 element_count = count >> 2;
 250         } else
 251                 return;
 252
 253         /* RX_ONLY mode needs dummy data in TX reg */
 254         if (tx == NULL)
 255                 __raw_writel(0, mcspi->base +
 256                              spi->chip_select * 0x14 + OMAP2_MCSPI_TX0);
 257
 258         if (tx != NULL) {
 259                 xfer->tx_dma = dma_map_single(&spi->dev, (void *) tx, count,
 260                                               DMA_TO_DEVICE);
 261                 if (dma_mapping_error(xfer->tx_dma)) {
 262                         printk(KERN_ERR "%s(): Couldn't DMA map a %d bytes TX buffer\n",
 263                                __FUNCTION__, count);
 264                         return;
 265                 }
 266
 267                 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
 268                                              data_type, element_count, 1,
 269                                              OMAP_DMA_SYNC_ELEMENT,
 270                                              mcspi_dma->dma_tx_sync_dev, 0);
 271
 272                 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
 273                                          OMAP_DMA_AMODE_CONSTANT,
 274                                          tx_reg, 0, 0);
 275
 276                 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
 277                                         OMAP_DMA_AMODE_POST_INC,
 278                                         xfer->tx_dma, 0, 0);
 279         }
 280
 281         if (rx != NULL) {
 282                 xfer->rx_dma = dma_map_single(&spi->dev, rx, count,
 283                                               DMA_FROM_DEVICE);
 284                 if (dma_mapping_error(xfer->rx_dma)) {
 285                         printk(KERN_ERR "%s(): Couldn't DMA map a %d bytes RX buffer\n",
 286                                __FUNCTION__, count);
 287                         if (tx != NULL)
 288                                 dma_unmap_single(NULL, xfer->tx_dma,
 289                                                  count, DMA_TO_DEVICE);
 290                         return;
 291                 }
 292
 293                 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
 294                                              data_type, element_count, 1,
 295                                              OMAP_DMA_SYNC_ELEMENT,
 296                                              mcspi_dma->dma_rx_sync_dev, 1);
 297
 298                 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
 299                                         OMAP_DMA_AMODE_CONSTANT,
 300                                         rx_reg, 0, 0);
 301
 302                 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
 303                                          OMAP_DMA_AMODE_POST_INC,
 304                                          xfer->rx_dma, 0, 0);
 305         }
 306
 307         if (tx != NULL) {
 308                 omap_start_dma(mcspi_dma->dma_tx_channel);
 309                 omap2_mcspi_set_dma_req(spi, 0, 1);
 310         }
 311
 312         if (rx != NULL) {
 313                 omap_start_dma(mcspi_dma->dma_rx_channel);
 314                 omap2_mcspi_set_dma_req(spi, 1, 1);
 315         }
 316
 317         if (tx != NULL) {
 318                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 319                 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
 320         }
 321
 322         if (rx != NULL) {
 323                 wait_for_completion(&mcspi_dma->dma_rx_completion);
 324                 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
 325         }
 326
 327         omap2_mcspi_set_enable(spi, 0);
 328 }
 329
 330 static void omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 331 {
 332         struct omap2_mcspi * mcspi;
 333         struct omap2_mcspi_cs *cs = spi->controller_state;
 334         unsigned int            count, c;
 335         u32                     l;
 336         unsigned long           base, tx_reg, rx_reg, chstat_reg;
 337         int                     word_len;
 338
 339         mcspi = class_get_devdata(&spi->master->cdev);
 340         count = xfer->len;
 341         c = count;
 342         word_len = cs->word_len;
 343
 344         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 345         l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 346         if (xfer->tx_buf == NULL)
 347                 l |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 348         else if (xfer->rx_buf == NULL)
 349                 l |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 350         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 351
 352         omap2_mcspi_set_enable(spi, 1);
 353
 354         /* We store the pre-calculated register addresses on stack to speed
 355          * up the transfer loop. */
 356         base = mcspi->base + spi->chip_select * 0x14;
 357         tx_reg          = base + OMAP2_MCSPI_TX0;
 358         rx_reg          = base + OMAP2_MCSPI_RX0;
 359         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 360
 361         /* RX_ONLY mode needs dummy data in TX reg */
 362         if (xfer->tx_buf == NULL)
 363                 __raw_writel(0, tx_reg);
 364
 365         if (word_len <= 8) {
 366                 u8              *rx;
 367                 const u8        *tx;
 368
 369                 rx = xfer->rx_buf;
 370                 tx = xfer->tx_buf;
 371
 372                 while (c--) {
 373                         if (tx != NULL) {
 374                                 while (!(__raw_readl(chstat_reg) & OMAP2_MCSPI_CHSTAT_TXS));
 375 #ifdef VERBOSE
 376                                 dev_dbg(&spi->dev, "write-%d %02x\n",
 377                                                 word_len, *tx);
 378 #endif
 379                                 __raw_writel(*tx, tx_reg);
 380                         }
 381                         if (rx != NULL) {
 382                                 while (!(__raw_readl(chstat_reg) & OMAP2_MCSPI_CHSTAT_RXS));
 383                                 if (c == 0 && tx == NULL)
 384                                         omap2_mcspi_set_enable(spi, 0);
 385                                 *rx++ = __raw_readl(rx_reg);
 386 #ifdef VERBOSE
 387                                 dev_dbg(&spi->dev, "read-%d %02x\n",
 388                                                 word_len, *(rx - 1));
 389 #endif
 390                         }
 391                 }
 392         } else if (word_len <= 16) {
 393                 u16             *rx;
 394                 const u16       *tx;
 395
 396                 rx = xfer->rx_buf;
 397                 tx = xfer->tx_buf;
 398                 c >>= 1;
 399                 while (c--) {
 400                         if (tx != NULL) {
 401                                 while (!(__raw_readl(chstat_reg) & OMAP2_MCSPI_CHSTAT_TXS));
 402 #ifdef VERBOSE
 403                                 dev_dbg(&spi->dev, "write-%d %04x\n",
 404                                                 word_len, *tx);
 405 #endif
 406                                 __raw_writel(*tx++, tx_reg);
 407                         }
 408                         if (rx != NULL) {
 409                                 while (!(__raw_readl(chstat_reg) & OMAP2_MCSPI_CHSTAT_RXS));
 410                                 if (c == 0 && tx == NULL)
 411                                         omap2_mcspi_set_enable(spi, 0);
 412                                 *rx++ = __raw_readl(rx_reg);
 413 #ifdef VERBOSE
 414                                 dev_dbg(&spi->dev, "read-%d %04x\n",
 415                                                 word_len, *(rx - 1));
 416 #endif
 417                         }
 418                 }
 419         } else if (word_len <= 32) {
 420                 u32             *rx;
 421                 const u32       *tx;
 422
 423                 rx = xfer->rx_buf;
 424                 tx = xfer->tx_buf;
 425                 c >>= 2;
 426                 while (c--) {
 427                         if (tx != NULL) {
 428                                 while (!(__raw_readl(chstat_reg) & OMAP2_MCSPI_CHSTAT_TXS));
 429 #ifdef VERBOSE
 430                                 dev_dbg(&spi->dev, "write-%d %04x\n",
 431                                                 word_len, *tx);
 432 #endif
 433                                 __raw_writel(*tx++, tx_reg);
 434                         }
 435                         if (rx != NULL) {
 436                                 while (!(__raw_readl(chstat_reg) & OMAP2_MCSPI_CHSTAT_RXS));
 437                                 if (c == 0 && tx == NULL)
 438                                         omap2_mcspi_set_enable(spi, 0);
 439                                 *rx++ = __raw_readl(rx_reg);
 440 #ifdef VERBOSE
 441                                 dev_dbg(&spi->dev, "read-%d %04x\n",
 442                                                 word_len, *(rx - 1));
 443 #endif
 444                         }
 445                 }
 446         }
 447
 448         if (xfer->tx_buf != NULL) {
 449                 while (!(__raw_readl(chstat_reg) & OMAP2_MCSPI_CHSTAT_TXS));
 450                 while (!(__raw_readl(chstat_reg) & OMAP2_MCSPI_CHSTAT_EOT));
 451                 omap2_mcspi_set_enable(spi, 0);
 452         }
 453 }
 454
 455 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 456                                       struct spi_transfer *t)
 457 {
 458         struct omap2_mcspi_cs *cs = spi->controller_state;
 459         struct omap2_mcspi_device_config *conf;
 460         u32 l = 0, div = 0;
 461         u8 word_len = spi->bits_per_word;
 462
 463         if (t != NULL && t->bits_per_word)
 464                 word_len = t->bits_per_word;
 465         if (!word_len)
 466                 word_len = 8;
 467
 468         if (spi->bits_per_word > 32)
 469                 return -EINVAL;
 470         cs->word_len = word_len;
 471
 472         conf = (struct omap2_mcspi_device_config *) spi->controller_data;
 473
 474         if (conf->single_channel == 1)
 475                 omap2_mcspi_set_master_mode(spi, 1);
 476         else
 477                 omap2_mcspi_set_master_mode(spi, 0);
 478
 479         if (spi->max_speed_hz) {
 480                 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div)) > spi->max_speed_hz)
 481                         div++;
 482         } else
 483                 div = 15;
 484
 485         if (spi->chip_select > 3 ||
 486             word_len < 4 || word_len > 32 ||
 487             div > 15) {
 488                 dev_err(&spi->dev, "Invalid McSPI channel setting\n");
 489                 return -EINVAL;
 490         }
 491
 492         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 493         l &= ~OMAP2_MCSPI_CHCONF_IS;
 494         l &= ~OMAP2_MCSPI_CHCONF_DPE1;
 495         l |= OMAP2_MCSPI_CHCONF_DPE0;
 496         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 497         l |= (word_len - 1) << 7;
 498         if (!(spi->mode & SPI_CS_HIGH))
 499                 l |= OMAP2_MCSPI_CHCONF_EPOL;
 500         else
 501                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 502         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 503         l |= div << 2;
 504         if (spi->mode & SPI_CPOL)
 505                 l |= OMAP2_MCSPI_CHCONF_POL;
 506         else
 507                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 508         if (spi->mode & SPI_CPHA)
 509                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 510         else
 511                 l |= OMAP2_MCSPI_CHCONF_PHA;
 512         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 513
 514         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s inverted\n",
 515                         OMAP2_MCSPI_MAX_FREQ / (1 << div),
 516                         (spi->mode & SPI_CPHA) ? "odd" : "even",
 517                         (spi->mode & SPI_CPOL) ? "" : "not");
 518
 519         return 0;
 520 }
 521
 522 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
 523 {
 524         struct spi_device * spi = (struct spi_device *)data;
 525         struct omap2_mcspi * mcspi;
 526         struct omap2_mcspi_dma * mcspi_dma;
 527
 528         mcspi = class_get_devdata(&spi->master->cdev);
 529         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 530
 531         complete(&mcspi_dma->dma_rx_completion);
 532
 533         /* We must disable the DMA RX request */
 534         omap2_mcspi_set_dma_req(spi, 1, 0);
 535 }
 536
 537 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
 538 {
 539         struct spi_device * spi = (struct spi_device *)data;
 540         struct omap2_mcspi * mcspi;
 541         struct omap2_mcspi_dma * mcspi_dma;
 542
 543         mcspi = class_get_devdata(&spi->master->cdev);
 544         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 545
 546         complete(&mcspi_dma->dma_tx_completion);
 547
 548         /* We must disable the DMA TX request */
 549         omap2_mcspi_set_dma_req(spi, 0, 0);
 550 }
 551
 552 static int omap2_mcspi_request_dma(struct spi_device *spi)
 553 {
 554         int rx_dev_id, tx_dev_id;
 555         struct spi_master *master = spi->master;
 556         struct omap2_mcspi * mcspi;
 557         struct omap2_mcspi_dma * mcspi_dma;
 558
 559         mcspi = class_get_devdata(&master->cdev);
 560         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 561
 562         if (master->bus_num == 1) {
 563                 switch (spi->chip_select) {
 564                 case 0:
 565                         rx_dev_id = OMAP24XX_DMA_SPI1_RX0;
 566                         tx_dev_id = OMAP24XX_DMA_SPI1_TX0;
 567                         break;
 568                 case 1:
 569                         rx_dev_id = OMAP24XX_DMA_SPI1_RX1;
 570                         tx_dev_id = OMAP24XX_DMA_SPI1_TX1;
 571                         break;
 572                 case 2:
 573                         rx_dev_id = OMAP24XX_DMA_SPI1_RX2;
 574                         tx_dev_id = OMAP24XX_DMA_SPI1_TX2;
 575                         break;
 576                 case 3:
 577                         rx_dev_id = OMAP24XX_DMA_SPI1_RX3;
 578                         tx_dev_id = OMAP24XX_DMA_SPI1_TX3;
 579                         break;
 580                 default:
 581                         return -EINVAL;
 582                 }
 583         } else if (master->bus_num == 2) {
 584                 /* McSPI 2 has 1 chipselect */
 585                 switch (spi->chip_select) {
 586                 case 0:
 587                         rx_dev_id = OMAP24XX_DMA_SPI2_RX0;
 588                         tx_dev_id = OMAP24XX_DMA_SPI2_TX0;
 589                         break;
 590                 case 1:
 591                         rx_dev_id = OMAP24XX_DMA_SPI2_RX1;
 592                         tx_dev_id = OMAP24XX_DMA_SPI2_TX1;
 593                         break;
 594                 default:
 595                         return -EINVAL;
 596                 }
 597         } else
 598                 return -EINVAL;
 599
 600
 601         if (omap_request_dma(rx_dev_id, "McSPI RX",
 602                              omap2_mcspi_dma_rx_callback, spi,
 603                              &mcspi_dma->dma_rx_channel)) {
 604                 printk(KERN_ERR "Unable to request DMA channel for McSPI RX\n");
 605                 return -EAGAIN;
 606         }
 607
 608         if (omap_request_dma(tx_dev_id, "McSPI TX",
 609                              omap2_mcspi_dma_tx_callback, spi,
 610                              &mcspi_dma->dma_tx_channel)) {
 611                 omap_free_dma(mcspi_dma->dma_rx_channel);
 612                 mcspi_dma->dma_rx_channel = -1;
 613                 printk(KERN_ERR "Unable to request DMA channel for McSPI TX\n");
 614                 return -EAGAIN;
 615         }
 616
 617         mcspi_dma->dma_rx_sync_dev = rx_dev_id;
 618         mcspi_dma->dma_tx_sync_dev = tx_dev_id;
 619
 620         init_completion(&mcspi_dma->dma_rx_completion);
 621         init_completion(&mcspi_dma->dma_tx_completion);
 622
 623         return 0;
 624 }
 625
 626 static int omap2_mcspi_setup(struct spi_device *spi)
 627 {
 628         int ret;
 629         struct omap2_mcspi * mcspi;
 630         struct omap2_mcspi_dma * mcspi_dma;
 631         struct omap2_mcspi_cs *cs = spi->controller_state;
 632
 633         mcspi = class_get_devdata(&spi->master->cdev);
 634         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 635
 636         if (!cs) {
 637                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 638                 if (!cs)
 639                         return -ENOMEM;
 640                 spi->controller_state = cs;
 641         }
 642
 643         if (mcspi_dma->dma_rx_channel == -1 ||
 644             mcspi_dma->dma_tx_channel == -1) {
 645                 ret = omap2_mcspi_request_dma(spi);
 646                 if (ret < 0)
 647                         return ret;
 648         }
 649
 650         return omap2_mcspi_setup_transfer(spi, NULL);
 651 }
 652
 653 static void omap2_mcspi_cleanup(struct spi_device *spi)
 654 {
 655         struct omap2_mcspi * mcspi;
 656         struct omap2_mcspi_dma * mcspi_dma;
 657
 658         mcspi = class_get_devdata(&spi->master->cdev);
 659         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 660
 661         if (spi->controller_state != NULL)
 662                 kfree(spi->controller_state);
 663
 664         if (mcspi_dma->dma_rx_channel != -1 &&
 665             mcspi_dma->dma_tx_channel != -1) {
 666                 omap_free_dma(mcspi_dma->dma_tx_channel);
 667                 omap_free_dma(mcspi_dma->dma_rx_channel);
 668         }
 669 }
 670
 671
 672 static void omap2_mcspi_work(struct work_struct *work)
 673 {
 674         struct omap2_mcspi      *mcspi = container_of(work, struct omap2_mcspi, work);
 675         unsigned long           flags;
 676
 677         spin_lock_irqsave(&mcspi->lock, flags);
 678         while (!list_empty(&mcspi->msg_queue)) {
 679                 struct spi_message              *m;
 680                 struct spi_device               *spi;
 681                 struct spi_transfer             *t = NULL;
 682                 int                             cs_active = 0;
 683                 struct omap2_mcspi_device_config *conf;
 684                 struct omap2_mcspi_cs           *cs;
 685                 int                             par_override = 0;
 686                 int status = 0;
 687
 688                 m = container_of(mcspi->msg_queue.next, struct spi_message,
 689                                  queue);
 690
 691                 list_del_init(&m->queue);
 692                 spin_unlock_irqrestore(&mcspi->lock, flags);
 693
 694                 spi = m->spi;
 695                 conf = (struct omap2_mcspi_device_config *) spi->controller_data;
 696                 cs = (struct omap2_mcspi_cs *) spi->controller_state;
 697
 698                 list_for_each_entry(t, &m->transfers, transfer_list) {
 699                         if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 700                                 status = -EINVAL;
 701                                 break;
 702                         }
 703                         if (par_override || t->speed_hz || t->bits_per_word) {
 704                                 par_override = 1;
 705                                 status = omap2_mcspi_setup_transfer(spi, t);
 706                                 if (status < 0)
 707                                         break;
 708                                 if (!t->speed_hz && !t->bits_per_word)
 709                                         par_override = 0;
 710                         }
 711
 712                         if (!cs_active) {
 713                                 omap2_mcspi_force_cs(spi, 1);
 714                                 cs_active = 1;
 715                         }
 716
 717                         if (m->is_dma_mapped &&
 718                             (t->tx_dma != 0 || t->rx_dma != 0))
 719                                 omap2_mcspi_txrx_dma(spi, t);
 720                         else
 721                                 omap2_mcspi_txrx_pio(spi, t);
 722
 723                         if (t->cs_change) {
 724                                 /* In the last transfer entry the flag means
 725                                  * _leave_ CS on */
 726                                 if (t->transfer_list.next != &m->transfers)
 727                                         omap2_mcspi_force_cs(spi, 0);
 728                                 cs_active = 0;
 729                         }
 730                 }
 731
 732                 /* Restore defaults they are overriden */
 733                 if (par_override) {
 734                         par_override = 0;
 735                         status = omap2_mcspi_setup_transfer(spi, NULL);
 736                 }
 737
 738                 if (cs_active)
 739                         omap2_mcspi_force_cs(spi, 0);
 740
 741                 m->status = status;
 742                 m->complete(m->context);
 743
 744                 spin_lock_irqsave(&mcspi->lock, flags);
 745         }
 746         spin_unlock_irqrestore(&mcspi->lock, flags);
 747 }
 748
 749 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
 750 {
 751         struct omap2_mcspi      *mcspi;
 752         unsigned long           flags;
 753
 754         m->actual_length = 0;
 755         m->status = 0;
 756
 757         mcspi = class_get_devdata(&spi->master->cdev);
 758
 759         spin_lock_irqsave(&mcspi->lock, flags);
 760         list_add_tail(&m->queue, &mcspi->msg_queue);
 761         spin_unlock_irqrestore(&mcspi->lock, flags);
 762
 763         queue_work(omap2_mcspi_wq, &mcspi->work);
 764
 765         return 0;
 766 }
 767
 768 static int __devinit omap2_mcspi_reset(struct spi_master *master)
 769 {
 770 #if 0
 771         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
 772                         OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
 773         while (!(mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS) & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
 774 #else
 775         return 0;
 776 #endif
 777 }
 778
 779 static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
 780 {
 781         struct spi_master               *master;
 782         struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data;
 783         struct omap2_mcspi              *mcspi;
 784         struct resource                 *r;
 785         int                             status = 0, i;
 786
 787         if (!pdata)
 788                 return -EINVAL;
 789
 790         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
 791         if (master == NULL) {
 792                 dev_err(&pdev->dev, "master allocation failed\n");
 793                 return -ENOMEM;
 794         }
 795
 796         if (pdev->id != -1)
 797                 master->bus_num = pdev->id;
 798
 799         master->setup = omap2_mcspi_setup;
 800         master->transfer = omap2_mcspi_transfer;
 801         master->cleanup = omap2_mcspi_cleanup;
 802         master->num_chipselect = pdata->num_cs;
 803
 804         if (class_device_get(&master->cdev) == NULL) {
 805                 dev_err(&pdev->dev, "no master->cdev");
 806                 status = -ENOMEM;
 807                 goto err0;
 808         }
 809
 810         dev_set_drvdata(&pdev->dev, master);
 811
 812         mcspi = class_get_devdata(&master->cdev);
 813         mcspi->master = master;
 814
 815         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 816         if (r == NULL) {
 817                 status = -ENODEV;
 818                 goto err1;
 819         }
 820
 821         mcspi->base = io_p2v(r->start);
 822
 823         INIT_WORK(&mcspi->work, omap2_mcspi_work);
 824
 825         spin_lock_init(&mcspi->lock);
 826         INIT_LIST_HEAD(&mcspi->msg_queue);
 827
 828         mcspi->ick = clk_get(&pdev->dev, "mcspi_ick");
 829         if (IS_ERR(mcspi->ick)) {
 830                 dev_err(&pdev->dev, "can't get mcspi_ick\n");
 831                 status = PTR_ERR(mcspi->ick);
 832                 goto err1;
 833         }
 834         clk_enable(mcspi->ick);
 835         mcspi->fck = clk_get(&pdev->dev, "mcspi_fck");
 836         if (IS_ERR(mcspi->fck)) {
 837                 dev_err(&pdev->dev, "can't get mcspi_fck\n");
 838                 status = PTR_ERR(mcspi->fck);
 839                 goto err2;
 840         }
 841         clk_enable(mcspi->fck);
 842
 843         mcspi->dma_channels =
 844                 (struct omap2_mcspi_dma *)kzalloc(master->num_chipselect *
 845                                                   sizeof(struct omap2_mcspi_dma),
 846                                                   GFP_KERNEL);
 847
 848         if (mcspi->dma_channels == NULL)
 849                 goto err3;
 850
 851         for (i = 0; i < master->num_chipselect; i++) {
 852                 mcspi->dma_channels[i].dma_rx_channel = -1;
 853                 mcspi->dma_channels[i].dma_tx_channel = -1;
 854         }
 855
 856         if (omap2_mcspi_reset(master) < 0)
 857                 goto err4;
 858
 859         status = spi_register_master(master);
 860         if (status < 0)
 861                 goto err4;
 862
 863         return status;
 864
 865 err4:
 866         kfree(mcspi->dma_channels);
 867 err3:
 868         clk_disable(mcspi->fck);
 869         clk_put(mcspi->fck);
 870 err2:
 871         clk_disable(mcspi->ick);
 872         clk_put(mcspi->ick);
 873 err1:
 874         class_device_put(&master->cdev);
 875 err0:
 876         return status;
 877 }
 878
 879 static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
 880 {
 881         struct spi_master               *master;
 882         struct omap2_mcspi              *mcspi;
 883
 884         master = dev_get_drvdata(&pdev->dev);
 885
 886         spi_unregister_master(master);
 887         mcspi = class_get_devdata(&master->cdev);
 888         clk_disable(mcspi->fck);
 889         clk_put(mcspi->fck);
 890         clk_disable(mcspi->ick);
 891         clk_put(mcspi->ick);
 892         class_device_put(&master->cdev);
 893         kfree(mcspi->dma_channels);
 894
 895         return 0;
 896 }
 897
 898 struct platform_driver omap2_mcspi_driver = {
 899         .driver = {
 900                 .name =         "omap2_mcspi",
 901                 .owner =        THIS_MODULE,
 902         },
 903         .probe =        omap2_mcspi_probe,
 904         .remove =       __devexit_p(omap2_mcspi_remove),
 905 };
 906 EXPORT_SYMBOL_GPL(omap2_mcspi_driver);
 907
 908
 909 static int __init omap2_mcspi_init(void)
 910 {
 911         printk(KERN_INFO "OMAP24xx McSPI driver initializing\n");
 912         omap2_mcspi_wq = create_workqueue("OMAP McSPI");
 913         if (omap2_mcspi_wq == NULL)
 914                 return -1;
 915         return platform_driver_register(&omap2_mcspi_driver);
 916 }
 917 subsys_initcall(omap2_mcspi_init);
 918
 919 static void __exit omap2_mcspi_exit(void)
 920 {
 921         platform_driver_unregister(&omap2_mcspi_driver);
 922 }
 923 module_exit(omap2_mcspi_exit);
 924
 925 MODULE_LICENSE("GPL");