drivers/spi/atmel_spi.c

   1 /*
   2  * Driver for Atmel AT32 and AT91 SPI Controllers
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21
  22 #include <asm/io.h>
  23 #include <asm/arch/board.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/cpu.h>
  26
  27 #include "atmel_spi.h"
  28
  29 /*
  30  * The core SPI transfer engine just talks to a register bank to set up
  31  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
  32  * framework provides the base clock, subdivided for each spi_device.
  33  *
  34  * Newer controllers, marked with "new_1" flag, have:
  35  *  - CR.LASTXFER
  36  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
  37  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
  38  *  - SPI_CSRx.CSAAT
  39  *  - SPI_CSRx.SBCR allows faster clocking
  40  */
  41 struct atmel_spi {
  42         spinlock_t              lock;
  43
  44         void __iomem            *regs;
  45         int                     irq;
  46         struct clk              *clk;
  47         struct platform_device  *pdev;
  48         unsigned                new_1:1;
  49         struct spi_device       *stay;
  50
  51         u8                      stopping;
  52         struct list_head        queue;
  53         struct spi_transfer     *current_transfer;
  54         unsigned long           current_remaining_bytes;
  55         struct spi_transfer     *next_transfer;
  56         unsigned long           next_remaining_bytes;
  57
  58         void                    *buffer;
  59         dma_addr_t              buffer_dma;
  60 };
  61
  62 #define BUFFER_SIZE             PAGE_SIZE
  63 #define INVALID_DMA_ADDRESS     0xffffffff
  64
  65 /*
  66  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
  67  * they assume that spi slave device state will not change on deselect, so
  68  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
  69  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
  70  * controllers have CSAAT and friends.
  71  *
  72  * Since the CSAAT functionality is a bit weird on newer controllers as
  73  * well, we use GPIO to control nCSx pins on all controllers, updating
  74  * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
  75  * support active-high chipselects despite the controller's belief that
  76  * only active-low devices/systems exists.
  77  *
  78  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
  79  * right when driven with GPIO.  ("Mode Fault does not allow more than one
  80  * Master on Chip Select 0.")  No workaround exists for that ... so for
  81  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
  82  * and (c) will trigger that first erratum in some cases.
  83  */
  84
  85 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
  86 {
  87         unsigned gpio = (unsigned) spi->controller_data;
  88         unsigned active = spi->mode & SPI_CS_HIGH;
  89         u32 mr;
  90
  91         mr = spi_readl(as, MR);
  92         mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
  93
  94         dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
  95                         gpio, active ? " (high)" : "",
  96                         mr);
  97
  98         if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
  99                 gpio_set_value(gpio, active);
 100         spi_writel(as, MR, mr);
 101 }
 102
 103 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 104 {
 105         unsigned gpio = (unsigned) spi->controller_data;
 106         unsigned active = spi->mode & SPI_CS_HIGH;
 107         u32 mr;
 108
 109         /* only deactivate *this* device; sometimes transfers to
 110          * another device may be active when this routine is called.
 111          */
 112         mr = spi_readl(as, MR);
 113         if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
 114                 mr = SPI_BFINS(PCS, 0xf, mr);
 115                 spi_writel(as, MR, mr);
 116         }
 117
 118         dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
 119                         gpio, active ? " (low)" : "",
 120                         mr);
 121
 122         if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
 123                 gpio_set_value(gpio, !active);
 124 }
 125
 126 static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
 127                                         struct spi_transfer *xfer)
 128 {
 129         return msg->transfers.prev == &xfer->transfer_list;
 130 }
 131
 132 static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
 133 {
 134         return xfer->delay_usecs == 0 && !xfer->cs_change;
 135 }
 136
 137 static void atmel_spi_next_xfer_data(struct spi_master *master,
 138                                 struct spi_transfer *xfer,
 139                                 dma_addr_t *tx_dma,
 140                                 dma_addr_t *rx_dma,
 141                                 u32 *plen)
 142 {
 143         struct atmel_spi        *as = spi_master_get_devdata(master);
 144         u32                     len = *plen;
 145
 146         /* use scratch buffer only when rx or tx data is unspecified */
 147         if (xfer->rx_buf)
 148                 *rx_dma = xfer->rx_dma + xfer->len - len;
 149         else {
 150                 *rx_dma = as->buffer_dma;
 151                 if (len > BUFFER_SIZE)
 152                         len = BUFFER_SIZE;
 153         }
 154         if (xfer->tx_buf)
 155                 *tx_dma = xfer->tx_dma + xfer->len - len;
 156         else {
 157                 *tx_dma = as->buffer_dma;
 158                 if (len > BUFFER_SIZE)
 159                         len = BUFFER_SIZE;
 160                 memset(as->buffer, 0, len);
 161                 dma_sync_single_for_device(&as->pdev->dev,
 162                                 as->buffer_dma, len, DMA_TO_DEVICE);
 163         }
 164
 165         *plen = len;
 166 }
 167
 168 /*
 169  * Submit next transfer for DMA.
 170  * lock is held, spi irq is blocked
 171  */
 172 static void atmel_spi_next_xfer(struct spi_master *master,
 173                                 struct spi_message *msg)
 174 {
 175         struct atmel_spi        *as = spi_master_get_devdata(master);
 176         struct spi_transfer     *xfer;
 177         u32                     len, remaining, total;
 178         dma_addr_t              tx_dma, rx_dma;
 179
 180         if (!as->current_transfer)
 181                 xfer = list_entry(msg->transfers.next,
 182                                 struct spi_transfer, transfer_list);
 183         else if (!as->next_transfer)
 184                 xfer = list_entry(as->current_transfer->transfer_list.next,
 185                                 struct spi_transfer, transfer_list);
 186         else
 187                 xfer = NULL;
 188
 189         if (xfer) {
 190                 len = xfer->len;
 191                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 192                 remaining = xfer->len - len;
 193
 194                 spi_writel(as, RPR, rx_dma);
 195                 spi_writel(as, TPR, tx_dma);
 196
 197                 if (msg->spi->bits_per_word > 8)
 198                         len >>= 1;
 199                 spi_writel(as, RCR, len);
 200                 spi_writel(as, TCR, len);
 201         } else {
 202                 xfer = as->next_transfer;
 203                 remaining = as->next_remaining_bytes;
 204         }
 205
 206         as->current_transfer = xfer;
 207         as->current_remaining_bytes = remaining;
 208
 209         if (remaining > 0)
 210                 len = remaining;
 211         else if (!atmel_spi_xfer_is_last(msg, xfer) &&
 212                 atmel_spi_xfer_can_be_chained(xfer)) {
 213                 xfer = list_entry(xfer->transfer_list.next,
 214                                 struct spi_transfer, transfer_list);
 215                 len = xfer->len;
 216         } else
 217                 xfer = NULL;
 218
 219         as->next_transfer = xfer;
 220
 221         if (xfer) {
 222                 total = len;
 223                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 224                 as->next_remaining_bytes = total - len;
 225
 226                 spi_writel(as, RNPR, rx_dma);
 227                 spi_writel(as, TNPR, tx_dma);
 228
 229                 if (msg->spi->bits_per_word > 8)
 230                         len >>= 1;
 231                 spi_writel(as, RNCR, len);
 232                 spi_writel(as, TNCR, len);
 233         } else {
 234                 spi_writel(as, RNCR, 0);
 235                 spi_writel(as, TNCR, 0);
 236         }
 237
 238         /* REVISIT: We're waiting for ENDRX before we start the next
 239          * transfer because we need to handle some difficult timing
 240          * issues otherwise. If we wait for ENDTX in one transfer and
 241          * then starts waiting for ENDRX in the next, it's difficult
 242          * to tell the difference between the ENDRX interrupt we're
 243          * actually waiting for and the ENDRX interrupt of the
 244          * previous transfer.
 245          *
 246          * It should be doable, though. Just not now...
 247          */
 248         spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
 249
 250         dev_dbg(&msg->spi->dev,
 251                 "  start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n",
 252                 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
 253                 xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR));
 254
 255         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 256 }
 257
 258 static void atmel_spi_next_message(struct spi_master *master)
 259 {
 260         struct atmel_spi        *as = spi_master_get_devdata(master);
 261         struct spi_message      *msg;
 262         struct spi_device       *spi;
 263
 264         BUG_ON(as->current_transfer);
 265
 266         msg = list_entry(as->queue.next, struct spi_message, queue);
 267         spi = msg->spi;
 268
 269         dev_dbg(master->dev.parent, "start message %p for %s\n",
 270                         msg, spi->dev.bus_id);
 271
 272         /* select chip if it's not still active */
 273         if (as->stay) {
 274                 if (as->stay != spi) {
 275                         cs_deactivate(as, as->stay);
 276                         cs_activate(as, spi);
 277                 }
 278                 as->stay = NULL;
 279         } else
 280                 cs_activate(as, spi);
 281
 282         atmel_spi_next_xfer(master, msg);
 283 }
 284
 285 /*
 286  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 287  *  - The buffer is either valid for CPU access, else NULL
 288  *  - If the buffer is valid, so is its DMA addresss
 289  *
 290  * This driver manages the dma addresss unless message->is_dma_mapped.
 291  */
 292 static int
 293 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 294 {
 295         struct device   *dev = &as->pdev->dev;
 296
 297         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 298         if (xfer->tx_buf) {
 299                 xfer->tx_dma = dma_map_single(dev,
 300                                 (void *) xfer->tx_buf, xfer->len,
 301                                 DMA_TO_DEVICE);
 302                 if (dma_mapping_error(xfer->tx_dma))
 303                         return -ENOMEM;
 304         }
 305         if (xfer->rx_buf) {
 306                 xfer->rx_dma = dma_map_single(dev,
 307                                 xfer->rx_buf, xfer->len,
 308                                 DMA_FROM_DEVICE);
 309                 if (dma_mapping_error(xfer->rx_dma)) {
 310                         if (xfer->tx_buf)
 311                                 dma_unmap_single(dev,
 312                                                 xfer->tx_dma, xfer->len,
 313                                                 DMA_TO_DEVICE);
 314                         return -ENOMEM;
 315                 }
 316         }
 317         return 0;
 318 }
 319
 320 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 321                                      struct spi_transfer *xfer)
 322 {
 323         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 324                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
 325                                  xfer->len, DMA_TO_DEVICE);
 326         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
 327                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
 328                                  xfer->len, DMA_FROM_DEVICE);
 329 }
 330
 331 static void
 332 atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
 333                 struct spi_message *msg, int status, int stay)
 334 {
 335         if (!stay || status < 0)
 336                 cs_deactivate(as, msg->spi);
 337         else
 338                 as->stay = msg->spi;
 339
 340         list_del(&msg->queue);
 341         msg->status = status;
 342
 343         dev_dbg(master->dev.parent,
 344                 "xfer complete: %u bytes transferred\n",
 345                 msg->actual_length);
 346
 347         spin_unlock(&as->lock);
 348         msg->complete(msg->context);
 349         spin_lock(&as->lock);
 350
 351         as->current_transfer = NULL;
 352         as->next_transfer = NULL;
 353
 354         /* continue if needed */
 355         if (list_empty(&as->queue) || as->stopping)
 356                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 357         else
 358                 atmel_spi_next_message(master);
 359 }
 360
 361 static irqreturn_t
 362 atmel_spi_interrupt(int irq, void *dev_id)
 363 {
 364         struct spi_master       *master = dev_id;
 365         struct atmel_spi        *as = spi_master_get_devdata(master);
 366         struct spi_message      *msg;
 367         struct spi_transfer     *xfer;
 368         u32                     status, pending, imr;
 369         int                     ret = IRQ_NONE;
 370
 371         spin_lock(&as->lock);
 372
 373         xfer = as->current_transfer;
 374         msg = list_entry(as->queue.next, struct spi_message, queue);
 375
 376         imr = spi_readl(as, IMR);
 377         status = spi_readl(as, SR);
 378         pending = status & imr;
 379
 380         if (pending & SPI_BIT(OVRES)) {
 381                 int timeout;
 382
 383                 ret = IRQ_HANDLED;
 384
 385                 spi_writel(as, IDR, (SPI_BIT(ENDTX) | SPI_BIT(ENDRX)
 386                                      | SPI_BIT(OVRES)));
 387
 388                 /*
 389                  * When we get an overrun, we disregard the current
 390                  * transfer. Data will not be copied back from any
 391                  * bounce buffer and msg->actual_len will not be
 392                  * updated with the last xfer.
 393                  *
 394                  * We will also not process any remaning transfers in
 395                  * the message.
 396                  *
 397                  * First, stop the transfer and unmap the DMA buffers.
 398                  */
 399                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 400                 if (!msg->is_dma_mapped)
 401                         atmel_spi_dma_unmap_xfer(master, xfer);
 402
 403                 /* REVISIT: udelay in irq is unfriendly */
 404                 if (xfer->delay_usecs)
 405                         udelay(xfer->delay_usecs);
 406
 407                 dev_warn(master->dev.parent, "fifo overrun (%u/%u remaining)\n",
 408                          spi_readl(as, TCR), spi_readl(as, RCR));
 409
 410                 /*
 411                  * Clean up DMA registers and make sure the data
 412                  * registers are empty.
 413                  */
 414                 spi_writel(as, RNCR, 0);
 415                 spi_writel(as, TNCR, 0);
 416                 spi_writel(as, RCR, 0);
 417                 spi_writel(as, TCR, 0);
 418                 for (timeout = 1000; timeout; timeout--)
 419                         if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
 420                                 break;
 421                 if (!timeout)
 422                         dev_warn(master->dev.parent,
 423                                  "timeout waiting for TXEMPTY");
 424                 while (spi_readl(as, SR) & SPI_BIT(RDRF))
 425                         spi_readl(as, RDR);
 426
 427                 /* Clear any overrun happening while cleaning up */
 428                 spi_readl(as, SR);
 429
 430                 atmel_spi_msg_done(master, as, msg, -EIO, 0);
 431         } else if (pending & SPI_BIT(ENDRX)) {
 432                 ret = IRQ_HANDLED;
 433
 434                 spi_writel(as, IDR, pending);
 435
 436                 if (as->current_remaining_bytes == 0) {
 437                         msg->actual_length += xfer->len;
 438
 439                         if (!msg->is_dma_mapped)
 440                                 atmel_spi_dma_unmap_xfer(master, xfer);
 441
 442                         /* REVISIT: udelay in irq is unfriendly */
 443                         if (xfer->delay_usecs)
 444                                 udelay(xfer->delay_usecs);
 445
 446                         if (atmel_spi_xfer_is_last(msg, xfer)) {
 447                                 /* report completed message */
 448                                 atmel_spi_msg_done(master, as, msg, 0,
 449                                                 xfer->cs_change);
 450                         } else {
 451                                 if (xfer->cs_change) {
 452                                         cs_deactivate(as, msg->spi);
 453                                         udelay(1);
 454                                         cs_activate(as, msg->spi);
 455                                 }
 456
 457                                 /*
 458                                  * Not done yet. Submit the next transfer.
 459                                  *
 460                                  * FIXME handle protocol options for xfer
 461                                  */
 462                                 atmel_spi_next_xfer(master, msg);
 463                         }
 464                 } else {
 465                         /*
 466                          * Keep going, we still have data to send in
 467                          * the current transfer.
 468                          */
 469                         atmel_spi_next_xfer(master, msg);
 470                 }
 471         }
 472
 473         spin_unlock(&as->lock);
 474
 475         return ret;
 476 }
 477
 478 /* the spi->mode bits understood by this driver: */
 479 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
 480
 481 static int atmel_spi_setup(struct spi_device *spi)
 482 {
 483         struct atmel_spi        *as;
 484         u32                     scbr, csr;
 485         unsigned int            bits = spi->bits_per_word;
 486         unsigned long           bus_hz, sck_hz;
 487         unsigned int            npcs_pin;
 488         int                     ret;
 489
 490         as = spi_master_get_devdata(spi->master);
 491
 492         if (as->stopping)
 493                 return -ESHUTDOWN;
 494
 495         if (spi->chip_select > spi->master->num_chipselect) {
 496                 dev_dbg(&spi->dev,
 497                                 "setup: invalid chipselect %u (%u defined)\n",
 498                                 spi->chip_select, spi->master->num_chipselect);
 499                 return -EINVAL;
 500         }
 501
 502         if (bits == 0)
 503                 bits = 8;
 504         if (bits < 8 || bits > 16) {
 505                 dev_dbg(&spi->dev,
 506                                 "setup: invalid bits_per_word %u (8 to 16)\n",
 507                                 bits);
 508                 return -EINVAL;
 509         }
 510
 511         if (spi->mode & ~MODEBITS) {
 512                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 513                         spi->mode & ~MODEBITS);
 514                 return -EINVAL;
 515         }
 516
 517         /* see notes above re chipselect */
 518         if (cpu_is_at91rm9200()
 519                         && spi->chip_select == 0
 520                         && (spi->mode & SPI_CS_HIGH)) {
 521                 dev_dbg(&spi->dev, "setup: can't be active-high\n");
 522                 return -EINVAL;
 523         }
 524
 525         /* speed zero convention is used by some upper layers */
 526         bus_hz = clk_get_rate(as->clk);
 527         if (spi->max_speed_hz) {
 528                 /* assume div32/fdiv/mbz == 0 */
 529                 if (!as->new_1)
 530                         bus_hz /= 2;
 531                 scbr = ((bus_hz + spi->max_speed_hz - 1)
 532                         / spi->max_speed_hz);
 533                 if (scbr >= (1 << SPI_SCBR_SIZE)) {
 534                         dev_dbg(&spi->dev,
 535                                 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 536                                 spi->max_speed_hz, scbr, bus_hz/255);
 537                         return -EINVAL;
 538                 }
 539         } else
 540                 scbr = 0xff;
 541         sck_hz = bus_hz / scbr;
 542
 543         csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
 544         if (spi->mode & SPI_CPOL)
 545                 csr |= SPI_BIT(CPOL);
 546         if (!(spi->mode & SPI_CPHA))
 547                 csr |= SPI_BIT(NCPHA);
 548
 549         /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
 550          *
 551          * DLYBCT would add delays between words, slowing down transfers.
 552          * It could potentially be useful to cope with DMA bottlenecks, but
 553          * in those cases it's probably best to just use a lower bitrate.
 554          */
 555         csr |= SPI_BF(DLYBS, 0);
 556         csr |= SPI_BF(DLYBCT, 0);
 557
 558         /* chipselect must have been muxed as GPIO (e.g. in board setup) */
 559         npcs_pin = (unsigned int)spi->controller_data;
 560         if (!spi->controller_state) {
 561                 ret = gpio_request(npcs_pin, spi->dev.bus_id);
 562                 if (ret)
 563                         return ret;
 564                 spi->controller_state = (void *)npcs_pin;
 565                 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
 566         } else {
 567                 unsigned long           flags;
 568
 569                 spin_lock_irqsave(&as->lock, flags);
 570                 if (as->stay == spi)
 571                         as->stay = NULL;
 572                 cs_deactivate(as, spi);
 573                 spin_unlock_irqrestore(&as->lock, flags);
 574         }
 575
 576         dev_dbg(&spi->dev,
 577                 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
 578                 sck_hz, bits, spi->mode, spi->chip_select, csr);
 579
 580         spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 581
 582         return 0;
 583 }
 584
 585 static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 586 {
 587         struct atmel_spi        *as;
 588         struct spi_transfer     *xfer;
 589         unsigned long           flags;
 590         struct device           *controller = spi->master->dev.parent;
 591
 592         as = spi_master_get_devdata(spi->master);
 593
 594         dev_dbg(controller, "new message %p submitted for %s\n",
 595                         msg, spi->dev.bus_id);
 596
 597         if (unlikely(list_empty(&msg->transfers)
 598                         || !spi->max_speed_hz))
 599                 return -EINVAL;
 600
 601         if (as->stopping)
 602                 return -ESHUTDOWN;
 603
 604         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 605                 if (!(xfer->tx_buf || xfer->rx_buf)) {
 606                         dev_dbg(&spi->dev, "missing rx or tx buf\n");
 607                         return -EINVAL;
 608                 }
 609
 610                 /* FIXME implement these protocol options!! */
 611                 if (xfer->bits_per_word || xfer->speed_hz) {
 612                         dev_dbg(&spi->dev, "no protocol options yet\n");
 613                         return -ENOPROTOOPT;
 614                 }
 615
 616                 /*
 617                  * DMA map early, for performance (empties dcache ASAP) and
 618                  * better fault reporting.  This is a DMA-only driver.
 619                  *
 620                  * NOTE that if dma_unmap_single() ever starts to do work on
 621                  * platforms supported by this driver, we would need to clean
 622                  * up mappings for previously-mapped transfers.
 623                  */
 624                 if (!msg->is_dma_mapped) {
 625                         if (atmel_spi_dma_map_xfer(as, xfer) < 0)
 626                                 return -ENOMEM;
 627                 }
 628         }
 629
 630 #ifdef VERBOSE
 631         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 632                 dev_dbg(controller,
 633                         "  xfer %p: len %u tx %p/%08x rx %p/%08x\n",
 634                         xfer, xfer->len,
 635                         xfer->tx_buf, xfer->tx_dma,
 636                         xfer->rx_buf, xfer->rx_dma);
 637         }
 638 #endif
 639
 640         msg->status = -EINPROGRESS;
 641         msg->actual_length = 0;
 642
 643         spin_lock_irqsave(&as->lock, flags);
 644         list_add_tail(&msg->queue, &as->queue);
 645         if (!as->current_transfer)
 646                 atmel_spi_next_message(spi->master);
 647         spin_unlock_irqrestore(&as->lock, flags);
 648
 649         return 0;
 650 }
 651
 652 static void atmel_spi_cleanup(struct spi_device *spi)
 653 {
 654         struct atmel_spi        *as = spi_master_get_devdata(spi->master);
 655         unsigned                gpio = (unsigned) spi->controller_data;
 656         unsigned long           flags;
 657
 658         if (!spi->controller_state)
 659                 return;
 660
 661         spin_lock_irqsave(&as->lock, flags);
 662         if (as->stay == spi) {
 663                 as->stay = NULL;
 664                 cs_deactivate(as, spi);
 665         }
 666         spin_unlock_irqrestore(&as->lock, flags);
 667
 668         gpio_free(gpio);
 669 }
 670
 671 /*-------------------------------------------------------------------------*/
 672
 673 static int __init atmel_spi_probe(struct platform_device *pdev)
 674 {
 675         struct resource         *regs;
 676         int                     irq;
 677         struct clk              *clk;
 678         int                     ret;
 679         struct spi_master       *master;
 680         struct atmel_spi        *as;
 681
 682         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 683         if (!regs)
 684                 return -ENXIO;
 685
 686         irq = platform_get_irq(pdev, 0);
 687         if (irq < 0)
 688                 return irq;
 689
 690         clk = clk_get(&pdev->dev, "spi_clk");
 691         if (IS_ERR(clk))
 692                 return PTR_ERR(clk);
 693
 694         /* setup spi core then atmel-specific driver state */
 695         ret = -ENOMEM;
 696         master = spi_alloc_master(&pdev->dev, sizeof *as);
 697         if (!master)
 698                 goto out_free;
 699
 700         master->bus_num = pdev->id;
 701         master->num_chipselect = 4;
 702         master->setup = atmel_spi_setup;
 703         master->transfer = atmel_spi_transfer;
 704         master->cleanup = atmel_spi_cleanup;
 705         platform_set_drvdata(pdev, master);
 706
 707         as = spi_master_get_devdata(master);
 708
 709         /*
 710          * Scratch buffer is used for throwaway rx and tx data.
 711          * It's coherent to minimize dcache pollution.
 712          */
 713         as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
 714                                         &as->buffer_dma, GFP_KERNEL);
 715         if (!as->buffer)
 716                 goto out_free;
 717
 718         spin_lock_init(&as->lock);
 719         INIT_LIST_HEAD(&as->queue);
 720         as->pdev = pdev;
 721         as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
 722         if (!as->regs)
 723                 goto out_free_buffer;
 724         as->irq = irq;
 725         as->clk = clk;
 726         if (!cpu_is_at91rm9200())
 727                 as->new_1 = 1;
 728
 729         ret = request_irq(irq, atmel_spi_interrupt, 0,
 730                         pdev->dev.bus_id, master);
 731         if (ret)
 732                 goto out_unmap_regs;
 733
 734         /* Initialize the hardware */
 735         clk_enable(clk);
 736         spi_writel(as, CR, SPI_BIT(SWRST));
 737         spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
 738         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 739         spi_writel(as, CR, SPI_BIT(SPIEN));
 740
 741         /* go! */
 742         dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
 743                         (unsigned long)regs->start, irq);
 744
 745         ret = spi_register_master(master);
 746         if (ret)
 747                 goto out_reset_hw;
 748
 749         return 0;
 750
 751 out_reset_hw:
 752         spi_writel(as, CR, SPI_BIT(SWRST));
 753         clk_disable(clk);
 754         free_irq(irq, master);
 755 out_unmap_regs:
 756         iounmap(as->regs);
 757 out_free_buffer:
 758         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 759                         as->buffer_dma);
 760 out_free:
 761         clk_put(clk);
 762         spi_master_put(master);
 763         return ret;
 764 }
 765
 766 static int __exit atmel_spi_remove(struct platform_device *pdev)
 767 {
 768         struct spi_master       *master = platform_get_drvdata(pdev);
 769         struct atmel_spi        *as = spi_master_get_devdata(master);
 770         struct spi_message      *msg;
 771
 772         /* reset the hardware and block queue progress */
 773         spin_lock_irq(&as->lock);
 774         as->stopping = 1;
 775         spi_writel(as, CR, SPI_BIT(SWRST));
 776         spi_readl(as, SR);
 777         spin_unlock_irq(&as->lock);
 778
 779         /* Terminate remaining queued transfers */
 780         list_for_each_entry(msg, &as->queue, queue) {
 781                 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
 782                  * but we shouldn't depend on that...
 783                  */
 784                 msg->status = -ESHUTDOWN;
 785                 msg->complete(msg->context);
 786         }
 787
 788         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 789                         as->buffer_dma);
 790
 791         clk_disable(as->clk);
 792         clk_put(as->clk);
 793         free_irq(as->irq, master);
 794         iounmap(as->regs);
 795
 796         spi_unregister_master(master);
 797
 798         return 0;
 799 }
 800
 801 #ifdef  CONFIG_PM
 802
 803 static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
 804 {
 805         struct spi_master       *master = platform_get_drvdata(pdev);
 806         struct atmel_spi        *as = spi_master_get_devdata(master);
 807
 808         clk_disable(as->clk);
 809         return 0;
 810 }
 811
 812 static int atmel_spi_resume(struct platform_device *pdev)
 813 {
 814         struct spi_master       *master = platform_get_drvdata(pdev);
 815         struct atmel_spi        *as = spi_master_get_devdata(master);
 816
 817         clk_enable(as->clk);
 818         return 0;
 819 }
 820
 821 #else
 822 #define atmel_spi_suspend       NULL
 823 #define atmel_spi_resume        NULL
 824 #endif
 825
 826
 827 static struct platform_driver atmel_spi_driver = {
 828         .driver         = {
 829                 .name   = "atmel_spi",
 830                 .owner  = THIS_MODULE,
 831         },
 832         .suspend        = atmel_spi_suspend,
 833         .resume         = atmel_spi_resume,
 834         .remove         = __exit_p(atmel_spi_remove),
 835 };
 836
 837 static int __init atmel_spi_init(void)
 838 {
 839         return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
 840 }
 841 module_init(atmel_spi_init);
 842
 843 static void __exit atmel_spi_exit(void)
 844 {
 845         platform_driver_unregister(&atmel_spi_driver);
 846 }
 847 module_exit(atmel_spi_exit);
 848
 849 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
 850 MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
 851 MODULE_LICENSE("GPL");