2 * linux/drivers/serial/imx.c
4 * Driver for Motorola IMX serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * [29-Mar-2005] Mike Lee
26 * Added hardware handshake
29 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33 #include <linux/module.h>
34 #include <linux/ioport.h>
35 #include <linux/init.h>
36 #include <linux/console.h>
37 #include <linux/sysrq.h>
38 #include <linux/platform_device.h>
39 #include <linux/tty.h>
40 #include <linux/tty_flip.h>
41 #include <linux/serial_core.h>
42 #include <linux/serial.h>
43 #include <linux/clk.h>
47 #include <asm/hardware.h>
48 #include <asm/arch/imx-uart.h>
50 /* Register definitions */
51 #define URXD0 0x0 /* Receiver Register */
52 #define URTX0 0x40 /* Transmitter Register */
53 #define UCR1 0x80 /* Control Register 1 */
54 #define UCR2 0x84 /* Control Register 2 */
55 #define UCR3 0x88 /* Control Register 3 */
56 #define UCR4 0x8c /* Control Register 4 */
57 #define UFCR 0x90 /* FIFO Control Register */
58 #define USR1 0x94 /* Status Register 1 */
59 #define USR2 0x98 /* Status Register 2 */
60 #define UESC 0x9c /* Escape Character Register */
61 #define UTIM 0xa0 /* Escape Timer Register */
62 #define UBIR 0xa4 /* BRM Incremental Register */
63 #define UBMR 0xa8 /* BRM Modulator Register */
64 #define UBRC 0xac /* Baud Rate Count Register */
65 #define BIPR1 0xb0 /* Incremental Preset Register 1 */
66 #define BIPR2 0xb4 /* Incremental Preset Register 2 */
67 #define BIPR3 0xb8 /* Incremental Preset Register 3 */
68 #define BIPR4 0xbc /* Incremental Preset Register 4 */
69 #define BMPR1 0xc0 /* BRM Modulator Register 1 */
70 #define BMPR2 0xc4 /* BRM Modulator Register 2 */
71 #define BMPR3 0xc8 /* BRM Modulator Register 3 */
72 #define BMPR4 0xcc /* BRM Modulator Register 4 */
73 #define UTS 0xd0 /* UART Test Register */
75 /* UART Control Register Bit Fields.*/
76 #define URXD_CHARRDY (1<<15)
77 #define URXD_ERR (1<<14)
78 #define URXD_OVRRUN (1<<13)
79 #define URXD_FRMERR (1<<12)
80 #define URXD_BRK (1<<11)
81 #define URXD_PRERR (1<<10)
82 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
83 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
84 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
85 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
86 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
87 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
88 #define UCR1_IREN (1<<7) /* Infrared interface enable */
89 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
90 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
91 #define UCR1_SNDBRK (1<<4) /* Send break */
92 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
93 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
94 #define UCR1_DOZE (1<<1) /* Doze */
95 #define UCR1_UARTEN (1<<0) /* UART enabled */
96 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
97 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
98 #define UCR2_CTSC (1<<13) /* CTS pin control */
99 #define UCR2_CTS (1<<12) /* Clear to send */
100 #define UCR2_ESCEN (1<<11) /* Escape enable */
101 #define UCR2_PREN (1<<8) /* Parity enable */
102 #define UCR2_PROE (1<<7) /* Parity odd/even */
103 #define UCR2_STPB (1<<6) /* Stop */
104 #define UCR2_WS (1<<5) /* Word size */
105 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
106 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
107 #define UCR2_RXEN (1<<1) /* Receiver enabled */
108 #define UCR2_SRST (1<<0) /* SW reset */
109 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
110 #define UCR3_PARERREN (1<<12) /* Parity enable */
111 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
112 #define UCR3_DSR (1<<10) /* Data set ready */
113 #define UCR3_DCD (1<<9) /* Data carrier detect */
114 #define UCR3_RI (1<<8) /* Ring indicator */
115 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
116 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
117 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
118 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
119 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
120 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
121 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
122 #define UCR3_BPEN (1<<0) /* Preset registers enable */
123 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
124 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
125 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
126 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
127 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
128 #define UCR4_IRSC (1<<5) /* IR special case */
129 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
130 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
131 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
132 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
133 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
134 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
135 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
136 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
137 #define USR1_RTSS (1<<14) /* RTS pin status */
138 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
139 #define USR1_RTSD (1<<12) /* RTS delta */
140 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
141 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
142 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
143 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
144 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
145 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
146 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
147 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
148 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
149 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
150 #define USR2_IDLE (1<<12) /* Idle condition */
151 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
152 #define USR2_WAKE (1<<7) /* Wake */
153 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
154 #define USR2_TXDC (1<<3) /* Transmitter complete */
155 #define USR2_BRCD (1<<2) /* Break condition */
156 #define USR2_ORE (1<<1) /* Overrun error */
157 #define USR2_RDR (1<<0) /* Recv data ready */
158 #define UTS_FRCPERR (1<<13) /* Force parity error */
159 #define UTS_LOOP (1<<12) /* Loop tx and rx */
160 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
161 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
162 #define UTS_TXFULL (1<<4) /* TxFIFO full */
163 #define UTS_RXFULL (1<<3) /* RxFIFO full */
164 #define UTS_SOFTRST (1<<0) /* Software reset */
166 /* We've been assigned a range on the "Low-density serial ports" major */
167 #define SERIAL_IMX_MAJOR 204
168 #define MINOR_START 41
171 * This determines how often we check the modem status signals
172 * for any change. They generally aren't connected to an IRQ
173 * so we have to poll them. We also check immediately before
174 * filling the TX fifo incase CTS has been dropped.
176 #define MCTRL_TIMEOUT (250*HZ/1000)
178 #define DRIVER_NAME "IMX-uart"
183 struct uart_port port;
184 struct timer_list timer;
185 unsigned int old_status;
186 int txirq,rxirq,rtsirq;
192 * Handle any change of modem status signal since we were last called.
194 static void imx_mctrl_check(struct imx_port *sport)
196 unsigned int status, changed;
198 status = sport->port.ops->get_mctrl(&sport->port);
199 changed = status ^ sport->old_status;
204 sport->old_status = status;
206 if (changed & TIOCM_RI)
207 sport->port.icount.rng++;
208 if (changed & TIOCM_DSR)
209 sport->port.icount.dsr++;
210 if (changed & TIOCM_CAR)
211 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
212 if (changed & TIOCM_CTS)
213 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
215 wake_up_interruptible(&sport->port.info->delta_msr_wait);
219 * This is our per-port timeout handler, for checking the
220 * modem status signals.
222 static void imx_timeout(unsigned long data)
224 struct imx_port *sport = (struct imx_port *)data;
227 if (sport->port.info) {
228 spin_lock_irqsave(&sport->port.lock, flags);
229 imx_mctrl_check(sport);
230 spin_unlock_irqrestore(&sport->port.lock, flags);
232 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
237 * interrupts disabled on entry
239 static void imx_stop_tx(struct uart_port *port)
241 struct imx_port *sport = (struct imx_port *)port;
244 temp = readl(sport->port.membase + UCR1);
245 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
249 * interrupts disabled on entry
251 static void imx_stop_rx(struct uart_port *port)
253 struct imx_port *sport = (struct imx_port *)port;
256 temp = readl(sport->port.membase + UCR2);
257 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
261 * Set the modem control timer to fire immediately.
263 static void imx_enable_ms(struct uart_port *port)
265 struct imx_port *sport = (struct imx_port *)port;
267 mod_timer(&sport->timer, jiffies);
270 static inline void imx_transmit_buffer(struct imx_port *sport)
272 struct circ_buf *xmit = &sport->port.info->xmit;
274 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
275 /* send xmit->buf[xmit->tail]
276 * out the port here */
277 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
278 xmit->tail = (xmit->tail + 1) &
279 (UART_XMIT_SIZE - 1);
280 sport->port.icount.tx++;
281 if (uart_circ_empty(xmit))
285 if (uart_circ_empty(xmit))
286 imx_stop_tx(&sport->port);
290 * interrupts disabled on entry
292 static void imx_start_tx(struct uart_port *port)
294 struct imx_port *sport = (struct imx_port *)port;
297 temp = readl(sport->port.membase + UCR1);
298 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
300 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
301 imx_transmit_buffer(sport);
304 static irqreturn_t imx_rtsint(int irq, void *dev_id)
306 struct imx_port *sport = dev_id;
307 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
310 spin_lock_irqsave(&sport->port.lock, flags);
312 writel(USR1_RTSD, sport->port.membase + USR1);
313 uart_handle_cts_change(&sport->port, !!val);
314 wake_up_interruptible(&sport->port.info->delta_msr_wait);
316 spin_unlock_irqrestore(&sport->port.lock, flags);
320 static irqreturn_t imx_txint(int irq, void *dev_id)
322 struct imx_port *sport = dev_id;
323 struct circ_buf *xmit = &sport->port.info->xmit;
326 spin_lock_irqsave(&sport->port.lock,flags);
327 if (sport->port.x_char)
330 writel(sport->port.x_char, sport->port.membase + URTX0);
334 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
335 imx_stop_tx(&sport->port);
339 imx_transmit_buffer(sport);
341 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
342 uart_write_wakeup(&sport->port);
345 spin_unlock_irqrestore(&sport->port.lock,flags);
349 static irqreturn_t imx_rxint(int irq, void *dev_id)
351 struct imx_port *sport = dev_id;
352 unsigned int rx,flg,ignored = 0;
353 struct tty_struct *tty = sport->port.info->tty;
354 unsigned long flags, temp;
356 spin_lock_irqsave(&sport->port.lock,flags);
358 while (readl(sport->port.membase + USR2) & USR2_RDR) {
360 sport->port.icount.rx++;
362 rx = readl(sport->port.membase + URXD0);
364 temp = readl(sport->port.membase + USR2);
365 if (temp & USR2_BRCD) {
366 writel(temp | USR2_BRCD, sport->port.membase + USR2);
367 if (uart_handle_break(&sport->port))
371 if (uart_handle_sysrq_char
372 (&sport->port, (unsigned char)rx))
375 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
377 sport->port.icount.parity++;
378 else if (rx & URXD_FRMERR)
379 sport->port.icount.frame++;
380 if (rx & URXD_OVRRUN)
381 sport->port.icount.overrun++;
383 if (rx & sport->port.ignore_status_mask) {
389 rx &= sport->port.read_status_mask;
393 else if (rx & URXD_FRMERR)
395 if (rx & URXD_OVRRUN)
399 sport->port.sysrq = 0;
403 tty_insert_flip_char(tty, rx, flg);
407 spin_unlock_irqrestore(&sport->port.lock,flags);
408 tty_flip_buffer_push(tty);
413 * Return TIOCSER_TEMT when transmitter is not busy.
415 static unsigned int imx_tx_empty(struct uart_port *port)
417 struct imx_port *sport = (struct imx_port *)port;
419 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
423 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
425 static unsigned int imx_get_mctrl(struct uart_port *port)
427 struct imx_port *sport = (struct imx_port *)port;
428 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
430 if (readl(sport->port.membase + USR1) & USR1_RTSS)
433 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
439 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
441 struct imx_port *sport = (struct imx_port *)port;
444 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
446 if (mctrl & TIOCM_RTS)
449 writel(temp, sport->port.membase + UCR2);
453 * Interrupts always disabled.
455 static void imx_break_ctl(struct uart_port *port, int break_state)
457 struct imx_port *sport = (struct imx_port *)port;
458 unsigned long flags, temp;
460 spin_lock_irqsave(&sport->port.lock, flags);
462 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
464 if ( break_state != 0 )
467 writel(temp, sport->port.membase + UCR1);
469 spin_unlock_irqrestore(&sport->port.lock, flags);
472 #define TXTL 2 /* reset default */
473 #define RXTL 1 /* reset default */
475 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
478 unsigned int ufcr_rfdiv;
480 /* set receiver / transmitter trigger level.
481 * RFDIV is set such way to satisfy requested uartclk value
483 val = TXTL << 10 | RXTL;
484 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
485 / sport->port.uartclk;
493 ufcr_rfdiv = 6 - ufcr_rfdiv;
495 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
497 writel(val, sport->port.membase + UFCR);
502 static int imx_startup(struct uart_port *port)
504 struct imx_port *sport = (struct imx_port *)port;
506 unsigned long flags, temp;
508 imx_setup_ufcr(sport, 0);
510 /* disable the DREN bit (Data Ready interrupt enable) before
513 temp = readl(sport->port.membase + UCR4);
514 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
519 retval = request_irq(sport->rxirq, imx_rxint, 0,
521 if (retval) goto error_out1;
523 retval = request_irq(sport->txirq, imx_txint, 0,
525 if (retval) goto error_out2;
527 retval = request_irq(sport->rtsirq, imx_rtsint,
528 (sport->rtsirq < IMX_IRQS) ? 0 :
529 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
531 if (retval) goto error_out3;
534 * Finally, clear and enable interrupts
536 writel(USR1_RTSD, sport->port.membase + USR1);
538 temp = readl(sport->port.membase + UCR1);
539 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
540 writel(temp, sport->port.membase + UCR1);
542 temp = readl(sport->port.membase + UCR2);
543 temp |= (UCR2_RXEN | UCR2_TXEN);
544 writel(temp, sport->port.membase + UCR2);
547 * Enable modem status interrupts
549 spin_lock_irqsave(&sport->port.lock,flags);
550 imx_enable_ms(&sport->port);
551 spin_unlock_irqrestore(&sport->port.lock,flags);
556 free_irq(sport->txirq, sport);
558 free_irq(sport->rxirq, sport);
563 static void imx_shutdown(struct uart_port *port)
565 struct imx_port *sport = (struct imx_port *)port;
571 del_timer_sync(&sport->timer);
574 * Free the interrupts
576 free_irq(sport->rtsirq, sport);
577 free_irq(sport->txirq, sport);
578 free_irq(sport->rxirq, sport);
581 * Disable all interrupts, port and break condition.
584 temp = readl(sport->port.membase + UCR1);
585 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
586 writel(temp, sport->port.membase + UCR1);
590 imx_set_termios(struct uart_port *port, struct ktermios *termios,
591 struct ktermios *old)
593 struct imx_port *sport = (struct imx_port *)port;
595 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
596 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
597 unsigned int div, num, denom, ufcr;
600 * If we don't support modem control lines, don't allow
604 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
605 termios->c_cflag |= CLOCAL;
609 * We only support CS7 and CS8.
611 while ((termios->c_cflag & CSIZE) != CS7 &&
612 (termios->c_cflag & CSIZE) != CS8) {
613 termios->c_cflag &= ~CSIZE;
614 termios->c_cflag |= old_csize;
618 if ((termios->c_cflag & CSIZE) == CS8)
619 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
621 ucr2 = UCR2_SRST | UCR2_IRTS;
623 if (termios->c_cflag & CRTSCTS) {
624 if( sport->have_rtscts ) {
628 termios->c_cflag &= ~CRTSCTS;
632 if (termios->c_cflag & CSTOPB)
634 if (termios->c_cflag & PARENB) {
636 if (termios->c_cflag & PARODD)
641 * Ask the core to calculate the divisor for us.
643 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
644 quot = uart_get_divisor(port, baud);
646 spin_lock_irqsave(&sport->port.lock, flags);
648 sport->port.read_status_mask = 0;
649 if (termios->c_iflag & INPCK)
650 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
651 if (termios->c_iflag & (BRKINT | PARMRK))
652 sport->port.read_status_mask |= URXD_BRK;
655 * Characters to ignore
657 sport->port.ignore_status_mask = 0;
658 if (termios->c_iflag & IGNPAR)
659 sport->port.ignore_status_mask |= URXD_PRERR;
660 if (termios->c_iflag & IGNBRK) {
661 sport->port.ignore_status_mask |= URXD_BRK;
663 * If we're ignoring parity and break indicators,
664 * ignore overruns too (for real raw support).
666 if (termios->c_iflag & IGNPAR)
667 sport->port.ignore_status_mask |= URXD_OVRRUN;
670 del_timer_sync(&sport->timer);
673 * Update the per-port timeout.
675 uart_update_timeout(port, termios->c_cflag, baud);
678 * disable interrupts and drain transmitter
680 old_ucr1 = readl(sport->port.membase + UCR1);
681 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
682 sport->port.membase + UCR1);
684 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
687 /* then, disable everything */
688 old_txrxen = readl(sport->port.membase + UCR2);
689 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
690 sport->port.membase + UCR2);
691 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
693 div = sport->port.uartclk / (baud * 16);
700 denom = port->uartclk / div / 16;
702 /* shift num and denom right until they fit into 16 bits */
703 while (num > 0x10000 || denom > 0x10000) {
712 writel(num, sport->port.membase + UBIR);
713 writel(denom, sport->port.membase + UBMR);
716 div = 6; /* 6 in RFDIV means divide by 7 */
720 ufcr = readl(sport->port.membase + UFCR);
721 ufcr = (ufcr & (~UFCR_RFDIV)) |
723 writel(ufcr, sport->port.membase + UFCR);
726 writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS);
729 writel(old_ucr1, sport->port.membase + UCR1);
731 /* set the parity, stop bits and data size */
732 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
734 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
735 imx_enable_ms(&sport->port);
737 spin_unlock_irqrestore(&sport->port.lock, flags);
740 static const char *imx_type(struct uart_port *port)
742 struct imx_port *sport = (struct imx_port *)port;
744 return sport->port.type == PORT_IMX ? "IMX" : NULL;
748 * Release the memory region(s) being used by 'port'.
750 static void imx_release_port(struct uart_port *port)
752 struct platform_device *pdev = to_platform_device(port->dev);
753 struct resource *mmres;
755 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
756 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
760 * Request the memory region(s) being used by 'port'.
762 static int imx_request_port(struct uart_port *port)
764 struct platform_device *pdev = to_platform_device(port->dev);
765 struct resource *mmres;
768 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
772 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
775 return ret ? 0 : -EBUSY;
779 * Configure/autoconfigure the port.
781 static void imx_config_port(struct uart_port *port, int flags)
783 struct imx_port *sport = (struct imx_port *)port;
785 if (flags & UART_CONFIG_TYPE &&
786 imx_request_port(&sport->port) == 0)
787 sport->port.type = PORT_IMX;
791 * Verify the new serial_struct (for TIOCSSERIAL).
792 * The only change we allow are to the flags and type, and
793 * even then only between PORT_IMX and PORT_UNKNOWN
796 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
798 struct imx_port *sport = (struct imx_port *)port;
801 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
803 if (sport->port.irq != ser->irq)
805 if (ser->io_type != UPIO_MEM)
807 if (sport->port.uartclk / 16 != ser->baud_base)
809 if ((void *)sport->port.mapbase != ser->iomem_base)
811 if (sport->port.iobase != ser->port)
818 static struct uart_ops imx_pops = {
819 .tx_empty = imx_tx_empty,
820 .set_mctrl = imx_set_mctrl,
821 .get_mctrl = imx_get_mctrl,
822 .stop_tx = imx_stop_tx,
823 .start_tx = imx_start_tx,
824 .stop_rx = imx_stop_rx,
825 .enable_ms = imx_enable_ms,
826 .break_ctl = imx_break_ctl,
827 .startup = imx_startup,
828 .shutdown = imx_shutdown,
829 .set_termios = imx_set_termios,
831 .release_port = imx_release_port,
832 .request_port = imx_request_port,
833 .config_port = imx_config_port,
834 .verify_port = imx_verify_port,
837 static struct imx_port *imx_ports[UART_NR];
839 #ifdef CONFIG_SERIAL_IMX_CONSOLE
840 static void imx_console_putchar(struct uart_port *port, int ch)
842 struct imx_port *sport = (struct imx_port *)port;
844 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
847 writel(ch, sport->port.membase + URTX0);
851 * Interrupts are disabled on entering
854 imx_console_write(struct console *co, const char *s, unsigned int count)
856 struct imx_port *sport = imx_ports[co->index];
857 unsigned int old_ucr1, old_ucr2;
860 * First, save UCR1/2 and then disable interrupts
862 old_ucr1 = readl(sport->port.membase + UCR1);
863 old_ucr2 = readl(sport->port.membase + UCR2);
865 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
866 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
867 sport->port.membase + UCR1);
869 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
871 uart_console_write(&sport->port, s, count, imx_console_putchar);
874 * Finally, wait for transmitter to become empty
877 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
879 writel(old_ucr1, sport->port.membase + UCR1);
880 writel(old_ucr2, sport->port.membase + UCR2);
884 * If the port was already initialised (eg, by a boot loader),
885 * try to determine the current setup.
888 imx_console_get_options(struct imx_port *sport, int *baud,
889 int *parity, int *bits)
892 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
893 /* ok, the port was enabled */
894 unsigned int ucr2, ubir,ubmr, uartclk;
895 unsigned int baud_raw;
896 unsigned int ucfr_rfdiv;
898 ucr2 = readl(sport->port.membase + UCR2);
901 if (ucr2 & UCR2_PREN) {
902 if (ucr2 & UCR2_PROE)
913 ubir = readl(sport->port.membase + UBIR) & 0xffff;
914 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
916 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
920 ucfr_rfdiv = 6 - ucfr_rfdiv;
922 uartclk = clk_get_rate(sport->clk);
923 uartclk /= ucfr_rfdiv;
926 * The next code provides exact computation of
927 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
928 * without need of float support or long long division,
929 * which would be required to prevent 32bit arithmetic overflow
931 unsigned int mul = ubir + 1;
932 unsigned int div = 16 * (ubmr + 1);
933 unsigned int rem = uartclk % div;
935 baud_raw = (uartclk / div) * mul;
936 baud_raw += (rem * mul + div / 2) / div;
937 *baud = (baud_raw + 50) / 100 * 100;
940 if(*baud != baud_raw)
941 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
947 imx_console_setup(struct console *co, char *options)
949 struct imx_port *sport;
956 * Check whether an invalid uart number has been specified, and
957 * if so, search for the first available port that does have
960 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
962 sport = imx_ports[co->index];
965 uart_parse_options(options, &baud, &parity, &bits, &flow);
967 imx_console_get_options(sport, &baud, &parity, &bits);
969 imx_setup_ufcr(sport, 0);
971 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
974 static struct uart_driver imx_reg;
975 static struct console imx_console = {
977 .write = imx_console_write,
978 .device = uart_console_device,
979 .setup = imx_console_setup,
980 .flags = CON_PRINTBUFFER,
985 #define IMX_CONSOLE &imx_console
987 #define IMX_CONSOLE NULL
990 static struct uart_driver imx_reg = {
991 .owner = THIS_MODULE,
992 .driver_name = DRIVER_NAME,
993 .dev_name = "ttySMX",
994 .major = SERIAL_IMX_MAJOR,
995 .minor = MINOR_START,
996 .nr = ARRAY_SIZE(imx_ports),
1000 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1002 struct imx_port *sport = platform_get_drvdata(dev);
1005 uart_suspend_port(&imx_reg, &sport->port);
1010 static int serial_imx_resume(struct platform_device *dev)
1012 struct imx_port *sport = platform_get_drvdata(dev);
1015 uart_resume_port(&imx_reg, &sport->port);
1020 static int serial_imx_probe(struct platform_device *pdev)
1022 struct imx_port *sport;
1023 struct imxuart_platform_data *pdata;
1026 struct resource *res;
1028 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1032 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1038 base = ioremap(res->start, PAGE_SIZE);
1044 sport->port.dev = &pdev->dev;
1045 sport->port.mapbase = res->start;
1046 sport->port.membase = base;
1047 sport->port.type = PORT_IMX,
1048 sport->port.iotype = UPIO_MEM;
1049 sport->port.irq = platform_get_irq(pdev, 0);
1050 sport->rxirq = platform_get_irq(pdev, 0);
1051 sport->txirq = platform_get_irq(pdev, 1);
1052 sport->rtsirq = platform_get_irq(pdev, 2);
1053 sport->port.fifosize = 32;
1054 sport->port.ops = &imx_pops;
1055 sport->port.flags = UPF_BOOT_AUTOCONF;
1056 sport->port.line = pdev->id;
1057 init_timer(&sport->timer);
1058 sport->timer.function = imx_timeout;
1059 sport->timer.data = (unsigned long)sport;
1061 sport->clk = clk_get(&pdev->dev, "uart_clk");
1062 if (IS_ERR(sport->clk)) {
1063 ret = PTR_ERR(sport->clk);
1066 clk_enable(sport->clk);
1068 sport->port.uartclk = clk_get_rate(sport->clk);
1070 imx_ports[pdev->id] = sport;
1072 pdata = pdev->dev.platform_data;
1073 if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1074 sport->have_rtscts = 1;
1079 uart_add_one_port(&imx_reg, &sport->port);
1080 platform_set_drvdata(pdev, &sport->port);
1084 iounmap(sport->port.membase);
1091 static int serial_imx_remove(struct platform_device *pdev)
1093 struct imxuart_platform_data *pdata;
1094 struct imx_port *sport = platform_get_drvdata(pdev);
1096 pdata = pdev->dev.platform_data;
1098 platform_set_drvdata(pdev, NULL);
1101 uart_remove_one_port(&imx_reg, &sport->port);
1102 clk_put(sport->clk);
1105 clk_disable(sport->clk);
1110 iounmap(sport->port.membase);
1116 static struct platform_driver serial_imx_driver = {
1117 .probe = serial_imx_probe,
1118 .remove = serial_imx_remove,
1120 .suspend = serial_imx_suspend,
1121 .resume = serial_imx_resume,
1124 .owner = THIS_MODULE,
1128 static int __init imx_serial_init(void)
1132 printk(KERN_INFO "Serial: IMX driver\n");
1134 ret = uart_register_driver(&imx_reg);
1138 ret = platform_driver_register(&serial_imx_driver);
1140 uart_unregister_driver(&imx_reg);
1145 static void __exit imx_serial_exit(void)
1147 platform_driver_unregister(&serial_imx_driver);
1148 uart_unregister_driver(&imx_reg);
1151 module_init(imx_serial_init);
1152 module_exit(imx_serial_exit);
1154 MODULE_AUTHOR("Sascha Hauer");
1155 MODULE_DESCRIPTION("IMX generic serial port driver");
1156 MODULE_LICENSE("GPL");
1157 MODULE_ALIAS("platform:imx-uart");