2 * linux/drivers/char/8250_pci.c
4 * Probe module for 8250/16550-type PCI serial ports.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/serial_core.h>
23 #include <linux/8250_pci.h>
24 #include <linux/bitops.h>
26 #include <asm/byteorder.h>
31 #undef SERIAL_DEBUG_PCI
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
39 struct pci_serial_quirk {
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_port *, int);
48 void (*exit)(struct pci_dev *dev);
51 #define PCI_NUM_BAR_RESOURCES 6
53 struct serial_private {
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
61 static void moan_device(const char *str, struct pci_dev *dev)
63 printk(KERN_WARNING "%s: %s\n"
64 KERN_WARNING "Please send the output of lspci -vv, this\n"
65 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
66 KERN_WARNING "manufacturer and name of serial board or\n"
67 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
68 pci_name(dev), str, dev->vendor, dev->device,
69 dev->subsystem_vendor, dev->subsystem_device);
73 setup_port(struct serial_private *priv, struct uart_port *port,
74 int bar, int offset, int regshift)
76 struct pci_dev *dev = priv->dev;
77 unsigned long base, len;
79 if (bar >= PCI_NUM_BAR_RESOURCES)
82 base = pci_resource_start(dev, bar);
84 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
85 len = pci_resource_len(dev, bar);
87 if (!priv->remapped_bar[bar])
88 priv->remapped_bar[bar] = ioremap_nocache(base, len);
89 if (!priv->remapped_bar[bar])
92 port->iotype = UPIO_MEM;
94 port->mapbase = base + offset;
95 port->membase = priv->remapped_bar[bar] + offset;
96 port->regshift = regshift;
98 port->iotype = UPIO_PORT;
99 port->iobase = base + offset;
101 port->membase = NULL;
108 * ADDI-DATA GmbH communication cards <info@addi-data.com>
110 static int addidata_apci7800_setup(struct serial_private *priv,
111 const struct pciserial_board *board,
112 struct uart_port *port, int idx)
114 unsigned int bar = 0, offset = board->first_offset;
115 bar = FL_GET_BASE(board->flags);
118 offset += idx * board->uart_offset;
119 } else if ((idx >= 2) && (idx < 4)) {
121 offset += ((idx - 2) * board->uart_offset);
122 } else if ((idx >= 4) && (idx < 6)) {
124 offset += ((idx - 4) * board->uart_offset);
125 } else if (idx >= 6) {
127 offset += ((idx - 6) * board->uart_offset);
130 return setup_port(priv, port, bar, offset, board->reg_shift);
134 * AFAVLAB uses a different mixture of BARs and offsets
135 * Not that ugly ;) -- HW
138 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
139 struct uart_port *port, int idx)
141 unsigned int bar, offset = board->first_offset;
143 bar = FL_GET_BASE(board->flags);
148 offset += (idx - 4) * board->uart_offset;
151 return setup_port(priv, port, bar, offset, board->reg_shift);
155 * HP's Remote Management Console. The Diva chip came in several
156 * different versions. N-class, L2000 and A500 have two Diva chips, each
157 * with 3 UARTs (the third UART on the second chip is unused). Superdome
158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
159 * one Diva chip, but it has been expanded to 5 UARTs.
161 static int pci_hp_diva_init(struct pci_dev *dev)
165 switch (dev->subsystem_device) {
166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
169 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
192 pci_hp_diva_setup(struct serial_private *priv,
193 const struct pciserial_board *board,
194 struct uart_port *port, int idx)
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
199 switch (priv->dev->subsystem_device) {
200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
214 offset += idx * board->uart_offset;
216 return setup_port(priv, port, bar, offset, board->reg_shift);
220 * Added for EKF Intel i960 serial boards
222 static int pci_inteli960ni_init(struct pci_dev *dev)
224 unsigned long oldval;
226 if (!(dev->subsystem_device & 0x1000))
229 /* is firmware started? */
230 pci_read_config_dword(dev, 0x44, (void *)&oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
232 printk(KERN_DEBUG "Local i960 firmware missing");
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
244 static int pci_plx9050_init(struct pci_dev *dev)
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
271 * enable/disable interrupts
273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
276 writel(irq_config, p + 0x4c);
279 * Read the register back to ensure that it took effect.
287 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
302 * Read the register back to ensure that it took effect.
310 #define MITE_IOWBSR1 0xc4
311 #define MITE_IOWCR1 0xf4
312 #define MITE_LCIMR1 0x08
313 #define MITE_LCIMR2 0x10
315 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
317 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
320 unsigned long base, len;
321 unsigned int bar = 0;
323 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
324 moan_device("no memory in bar", dev);
328 base = pci_resource_start(dev, bar);
329 len = pci_resource_len(dev, bar);
330 p = ioremap_nocache(base, len);
334 /* Disable the CPU Interrupt */
335 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
339 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
341 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
342 struct uart_port *port, int idx)
344 unsigned int bar, offset = board->first_offset;
349 /* first four channels map to 0, 0x100, 0x200, 0x300 */
350 offset += idx * board->uart_offset;
351 } else if (idx < 8) {
352 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
353 offset += idx * board->uart_offset + 0xC00;
354 } else /* we have only 8 ports on PMC-OCTALPRO */
357 return setup_port(priv, port, bar, offset, board->reg_shift);
361 * This does initialization for PMC OCTALPRO cards:
362 * maps the device memory, resets the UARTs (needed, bc
363 * if the module is removed and inserted again, the card
364 * is in the sleep mode) and enables global interrupt.
367 /* global control register offset for SBS PMC-OctalPro */
368 #define OCT_REG_CR_OFF 0x500
370 static int sbs_init(struct pci_dev *dev)
374 p = ioremap_nocache(pci_resource_start(dev, 0),
375 pci_resource_len(dev, 0));
379 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
380 writeb(0x10, p + OCT_REG_CR_OFF);
382 writeb(0x0, p + OCT_REG_CR_OFF);
384 /* Set bit-2 (INTENABLE) of Control Register */
385 writeb(0x4, p + OCT_REG_CR_OFF);
392 * Disables the global interrupt of PMC-OctalPro
395 static void __devexit sbs_exit(struct pci_dev *dev)
399 p = ioremap_nocache(pci_resource_start(dev, 0),
400 pci_resource_len(dev, 0));
401 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
403 writeb(0, p + OCT_REG_CR_OFF);
408 * SIIG serial cards have an PCI interface chip which also controls
409 * the UART clocking frequency. Each UART can be clocked independently
410 * (except cards equiped with 4 UARTs) and initial clocking settings
411 * are stored in the EEPROM chip. It can cause problems because this
412 * version of serial driver doesn't support differently clocked UART's
413 * on single PCI card. To prevent this, initialization functions set
414 * high frequency clocking for all UART's on given card. It is safe (I
415 * hope) because it doesn't touch EEPROM settings to prevent conflicts
416 * with other OSes (like M$ DOS).
418 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
420 * There is two family of SIIG serial cards with different PCI
421 * interface chip and different configuration methods:
422 * - 10x cards have control registers in IO and/or memory space;
423 * - 20x cards have control registers in standard PCI configuration space.
425 * Note: all 10x cards have PCI device ids 0x10..
426 * all 20x cards have PCI device ids 0x20..
428 * There are also Quartet Serial cards which use Oxford Semiconductor
429 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
431 * Note: some SIIG cards are probed by the parport_serial object.
434 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
435 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
437 static int pci_siig10x_init(struct pci_dev *dev)
442 switch (dev->device & 0xfff8) {
443 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
446 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
449 default: /* 1S1P, 4S */
454 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
458 writew(readw(p + 0x28) & data, p + 0x28);
464 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
465 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
467 static int pci_siig20x_init(struct pci_dev *dev)
471 /* Change clock frequency for the first UART. */
472 pci_read_config_byte(dev, 0x6f, &data);
473 pci_write_config_byte(dev, 0x6f, data & 0xef);
475 /* If this card has 2 UART, we have to do the same with second UART. */
476 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
477 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
478 pci_read_config_byte(dev, 0x73, &data);
479 pci_write_config_byte(dev, 0x73, data & 0xef);
484 static int pci_siig_init(struct pci_dev *dev)
486 unsigned int type = dev->device & 0xff00;
489 return pci_siig10x_init(dev);
490 else if (type == 0x2000)
491 return pci_siig20x_init(dev);
493 moan_device("Unknown SIIG card", dev);
497 static int pci_siig_setup(struct serial_private *priv,
498 const struct pciserial_board *board,
499 struct uart_port *port, int idx)
501 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
505 offset = (idx - 4) * 8;
508 return setup_port(priv, port, bar, offset, 0);
512 * Timedia has an explosion of boards, and to avoid the PCI table from
513 * growing *huge*, we use this function to collapse some 70 entries
514 * in the PCI table into one, for sanity's and compactness's sake.
516 static const unsigned short timedia_single_port[] = {
517 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
520 static const unsigned short timedia_dual_port[] = {
521 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
522 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
523 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
524 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
528 static const unsigned short timedia_quad_port[] = {
529 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
530 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
531 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
535 static const unsigned short timedia_eight_port[] = {
536 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
537 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
540 static const struct timedia_struct {
542 const unsigned short *ids;
544 { 1, timedia_single_port },
545 { 2, timedia_dual_port },
546 { 4, timedia_quad_port },
547 { 8, timedia_eight_port }
550 static int pci_timedia_init(struct pci_dev *dev)
552 const unsigned short *ids;
555 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
556 ids = timedia_data[i].ids;
557 for (j = 0; ids[j]; j++)
558 if (dev->subsystem_device == ids[j])
559 return timedia_data[i].num;
565 * Timedia/SUNIX uses a mixture of BARs and offsets
566 * Ugh, this is ugly as all hell --- TYT
569 pci_timedia_setup(struct serial_private *priv,
570 const struct pciserial_board *board,
571 struct uart_port *port, int idx)
573 unsigned int bar = 0, offset = board->first_offset;
580 offset = board->uart_offset;
587 offset = board->uart_offset;
596 return setup_port(priv, port, bar, offset, board->reg_shift);
600 * Some Titan cards are also a little weird
603 titan_400l_800l_setup(struct serial_private *priv,
604 const struct pciserial_board *board,
605 struct uart_port *port, int idx)
607 unsigned int bar, offset = board->first_offset;
618 offset = (idx - 2) * board->uart_offset;
621 return setup_port(priv, port, bar, offset, board->reg_shift);
624 static int pci_xircom_init(struct pci_dev *dev)
630 #define MITE_IOWBSR1_WSIZE 0xa
631 #define MITE_IOWBSR1_WIN_OFFSET 0x800
632 #define MITE_IOWBSR1_WENAB (1 << 7)
633 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
634 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
635 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
637 static int pci_ni8430_init(struct pci_dev *dev)
640 unsigned long base, len;
642 unsigned int bar = 0;
644 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
645 moan_device("no memory in bar", dev);
649 base = pci_resource_start(dev, bar);
650 len = pci_resource_len(dev, bar);
651 p = ioremap_nocache(base, len);
655 /* Set device window address and size in BAR0 */
656 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
657 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
658 writel(device_window, p + MITE_IOWBSR1);
660 /* Set window access to go to RAMSEL IO address space */
661 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
664 /* Enable IO Bus Interrupt 0 */
665 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
667 /* Enable CPU Interrupt */
668 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
674 /* UART Port Control Register */
675 #define NI8430_PORTCON 0x0f
676 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
679 pci_ni8430_setup(struct serial_private *priv, struct pciserial_board *board,
680 struct uart_port *port, int idx)
683 unsigned long base, len;
684 unsigned int bar, offset = board->first_offset;
686 if (idx >= board->num_ports)
689 bar = FL_GET_BASE(board->flags);
690 offset += idx * board->uart_offset;
692 base = pci_resource_start(priv->dev, bar);
693 len = pci_resource_len(priv->dev, bar);
694 p = ioremap_nocache(base, len);
696 /* enable the transciever */
697 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
698 p + offset + NI8430_PORTCON);
702 return setup_port(priv, port, bar, offset, board->reg_shift);
706 static int pci_netmos_init(struct pci_dev *dev)
708 /* subdevice 0x00PS means <P> parallel, <S> serial */
709 unsigned int num_serial = dev->subsystem_device & 0xf;
711 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
712 dev->subsystem_device == 0x0299)
721 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
723 * These chips are available with optionally one parallel port and up to
724 * two serial ports. Unfortunately they all have the same product id.
726 * Basic configuration is done over a region of 32 I/O ports. The base
727 * ioport is called INTA or INTC, depending on docs/other drivers.
729 * The region of the 32 I/O ports is configured in POSIO0R...
733 #define ITE_887x_MISCR 0x9c
734 #define ITE_887x_INTCBAR 0x78
735 #define ITE_887x_UARTBAR 0x7c
736 #define ITE_887x_PS0BAR 0x10
737 #define ITE_887x_POSIO0 0x60
740 #define ITE_887x_IOSIZE 32
741 /* I/O space size (bits 26-24; 8 bytes = 011b) */
742 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
743 /* I/O space size (bits 26-24; 32 bytes = 101b) */
744 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
745 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
746 #define ITE_887x_POSIO_SPEED (3 << 29)
747 /* enable IO_Space bit */
748 #define ITE_887x_POSIO_ENABLE (1 << 31)
750 static int pci_ite887x_init(struct pci_dev *dev)
752 /* inta_addr are the configuration addresses of the ITE */
753 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
756 struct resource *iobase = NULL;
757 u32 miscr, uartbar, ioport;
759 /* search for the base-ioport */
761 while (inta_addr[i] && iobase == NULL) {
762 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
764 if (iobase != NULL) {
765 /* write POSIO0R - speed | size | ioport */
766 pci_write_config_dword(dev, ITE_887x_POSIO0,
767 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
768 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
769 /* write INTCBAR - ioport */
770 pci_write_config_dword(dev, ITE_887x_INTCBAR,
772 ret = inb(inta_addr[i]);
774 /* ioport connected */
777 release_region(iobase->start, ITE_887x_IOSIZE);
784 printk(KERN_ERR "ite887x: could not find iobase\n");
788 /* start of undocumented type checking (see parport_pc.c) */
789 type = inb(iobase->start + 0x18) & 0x0f;
792 case 0x2: /* ITE8871 (1P) */
793 case 0xa: /* ITE8875 (1P) */
796 case 0xe: /* ITE8872 (2S1P) */
799 case 0x6: /* ITE8873 (1S) */
802 case 0x8: /* ITE8874 (2S) */
806 moan_device("Unknown ITE887x", dev);
810 /* configure all serial ports */
811 for (i = 0; i < ret; i++) {
812 /* read the I/O port from the device */
813 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
815 ioport &= 0x0000FF00; /* the actual base address */
816 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
817 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
818 ITE_887x_POSIO_IOSIZE_8 | ioport);
820 /* write the ioport to the UARTBAR */
821 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
822 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
823 uartbar |= (ioport << (16 * i)); /* set the ioport */
824 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
826 /* get current config */
827 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
828 /* disable interrupts (UARTx_Routing[3:0]) */
829 miscr &= ~(0xf << (12 - 4 * i));
830 /* activate the UART (UARTx_En) */
831 miscr |= 1 << (23 - i);
832 /* write new config with activated UART */
833 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
837 /* the device has no UARTs if we get here */
838 release_region(iobase->start, ITE_887x_IOSIZE);
844 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
847 /* the ioport is bit 0-15 in POSIO0R */
848 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
850 release_region(ioport, ITE_887x_IOSIZE);
854 * Oxford Semiconductor Inc.
855 * Check that device is part of the Tornado range of devices, then determine
856 * the number of ports available on the device.
858 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
861 unsigned long deviceID;
862 unsigned int number_uarts = 0;
864 /* OxSemi Tornado devices are all 0xCxxx */
865 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
866 (dev->device & 0xF000) != 0xC000)
869 p = pci_iomap(dev, 0, 5);
873 deviceID = ioread32(p);
875 if (deviceID == 0x07000200) {
876 number_uarts = ioread8(p + 4);
878 "%d ports detected on Oxford PCI Express device\n",
886 pci_default_setup(struct serial_private *priv,
887 const struct pciserial_board *board,
888 struct uart_port *port, int idx)
890 unsigned int bar, offset = board->first_offset, maxnr;
892 bar = FL_GET_BASE(board->flags);
893 if (board->flags & FL_BASE_BARS)
896 offset += idx * board->uart_offset;
898 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
899 (board->reg_shift + 3);
901 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
904 return setup_port(priv, port, bar, offset, board->reg_shift);
907 static int skip_tx_en_setup(struct serial_private *priv,
908 const struct pciserial_board *board,
909 struct uart_port *port, int idx)
911 port->flags |= UPF_NO_TXEN_TEST;
912 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
913 "[%04x:%04x] subsystem [%04x:%04x]\n",
916 priv->dev->subsystem_vendor,
917 priv->dev->subsystem_device);
919 return pci_default_setup(priv, board, port, idx);
922 /* This should be in linux/pci_ids.h */
923 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
924 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
925 #define PCI_DEVICE_ID_OCTPRO 0x0001
926 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
927 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
928 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
929 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
930 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
931 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
933 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
934 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
937 * Master list of serial port init/setup/exit quirks.
938 * This does not describe the general nature of the port.
939 * (ie, baud base, number and location of ports, etc)
941 * This list is ordered alphabetically by vendor then device.
942 * Specific entries must come before more generic entries.
944 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
946 * ADDI-DATA GmbH communication cards <info@addi-data.com>
949 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
950 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
951 .subvendor = PCI_ANY_ID,
952 .subdevice = PCI_ANY_ID,
953 .setup = addidata_apci7800_setup,
956 * AFAVLAB cards - these may be called via parport_serial
957 * It is not clear whether this applies to all products.
960 .vendor = PCI_VENDOR_ID_AFAVLAB,
961 .device = PCI_ANY_ID,
962 .subvendor = PCI_ANY_ID,
963 .subdevice = PCI_ANY_ID,
964 .setup = afavlab_setup,
970 .vendor = PCI_VENDOR_ID_HP,
971 .device = PCI_DEVICE_ID_HP_DIVA,
972 .subvendor = PCI_ANY_ID,
973 .subdevice = PCI_ANY_ID,
974 .init = pci_hp_diva_init,
975 .setup = pci_hp_diva_setup,
981 .vendor = PCI_VENDOR_ID_INTEL,
982 .device = PCI_DEVICE_ID_INTEL_80960_RP,
984 .subdevice = PCI_ANY_ID,
985 .init = pci_inteli960ni_init,
986 .setup = pci_default_setup,
989 .vendor = PCI_VENDOR_ID_INTEL,
990 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
991 .subvendor = PCI_ANY_ID,
992 .subdevice = PCI_ANY_ID,
993 .setup = skip_tx_en_setup,
996 .vendor = PCI_VENDOR_ID_INTEL,
997 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
998 .subvendor = PCI_ANY_ID,
999 .subdevice = PCI_ANY_ID,
1000 .setup = skip_tx_en_setup,
1003 .vendor = PCI_VENDOR_ID_INTEL,
1004 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1005 .subvendor = PCI_ANY_ID,
1006 .subdevice = PCI_ANY_ID,
1007 .setup = skip_tx_en_setup,
1013 .vendor = PCI_VENDOR_ID_ITE,
1014 .device = PCI_DEVICE_ID_ITE_8872,
1015 .subvendor = PCI_ANY_ID,
1016 .subdevice = PCI_ANY_ID,
1017 .init = pci_ite887x_init,
1018 .setup = pci_default_setup,
1019 .exit = __devexit_p(pci_ite887x_exit),
1022 * National Instruments
1025 .vendor = PCI_VENDOR_ID_NI,
1026 .device = PCI_ANY_ID,
1027 .subvendor = PCI_ANY_ID,
1028 .subdevice = PCI_ANY_ID,
1029 .init = pci_ni8430_init,
1030 .setup = pci_ni8430_setup,
1031 .exit = __devexit_p(pci_ni8430_exit),
1037 .vendor = PCI_VENDOR_ID_PANACOM,
1038 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1039 .subvendor = PCI_ANY_ID,
1040 .subdevice = PCI_ANY_ID,
1041 .init = pci_plx9050_init,
1042 .setup = pci_default_setup,
1043 .exit = __devexit_p(pci_plx9050_exit),
1046 .vendor = PCI_VENDOR_ID_PANACOM,
1047 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1048 .subvendor = PCI_ANY_ID,
1049 .subdevice = PCI_ANY_ID,
1050 .init = pci_plx9050_init,
1051 .setup = pci_default_setup,
1052 .exit = __devexit_p(pci_plx9050_exit),
1058 .vendor = PCI_VENDOR_ID_PLX,
1059 .device = PCI_DEVICE_ID_PLX_9030,
1060 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1061 .subdevice = PCI_ANY_ID,
1062 .setup = pci_default_setup,
1065 .vendor = PCI_VENDOR_ID_PLX,
1066 .device = PCI_DEVICE_ID_PLX_9050,
1067 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1068 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1069 .init = pci_plx9050_init,
1070 .setup = pci_default_setup,
1071 .exit = __devexit_p(pci_plx9050_exit),
1074 .vendor = PCI_VENDOR_ID_PLX,
1075 .device = PCI_DEVICE_ID_PLX_9050,
1076 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1077 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1078 .init = pci_plx9050_init,
1079 .setup = pci_default_setup,
1080 .exit = __devexit_p(pci_plx9050_exit),
1083 .vendor = PCI_VENDOR_ID_PLX,
1084 .device = PCI_DEVICE_ID_PLX_9050,
1085 .subvendor = PCI_VENDOR_ID_PLX,
1086 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1087 .init = pci_plx9050_init,
1088 .setup = pci_default_setup,
1089 .exit = __devexit_p(pci_plx9050_exit),
1092 .vendor = PCI_VENDOR_ID_PLX,
1093 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1094 .subvendor = PCI_VENDOR_ID_PLX,
1095 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1096 .init = pci_plx9050_init,
1097 .setup = pci_default_setup,
1098 .exit = __devexit_p(pci_plx9050_exit),
1101 * SBS Technologies, Inc., PMC-OCTALPRO 232
1104 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1105 .device = PCI_DEVICE_ID_OCTPRO,
1106 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1107 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1110 .exit = __devexit_p(sbs_exit),
1113 * SBS Technologies, Inc., PMC-OCTALPRO 422
1116 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1117 .device = PCI_DEVICE_ID_OCTPRO,
1118 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1119 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1122 .exit = __devexit_p(sbs_exit),
1125 * SBS Technologies, Inc., P-Octal 232
1128 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1129 .device = PCI_DEVICE_ID_OCTPRO,
1130 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1131 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1134 .exit = __devexit_p(sbs_exit),
1137 * SBS Technologies, Inc., P-Octal 422
1140 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1141 .device = PCI_DEVICE_ID_OCTPRO,
1142 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1143 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1146 .exit = __devexit_p(sbs_exit),
1149 * SIIG cards - these may be called via parport_serial
1152 .vendor = PCI_VENDOR_ID_SIIG,
1153 .device = PCI_ANY_ID,
1154 .subvendor = PCI_ANY_ID,
1155 .subdevice = PCI_ANY_ID,
1156 .init = pci_siig_init,
1157 .setup = pci_siig_setup,
1163 .vendor = PCI_VENDOR_ID_TITAN,
1164 .device = PCI_DEVICE_ID_TITAN_400L,
1165 .subvendor = PCI_ANY_ID,
1166 .subdevice = PCI_ANY_ID,
1167 .setup = titan_400l_800l_setup,
1170 .vendor = PCI_VENDOR_ID_TITAN,
1171 .device = PCI_DEVICE_ID_TITAN_800L,
1172 .subvendor = PCI_ANY_ID,
1173 .subdevice = PCI_ANY_ID,
1174 .setup = titan_400l_800l_setup,
1180 .vendor = PCI_VENDOR_ID_TIMEDIA,
1181 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1182 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1183 .subdevice = PCI_ANY_ID,
1184 .init = pci_timedia_init,
1185 .setup = pci_timedia_setup,
1188 .vendor = PCI_VENDOR_ID_TIMEDIA,
1189 .device = PCI_ANY_ID,
1190 .subvendor = PCI_ANY_ID,
1191 .subdevice = PCI_ANY_ID,
1192 .setup = pci_timedia_setup,
1198 .vendor = PCI_VENDOR_ID_XIRCOM,
1199 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1200 .subvendor = PCI_ANY_ID,
1201 .subdevice = PCI_ANY_ID,
1202 .init = pci_xircom_init,
1203 .setup = pci_default_setup,
1206 * Netmos cards - these may be called via parport_serial
1209 .vendor = PCI_VENDOR_ID_NETMOS,
1210 .device = PCI_ANY_ID,
1211 .subvendor = PCI_ANY_ID,
1212 .subdevice = PCI_ANY_ID,
1213 .init = pci_netmos_init,
1214 .setup = pci_default_setup,
1217 * For Oxford Semiconductor and Mainpine
1220 .vendor = PCI_VENDOR_ID_OXSEMI,
1221 .device = PCI_ANY_ID,
1222 .subvendor = PCI_ANY_ID,
1223 .subdevice = PCI_ANY_ID,
1224 .init = pci_oxsemi_tornado_init,
1225 .setup = pci_default_setup,
1228 .vendor = PCI_VENDOR_ID_MAINPINE,
1229 .device = PCI_ANY_ID,
1230 .subvendor = PCI_ANY_ID,
1231 .subdevice = PCI_ANY_ID,
1232 .init = pci_oxsemi_tornado_init,
1233 .setup = pci_default_setup,
1236 * Default "match everything" terminator entry
1239 .vendor = PCI_ANY_ID,
1240 .device = PCI_ANY_ID,
1241 .subvendor = PCI_ANY_ID,
1242 .subdevice = PCI_ANY_ID,
1243 .setup = pci_default_setup,
1247 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1249 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1252 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1254 struct pci_serial_quirk *quirk;
1256 for (quirk = pci_serial_quirks; ; quirk++)
1257 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1258 quirk_id_matches(quirk->device, dev->device) &&
1259 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1260 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1265 static inline int get_pci_irq(struct pci_dev *dev,
1266 const struct pciserial_board *board)
1268 if (board->flags & FL_NOIRQ)
1275 * This is the configuration table for all of the PCI serial boards
1276 * which we support. It is directly indexed by the pci_board_num_t enum
1277 * value, which is encoded in the pci_device_id PCI probe table's
1278 * driver_data member.
1280 * The makeup of these names are:
1281 * pbn_bn{_bt}_n_baud{_offsetinhex}
1283 * bn = PCI BAR number
1284 * bt = Index using PCI BARs
1285 * n = number of serial ports
1287 * offsetinhex = offset for each sequential port (in hex)
1289 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1291 * Please note: in theory if n = 1, _bt infix should make no difference.
1292 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1294 enum pci_board_num_t {
1314 pbn_b0_2_1843200_200,
1315 pbn_b0_4_1843200_200,
1316 pbn_b0_8_1843200_200,
1379 * Board-specific versions.
1387 pbn_oxsemi_1_4000000,
1388 pbn_oxsemi_2_4000000,
1389 pbn_oxsemi_4_4000000,
1390 pbn_oxsemi_8_4000000,
1408 * uart_offset - the space between channels
1409 * reg_shift - describes how the UART registers are mapped
1410 * to PCI memory by the card.
1411 * For example IER register on SBS, Inc. PMC-OctPro is located at
1412 * offset 0x10 from the UART base, while UART_IER is defined as 1
1413 * in include/linux/serial_reg.h,
1414 * see first lines of serial_in() and serial_out() in 8250.c
1417 static struct pciserial_board pci_boards[] __devinitdata = {
1421 .base_baud = 115200,
1424 [pbn_b0_1_115200] = {
1427 .base_baud = 115200,
1430 [pbn_b0_2_115200] = {
1433 .base_baud = 115200,
1436 [pbn_b0_4_115200] = {
1439 .base_baud = 115200,
1442 [pbn_b0_5_115200] = {
1445 .base_baud = 115200,
1448 [pbn_b0_8_115200] = {
1451 .base_baud = 115200,
1454 [pbn_b0_1_921600] = {
1457 .base_baud = 921600,
1460 [pbn_b0_2_921600] = {
1463 .base_baud = 921600,
1466 [pbn_b0_4_921600] = {
1469 .base_baud = 921600,
1473 [pbn_b0_2_1130000] = {
1476 .base_baud = 1130000,
1480 [pbn_b0_4_1152000] = {
1483 .base_baud = 1152000,
1487 [pbn_b0_2_1843200] = {
1490 .base_baud = 1843200,
1493 [pbn_b0_4_1843200] = {
1496 .base_baud = 1843200,
1500 [pbn_b0_2_1843200_200] = {
1503 .base_baud = 1843200,
1504 .uart_offset = 0x200,
1506 [pbn_b0_4_1843200_200] = {
1509 .base_baud = 1843200,
1510 .uart_offset = 0x200,
1512 [pbn_b0_8_1843200_200] = {
1515 .base_baud = 1843200,
1516 .uart_offset = 0x200,
1518 [pbn_b0_1_4000000] = {
1521 .base_baud = 4000000,
1525 [pbn_b0_bt_1_115200] = {
1526 .flags = FL_BASE0|FL_BASE_BARS,
1528 .base_baud = 115200,
1531 [pbn_b0_bt_2_115200] = {
1532 .flags = FL_BASE0|FL_BASE_BARS,
1534 .base_baud = 115200,
1537 [pbn_b0_bt_8_115200] = {
1538 .flags = FL_BASE0|FL_BASE_BARS,
1540 .base_baud = 115200,
1544 [pbn_b0_bt_1_460800] = {
1545 .flags = FL_BASE0|FL_BASE_BARS,
1547 .base_baud = 460800,
1550 [pbn_b0_bt_2_460800] = {
1551 .flags = FL_BASE0|FL_BASE_BARS,
1553 .base_baud = 460800,
1556 [pbn_b0_bt_4_460800] = {
1557 .flags = FL_BASE0|FL_BASE_BARS,
1559 .base_baud = 460800,
1563 [pbn_b0_bt_1_921600] = {
1564 .flags = FL_BASE0|FL_BASE_BARS,
1566 .base_baud = 921600,
1569 [pbn_b0_bt_2_921600] = {
1570 .flags = FL_BASE0|FL_BASE_BARS,
1572 .base_baud = 921600,
1575 [pbn_b0_bt_4_921600] = {
1576 .flags = FL_BASE0|FL_BASE_BARS,
1578 .base_baud = 921600,
1581 [pbn_b0_bt_8_921600] = {
1582 .flags = FL_BASE0|FL_BASE_BARS,
1584 .base_baud = 921600,
1588 [pbn_b1_1_115200] = {
1591 .base_baud = 115200,
1594 [pbn_b1_2_115200] = {
1597 .base_baud = 115200,
1600 [pbn_b1_4_115200] = {
1603 .base_baud = 115200,
1606 [pbn_b1_8_115200] = {
1609 .base_baud = 115200,
1613 [pbn_b1_1_921600] = {
1616 .base_baud = 921600,
1619 [pbn_b1_2_921600] = {
1622 .base_baud = 921600,
1625 [pbn_b1_4_921600] = {
1628 .base_baud = 921600,
1631 [pbn_b1_8_921600] = {
1634 .base_baud = 921600,
1637 [pbn_b1_2_1250000] = {
1640 .base_baud = 1250000,
1644 [pbn_b1_bt_1_115200] = {
1645 .flags = FL_BASE1|FL_BASE_BARS,
1647 .base_baud = 115200,
1651 [pbn_b1_bt_2_921600] = {
1652 .flags = FL_BASE1|FL_BASE_BARS,
1654 .base_baud = 921600,
1658 [pbn_b1_1_1382400] = {
1661 .base_baud = 1382400,
1664 [pbn_b1_2_1382400] = {
1667 .base_baud = 1382400,
1670 [pbn_b1_4_1382400] = {
1673 .base_baud = 1382400,
1676 [pbn_b1_8_1382400] = {
1679 .base_baud = 1382400,
1683 [pbn_b2_1_115200] = {
1686 .base_baud = 115200,
1689 [pbn_b2_2_115200] = {
1692 .base_baud = 115200,
1695 [pbn_b2_4_115200] = {
1698 .base_baud = 115200,
1701 [pbn_b2_8_115200] = {
1704 .base_baud = 115200,
1708 [pbn_b2_1_460800] = {
1711 .base_baud = 460800,
1714 [pbn_b2_4_460800] = {
1717 .base_baud = 460800,
1720 [pbn_b2_8_460800] = {
1723 .base_baud = 460800,
1726 [pbn_b2_16_460800] = {
1729 .base_baud = 460800,
1733 [pbn_b2_1_921600] = {
1736 .base_baud = 921600,
1739 [pbn_b2_4_921600] = {
1742 .base_baud = 921600,
1745 [pbn_b2_8_921600] = {
1748 .base_baud = 921600,
1752 [pbn_b2_bt_1_115200] = {
1753 .flags = FL_BASE2|FL_BASE_BARS,
1755 .base_baud = 115200,
1758 [pbn_b2_bt_2_115200] = {
1759 .flags = FL_BASE2|FL_BASE_BARS,
1761 .base_baud = 115200,
1764 [pbn_b2_bt_4_115200] = {
1765 .flags = FL_BASE2|FL_BASE_BARS,
1767 .base_baud = 115200,
1771 [pbn_b2_bt_2_921600] = {
1772 .flags = FL_BASE2|FL_BASE_BARS,
1774 .base_baud = 921600,
1777 [pbn_b2_bt_4_921600] = {
1778 .flags = FL_BASE2|FL_BASE_BARS,
1780 .base_baud = 921600,
1784 [pbn_b3_2_115200] = {
1787 .base_baud = 115200,
1790 [pbn_b3_4_115200] = {
1793 .base_baud = 115200,
1796 [pbn_b3_8_115200] = {
1799 .base_baud = 115200,
1804 * Entries following this are board-specific.
1813 .base_baud = 921600,
1814 .uart_offset = 0x400,
1818 .flags = FL_BASE2|FL_BASE_BARS,
1820 .base_baud = 921600,
1821 .uart_offset = 0x400,
1825 .flags = FL_BASE2|FL_BASE_BARS,
1827 .base_baud = 921600,
1828 .uart_offset = 0x400,
1832 [pbn_exsys_4055] = {
1835 .base_baud = 115200,
1839 /* I think this entry is broken - the first_offset looks wrong --rmk */
1840 [pbn_plx_romulus] = {
1843 .base_baud = 921600,
1844 .uart_offset = 8 << 2,
1846 .first_offset = 0x03,
1850 * This board uses the size of PCI Base region 0 to
1851 * signal now many ports are available
1854 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1856 .base_baud = 115200,
1859 [pbn_oxsemi_1_4000000] = {
1862 .base_baud = 4000000,
1863 .uart_offset = 0x200,
1864 .first_offset = 0x1000,
1866 [pbn_oxsemi_2_4000000] = {
1869 .base_baud = 4000000,
1870 .uart_offset = 0x200,
1871 .first_offset = 0x1000,
1873 [pbn_oxsemi_4_4000000] = {
1876 .base_baud = 4000000,
1877 .uart_offset = 0x200,
1878 .first_offset = 0x1000,
1880 [pbn_oxsemi_8_4000000] = {
1883 .base_baud = 4000000,
1884 .uart_offset = 0x200,
1885 .first_offset = 0x1000,
1890 * EKF addition for i960 Boards form EKF with serial port.
1893 [pbn_intel_i960] = {
1896 .base_baud = 921600,
1897 .uart_offset = 8 << 2,
1899 .first_offset = 0x10000,
1902 .flags = FL_BASE0|FL_NOIRQ,
1904 .base_baud = 458333,
1907 .first_offset = 0x20178,
1911 * Computone - uses IOMEM.
1913 [pbn_computone_4] = {
1916 .base_baud = 921600,
1917 .uart_offset = 0x40,
1919 .first_offset = 0x200,
1921 [pbn_computone_6] = {
1924 .base_baud = 921600,
1925 .uart_offset = 0x40,
1927 .first_offset = 0x200,
1929 [pbn_computone_8] = {
1932 .base_baud = 921600,
1933 .uart_offset = 0x40,
1935 .first_offset = 0x200,
1940 .base_baud = 460800,
1945 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1946 * Only basic 16550A support.
1947 * XR17C15[24] are not tested, but they should work.
1949 [pbn_exar_XR17C152] = {
1952 .base_baud = 921600,
1953 .uart_offset = 0x200,
1955 [pbn_exar_XR17C154] = {
1958 .base_baud = 921600,
1959 .uart_offset = 0x200,
1961 [pbn_exar_XR17C158] = {
1964 .base_baud = 921600,
1965 .uart_offset = 0x200,
1968 * PA Semi PWRficient PA6T-1682M on-chip UART
1970 [pbn_pasemi_1682M] = {
1973 .base_baud = 8333333,
1976 * National Instruments 843x
1981 .base_baud = 3686400,
1982 .uart_offset = 0x10,
1983 .first_offset = 0x800,
1988 .base_baud = 3686400,
1989 .uart_offset = 0x10,
1990 .first_offset = 0x800,
1995 .base_baud = 3686400,
1996 .uart_offset = 0x10,
1997 .first_offset = 0x800,
2002 .base_baud = 3686400,
2003 .uart_offset = 0x10,
2004 .first_offset = 0x800,
2008 static const struct pci_device_id softmodem_blacklist[] = {
2009 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2013 * Given a complete unknown PCI device, try to use some heuristics to
2014 * guess what the configuration might be, based on the pitiful PCI
2015 * serial specs. Returns 0 on success, 1 on failure.
2017 static int __devinit
2018 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2020 const struct pci_device_id *blacklist;
2021 int num_iomem, num_port, first_port = -1, i;
2024 * If it is not a communications device or the programming
2025 * interface is greater than 6, give up.
2027 * (Should we try to make guesses for multiport serial devices
2030 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2031 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2032 (dev->class & 0xff) > 6)
2036 * Do not access blacklisted devices that are known not to
2037 * feature serial ports.
2039 for (blacklist = softmodem_blacklist;
2040 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2042 if (dev->vendor == blacklist->vendor &&
2043 dev->device == blacklist->device)
2047 num_iomem = num_port = 0;
2048 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2049 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2051 if (first_port == -1)
2054 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2059 * If there is 1 or 0 iomem regions, and exactly one port,
2060 * use it. We guess the number of ports based on the IO
2063 if (num_iomem <= 1 && num_port == 1) {
2064 board->flags = first_port;
2065 board->num_ports = pci_resource_len(dev, first_port) / 8;
2070 * Now guess if we've got a board which indexes by BARs.
2071 * Each IO BAR should be 8 bytes, and they should follow
2076 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2077 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2078 pci_resource_len(dev, i) == 8 &&
2079 (first_port == -1 || (first_port + num_port) == i)) {
2081 if (first_port == -1)
2087 board->flags = first_port | FL_BASE_BARS;
2088 board->num_ports = num_port;
2096 serial_pci_matches(const struct pciserial_board *board,
2097 const struct pciserial_board *guessed)
2100 board->num_ports == guessed->num_ports &&
2101 board->base_baud == guessed->base_baud &&
2102 board->uart_offset == guessed->uart_offset &&
2103 board->reg_shift == guessed->reg_shift &&
2104 board->first_offset == guessed->first_offset;
2107 struct serial_private *
2108 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2110 struct uart_port serial_port;
2111 struct serial_private *priv;
2112 struct pci_serial_quirk *quirk;
2113 int rc, nr_ports, i;
2115 nr_ports = board->num_ports;
2118 * Find an init and setup quirks.
2120 quirk = find_quirk(dev);
2123 * Run the new-style initialization function.
2124 * The initialization function returns:
2126 * 0 - use board->num_ports
2127 * >0 - number of ports
2130 rc = quirk->init(dev);
2139 priv = kzalloc(sizeof(struct serial_private) +
2140 sizeof(unsigned int) * nr_ports,
2143 priv = ERR_PTR(-ENOMEM);
2148 priv->quirk = quirk;
2150 memset(&serial_port, 0, sizeof(struct uart_port));
2151 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2152 serial_port.uartclk = board->base_baud * 16;
2153 serial_port.irq = get_pci_irq(dev, board);
2154 serial_port.dev = &dev->dev;
2156 for (i = 0; i < nr_ports; i++) {
2157 if (quirk->setup(priv, board, &serial_port, i))
2160 #ifdef SERIAL_DEBUG_PCI
2161 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
2162 serial_port.iobase, serial_port.irq, serial_port.iotype);
2165 priv->line[i] = serial8250_register_port(&serial_port);
2166 if (priv->line[i] < 0) {
2167 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2180 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2182 void pciserial_remove_ports(struct serial_private *priv)
2184 struct pci_serial_quirk *quirk;
2187 for (i = 0; i < priv->nr; i++)
2188 serial8250_unregister_port(priv->line[i]);
2190 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2191 if (priv->remapped_bar[i])
2192 iounmap(priv->remapped_bar[i]);
2193 priv->remapped_bar[i] = NULL;
2197 * Find the exit quirks.
2199 quirk = find_quirk(priv->dev);
2201 quirk->exit(priv->dev);
2205 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2207 void pciserial_suspend_ports(struct serial_private *priv)
2211 for (i = 0; i < priv->nr; i++)
2212 if (priv->line[i] >= 0)
2213 serial8250_suspend_port(priv->line[i]);
2215 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2217 void pciserial_resume_ports(struct serial_private *priv)
2222 * Ensure that the board is correctly configured.
2224 if (priv->quirk->init)
2225 priv->quirk->init(priv->dev);
2227 for (i = 0; i < priv->nr; i++)
2228 if (priv->line[i] >= 0)
2229 serial8250_resume_port(priv->line[i]);
2231 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2234 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2235 * to the arrangement of serial ports on a PCI card.
2237 static int __devinit
2238 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2240 struct serial_private *priv;
2241 const struct pciserial_board *board;
2242 struct pciserial_board tmp;
2245 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2246 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2251 board = &pci_boards[ent->driver_data];
2253 rc = pci_enable_device(dev);
2257 if (ent->driver_data == pbn_default) {
2259 * Use a copy of the pci_board entry for this;
2260 * avoid changing entries in the table.
2262 memcpy(&tmp, board, sizeof(struct pciserial_board));
2266 * We matched one of our class entries. Try to
2267 * determine the parameters of this board.
2269 rc = serial_pci_guess_board(dev, &tmp);
2274 * We matched an explicit entry. If we are able to
2275 * detect this boards settings with our heuristic,
2276 * then we no longer need this entry.
2278 memcpy(&tmp, &pci_boards[pbn_default],
2279 sizeof(struct pciserial_board));
2280 rc = serial_pci_guess_board(dev, &tmp);
2281 if (rc == 0 && serial_pci_matches(board, &tmp))
2282 moan_device("Redundant entry in serial pci_table.",
2286 priv = pciserial_init_ports(dev, board);
2287 if (!IS_ERR(priv)) {
2288 pci_set_drvdata(dev, priv);
2295 pci_disable_device(dev);
2299 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2301 struct serial_private *priv = pci_get_drvdata(dev);
2303 pci_set_drvdata(dev, NULL);
2305 pciserial_remove_ports(priv);
2307 pci_disable_device(dev);
2311 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2313 struct serial_private *priv = pci_get_drvdata(dev);
2316 pciserial_suspend_ports(priv);
2318 pci_save_state(dev);
2319 pci_set_power_state(dev, pci_choose_state(dev, state));
2323 static int pciserial_resume_one(struct pci_dev *dev)
2326 struct serial_private *priv = pci_get_drvdata(dev);
2328 pci_set_power_state(dev, PCI_D0);
2329 pci_restore_state(dev);
2333 * The device may have been disabled. Re-enable it.
2335 err = pci_enable_device(dev);
2336 /* FIXME: We cannot simply error out here */
2338 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2339 pciserial_resume_ports(priv);
2345 static struct pci_device_id serial_pci_tbl[] = {
2346 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2347 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2348 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2350 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2351 PCI_SUBVENDOR_ID_CONNECT_TECH,
2352 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2354 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2355 PCI_SUBVENDOR_ID_CONNECT_TECH,
2356 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2358 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2359 PCI_SUBVENDOR_ID_CONNECT_TECH,
2360 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2362 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2363 PCI_SUBVENDOR_ID_CONNECT_TECH,
2364 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2366 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2367 PCI_SUBVENDOR_ID_CONNECT_TECH,
2368 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2370 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2371 PCI_SUBVENDOR_ID_CONNECT_TECH,
2372 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2374 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2375 PCI_SUBVENDOR_ID_CONNECT_TECH,
2376 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2378 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2379 PCI_SUBVENDOR_ID_CONNECT_TECH,
2380 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2382 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2383 PCI_SUBVENDOR_ID_CONNECT_TECH,
2384 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2386 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2387 PCI_SUBVENDOR_ID_CONNECT_TECH,
2388 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2390 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2391 PCI_SUBVENDOR_ID_CONNECT_TECH,
2392 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2394 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2395 PCI_SUBVENDOR_ID_CONNECT_TECH,
2396 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2398 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2399 PCI_SUBVENDOR_ID_CONNECT_TECH,
2400 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2402 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2403 PCI_SUBVENDOR_ID_CONNECT_TECH,
2404 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2406 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2407 PCI_SUBVENDOR_ID_CONNECT_TECH,
2408 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2410 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2411 PCI_SUBVENDOR_ID_CONNECT_TECH,
2412 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2414 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2415 PCI_SUBVENDOR_ID_CONNECT_TECH,
2416 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2418 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2419 PCI_VENDOR_ID_AFAVLAB,
2420 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2422 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2423 PCI_SUBVENDOR_ID_CONNECT_TECH,
2424 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2425 pbn_b0_2_1843200_200 },
2426 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2427 PCI_SUBVENDOR_ID_CONNECT_TECH,
2428 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2429 pbn_b0_4_1843200_200 },
2430 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2431 PCI_SUBVENDOR_ID_CONNECT_TECH,
2432 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2433 pbn_b0_8_1843200_200 },
2434 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2435 PCI_SUBVENDOR_ID_CONNECT_TECH,
2436 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2437 pbn_b0_2_1843200_200 },
2438 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2439 PCI_SUBVENDOR_ID_CONNECT_TECH,
2440 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2441 pbn_b0_4_1843200_200 },
2442 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2443 PCI_SUBVENDOR_ID_CONNECT_TECH,
2444 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2445 pbn_b0_8_1843200_200 },
2446 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2447 PCI_SUBVENDOR_ID_CONNECT_TECH,
2448 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2449 pbn_b0_2_1843200_200 },
2450 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2451 PCI_SUBVENDOR_ID_CONNECT_TECH,
2452 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2453 pbn_b0_4_1843200_200 },
2454 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2455 PCI_SUBVENDOR_ID_CONNECT_TECH,
2456 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2457 pbn_b0_8_1843200_200 },
2458 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2459 PCI_SUBVENDOR_ID_CONNECT_TECH,
2460 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2461 pbn_b0_2_1843200_200 },
2462 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2463 PCI_SUBVENDOR_ID_CONNECT_TECH,
2464 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2465 pbn_b0_4_1843200_200 },
2466 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2467 PCI_SUBVENDOR_ID_CONNECT_TECH,
2468 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2469 pbn_b0_8_1843200_200 },
2471 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2473 pbn_b2_bt_1_115200 },
2474 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2476 pbn_b2_bt_2_115200 },
2477 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2479 pbn_b2_bt_4_115200 },
2480 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2482 pbn_b2_bt_2_115200 },
2483 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2485 pbn_b2_bt_4_115200 },
2486 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2489 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2492 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2496 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2498 pbn_b2_bt_2_115200 },
2499 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2501 pbn_b2_bt_2_921600 },
2503 * VScom SPCOM800, from sl@s.pl
2505 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2508 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2511 /* Unknown card - subdevice 0x1584 */
2512 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2514 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2516 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2517 PCI_SUBVENDOR_ID_KEYSPAN,
2518 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2520 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2523 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2526 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2527 PCI_VENDOR_ID_ESDGMBH,
2528 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2530 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2531 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2532 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2534 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2535 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2536 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2538 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2539 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2540 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2542 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2543 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2544 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2546 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2547 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2548 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2550 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2551 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2552 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2554 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2555 PCI_SUBVENDOR_ID_EXSYS,
2556 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2559 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2562 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2563 0x10b5, 0x106a, 0, 0,
2565 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2566 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2568 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2571 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2574 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2577 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2578 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2581 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2582 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2587 * The below card is a little controversial since it is the
2588 * subject of a PCI vendor/device ID clash. (See
2589 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2590 * For now just used the hex ID 0x950a.
2592 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2593 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2595 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2598 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2601 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2603 pbn_b0_bt_2_921600 },
2606 * Oxford Semiconductor Inc. Tornado PCI express device range.
2608 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2611 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2614 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2616 pbn_oxsemi_1_4000000 },
2617 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2619 pbn_oxsemi_1_4000000 },
2620 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2623 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2626 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2628 pbn_oxsemi_1_4000000 },
2629 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2631 pbn_oxsemi_1_4000000 },
2632 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2635 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2638 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2641 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2644 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2646 pbn_oxsemi_2_4000000 },
2647 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2649 pbn_oxsemi_2_4000000 },
2650 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2652 pbn_oxsemi_4_4000000 },
2653 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2655 pbn_oxsemi_4_4000000 },
2656 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2658 pbn_oxsemi_8_4000000 },
2659 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2661 pbn_oxsemi_8_4000000 },
2662 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2664 pbn_oxsemi_1_4000000 },
2665 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2666 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2667 pbn_oxsemi_1_4000000 },
2668 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2669 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2670 pbn_oxsemi_1_4000000 },
2671 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2673 pbn_oxsemi_1_4000000 },
2674 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2676 pbn_oxsemi_1_4000000 },
2677 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2678 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2679 pbn_oxsemi_1_4000000 },
2680 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2682 pbn_oxsemi_1_4000000 },
2683 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2684 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2685 pbn_oxsemi_1_4000000 },
2686 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2688 pbn_oxsemi_1_4000000 },
2689 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2691 pbn_oxsemi_1_4000000 },
2692 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2694 pbn_oxsemi_1_4000000 },
2695 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2697 pbn_oxsemi_1_4000000 },
2698 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2700 pbn_oxsemi_1_4000000 },
2701 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2703 pbn_oxsemi_1_4000000 },
2704 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2706 pbn_oxsemi_1_4000000 },
2707 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2709 pbn_oxsemi_1_4000000 },
2710 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2712 pbn_oxsemi_1_4000000 },
2713 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2715 pbn_oxsemi_1_4000000 },
2716 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
2717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2718 pbn_oxsemi_1_4000000 },
2719 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
2720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2721 pbn_oxsemi_1_4000000 },
2722 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
2723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2724 pbn_oxsemi_1_4000000 },
2725 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
2726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2727 pbn_oxsemi_1_4000000 },
2728 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
2729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2730 pbn_oxsemi_1_4000000 },
2731 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
2732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2733 pbn_oxsemi_1_4000000 },
2734 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
2735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2736 pbn_oxsemi_1_4000000 },
2737 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
2738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2739 pbn_oxsemi_1_4000000 },
2741 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2743 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2744 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2745 pbn_oxsemi_1_4000000 },
2746 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2747 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2748 pbn_oxsemi_2_4000000 },
2749 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2750 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2751 pbn_oxsemi_4_4000000 },
2752 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2753 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2754 pbn_oxsemi_8_4000000 },
2756 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2757 * from skokodyn@yahoo.com
2759 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2760 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2762 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2763 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2765 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2766 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2768 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2769 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2773 * Digitan DS560-558, from jimd@esoft.com
2775 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2780 * Titan Electronic cards
2781 * The 400L and 800L have a custom setup quirk.
2783 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2786 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2789 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2792 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2795 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2798 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2800 pbn_b1_bt_2_921600 },
2801 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2803 pbn_b0_bt_4_921600 },
2804 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2806 pbn_b0_bt_8_921600 },
2808 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2811 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2814 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2817 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2819 pbn_b2_bt_2_921600 },
2820 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2822 pbn_b2_bt_2_921600 },
2823 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2825 pbn_b2_bt_2_921600 },
2826 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2828 pbn_b2_bt_4_921600 },
2829 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2831 pbn_b2_bt_4_921600 },
2832 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2834 pbn_b2_bt_4_921600 },
2835 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2838 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2841 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2844 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2846 pbn_b0_bt_2_921600 },
2847 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2849 pbn_b0_bt_2_921600 },
2850 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2852 pbn_b0_bt_2_921600 },
2853 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2855 pbn_b0_bt_4_921600 },
2856 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2857 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2858 pbn_b0_bt_4_921600 },
2859 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2861 pbn_b0_bt_4_921600 },
2862 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2864 pbn_b0_bt_8_921600 },
2865 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2867 pbn_b0_bt_8_921600 },
2868 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2870 pbn_b0_bt_8_921600 },
2873 * Computone devices submitted by Doug McNash dmcnash@computone.com
2875 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2876 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2877 0, 0, pbn_computone_4 },
2878 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2879 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2880 0, 0, pbn_computone_8 },
2881 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2882 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2883 0, 0, pbn_computone_6 },
2885 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2888 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2889 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2890 pbn_b0_bt_1_921600 },
2893 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2895 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2897 pbn_b0_bt_8_115200 },
2898 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2900 pbn_b0_bt_8_115200 },
2902 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2904 pbn_b0_bt_2_115200 },
2905 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2907 pbn_b0_bt_2_115200 },
2908 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2910 pbn_b0_bt_2_115200 },
2911 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2913 pbn_b0_bt_4_460800 },
2914 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2916 pbn_b0_bt_4_460800 },
2917 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2919 pbn_b0_bt_2_460800 },
2920 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2922 pbn_b0_bt_2_460800 },
2923 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2925 pbn_b0_bt_2_460800 },
2926 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2928 pbn_b0_bt_1_115200 },
2929 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2931 pbn_b0_bt_1_460800 },
2934 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2935 * Cards are identified by their subsystem vendor IDs, which
2936 * (in hex) match the model number.
2938 * Note that JC140x are RS422/485 cards which require ox950
2939 * ACR = 0x10, and as such are not currently fully supported.
2941 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2942 0x1204, 0x0004, 0, 0,
2944 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2945 0x1208, 0x0004, 0, 0,
2947 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2948 0x1402, 0x0002, 0, 0,
2949 pbn_b0_2_921600 }, */
2950 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2951 0x1404, 0x0004, 0, 0,
2952 pbn_b0_4_921600 }, */
2953 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2954 0x1208, 0x0004, 0, 0,
2958 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2960 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2965 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2967 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2972 * RAStel 2 port modem, gerg@moreton.com.au
2974 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2976 pbn_b2_bt_2_115200 },
2979 * EKF addition for i960 Boards form EKF with serial port
2981 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2982 0xE4BF, PCI_ANY_ID, 0, 0,
2986 * Xircom Cardbus/Ethernet combos
2988 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2992 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2994 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2999 * Untested PCI modems, sent in from various folks...
3003 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3005 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3006 0x1048, 0x1500, 0, 0,
3009 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3016 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3017 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3019 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3022 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3026 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3029 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3032 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3037 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3039 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3040 PCI_ANY_ID, PCI_ANY_ID,
3042 0, pbn_exar_XR17C152 },
3043 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3044 PCI_ANY_ID, PCI_ANY_ID,
3046 0, pbn_exar_XR17C154 },
3047 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3048 PCI_ANY_ID, PCI_ANY_ID,
3050 0, pbn_exar_XR17C158 },
3053 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3055 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3061 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3062 PCI_ANY_ID, PCI_ANY_ID,
3064 pbn_b1_bt_1_115200 },
3069 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3070 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3075 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3076 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3079 * Perle PCI-RAS cards
3081 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3082 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3083 0, 0, pbn_b2_4_921600 },
3084 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3085 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3086 0, 0, pbn_b2_8_921600 },
3089 * Mainpine series cards: Fairly standard layout but fools
3090 * parts of the autodetect in some cases and uses otherwise
3091 * unmatched communications subclasses in the PCI Express case
3094 { /* RockForceDUO */
3095 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3096 PCI_VENDOR_ID_MAINPINE, 0x0200,
3097 0, 0, pbn_b0_2_115200 },
3098 { /* RockForceQUATRO */
3099 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3100 PCI_VENDOR_ID_MAINPINE, 0x0300,
3101 0, 0, pbn_b0_4_115200 },
3102 { /* RockForceDUO+ */
3103 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3104 PCI_VENDOR_ID_MAINPINE, 0x0400,
3105 0, 0, pbn_b0_2_115200 },
3106 { /* RockForceQUATRO+ */
3107 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3108 PCI_VENDOR_ID_MAINPINE, 0x0500,
3109 0, 0, pbn_b0_4_115200 },
3111 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3112 PCI_VENDOR_ID_MAINPINE, 0x0600,
3113 0, 0, pbn_b0_2_115200 },
3115 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3116 PCI_VENDOR_ID_MAINPINE, 0x0700,
3117 0, 0, pbn_b0_4_115200 },
3118 { /* RockForceOCTO+ */
3119 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3120 PCI_VENDOR_ID_MAINPINE, 0x0800,
3121 0, 0, pbn_b0_8_115200 },
3122 { /* RockForceDUO+ */
3123 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3124 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3125 0, 0, pbn_b0_2_115200 },
3126 { /* RockForceQUARTRO+ */
3127 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3128 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3129 0, 0, pbn_b0_4_115200 },
3130 { /* RockForceOCTO+ */
3131 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3132 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3133 0, 0, pbn_b0_8_115200 },
3135 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3136 PCI_VENDOR_ID_MAINPINE, 0x2000,
3137 0, 0, pbn_b0_1_115200 },
3139 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3140 PCI_VENDOR_ID_MAINPINE, 0x2100,
3141 0, 0, pbn_b0_1_115200 },
3143 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3144 PCI_VENDOR_ID_MAINPINE, 0x2200,
3145 0, 0, pbn_b0_2_115200 },
3147 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3148 PCI_VENDOR_ID_MAINPINE, 0x2300,
3149 0, 0, pbn_b0_2_115200 },
3151 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3152 PCI_VENDOR_ID_MAINPINE, 0x2400,
3153 0, 0, pbn_b0_4_115200 },
3155 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3156 PCI_VENDOR_ID_MAINPINE, 0x2500,
3157 0, 0, pbn_b0_4_115200 },
3159 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3160 PCI_VENDOR_ID_MAINPINE, 0x2600,
3161 0, 0, pbn_b0_8_115200 },
3163 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3164 PCI_VENDOR_ID_MAINPINE, 0x2700,
3165 0, 0, pbn_b0_8_115200 },
3166 { /* IQ Express D1 */
3167 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3168 PCI_VENDOR_ID_MAINPINE, 0x3000,
3169 0, 0, pbn_b0_1_115200 },
3170 { /* IQ Express F1 */
3171 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3172 PCI_VENDOR_ID_MAINPINE, 0x3100,
3173 0, 0, pbn_b0_1_115200 },
3174 { /* IQ Express D2 */
3175 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3176 PCI_VENDOR_ID_MAINPINE, 0x3200,
3177 0, 0, pbn_b0_2_115200 },
3178 { /* IQ Express F2 */
3179 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3180 PCI_VENDOR_ID_MAINPINE, 0x3300,
3181 0, 0, pbn_b0_2_115200 },
3182 { /* IQ Express D4 */
3183 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3184 PCI_VENDOR_ID_MAINPINE, 0x3400,
3185 0, 0, pbn_b0_4_115200 },
3186 { /* IQ Express F4 */
3187 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3188 PCI_VENDOR_ID_MAINPINE, 0x3500,
3189 0, 0, pbn_b0_4_115200 },
3190 { /* IQ Express D8 */
3191 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3192 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3193 0, 0, pbn_b0_8_115200 },
3194 { /* IQ Express F8 */
3195 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3196 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3197 0, 0, pbn_b0_8_115200 },
3201 * PA Semi PA6T-1682M on-chip UART
3203 { PCI_VENDOR_ID_PASEMI, 0xa004,
3204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3208 * National Instruments
3210 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3213 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3216 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3219 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3222 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3225 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3228 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3231 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3234 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3237 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3240 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3243 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3250 { PCI_VENDOR_ID_ADDIDATA,
3251 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3258 { PCI_VENDOR_ID_ADDIDATA,
3259 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3266 { PCI_VENDOR_ID_ADDIDATA,
3267 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3274 { PCI_VENDOR_ID_ADDIDATA_OLD,
3275 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3282 { PCI_VENDOR_ID_ADDIDATA,
3283 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3290 { PCI_VENDOR_ID_ADDIDATA,
3291 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3298 { PCI_VENDOR_ID_ADDIDATA,
3299 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3306 { PCI_VENDOR_ID_ADDIDATA,
3307 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3314 { PCI_VENDOR_ID_ADDIDATA,
3315 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3322 { PCI_VENDOR_ID_ADDIDATA,
3323 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3330 { PCI_VENDOR_ID_ADDIDATA,
3331 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3338 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3339 PCI_VENDOR_ID_IBM, 0x0299,
3340 0, 0, pbn_b0_bt_2_115200 },
3343 * These entries match devices with class COMMUNICATION_SERIAL,
3344 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3346 { PCI_ANY_ID, PCI_ANY_ID,
3347 PCI_ANY_ID, PCI_ANY_ID,
3348 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3349 0xffff00, pbn_default },
3350 { PCI_ANY_ID, PCI_ANY_ID,
3351 PCI_ANY_ID, PCI_ANY_ID,
3352 PCI_CLASS_COMMUNICATION_MODEM << 8,
3353 0xffff00, pbn_default },
3354 { PCI_ANY_ID, PCI_ANY_ID,
3355 PCI_ANY_ID, PCI_ANY_ID,
3356 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3357 0xffff00, pbn_default },
3361 static struct pci_driver serial_pci_driver = {
3363 .probe = pciserial_init_one,
3364 .remove = __devexit_p(pciserial_remove_one),
3366 .suspend = pciserial_suspend_one,
3367 .resume = pciserial_resume_one,
3369 .id_table = serial_pci_tbl,
3372 static int __init serial8250_pci_init(void)
3374 return pci_register_driver(&serial_pci_driver);
3377 static void __exit serial8250_pci_exit(void)
3379 pci_unregister_driver(&serial_pci_driver);
3382 module_init(serial8250_pci_init);
3383 module_exit(serial8250_pci_exit);
3385 MODULE_LICENSE("GPL");
3386 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3387 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);