2 * linux/drivers/char/8250.c
4 * Driver for 8250/16550-type serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
17 * A note about mapbase / membase
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
23 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ioport.h>
30 #include <linux/init.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/tty.h>
36 #include <linux/tty_flip.h>
37 #include <linux/serial_reg.h>
38 #include <linux/serial_core.h>
39 #include <linux/serial.h>
40 #include <linux/serial_8250.h>
41 #include <linux/nmi.h>
42 #include <linux/mutex.h>
51 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
52 * is unsafe when used on edge-triggered interrupts.
54 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
56 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
62 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
64 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
68 #define DEBUG_INTR(fmt...) printk(fmt)
70 #define DEBUG_INTR(fmt...) do { } while (0)
73 #define PASS_LIMIT 256
76 * We default to IRQ0 for the "no irq" hack. Some
77 * machine types want others as well - they're free
78 * to redefine this in their header file.
80 #define is_real_interrupt(irq) ((irq) != 0)
82 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
83 #define CONFIG_SERIAL_DETECT_IRQ 1
85 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
86 #define CONFIG_SERIAL_MANY_PORTS 1
90 * HUB6 is always on. This will be removed once the header
91 * files have been cleaned.
95 #include <asm/serial.h>
98 * SERIAL_PORT_DFNS tells us about built-in ports that have no
99 * standard enumeration mechanism. Platforms that can find all
100 * serial ports via mechanisms like ACPI or PCI need not supply it.
102 #ifndef SERIAL_PORT_DFNS
103 #define SERIAL_PORT_DFNS
106 static const struct old_serial_port old_serial_port[] = {
107 SERIAL_PORT_DFNS /* defined in asm/serial.h */
110 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
112 #ifdef CONFIG_SERIAL_8250_RSA
114 #define PORT_RSA_MAX 4
115 static unsigned long probe_rsa[PORT_RSA_MAX];
116 static unsigned int probe_rsa_count;
117 #endif /* CONFIG_SERIAL_8250_RSA */
119 struct uart_8250_port {
120 struct uart_port port;
121 struct timer_list timer; /* "no irq" timer */
122 struct list_head list; /* ports on this IRQ */
123 unsigned short capabilities; /* port capabilities */
124 unsigned short bugs; /* port bugs */
125 unsigned int tx_loadsz; /* transmit fifo load size */
130 unsigned char mcr_mask; /* mask of user bits */
131 unsigned char mcr_force; /* mask of forced bits */
134 * Some bits in registers are cleared on a read, so they must
135 * be saved whenever the register is read but the bits will not
136 * be immediately processed.
138 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
139 unsigned char lsr_saved_flags;
140 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
141 unsigned char msr_saved_flags;
144 * We provide a per-port pm hook.
146 void (*pm)(struct uart_port *port,
147 unsigned int state, unsigned int old);
152 struct list_head *head;
155 static struct irq_info irq_lists[NR_IRQS];
158 * Here we define the default xmit fifo size used for each type of UART.
160 static const struct serial8250_config uart_config[] = {
185 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
186 .flags = UART_CAP_FIFO,
197 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
205 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
213 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
221 .name = "16C950/954",
224 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
225 .flags = UART_CAP_FIFO,
231 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
233 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
247 .flags = UART_CAP_FIFO,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO | UART_NATSEMI,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261 .flags = UART_CAP_FIFO | UART_CAP_UUE,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO,
272 #if defined (CONFIG_SERIAL_8250_AU1X00)
274 /* Au1x00 UART hardware has a weird register layout */
275 static const u8 au_io_in_map[] = {
285 static const u8 au_io_out_map[] = {
293 /* sane hardware needs no mapping */
294 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
296 if (up->port.iotype != UPIO_AU)
298 return au_io_in_map[offset];
301 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
303 if (up->port.iotype != UPIO_AU)
305 return au_io_out_map[offset];
308 #elif defined(CONFIG_SERIAL_8250_RM9K)
332 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
334 if (up->port.iotype != UPIO_RM9000)
336 return regmap_in[offset];
339 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
341 if (up->port.iotype != UPIO_RM9000)
343 return regmap_out[offset];
348 /* sane hardware needs no mapping */
349 #define map_8250_in_reg(up, offset) (offset)
350 #define map_8250_out_reg(up, offset) (offset)
354 static unsigned int serial_in(struct uart_8250_port *up, int offset)
357 offset = map_8250_in_reg(up, offset) << up->port.regshift;
359 switch (up->port.iotype) {
361 outb(up->port.hub6 - 1 + offset, up->port.iobase);
362 return inb(up->port.iobase + 1);
366 return readb(up->port.membase + offset);
370 return readl(up->port.membase + offset);
372 #ifdef CONFIG_SERIAL_8250_AU1X00
374 return __raw_readl(up->port.membase + offset);
378 if (offset == UART_IIR) {
379 tmp = readl(up->port.membase + (UART_IIR & ~3));
380 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
382 return readb(up->port.membase + offset);
385 return inb(up->port.iobase + offset);
390 serial_out(struct uart_8250_port *up, int offset, int value)
392 /* Save the offset before it's remapped */
393 int save_offset = offset;
394 offset = map_8250_out_reg(up, offset) << up->port.regshift;
396 switch (up->port.iotype) {
398 outb(up->port.hub6 - 1 + offset, up->port.iobase);
399 outb(value, up->port.iobase + 1);
403 writeb(value, up->port.membase + offset);
408 writel(value, up->port.membase + offset);
411 #ifdef CONFIG_SERIAL_8250_AU1X00
413 __raw_writel(value, up->port.membase + offset);
417 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
418 writeb(value, up->port.membase + offset);
422 /* Save the LCR value so it can be re-written when a
423 * Busy Detect interrupt occurs. */
424 if (save_offset == UART_LCR)
426 writeb(value, up->port.membase + offset);
427 /* Read the IER to ensure any interrupt is cleared before
428 * returning from ISR. */
429 if (save_offset == UART_TX || save_offset == UART_IER)
430 value = serial_in(up, UART_IER);
434 outb(value, up->port.iobase + offset);
439 serial_out_sync(struct uart_8250_port *up, int offset, int value)
441 switch (up->port.iotype) {
444 #ifdef CONFIG_SERIAL_8250_AU1X00
448 serial_out(up, offset, value);
449 serial_in(up, UART_LCR); /* safe, no side-effects */
452 serial_out(up, offset, value);
457 * We used to support using pause I/O for certain machines. We
458 * haven't supported this for a while, but just in case it's badly
459 * needed for certain old 386 machines, I've left these #define's
462 #define serial_inp(up, offset) serial_in(up, offset)
463 #define serial_outp(up, offset, value) serial_out(up, offset, value)
465 /* Uart divisor latch read */
466 static inline int _serial_dl_read(struct uart_8250_port *up)
468 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
471 /* Uart divisor latch write */
472 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
474 serial_outp(up, UART_DLL, value & 0xff);
475 serial_outp(up, UART_DLM, value >> 8 & 0xff);
478 #if defined(CONFIG_SERIAL_8250_AU1X00)
479 /* Au1x00 haven't got a standard divisor latch */
480 static int serial_dl_read(struct uart_8250_port *up)
482 if (up->port.iotype == UPIO_AU)
483 return __raw_readl(up->port.membase + 0x28);
485 return _serial_dl_read(up);
488 static void serial_dl_write(struct uart_8250_port *up, int value)
490 if (up->port.iotype == UPIO_AU)
491 __raw_writel(value, up->port.membase + 0x28);
493 _serial_dl_write(up, value);
495 #elif defined(CONFIG_SERIAL_8250_RM9K)
496 static int serial_dl_read(struct uart_8250_port *up)
498 return (up->port.iotype == UPIO_RM9000) ?
499 (((__raw_readl(up->port.membase + 0x10) << 8) |
500 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
504 static void serial_dl_write(struct uart_8250_port *up, int value)
506 if (up->port.iotype == UPIO_RM9000) {
507 __raw_writel(value, up->port.membase + 0x08);
508 __raw_writel(value >> 8, up->port.membase + 0x10);
510 _serial_dl_write(up, value);
514 #define serial_dl_read(up) _serial_dl_read(up)
515 #define serial_dl_write(up, value) _serial_dl_write(up, value)
521 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
523 serial_out(up, UART_SCR, offset);
524 serial_out(up, UART_ICR, value);
527 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
531 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
532 serial_out(up, UART_SCR, offset);
533 value = serial_in(up, UART_ICR);
534 serial_icr_write(up, UART_ACR, up->acr);
542 static inline void serial8250_clear_fifos(struct uart_8250_port *p)
544 if (p->capabilities & UART_CAP_FIFO) {
545 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
546 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
547 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
548 serial_outp(p, UART_FCR, 0);
553 * IER sleep support. UARTs which have EFRs need the "extended
554 * capability" bit enabled. Note that on XR16C850s, we need to
555 * reset LCR to write to IER.
557 static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
559 if (p->capabilities & UART_CAP_SLEEP) {
560 if (p->capabilities & UART_CAP_EFR) {
561 serial_outp(p, UART_LCR, 0xBF);
562 serial_outp(p, UART_EFR, UART_EFR_ECB);
563 serial_outp(p, UART_LCR, 0);
565 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
566 if (p->capabilities & UART_CAP_EFR) {
567 serial_outp(p, UART_LCR, 0xBF);
568 serial_outp(p, UART_EFR, 0);
569 serial_outp(p, UART_LCR, 0);
574 #ifdef CONFIG_SERIAL_8250_RSA
576 * Attempts to turn on the RSA FIFO. Returns zero on failure.
577 * We set the port uart clock rate if we succeed.
579 static int __enable_rsa(struct uart_8250_port *up)
584 mode = serial_inp(up, UART_RSA_MSR);
585 result = mode & UART_RSA_MSR_FIFO;
588 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
589 mode = serial_inp(up, UART_RSA_MSR);
590 result = mode & UART_RSA_MSR_FIFO;
594 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
599 static void enable_rsa(struct uart_8250_port *up)
601 if (up->port.type == PORT_RSA) {
602 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
603 spin_lock_irq(&up->port.lock);
605 spin_unlock_irq(&up->port.lock);
607 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
608 serial_outp(up, UART_RSA_FRR, 0);
613 * Attempts to turn off the RSA FIFO. Returns zero on failure.
614 * It is unknown why interrupts were disabled in here. However,
615 * the caller is expected to preserve this behaviour by grabbing
616 * the spinlock before calling this function.
618 static void disable_rsa(struct uart_8250_port *up)
623 if (up->port.type == PORT_RSA &&
624 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
625 spin_lock_irq(&up->port.lock);
627 mode = serial_inp(up, UART_RSA_MSR);
628 result = !(mode & UART_RSA_MSR_FIFO);
631 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
632 mode = serial_inp(up, UART_RSA_MSR);
633 result = !(mode & UART_RSA_MSR_FIFO);
637 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
638 spin_unlock_irq(&up->port.lock);
641 #endif /* CONFIG_SERIAL_8250_RSA */
644 * This is a quickie test to see how big the FIFO is.
645 * It doesn't work at all the time, more's the pity.
647 static int size_fifo(struct uart_8250_port *up)
649 unsigned char old_fcr, old_mcr, old_lcr;
650 unsigned short old_dl;
653 old_lcr = serial_inp(up, UART_LCR);
654 serial_outp(up, UART_LCR, 0);
655 old_fcr = serial_inp(up, UART_FCR);
656 old_mcr = serial_inp(up, UART_MCR);
657 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
658 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
659 serial_outp(up, UART_MCR, UART_MCR_LOOP);
660 serial_outp(up, UART_LCR, UART_LCR_DLAB);
661 old_dl = serial_dl_read(up);
662 serial_dl_write(up, 0x0001);
663 serial_outp(up, UART_LCR, 0x03);
664 for (count = 0; count < 256; count++)
665 serial_outp(up, UART_TX, count);
666 mdelay(20);/* FIXME - schedule_timeout */
667 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
668 (count < 256); count++)
669 serial_inp(up, UART_RX);
670 serial_outp(up, UART_FCR, old_fcr);
671 serial_outp(up, UART_MCR, old_mcr);
672 serial_outp(up, UART_LCR, UART_LCR_DLAB);
673 serial_dl_write(up, old_dl);
674 serial_outp(up, UART_LCR, old_lcr);
680 * Read UART ID using the divisor method - set DLL and DLM to zero
681 * and the revision will be in DLL and device type in DLM. We
682 * preserve the device state across this.
684 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
686 unsigned char old_dll, old_dlm, old_lcr;
689 old_lcr = serial_inp(p, UART_LCR);
690 serial_outp(p, UART_LCR, UART_LCR_DLAB);
692 old_dll = serial_inp(p, UART_DLL);
693 old_dlm = serial_inp(p, UART_DLM);
695 serial_outp(p, UART_DLL, 0);
696 serial_outp(p, UART_DLM, 0);
698 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
700 serial_outp(p, UART_DLL, old_dll);
701 serial_outp(p, UART_DLM, old_dlm);
702 serial_outp(p, UART_LCR, old_lcr);
708 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
709 * When this function is called we know it is at least a StarTech
710 * 16650 V2, but it might be one of several StarTech UARTs, or one of
711 * its clones. (We treat the broken original StarTech 16650 V1 as a
712 * 16550, and why not? Startech doesn't seem to even acknowledge its
715 * What evil have men's minds wrought...
717 static void autoconfig_has_efr(struct uart_8250_port *up)
719 unsigned int id1, id2, id3, rev;
722 * Everything with an EFR has SLEEP
724 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
727 * First we check to see if it's an Oxford Semiconductor UART.
729 * If we have to do this here because some non-National
730 * Semiconductor clone chips lock up if you try writing to the
731 * LSR register (which serial_icr_read does)
735 * Check for Oxford Semiconductor 16C950.
737 * EFR [4] must be set else this test fails.
739 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
740 * claims that it's needed for 952 dual UART's (which are not
741 * recommended for new designs).
744 serial_out(up, UART_LCR, 0xBF);
745 serial_out(up, UART_EFR, UART_EFR_ECB);
746 serial_out(up, UART_LCR, 0x00);
747 id1 = serial_icr_read(up, UART_ID1);
748 id2 = serial_icr_read(up, UART_ID2);
749 id3 = serial_icr_read(up, UART_ID3);
750 rev = serial_icr_read(up, UART_REV);
752 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
754 if (id1 == 0x16 && id2 == 0xC9 &&
755 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
756 up->port.type = PORT_16C950;
759 * Enable work around for the Oxford Semiconductor 952 rev B
760 * chip which causes it to seriously miscalculate baud rates
763 if (id3 == 0x52 && rev == 0x01)
764 up->bugs |= UART_BUG_QUOT;
769 * We check for a XR16C850 by setting DLL and DLM to 0, and then
770 * reading back DLL and DLM. The chip type depends on the DLM
772 * 0x10 - XR16C850 and the DLL contains the chip revision.
776 id1 = autoconfig_read_divisor_id(up);
777 DEBUG_AUTOCONF("850id=%04x ", id1);
780 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
781 up->port.type = PORT_16850;
786 * It wasn't an XR16C850.
788 * We distinguish between the '654 and the '650 by counting
789 * how many bytes are in the FIFO. I'm using this for now,
790 * since that's the technique that was sent to me in the
791 * serial driver update, but I'm not convinced this works.
792 * I've had problems doing this in the past. -TYT
794 if (size_fifo(up) == 64)
795 up->port.type = PORT_16654;
797 up->port.type = PORT_16650V2;
801 * We detected a chip without a FIFO. Only two fall into
802 * this category - the original 8250 and the 16450. The
803 * 16450 has a scratch register (accessible with LCR=0)
805 static void autoconfig_8250(struct uart_8250_port *up)
807 unsigned char scratch, status1, status2;
809 up->port.type = PORT_8250;
811 scratch = serial_in(up, UART_SCR);
812 serial_outp(up, UART_SCR, 0xa5);
813 status1 = serial_in(up, UART_SCR);
814 serial_outp(up, UART_SCR, 0x5a);
815 status2 = serial_in(up, UART_SCR);
816 serial_outp(up, UART_SCR, scratch);
818 if (status1 == 0xa5 && status2 == 0x5a)
819 up->port.type = PORT_16450;
822 static int broken_efr(struct uart_8250_port *up)
825 * Exar ST16C2550 "A2" devices incorrectly detect as
826 * having an EFR, and report an ID of 0x0201. See
827 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
829 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
836 * We know that the chip has FIFOs. Does it have an EFR? The
837 * EFR is located in the same register position as the IIR and
838 * we know the top two bits of the IIR are currently set. The
839 * EFR should contain zero. Try to read the EFR.
841 static void autoconfig_16550a(struct uart_8250_port *up)
843 unsigned char status1, status2;
844 unsigned int iersave;
846 up->port.type = PORT_16550A;
847 up->capabilities |= UART_CAP_FIFO;
850 * Check for presence of the EFR when DLAB is set.
851 * Only ST16C650V1 UARTs pass this test.
853 serial_outp(up, UART_LCR, UART_LCR_DLAB);
854 if (serial_in(up, UART_EFR) == 0) {
855 serial_outp(up, UART_EFR, 0xA8);
856 if (serial_in(up, UART_EFR) != 0) {
857 DEBUG_AUTOCONF("EFRv1 ");
858 up->port.type = PORT_16650;
859 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
861 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
863 serial_outp(up, UART_EFR, 0);
868 * Maybe it requires 0xbf to be written to the LCR.
869 * (other ST16C650V2 UARTs, TI16C752A, etc)
871 serial_outp(up, UART_LCR, 0xBF);
872 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
873 DEBUG_AUTOCONF("EFRv2 ");
874 autoconfig_has_efr(up);
879 * Check for a National Semiconductor SuperIO chip.
880 * Attempt to switch to bank 2, read the value of the LOOP bit
881 * from EXCR1. Switch back to bank 0, change it in MCR. Then
882 * switch back to bank 2, read it from EXCR1 again and check
883 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
885 serial_outp(up, UART_LCR, 0);
886 status1 = serial_in(up, UART_MCR);
887 serial_outp(up, UART_LCR, 0xE0);
888 status2 = serial_in(up, 0x02); /* EXCR1 */
890 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
891 serial_outp(up, UART_LCR, 0);
892 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
893 serial_outp(up, UART_LCR, 0xE0);
894 status2 = serial_in(up, 0x02); /* EXCR1 */
895 serial_outp(up, UART_LCR, 0);
896 serial_outp(up, UART_MCR, status1);
898 if ((status2 ^ status1) & UART_MCR_LOOP) {
901 serial_outp(up, UART_LCR, 0xE0);
903 quot = serial_dl_read(up);
906 status1 = serial_in(up, 0x04); /* EXCR2 */
907 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
908 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
909 serial_outp(up, 0x04, status1);
911 serial_dl_write(up, quot);
913 serial_outp(up, UART_LCR, 0);
915 up->port.uartclk = 921600*16;
916 up->port.type = PORT_NS16550A;
917 up->capabilities |= UART_NATSEMI;
923 * No EFR. Try to detect a TI16750, which only sets bit 5 of
924 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
925 * Try setting it with and without DLAB set. Cheap clones
926 * set bit 5 without DLAB set.
928 serial_outp(up, UART_LCR, 0);
929 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
930 status1 = serial_in(up, UART_IIR) >> 5;
931 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
932 serial_outp(up, UART_LCR, UART_LCR_DLAB);
933 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
934 status2 = serial_in(up, UART_IIR) >> 5;
935 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
936 serial_outp(up, UART_LCR, 0);
938 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
940 if (status1 == 6 && status2 == 7) {
941 up->port.type = PORT_16750;
942 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
947 * Try writing and reading the UART_IER_UUE bit (b6).
948 * If it works, this is probably one of the Xscale platform's
950 * We're going to explicitly set the UUE bit to 0 before
951 * trying to write and read a 1 just to make sure it's not
952 * already a 1 and maybe locked there before we even start start.
954 iersave = serial_in(up, UART_IER);
955 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
956 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
958 * OK it's in a known zero state, try writing and reading
959 * without disturbing the current state of the other bits.
961 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
962 if (serial_in(up, UART_IER) & UART_IER_UUE) {
965 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
967 DEBUG_AUTOCONF("Xscale ");
968 up->port.type = PORT_XSCALE;
969 up->capabilities |= UART_CAP_UUE;
974 * If we got here we couldn't force the IER_UUE bit to 0.
975 * Log it and continue.
977 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
979 serial_outp(up, UART_IER, iersave);
983 * This routine is called by rs_init() to initialize a specific serial
984 * port. It determines what type of UART chip this serial port is
985 * using: 8250, 16450, 16550, 16550A. The important question is
986 * whether or not this UART is a 16550A or not, since this will
987 * determine whether or not we can use its FIFO features or not.
989 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
991 unsigned char status1, scratch, scratch2, scratch3;
992 unsigned char save_lcr, save_mcr;
995 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
998 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
999 up->port.line, up->port.iobase, up->port.membase);
1002 * We really do need global IRQs disabled here - we're going to
1003 * be frobbing the chips IRQ enable register to see if it exists.
1005 spin_lock_irqsave(&up->port.lock, flags);
1007 up->capabilities = 0;
1010 if (!(up->port.flags & UPF_BUGGY_UART)) {
1012 * Do a simple existence test first; if we fail this,
1013 * there's no point trying anything else.
1015 * 0x80 is used as a nonsense port to prevent against
1016 * false positives due to ISA bus float. The
1017 * assumption is that 0x80 is a non-existent port;
1018 * which should be safe since include/asm/io.h also
1019 * makes this assumption.
1021 * Note: this is safe as long as MCR bit 4 is clear
1022 * and the device is in "PC" mode.
1024 scratch = serial_inp(up, UART_IER);
1025 serial_outp(up, UART_IER, 0);
1030 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1031 * 16C754B) allow only to modify them if an EFR bit is set.
1033 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1034 serial_outp(up, UART_IER, 0x0F);
1038 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1039 serial_outp(up, UART_IER, scratch);
1040 if (scratch2 != 0 || scratch3 != 0x0F) {
1042 * We failed; there's nothing here
1044 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1045 scratch2, scratch3);
1050 save_mcr = serial_in(up, UART_MCR);
1051 save_lcr = serial_in(up, UART_LCR);
1054 * Check to see if a UART is really there. Certain broken
1055 * internal modems based on the Rockwell chipset fail this
1056 * test, because they apparently don't implement the loopback
1057 * test mode. So this test is skipped on the COM 1 through
1058 * COM 4 ports. This *should* be safe, since no board
1059 * manufacturer would be stupid enough to design a board
1060 * that conflicts with COM 1-4 --- we hope!
1062 if (!(up->port.flags & UPF_SKIP_TEST)) {
1063 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1064 status1 = serial_inp(up, UART_MSR) & 0xF0;
1065 serial_outp(up, UART_MCR, save_mcr);
1066 if (status1 != 0x90) {
1067 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1074 * We're pretty sure there's a port here. Lets find out what
1075 * type of port it is. The IIR top two bits allows us to find
1076 * out if it's 8250 or 16450, 16550, 16550A or later. This
1077 * determines what we test for next.
1079 * We also initialise the EFR (if any) to zero for later. The
1080 * EFR occupies the same register location as the FCR and IIR.
1082 serial_outp(up, UART_LCR, 0xBF);
1083 serial_outp(up, UART_EFR, 0);
1084 serial_outp(up, UART_LCR, 0);
1086 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1087 scratch = serial_in(up, UART_IIR) >> 6;
1089 DEBUG_AUTOCONF("iir=%d ", scratch);
1093 autoconfig_8250(up);
1096 up->port.type = PORT_UNKNOWN;
1099 up->port.type = PORT_16550;
1102 autoconfig_16550a(up);
1106 #ifdef CONFIG_SERIAL_8250_RSA
1108 * Only probe for RSA ports if we got the region.
1110 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1113 for (i = 0 ; i < probe_rsa_count; ++i) {
1114 if (probe_rsa[i] == up->port.iobase &&
1116 up->port.type = PORT_RSA;
1123 #ifdef CONFIG_SERIAL_8250_AU1X00
1124 /* if access method is AU, it is a 16550 with a quirk */
1125 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1126 up->bugs |= UART_BUG_NOMSR;
1129 serial_outp(up, UART_LCR, save_lcr);
1131 if (up->capabilities != uart_config[up->port.type].flags) {
1133 "ttyS%d: detected caps %08x should be %08x\n",
1134 up->port.line, up->capabilities,
1135 uart_config[up->port.type].flags);
1138 up->port.fifosize = uart_config[up->port.type].fifo_size;
1139 up->capabilities = uart_config[up->port.type].flags;
1140 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1142 if (up->port.type == PORT_UNKNOWN)
1148 #ifdef CONFIG_SERIAL_8250_RSA
1149 if (up->port.type == PORT_RSA)
1150 serial_outp(up, UART_RSA_FRR, 0);
1152 serial_outp(up, UART_MCR, save_mcr);
1153 serial8250_clear_fifos(up);
1154 serial_in(up, UART_RX);
1155 if (up->capabilities & UART_CAP_UUE)
1156 serial_outp(up, UART_IER, UART_IER_UUE);
1158 serial_outp(up, UART_IER, 0);
1161 spin_unlock_irqrestore(&up->port.lock, flags);
1162 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1165 static void autoconfig_irq(struct uart_8250_port *up)
1167 unsigned char save_mcr, save_ier;
1168 unsigned char save_ICP = 0;
1169 unsigned int ICP = 0;
1173 if (up->port.flags & UPF_FOURPORT) {
1174 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1175 save_ICP = inb_p(ICP);
1180 /* forget possible initially masked and pending IRQ */
1181 probe_irq_off(probe_irq_on());
1182 save_mcr = serial_inp(up, UART_MCR);
1183 save_ier = serial_inp(up, UART_IER);
1184 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1186 irqs = probe_irq_on();
1187 serial_outp(up, UART_MCR, 0);
1189 if (up->port.flags & UPF_FOURPORT) {
1190 serial_outp(up, UART_MCR,
1191 UART_MCR_DTR | UART_MCR_RTS);
1193 serial_outp(up, UART_MCR,
1194 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1196 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1197 (void)serial_inp(up, UART_LSR);
1198 (void)serial_inp(up, UART_RX);
1199 (void)serial_inp(up, UART_IIR);
1200 (void)serial_inp(up, UART_MSR);
1201 serial_outp(up, UART_TX, 0xFF);
1203 irq = probe_irq_off(irqs);
1205 serial_outp(up, UART_MCR, save_mcr);
1206 serial_outp(up, UART_IER, save_ier);
1208 if (up->port.flags & UPF_FOURPORT)
1209 outb_p(save_ICP, ICP);
1211 up->port.irq = (irq > 0) ? irq : 0;
1214 static inline void __stop_tx(struct uart_8250_port *p)
1216 if (p->ier & UART_IER_THRI) {
1217 p->ier &= ~UART_IER_THRI;
1218 serial_out(p, UART_IER, p->ier);
1222 static void serial8250_stop_tx(struct uart_port *port)
1224 struct uart_8250_port *up = (struct uart_8250_port *)port;
1229 * We really want to stop the transmitter from sending.
1231 if (up->port.type == PORT_16C950) {
1232 up->acr |= UART_ACR_TXDIS;
1233 serial_icr_write(up, UART_ACR, up->acr);
1237 static void transmit_chars(struct uart_8250_port *up);
1239 static void serial8250_start_tx(struct uart_port *port)
1241 struct uart_8250_port *up = (struct uart_8250_port *)port;
1243 if (!(up->ier & UART_IER_THRI)) {
1244 up->ier |= UART_IER_THRI;
1245 serial_out(up, UART_IER, up->ier);
1247 if (up->bugs & UART_BUG_TXEN) {
1248 unsigned char lsr, iir;
1249 lsr = serial_in(up, UART_LSR);
1250 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1251 iir = serial_in(up, UART_IIR) & 0x0f;
1252 if ((up->port.type == PORT_RM9000) ?
1253 (lsr & UART_LSR_THRE &&
1254 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1255 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
1261 * Re-enable the transmitter if we disabled it.
1263 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1264 up->acr &= ~UART_ACR_TXDIS;
1265 serial_icr_write(up, UART_ACR, up->acr);
1269 static void serial8250_stop_rx(struct uart_port *port)
1271 struct uart_8250_port *up = (struct uart_8250_port *)port;
1273 up->ier &= ~UART_IER_RLSI;
1274 up->port.read_status_mask &= ~UART_LSR_DR;
1275 serial_out(up, UART_IER, up->ier);
1278 static void serial8250_enable_ms(struct uart_port *port)
1280 struct uart_8250_port *up = (struct uart_8250_port *)port;
1282 /* no MSR capabilities */
1283 if (up->bugs & UART_BUG_NOMSR)
1286 up->ier |= UART_IER_MSI;
1287 serial_out(up, UART_IER, up->ier);
1291 receive_chars(struct uart_8250_port *up, unsigned int *status)
1293 struct tty_struct *tty = up->port.info->tty;
1294 unsigned char ch, lsr = *status;
1295 int max_count = 256;
1299 ch = serial_inp(up, UART_RX);
1301 up->port.icount.rx++;
1303 lsr |= up->lsr_saved_flags;
1304 up->lsr_saved_flags = 0;
1306 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1308 * For statistics only
1310 if (lsr & UART_LSR_BI) {
1311 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1312 up->port.icount.brk++;
1314 * We do the SysRQ and SAK checking
1315 * here because otherwise the break
1316 * may get masked by ignore_status_mask
1317 * or read_status_mask.
1319 if (uart_handle_break(&up->port))
1321 } else if (lsr & UART_LSR_PE)
1322 up->port.icount.parity++;
1323 else if (lsr & UART_LSR_FE)
1324 up->port.icount.frame++;
1325 if (lsr & UART_LSR_OE)
1326 up->port.icount.overrun++;
1329 * Mask off conditions which should be ignored.
1331 lsr &= up->port.read_status_mask;
1333 if (lsr & UART_LSR_BI) {
1334 DEBUG_INTR("handling break....");
1336 } else if (lsr & UART_LSR_PE)
1338 else if (lsr & UART_LSR_FE)
1341 if (uart_handle_sysrq_char(&up->port, ch))
1344 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1347 lsr = serial_inp(up, UART_LSR);
1348 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1349 spin_unlock(&up->port.lock);
1350 tty_flip_buffer_push(tty);
1351 spin_lock(&up->port.lock);
1355 static void transmit_chars(struct uart_8250_port *up)
1357 struct circ_buf *xmit = &up->port.info->xmit;
1360 if (up->port.x_char) {
1361 serial_outp(up, UART_TX, up->port.x_char);
1362 up->port.icount.tx++;
1363 up->port.x_char = 0;
1366 if (uart_tx_stopped(&up->port)) {
1367 serial8250_stop_tx(&up->port);
1370 if (uart_circ_empty(xmit)) {
1375 count = up->tx_loadsz;
1377 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1378 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1379 up->port.icount.tx++;
1380 if (uart_circ_empty(xmit))
1382 } while (--count > 0);
1384 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1385 uart_write_wakeup(&up->port);
1387 DEBUG_INTR("THRE...");
1389 if (uart_circ_empty(xmit))
1393 static unsigned int check_modem_status(struct uart_8250_port *up)
1395 unsigned int status = serial_in(up, UART_MSR);
1397 status |= up->msr_saved_flags;
1398 up->msr_saved_flags = 0;
1399 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1400 up->port.info != NULL) {
1401 if (status & UART_MSR_TERI)
1402 up->port.icount.rng++;
1403 if (status & UART_MSR_DDSR)
1404 up->port.icount.dsr++;
1405 if (status & UART_MSR_DDCD)
1406 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1407 if (status & UART_MSR_DCTS)
1408 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1410 wake_up_interruptible(&up->port.info->delta_msr_wait);
1417 * This handles the interrupt from one port.
1420 serial8250_handle_port(struct uart_8250_port *up)
1422 unsigned int status;
1423 unsigned long flags;
1425 spin_lock_irqsave(&up->port.lock, flags);
1427 status = serial_inp(up, UART_LSR);
1429 DEBUG_INTR("status = %x...", status);
1431 if (status & UART_LSR_DR)
1432 receive_chars(up, &status);
1433 check_modem_status(up);
1434 if (status & UART_LSR_THRE)
1437 spin_unlock_irqrestore(&up->port.lock, flags);
1441 * This is the serial driver's interrupt routine.
1443 * Arjan thinks the old way was overly complex, so it got simplified.
1444 * Alan disagrees, saying that need the complexity to handle the weird
1445 * nature of ISA shared interrupts. (This is a special exception.)
1447 * In order to handle ISA shared interrupts properly, we need to check
1448 * that all ports have been serviced, and therefore the ISA interrupt
1449 * line has been de-asserted.
1451 * This means we need to loop through all ports. checking that they
1452 * don't have an interrupt pending.
1454 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1456 struct irq_info *i = dev_id;
1457 struct list_head *l, *end = NULL;
1458 int pass_counter = 0, handled = 0;
1460 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1462 spin_lock(&i->lock);
1466 struct uart_8250_port *up;
1469 up = list_entry(l, struct uart_8250_port, list);
1471 iir = serial_in(up, UART_IIR);
1472 if (!(iir & UART_IIR_NO_INT)) {
1473 serial8250_handle_port(up);
1478 } else if (up->port.iotype == UPIO_DWAPB &&
1479 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1480 /* The DesignWare APB UART has an Busy Detect (0x07)
1481 * interrupt meaning an LCR write attempt occured while the
1482 * UART was busy. The interrupt must be cleared by reading
1483 * the UART status register (USR) and the LCR re-written. */
1484 unsigned int status;
1485 status = *(volatile u32 *)up->port.private_data;
1486 serial_out(up, UART_LCR, up->lcr);
1491 } else if (end == NULL)
1496 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1497 /* If we hit this, we're dead. */
1498 printk(KERN_ERR "serial8250: too much work for "
1504 spin_unlock(&i->lock);
1506 DEBUG_INTR("end.\n");
1508 #ifdef CONFIG_ARCH_OMAP15XX
1509 return IRQ_HANDLED; /* FIXME: iir status not ready on 1510 */
1511 return IRQ_RETVAL(handled);
1516 * To support ISA shared interrupts, we need to have one interrupt
1517 * handler that ensures that the IRQ line has been deasserted
1518 * before returning. Failing to do this will result in the IRQ
1519 * line being stuck active, and, since ISA irqs are edge triggered,
1520 * no more IRQs will be seen.
1522 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1524 spin_lock_irq(&i->lock);
1526 if (!list_empty(i->head)) {
1527 if (i->head == &up->list)
1528 i->head = i->head->next;
1529 list_del(&up->list);
1531 BUG_ON(i->head != &up->list);
1535 spin_unlock_irq(&i->lock);
1538 static int serial_link_irq_chain(struct uart_8250_port *up)
1540 struct irq_info *i = irq_lists + up->port.irq;
1541 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1543 spin_lock_irq(&i->lock);
1546 list_add(&up->list, i->head);
1547 spin_unlock_irq(&i->lock);
1551 INIT_LIST_HEAD(&up->list);
1552 i->head = &up->list;
1553 spin_unlock_irq(&i->lock);
1555 ret = request_irq(up->port.irq, serial8250_interrupt,
1556 irq_flags, "serial", i);
1558 serial_do_unlink(i, up);
1564 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1566 struct irq_info *i = irq_lists + up->port.irq;
1568 BUG_ON(i->head == NULL);
1570 if (list_empty(i->head))
1571 free_irq(up->port.irq, i);
1573 serial_do_unlink(i, up);
1576 /* Base timer interval for polling */
1577 static inline int poll_timeout(int timeout)
1579 return timeout > 6 ? (timeout / 2 - 2) : 1;
1583 * This function is used to handle ports that do not have an
1584 * interrupt. This doesn't work very well for 16450's, but gives
1585 * barely passable results for a 16550A. (Although at the expense
1586 * of much CPU overhead).
1588 static void serial8250_timeout(unsigned long data)
1590 struct uart_8250_port *up = (struct uart_8250_port *)data;
1593 iir = serial_in(up, UART_IIR);
1594 if (!(iir & UART_IIR_NO_INT))
1595 serial8250_handle_port(up);
1596 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1599 static void serial8250_backup_timeout(unsigned long data)
1601 struct uart_8250_port *up = (struct uart_8250_port *)data;
1602 unsigned int iir, ier = 0, lsr;
1603 unsigned long flags;
1606 * Must disable interrupts or else we risk racing with the interrupt
1609 if (is_real_interrupt(up->port.irq)) {
1610 ier = serial_in(up, UART_IER);
1611 serial_out(up, UART_IER, 0);
1614 iir = serial_in(up, UART_IIR);
1617 * This should be a safe test for anyone who doesn't trust the
1618 * IIR bits on their UART, but it's specifically designed for
1619 * the "Diva" UART used on the management processor on many HP
1620 * ia64 and parisc boxes.
1622 spin_lock_irqsave(&up->port.lock, flags);
1623 lsr = serial_in(up, UART_LSR);
1624 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1625 spin_unlock_irqrestore(&up->port.lock, flags);
1626 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1627 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1628 (lsr & UART_LSR_THRE)) {
1629 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1630 iir |= UART_IIR_THRI;
1633 if (!(iir & UART_IIR_NO_INT))
1634 serial8250_handle_port(up);
1636 if (is_real_interrupt(up->port.irq))
1637 serial_out(up, UART_IER, ier);
1639 /* Standard timer interval plus 0.2s to keep the port running */
1640 mod_timer(&up->timer,
1641 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1644 static unsigned int serial8250_tx_empty(struct uart_port *port)
1646 struct uart_8250_port *up = (struct uart_8250_port *)port;
1647 unsigned long flags;
1650 spin_lock_irqsave(&up->port.lock, flags);
1651 lsr = serial_in(up, UART_LSR);
1652 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1653 spin_unlock_irqrestore(&up->port.lock, flags);
1655 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1658 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1660 struct uart_8250_port *up = (struct uart_8250_port *)port;
1661 unsigned int status;
1664 status = check_modem_status(up);
1667 if (status & UART_MSR_DCD)
1669 if (status & UART_MSR_RI)
1671 if (status & UART_MSR_DSR)
1673 if (status & UART_MSR_CTS)
1678 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1680 struct uart_8250_port *up = (struct uart_8250_port *)port;
1681 unsigned char mcr = 0;
1683 if (mctrl & TIOCM_RTS)
1684 mcr |= UART_MCR_RTS;
1685 if (mctrl & TIOCM_DTR)
1686 mcr |= UART_MCR_DTR;
1687 if (mctrl & TIOCM_OUT1)
1688 mcr |= UART_MCR_OUT1;
1689 if (mctrl & TIOCM_OUT2)
1690 mcr |= UART_MCR_OUT2;
1691 if (mctrl & TIOCM_LOOP)
1692 mcr |= UART_MCR_LOOP;
1694 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1696 serial_out(up, UART_MCR, mcr);
1699 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1701 struct uart_8250_port *up = (struct uart_8250_port *)port;
1702 unsigned long flags;
1704 spin_lock_irqsave(&up->port.lock, flags);
1705 if (break_state == -1)
1706 up->lcr |= UART_LCR_SBC;
1708 up->lcr &= ~UART_LCR_SBC;
1709 serial_out(up, UART_LCR, up->lcr);
1710 spin_unlock_irqrestore(&up->port.lock, flags);
1713 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1716 * Wait for transmitter & holding register to empty
1718 static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1720 unsigned int status, tmout = 10000;
1722 /* Wait up to 10ms for the character(s) to be sent. */
1724 status = serial_in(up, UART_LSR);
1726 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1731 } while ((status & bits) != bits);
1733 /* Wait up to 1s for flow control if necessary */
1734 if (up->port.flags & UPF_CONS_FLOW) {
1736 for (tmout = 1000000; tmout; tmout--) {
1737 unsigned int msr = serial_in(up, UART_MSR);
1738 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1739 if (msr & UART_MSR_CTS)
1742 touch_nmi_watchdog();
1747 #ifdef CONFIG_CONSOLE_POLL
1749 * Console polling routines for writing and reading from the uart while
1750 * in an interrupt or debug context.
1753 static int serial8250_get_poll_char(struct uart_port *port)
1755 struct uart_8250_port *up = (struct uart_8250_port *)port;
1756 unsigned char lsr = serial_inp(up, UART_LSR);
1758 while (!(lsr & UART_LSR_DR))
1759 lsr = serial_inp(up, UART_LSR);
1761 return serial_inp(up, UART_RX);
1765 static void serial8250_put_poll_char(struct uart_port *port,
1769 struct uart_8250_port *up = (struct uart_8250_port *)port;
1772 * First save the IER then disable the interrupts
1774 ier = serial_in(up, UART_IER);
1775 if (up->capabilities & UART_CAP_UUE)
1776 serial_out(up, UART_IER, UART_IER_UUE);
1778 serial_out(up, UART_IER, 0);
1780 wait_for_xmitr(up, BOTH_EMPTY);
1782 * Send the character out.
1783 * If a LF, also do CR...
1785 serial_out(up, UART_TX, c);
1787 wait_for_xmitr(up, BOTH_EMPTY);
1788 serial_out(up, UART_TX, 13);
1792 * Finally, wait for transmitter to become empty
1793 * and restore the IER
1795 wait_for_xmitr(up, BOTH_EMPTY);
1796 serial_out(up, UART_IER, ier);
1799 #endif /* CONFIG_CONSOLE_POLL */
1801 static int serial8250_startup(struct uart_port *port)
1803 struct uart_8250_port *up = (struct uart_8250_port *)port;
1804 unsigned long flags;
1805 unsigned char lsr, iir;
1808 up->capabilities = uart_config[up->port.type].flags;
1811 if (up->port.type == PORT_16C950) {
1812 /* Wake up and initialize UART */
1814 serial_outp(up, UART_LCR, 0xBF);
1815 serial_outp(up, UART_EFR, UART_EFR_ECB);
1816 serial_outp(up, UART_IER, 0);
1817 serial_outp(up, UART_LCR, 0);
1818 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1819 serial_outp(up, UART_LCR, 0xBF);
1820 serial_outp(up, UART_EFR, UART_EFR_ECB);
1821 serial_outp(up, UART_LCR, 0);
1824 #ifdef CONFIG_SERIAL_8250_RSA
1826 * If this is an RSA port, see if we can kick it up to the
1827 * higher speed clock.
1833 * Clear the FIFO buffers and disable them.
1834 * (they will be reenabled in set_termios())
1836 serial8250_clear_fifos(up);
1839 * Clear the interrupt registers.
1841 (void) serial_inp(up, UART_LSR);
1842 (void) serial_inp(up, UART_RX);
1843 (void) serial_inp(up, UART_IIR);
1844 (void) serial_inp(up, UART_MSR);
1847 * At this point, there's no way the LSR could still be 0xff;
1848 * if it is, then bail out, because there's likely no UART
1851 if (!(up->port.flags & UPF_BUGGY_UART) &&
1852 (serial_inp(up, UART_LSR) == 0xff)) {
1853 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1858 * For a XR16C850, we need to set the trigger levels
1860 if (up->port.type == PORT_16850) {
1863 serial_outp(up, UART_LCR, 0xbf);
1865 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1866 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1867 serial_outp(up, UART_TRG, UART_TRG_96);
1868 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1869 serial_outp(up, UART_TRG, UART_TRG_96);
1871 serial_outp(up, UART_LCR, 0);
1874 if (is_real_interrupt(up->port.irq)) {
1877 * Test for UARTs that do not reassert THRE when the
1878 * transmitter is idle and the interrupt has already
1879 * been cleared. Real 16550s should always reassert
1880 * this interrupt whenever the transmitter is idle and
1881 * the interrupt is enabled. Delays are necessary to
1882 * allow register changes to become visible.
1884 spin_lock_irqsave(&up->port.lock, flags);
1886 wait_for_xmitr(up, UART_LSR_THRE);
1887 serial_out_sync(up, UART_IER, UART_IER_THRI);
1888 udelay(1); /* allow THRE to set */
1889 iir1 = serial_in(up, UART_IIR);
1890 serial_out(up, UART_IER, 0);
1891 serial_out_sync(up, UART_IER, UART_IER_THRI);
1892 udelay(1); /* allow a working UART time to re-assert THRE */
1893 iir = serial_in(up, UART_IIR);
1894 serial_out(up, UART_IER, 0);
1896 spin_unlock_irqrestore(&up->port.lock, flags);
1899 * If the interrupt is not reasserted, setup a timer to
1900 * kick the UART on a regular basis.
1902 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
1903 pr_debug("ttyS%d - using backup timer\n", port->line);
1904 up->timer.function = serial8250_backup_timeout;
1905 up->timer.data = (unsigned long)up;
1906 mod_timer(&up->timer, jiffies +
1907 poll_timeout(up->port.timeout) + HZ / 5);
1912 * If the "interrupt" for this port doesn't correspond with any
1913 * hardware interrupt, we use a timer-based system. The original
1914 * driver used to do this with IRQ0.
1916 if (!is_real_interrupt(up->port.irq)) {
1917 up->timer.data = (unsigned long)up;
1918 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1920 retval = serial_link_irq_chain(up);
1926 * Now, initialize the UART
1928 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1930 spin_lock_irqsave(&up->port.lock, flags);
1931 if (up->port.flags & UPF_FOURPORT) {
1932 if (!is_real_interrupt(up->port.irq))
1933 up->port.mctrl |= TIOCM_OUT1;
1936 * Most PC uarts need OUT2 raised to enable interrupts.
1938 if (is_real_interrupt(up->port.irq))
1939 up->port.mctrl |= TIOCM_OUT2;
1941 serial8250_set_mctrl(&up->port, up->port.mctrl);
1944 * Do a quick test to see if we receive an
1945 * interrupt when we enable the TX irq.
1947 serial_outp(up, UART_IER, UART_IER_THRI);
1948 lsr = serial_in(up, UART_LSR);
1949 iir = serial_in(up, UART_IIR);
1950 serial_outp(up, UART_IER, 0);
1952 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1953 if (!(up->bugs & UART_BUG_TXEN)) {
1954 up->bugs |= UART_BUG_TXEN;
1955 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1959 up->bugs &= ~UART_BUG_TXEN;
1962 spin_unlock_irqrestore(&up->port.lock, flags);
1965 * Clear the interrupt registers again for luck, and clear the
1966 * saved flags to avoid getting false values from polling
1967 * routines or the previous session.
1969 serial_inp(up, UART_LSR);
1970 serial_inp(up, UART_RX);
1971 serial_inp(up, UART_IIR);
1972 serial_inp(up, UART_MSR);
1973 up->lsr_saved_flags = 0;
1974 up->msr_saved_flags = 0;
1977 * Finally, enable interrupts. Note: Modem status interrupts
1978 * are set via set_termios(), which will be occurring imminently
1979 * anyway, so we don't enable them here.
1981 up->ier = UART_IER_RLSI | UART_IER_RDI;
1982 serial_outp(up, UART_IER, up->ier);
1984 if (up->port.flags & UPF_FOURPORT) {
1987 * Enable interrupts on the AST Fourport board
1989 icp = (up->port.iobase & 0xfe0) | 0x01f;
1997 static void serial8250_shutdown(struct uart_port *port)
1999 struct uart_8250_port *up = (struct uart_8250_port *)port;
2000 unsigned long flags;
2003 * Disable interrupts from this port
2006 serial_outp(up, UART_IER, 0);
2008 spin_lock_irqsave(&up->port.lock, flags);
2009 if (up->port.flags & UPF_FOURPORT) {
2010 /* reset interrupts on the AST Fourport board */
2011 inb((up->port.iobase & 0xfe0) | 0x1f);
2012 up->port.mctrl |= TIOCM_OUT1;
2014 up->port.mctrl &= ~TIOCM_OUT2;
2016 serial8250_set_mctrl(&up->port, up->port.mctrl);
2017 spin_unlock_irqrestore(&up->port.lock, flags);
2020 * Disable break condition and FIFOs
2022 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2023 serial8250_clear_fifos(up);
2025 #ifdef CONFIG_SERIAL_8250_RSA
2027 * Reset the RSA board back to 115kbps compat mode.
2033 * Read data port to reset things, and then unlink from
2036 (void) serial_in(up, UART_RX);
2038 del_timer_sync(&up->timer);
2039 up->timer.function = serial8250_timeout;
2040 if (is_real_interrupt(up->port.irq))
2041 serial_unlink_irq_chain(up);
2044 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2049 * Handle magic divisors for baud rates above baud_base on
2050 * SMSC SuperIO chips.
2052 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2053 baud == (port->uartclk/4))
2055 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2056 baud == (port->uartclk/8))
2059 quot = uart_get_divisor(port, baud);
2065 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2066 struct ktermios *old)
2068 struct uart_8250_port *up = (struct uart_8250_port *)port;
2069 unsigned char cval, fcr = 0;
2070 unsigned long flags;
2071 unsigned int baud, quot;
2073 switch (termios->c_cflag & CSIZE) {
2075 cval = UART_LCR_WLEN5;
2078 cval = UART_LCR_WLEN6;
2081 cval = UART_LCR_WLEN7;
2085 cval = UART_LCR_WLEN8;
2089 if (termios->c_cflag & CSTOPB)
2090 cval |= UART_LCR_STOP;
2091 if (termios->c_cflag & PARENB)
2092 cval |= UART_LCR_PARITY;
2093 if (!(termios->c_cflag & PARODD))
2094 cval |= UART_LCR_EPAR;
2096 if (termios->c_cflag & CMSPAR)
2097 cval |= UART_LCR_SPAR;
2101 * Ask the core to calculate the divisor for us.
2103 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
2104 quot = serial8250_get_divisor(port, baud);
2107 * Oxford Semi 952 rev B workaround
2109 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2112 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2114 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2116 fcr = uart_config[up->port.type].fcr;
2120 * MCR-based auto flow control. When AFE is enabled, RTS will be
2121 * deasserted when the receive FIFO contains more characters than
2122 * the trigger, or the MCR RTS bit is cleared. In the case where
2123 * the remote UART is not using CTS auto flow control, we must
2124 * have sufficient FIFO entries for the latency of the remote
2125 * UART to respond. IOW, at least 32 bytes of FIFO.
2127 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2128 up->mcr &= ~UART_MCR_AFE;
2129 if (termios->c_cflag & CRTSCTS)
2130 up->mcr |= UART_MCR_AFE;
2134 * Ok, we're now changing the port state. Do it with
2135 * interrupts disabled.
2137 spin_lock_irqsave(&up->port.lock, flags);
2140 * Update the per-port timeout.
2142 uart_update_timeout(port, termios->c_cflag, baud);
2144 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2145 if (termios->c_iflag & INPCK)
2146 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2147 if (termios->c_iflag & (BRKINT | PARMRK))
2148 up->port.read_status_mask |= UART_LSR_BI;
2151 * Characteres to ignore
2153 up->port.ignore_status_mask = 0;
2154 if (termios->c_iflag & IGNPAR)
2155 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2156 if (termios->c_iflag & IGNBRK) {
2157 up->port.ignore_status_mask |= UART_LSR_BI;
2159 * If we're ignoring parity and break indicators,
2160 * ignore overruns too (for real raw support).
2162 if (termios->c_iflag & IGNPAR)
2163 up->port.ignore_status_mask |= UART_LSR_OE;
2167 * ignore all characters if CREAD is not set
2169 if ((termios->c_cflag & CREAD) == 0)
2170 up->port.ignore_status_mask |= UART_LSR_DR;
2173 * CTS flow control flag and modem status interrupts
2175 up->ier &= ~UART_IER_MSI;
2176 if (!(up->bugs & UART_BUG_NOMSR) &&
2177 UART_ENABLE_MS(&up->port, termios->c_cflag))
2178 up->ier |= UART_IER_MSI;
2179 if (up->capabilities & UART_CAP_UUE)
2180 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2182 serial_out(up, UART_IER, up->ier);
2184 if (up->capabilities & UART_CAP_EFR) {
2185 unsigned char efr = 0;
2187 * TI16C752/Startech hardware flow control. FIXME:
2188 * - TI16C752 requires control thresholds to be set.
2189 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2191 if (termios->c_cflag & CRTSCTS)
2192 efr |= UART_EFR_CTS;
2194 serial_outp(up, UART_LCR, 0xBF);
2195 serial_outp(up, UART_EFR, efr);
2198 #ifdef CONFIG_ARCH_OMAP15XX
2199 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2200 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
2201 if (baud == 115200) {
2203 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2205 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2209 if (up->capabilities & UART_NATSEMI) {
2210 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2211 serial_outp(up, UART_LCR, 0xe0);
2213 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2216 serial_dl_write(up, quot);
2219 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2220 * is written without DLAB set, this mode will be disabled.
2222 if (up->port.type == PORT_16750)
2223 serial_outp(up, UART_FCR, fcr);
2225 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2226 up->lcr = cval; /* Save LCR */
2227 if (up->port.type != PORT_16750) {
2228 if (fcr & UART_FCR_ENABLE_FIFO) {
2229 /* emulated UARTs (Lucent Venus 167x) need two steps */
2230 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2233 /* Note that we need to set ECB to access write water mark
2234 * bits. First allow FCR tx fifo write, then set fcr with
2235 * possible TX fifo settings. */
2236 if (uart_config[up->port.type].flags & UART_CAP_EFR) {
2237 serial_outp(up, UART_LCR, 0xbf); /* Access EFR */
2238 serial_outp(up, UART_EFR, UART_EFR_ECB);
2239 serial_outp(up, UART_LCR, 0x0); /* Access FCR */
2240 serial_outp(up, UART_FCR, fcr);
2241 serial_outp(up, UART_LCR, 0xbf); /* Access EFR */
2242 serial_outp(up, UART_EFR, 0);
2243 serial_outp(up, UART_LCR, cval); /* Access FCR */
2245 serial_outp(up, UART_FCR, fcr); /* set fcr */
2247 serial8250_set_mctrl(&up->port, up->port.mctrl);
2248 spin_unlock_irqrestore(&up->port.lock, flags);
2249 /* Don't rewrite B0 */
2250 if (tty_termios_baud_rate(termios))
2251 tty_termios_encode_baud_rate(termios, baud, baud);
2255 serial8250_pm(struct uart_port *port, unsigned int state,
2256 unsigned int oldstate)
2258 struct uart_8250_port *p = (struct uart_8250_port *)port;
2260 serial8250_set_sleep(p, state != 0);
2263 p->pm(port, state, oldstate);
2267 * Resource handling.
2269 static int serial8250_request_std_resource(struct uart_8250_port *up)
2271 unsigned int size = 8 << up->port.regshift;
2274 #ifdef CONFIG_ARCH_OMAP
2275 if (is_omap_port((unsigned int)up->port.membase))
2276 size = 0x16 << up->port.regshift;
2279 switch (up->port.iotype) {
2287 if (!up->port.mapbase)
2290 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2295 if (up->port.flags & UPF_IOREMAP) {
2296 up->port.membase = ioremap_nocache(up->port.mapbase,
2298 if (!up->port.membase) {
2299 release_mem_region(up->port.mapbase, size);
2307 if (!request_region(up->port.iobase, size, "serial"))
2314 static void serial8250_release_std_resource(struct uart_8250_port *up)
2316 unsigned int size = 8 << up->port.regshift;
2318 switch (up->port.iotype) {
2326 if (!up->port.mapbase)
2329 if (up->port.flags & UPF_IOREMAP) {
2330 iounmap(up->port.membase);
2331 up->port.membase = NULL;
2334 release_mem_region(up->port.mapbase, size);
2339 release_region(up->port.iobase, size);
2344 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2346 unsigned long start = UART_RSA_BASE << up->port.regshift;
2347 unsigned int size = 8 << up->port.regshift;
2350 switch (up->port.iotype) {
2353 start += up->port.iobase;
2354 if (request_region(start, size, "serial-rsa"))
2364 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2366 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2367 unsigned int size = 8 << up->port.regshift;
2369 switch (up->port.iotype) {
2372 release_region(up->port.iobase + offset, size);
2377 static void serial8250_release_port(struct uart_port *port)
2379 struct uart_8250_port *up = (struct uart_8250_port *)port;
2381 serial8250_release_std_resource(up);
2382 if (up->port.type == PORT_RSA)
2383 serial8250_release_rsa_resource(up);
2386 static int serial8250_request_port(struct uart_port *port)
2388 struct uart_8250_port *up = (struct uart_8250_port *)port;
2391 ret = serial8250_request_std_resource(up);
2392 if (ret == 0 && up->port.type == PORT_RSA) {
2393 ret = serial8250_request_rsa_resource(up);
2395 serial8250_release_std_resource(up);
2401 static void serial8250_config_port(struct uart_port *port, int flags)
2403 struct uart_8250_port *up = (struct uart_8250_port *)port;
2404 int probeflags = PROBE_ANY;
2408 * Find the region that we can probe for. This in turn
2409 * tells us whether we can probe for the type of port.
2411 ret = serial8250_request_std_resource(up);
2415 ret = serial8250_request_rsa_resource(up);
2417 probeflags &= ~PROBE_RSA;
2419 if (flags & UART_CONFIG_TYPE)
2420 autoconfig(up, probeflags);
2421 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2424 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2425 serial8250_release_rsa_resource(up);
2426 if (up->port.type == PORT_UNKNOWN)
2427 serial8250_release_std_resource(up);
2431 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2433 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2434 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2435 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2436 ser->type == PORT_STARTECH)
2442 serial8250_type(struct uart_port *port)
2444 int type = port->type;
2446 if (type >= ARRAY_SIZE(uart_config))
2448 return uart_config[type].name;
2451 static struct uart_ops serial8250_pops = {
2452 .tx_empty = serial8250_tx_empty,
2453 .set_mctrl = serial8250_set_mctrl,
2454 .get_mctrl = serial8250_get_mctrl,
2455 .stop_tx = serial8250_stop_tx,
2456 .start_tx = serial8250_start_tx,
2457 .stop_rx = serial8250_stop_rx,
2458 .enable_ms = serial8250_enable_ms,
2459 .break_ctl = serial8250_break_ctl,
2460 .startup = serial8250_startup,
2461 .shutdown = serial8250_shutdown,
2462 .set_termios = serial8250_set_termios,
2463 .pm = serial8250_pm,
2464 .type = serial8250_type,
2465 .release_port = serial8250_release_port,
2466 .request_port = serial8250_request_port,
2467 .config_port = serial8250_config_port,
2468 .verify_port = serial8250_verify_port,
2469 #ifdef CONFIG_CONSOLE_POLL
2470 .poll_get_char = serial8250_get_poll_char,
2471 .poll_put_char = serial8250_put_poll_char,
2475 static struct uart_8250_port serial8250_ports[UART_NR];
2477 static void __init serial8250_isa_init_ports(void)
2479 struct uart_8250_port *up;
2480 static int first = 1;
2487 for (i = 0; i < nr_uarts; i++) {
2488 struct uart_8250_port *up = &serial8250_ports[i];
2491 spin_lock_init(&up->port.lock);
2493 init_timer(&up->timer);
2494 up->timer.function = serial8250_timeout;
2497 * ALPHA_KLUDGE_MCR needs to be killed.
2499 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2500 up->mcr_force = ALPHA_KLUDGE_MCR;
2502 up->port.ops = &serial8250_pops;
2505 for (i = 0, up = serial8250_ports;
2506 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2508 up->port.iobase = old_serial_port[i].port;
2509 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2510 up->port.uartclk = old_serial_port[i].baud_base * 16;
2511 up->port.flags = old_serial_port[i].flags;
2512 up->port.hub6 = old_serial_port[i].hub6;
2513 up->port.membase = old_serial_port[i].iomem_base;
2514 up->port.iotype = old_serial_port[i].io_type;
2515 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2517 up->port.flags |= UPF_SHARE_IRQ;
2522 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2526 serial8250_isa_init_ports();
2528 for (i = 0; i < nr_uarts; i++) {
2529 struct uart_8250_port *up = &serial8250_ports[i];
2532 uart_add_one_port(drv, &up->port);
2536 #ifdef CONFIG_SERIAL_8250_CONSOLE
2538 static void serial8250_console_putchar(struct uart_port *port, int ch)
2540 struct uart_8250_port *up = (struct uart_8250_port *)port;
2542 wait_for_xmitr(up, UART_LSR_THRE);
2543 serial_out(up, UART_TX, ch);
2547 * Print a string to the serial port trying not to disturb
2548 * any possible real use of the port...
2550 * The console_lock must be held when we get here.
2553 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2555 struct uart_8250_port *up = &serial8250_ports[co->index];
2556 unsigned long flags;
2560 touch_nmi_watchdog();
2562 local_irq_save(flags);
2563 if (up->port.sysrq) {
2564 /* serial8250_handle_port() already took the lock */
2566 } else if (oops_in_progress) {
2567 locked = spin_trylock(&up->port.lock);
2569 spin_lock(&up->port.lock);
2572 * First save the IER then disable the interrupts
2574 ier = serial_in(up, UART_IER);
2576 if (up->capabilities & UART_CAP_UUE)
2577 serial_out(up, UART_IER, UART_IER_UUE);
2579 serial_out(up, UART_IER, 0);
2581 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2584 * Finally, wait for transmitter to become empty
2585 * and restore the IER
2587 wait_for_xmitr(up, BOTH_EMPTY);
2588 serial_out(up, UART_IER, ier);
2591 * The receive handling will happen properly because the
2592 * receive ready bit will still be set; it is not cleared
2593 * on read. However, modem control will not, we must
2594 * call it if we have saved something in the saved flags
2595 * while processing with interrupts off.
2597 if (up->msr_saved_flags)
2598 check_modem_status(up);
2601 spin_unlock(&up->port.lock);
2602 local_irq_restore(flags);
2605 static int __init serial8250_console_setup(struct console *co, char *options)
2607 struct uart_port *port;
2614 * Check whether an invalid uart number has been specified, and
2615 * if so, search for the first available port that does have
2618 if (co->index >= nr_uarts)
2620 port = &serial8250_ports[co->index].port;
2621 if (!port->iobase && !port->membase)
2625 uart_parse_options(options, &baud, &parity, &bits, &flow);
2627 return uart_set_options(port, co, baud, parity, bits, flow);
2630 static int serial8250_console_early_setup(void)
2632 return serial8250_find_port_for_earlycon();
2635 static struct uart_driver serial8250_reg;
2636 static struct console serial8250_console = {
2638 .write = serial8250_console_write,
2639 .device = uart_console_device,
2640 .setup = serial8250_console_setup,
2641 .early_setup = serial8250_console_early_setup,
2642 .flags = CON_PRINTBUFFER,
2644 .data = &serial8250_reg,
2647 static int __init serial8250_console_init(void)
2649 serial8250_isa_init_ports();
2650 register_console(&serial8250_console);
2653 console_initcall(serial8250_console_init);
2655 int serial8250_find_port(struct uart_port *p)
2658 struct uart_port *port;
2660 for (line = 0; line < nr_uarts; line++) {
2661 port = &serial8250_ports[line].port;
2662 if (uart_match_port(p, port))
2668 #define SERIAL8250_CONSOLE &serial8250_console
2670 #define SERIAL8250_CONSOLE NULL
2673 static struct uart_driver serial8250_reg = {
2674 .owner = THIS_MODULE,
2675 .driver_name = "serial",
2680 .cons = SERIAL8250_CONSOLE,
2684 * early_serial_setup - early registration for 8250 ports
2686 * Setup an 8250 port structure prior to console initialisation. Use
2687 * after console initialisation will cause undefined behaviour.
2689 int __init early_serial_setup(struct uart_port *port)
2691 if (port->line >= ARRAY_SIZE(serial8250_ports))
2694 serial8250_isa_init_ports();
2695 serial8250_ports[port->line].port = *port;
2696 serial8250_ports[port->line].port.ops = &serial8250_pops;
2701 * serial8250_suspend_port - suspend one serial port
2702 * @line: serial line number
2704 * Suspend one serial port.
2706 void serial8250_suspend_port(int line)
2708 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2712 * serial8250_resume_port - resume one serial port
2713 * @line: serial line number
2715 * Resume one serial port.
2717 void serial8250_resume_port(int line)
2719 struct uart_8250_port *up = &serial8250_ports[line];
2721 if (up->capabilities & UART_NATSEMI) {
2724 /* Ensure it's still in high speed mode */
2725 serial_outp(up, UART_LCR, 0xE0);
2727 tmp = serial_in(up, 0x04); /* EXCR2 */
2728 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2729 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2730 serial_outp(up, 0x04, tmp);
2732 serial_outp(up, UART_LCR, 0);
2734 uart_resume_port(&serial8250_reg, &up->port);
2738 * Register a set of serial devices attached to a platform device. The
2739 * list is terminated with a zero flags entry, which means we expect
2740 * all entries to have at least UPF_BOOT_AUTOCONF set.
2742 static int __devinit serial8250_probe(struct platform_device *dev)
2744 struct plat_serial8250_port *p = dev->dev.platform_data;
2745 struct uart_port port;
2748 memset(&port, 0, sizeof(struct uart_port));
2750 for (i = 0; p && p->flags != 0; p++, i++) {
2751 port.iobase = p->iobase;
2752 port.membase = p->membase;
2754 port.uartclk = p->uartclk;
2755 port.regshift = p->regshift;
2756 port.iotype = p->iotype;
2757 port.flags = p->flags;
2758 port.mapbase = p->mapbase;
2759 port.hub6 = p->hub6;
2760 port.private_data = p->private_data;
2761 port.dev = &dev->dev;
2763 port.flags |= UPF_SHARE_IRQ;
2764 ret = serial8250_register_port(&port);
2766 dev_err(&dev->dev, "unable to register port at index %d "
2767 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2768 p->iobase, (unsigned long long)p->mapbase,
2776 * Remove serial ports registered against a platform device.
2778 static int __devexit serial8250_remove(struct platform_device *dev)
2782 for (i = 0; i < nr_uarts; i++) {
2783 struct uart_8250_port *up = &serial8250_ports[i];
2785 if (up->port.dev == &dev->dev)
2786 serial8250_unregister_port(i);
2791 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2795 for (i = 0; i < UART_NR; i++) {
2796 struct uart_8250_port *up = &serial8250_ports[i];
2798 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2799 uart_suspend_port(&serial8250_reg, &up->port);
2805 static int serial8250_resume(struct platform_device *dev)
2809 for (i = 0; i < UART_NR; i++) {
2810 struct uart_8250_port *up = &serial8250_ports[i];
2812 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2813 serial8250_resume_port(i);
2819 static struct platform_driver serial8250_isa_driver = {
2820 .probe = serial8250_probe,
2821 .remove = __devexit_p(serial8250_remove),
2822 .suspend = serial8250_suspend,
2823 .resume = serial8250_resume,
2825 .name = "serial8250",
2826 .owner = THIS_MODULE,
2831 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2832 * in the table in include/asm/serial.h
2834 static struct platform_device *serial8250_isa_devs;
2837 * serial8250_register_port and serial8250_unregister_port allows for
2838 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2839 * modems and PCI multiport cards.
2841 static DEFINE_MUTEX(serial_mutex);
2843 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2848 * First, find a port entry which matches.
2850 for (i = 0; i < nr_uarts; i++)
2851 if (uart_match_port(&serial8250_ports[i].port, port))
2852 return &serial8250_ports[i];
2855 * We didn't find a matching entry, so look for the first
2856 * free entry. We look for one which hasn't been previously
2857 * used (indicated by zero iobase).
2859 for (i = 0; i < nr_uarts; i++)
2860 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2861 serial8250_ports[i].port.iobase == 0)
2862 return &serial8250_ports[i];
2865 * That also failed. Last resort is to find any entry which
2866 * doesn't have a real port associated with it.
2868 for (i = 0; i < nr_uarts; i++)
2869 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2870 return &serial8250_ports[i];
2876 * serial8250_register_port - register a serial port
2877 * @port: serial port template
2879 * Configure the serial port specified by the request. If the
2880 * port exists and is in use, it is hung up and unregistered
2883 * The port is then probed and if necessary the IRQ is autodetected
2884 * If this fails an error is returned.
2886 * On success the port is ready to use and the line number is returned.
2888 int serial8250_register_port(struct uart_port *port)
2890 struct uart_8250_port *uart;
2893 if (port->uartclk == 0)
2896 mutex_lock(&serial_mutex);
2898 uart = serial8250_find_match_or_unused(port);
2900 uart_remove_one_port(&serial8250_reg, &uart->port);
2902 uart->port.iobase = port->iobase;
2903 uart->port.membase = port->membase;
2904 uart->port.irq = port->irq;
2905 uart->port.uartclk = port->uartclk;
2906 uart->port.fifosize = port->fifosize;
2907 uart->port.regshift = port->regshift;
2908 uart->port.iotype = port->iotype;
2909 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2910 uart->port.mapbase = port->mapbase;
2911 uart->port.private_data = port->private_data;
2913 uart->port.dev = port->dev;
2915 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2917 ret = uart->port.line;
2919 mutex_unlock(&serial_mutex);
2923 EXPORT_SYMBOL(serial8250_register_port);
2926 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2927 * @line: serial line number
2929 * Remove one serial port. This may not be called from interrupt
2930 * context. We hand the port back to the our control.
2932 void serial8250_unregister_port(int line)
2934 struct uart_8250_port *uart = &serial8250_ports[line];
2936 mutex_lock(&serial_mutex);
2937 uart_remove_one_port(&serial8250_reg, &uart->port);
2938 if (serial8250_isa_devs) {
2939 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2940 uart->port.type = PORT_UNKNOWN;
2941 uart->port.dev = &serial8250_isa_devs->dev;
2942 uart_add_one_port(&serial8250_reg, &uart->port);
2944 uart->port.dev = NULL;
2946 mutex_unlock(&serial_mutex);
2948 EXPORT_SYMBOL(serial8250_unregister_port);
2950 static int __init serial8250_init(void)
2954 if (nr_uarts > UART_NR)
2957 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2958 "%d ports, IRQ sharing %sabled\n", nr_uarts,
2959 share_irqs ? "en" : "dis");
2961 for (i = 0; i < NR_IRQS; i++)
2962 spin_lock_init(&irq_lists[i].lock);
2964 ret = uart_register_driver(&serial8250_reg);
2968 serial8250_isa_devs = platform_device_alloc("serial8250",
2969 PLAT8250_DEV_LEGACY);
2970 if (!serial8250_isa_devs) {
2972 goto unreg_uart_drv;
2975 ret = platform_device_add(serial8250_isa_devs);
2979 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2981 ret = platform_driver_register(&serial8250_isa_driver);
2985 platform_device_del(serial8250_isa_devs);
2987 platform_device_put(serial8250_isa_devs);
2989 uart_unregister_driver(&serial8250_reg);
2994 static void __exit serial8250_exit(void)
2996 struct platform_device *isa_dev = serial8250_isa_devs;
2999 * This tells serial8250_unregister_port() not to re-register
3000 * the ports (thereby making serial8250_isa_driver permanently
3003 serial8250_isa_devs = NULL;
3005 platform_driver_unregister(&serial8250_isa_driver);
3006 platform_device_unregister(isa_dev);
3008 uart_unregister_driver(&serial8250_reg);
3011 module_init(serial8250_init);
3012 module_exit(serial8250_exit);
3014 EXPORT_SYMBOL(serial8250_suspend_port);
3015 EXPORT_SYMBOL(serial8250_resume_port);
3017 MODULE_LICENSE("GPL");
3018 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
3020 module_param(share_irqs, uint, 0644);
3021 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3024 module_param(nr_uarts, uint, 0644);
3025 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3027 #ifdef CONFIG_SERIAL_8250_RSA
3028 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3029 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3031 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);