2 * linux/drivers/char/8250.c
4 * Driver for 8250/16550-type serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
17 * A note about mapbase / membase
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
23 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ioport.h>
30 #include <linux/init.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/tty.h>
36 #include <linux/tty_flip.h>
37 #include <linux/serial_reg.h>
38 #include <linux/serial_core.h>
39 #include <linux/serial.h>
40 #include <linux/serial_8250.h>
41 #include <linux/nmi.h>
42 #include <linux/mutex.h>
51 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
52 * is unsafe when used on edge-triggered interrupts.
54 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
56 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
62 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
64 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
68 #define DEBUG_INTR(fmt...) printk(fmt)
70 #define DEBUG_INTR(fmt...) do { } while (0)
73 #define PASS_LIMIT 256
76 * We default to IRQ0 for the "no irq" hack. Some
77 * machine types want others as well - they're free
78 * to redefine this in their header file.
80 #define is_real_interrupt(irq) ((irq) != 0)
82 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
83 #define CONFIG_SERIAL_DETECT_IRQ 1
85 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
86 #define CONFIG_SERIAL_MANY_PORTS 1
90 * HUB6 is always on. This will be removed once the header
91 * files have been cleaned.
95 #include <asm/serial.h>
98 * SERIAL_PORT_DFNS tells us about built-in ports that have no
99 * standard enumeration mechanism. Platforms that can find all
100 * serial ports via mechanisms like ACPI or PCI need not supply it.
102 #ifndef SERIAL_PORT_DFNS
103 #define SERIAL_PORT_DFNS
106 static const struct old_serial_port old_serial_port[] = {
107 SERIAL_PORT_DFNS /* defined in asm/serial.h */
110 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
112 #ifdef CONFIG_SERIAL_8250_RSA
114 #define PORT_RSA_MAX 4
115 static unsigned long probe_rsa[PORT_RSA_MAX];
116 static unsigned int probe_rsa_count;
117 #endif /* CONFIG_SERIAL_8250_RSA */
119 struct uart_8250_port {
120 struct uart_port port;
121 struct timer_list timer; /* "no irq" timer */
122 struct list_head list; /* ports on this IRQ */
123 unsigned short capabilities; /* port capabilities */
124 unsigned short bugs; /* port bugs */
125 unsigned int tx_loadsz; /* transmit fifo load size */
130 unsigned char mcr_mask; /* mask of user bits */
131 unsigned char mcr_force; /* mask of forced bits */
132 unsigned char lsr_break_flag;
135 * We provide a per-port pm hook.
137 void (*pm)(struct uart_port *port,
138 unsigned int state, unsigned int old);
143 struct list_head *head;
146 static struct irq_info irq_lists[NR_IRQS];
149 * Here we define the default xmit fifo size used for each type of UART.
151 static const struct serial8250_config uart_config[] = {
176 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
177 .flags = UART_CAP_FIFO,
188 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
196 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
212 .name = "16C950/954",
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
216 .flags = UART_CAP_FIFO,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
224 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
231 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
238 .flags = UART_CAP_FIFO,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_NATSEMI,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_UUE,
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
259 .flags = UART_CAP_FIFO,
263 #if defined (CONFIG_SERIAL_8250_AU1X00)
265 /* Au1x00 UART hardware has a weird register layout */
266 static const u8 au_io_in_map[] = {
276 static const u8 au_io_out_map[] = {
284 /* sane hardware needs no mapping */
285 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
287 if (up->port.iotype != UPIO_AU)
289 return au_io_in_map[offset];
292 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
294 if (up->port.iotype != UPIO_AU)
296 return au_io_out_map[offset];
299 #elif defined (CONFIG_SERIAL_8250_RM9K)
323 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
325 if (up->port.iotype != UPIO_RM9000)
327 return regmap_in[offset];
330 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
332 if (up->port.iotype != UPIO_RM9000)
334 return regmap_out[offset];
339 /* sane hardware needs no mapping */
340 #define map_8250_in_reg(up, offset) (offset)
341 #define map_8250_out_reg(up, offset) (offset)
345 static unsigned int serial_in(struct uart_8250_port *up, int offset)
348 offset = map_8250_in_reg(up, offset) << up->port.regshift;
350 switch (up->port.iotype) {
352 outb(up->port.hub6 - 1 + offset, up->port.iobase);
353 return inb(up->port.iobase + 1);
357 return readb(up->port.membase + offset);
361 return readl(up->port.membase + offset);
363 #ifdef CONFIG_SERIAL_8250_AU1X00
365 return __raw_readl(up->port.membase + offset);
369 if (offset == UART_IIR) {
370 tmp = readl(up->port.membase + (UART_IIR & ~3));
371 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
373 return readb(up->port.membase + offset);
376 return inb(up->port.iobase + offset);
381 serial_out(struct uart_8250_port *up, int offset, int value)
383 /* Save the offset before it's remapped */
384 int save_offset = offset;
385 offset = map_8250_out_reg(up, offset) << up->port.regshift;
387 switch (up->port.iotype) {
389 outb(up->port.hub6 - 1 + offset, up->port.iobase);
390 outb(value, up->port.iobase + 1);
394 writeb(value, up->port.membase + offset);
399 writel(value, up->port.membase + offset);
402 #ifdef CONFIG_SERIAL_8250_AU1X00
404 __raw_writel(value, up->port.membase + offset);
408 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
409 writeb(value, up->port.membase + offset);
413 /* Save the LCR value so it can be re-written when a
414 * Busy Detect interrupt occurs. */
415 if (save_offset == UART_LCR)
417 writeb(value, up->port.membase + offset);
418 /* Read the IER to ensure any interrupt is cleared before
419 * returning from ISR. */
420 if (save_offset == UART_TX || save_offset == UART_IER)
421 value = serial_in(up, UART_IER);
425 outb(value, up->port.iobase + offset);
430 serial_out_sync(struct uart_8250_port *up, int offset, int value)
432 switch (up->port.iotype) {
435 #ifdef CONFIG_SERIAL_8250_AU1X00
439 serial_out(up, offset, value);
440 serial_in(up, UART_LCR); /* safe, no side-effects */
443 serial_out(up, offset, value);
448 * We used to support using pause I/O for certain machines. We
449 * haven't supported this for a while, but just in case it's badly
450 * needed for certain old 386 machines, I've left these #define's
453 #define serial_inp(up, offset) serial_in(up, offset)
454 #define serial_outp(up, offset, value) serial_out(up, offset, value)
456 /* Uart divisor latch read */
457 static inline int _serial_dl_read(struct uart_8250_port *up)
459 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
462 /* Uart divisor latch write */
463 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
465 serial_outp(up, UART_DLL, value & 0xff);
466 serial_outp(up, UART_DLM, value >> 8 & 0xff);
469 #if defined (CONFIG_SERIAL_8250_AU1X00)
470 /* Au1x00 haven't got a standard divisor latch */
471 static int serial_dl_read(struct uart_8250_port *up)
473 if (up->port.iotype == UPIO_AU)
474 return __raw_readl(up->port.membase + 0x28);
476 return _serial_dl_read(up);
479 static void serial_dl_write(struct uart_8250_port *up, int value)
481 if (up->port.iotype == UPIO_AU)
482 __raw_writel(value, up->port.membase + 0x28);
484 _serial_dl_write(up, value);
486 #elif defined (CONFIG_SERIAL_8250_RM9K)
487 static int serial_dl_read(struct uart_8250_port *up)
489 return (up->port.iotype == UPIO_RM9000) ?
490 (((__raw_readl(up->port.membase + 0x10) << 8) |
491 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
495 static void serial_dl_write(struct uart_8250_port *up, int value)
497 if (up->port.iotype == UPIO_RM9000) {
498 __raw_writel(value, up->port.membase + 0x08);
499 __raw_writel(value >> 8, up->port.membase + 0x10);
501 _serial_dl_write(up, value);
505 #define serial_dl_read(up) _serial_dl_read(up)
506 #define serial_dl_write(up, value) _serial_dl_write(up, value)
512 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
514 serial_out(up, UART_SCR, offset);
515 serial_out(up, UART_ICR, value);
518 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
522 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
523 serial_out(up, UART_SCR, offset);
524 value = serial_in(up, UART_ICR);
525 serial_icr_write(up, UART_ACR, up->acr);
533 static inline void serial8250_clear_fifos(struct uart_8250_port *p)
535 if (p->capabilities & UART_CAP_FIFO) {
536 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
537 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
538 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
539 serial_outp(p, UART_FCR, 0);
544 * IER sleep support. UARTs which have EFRs need the "extended
545 * capability" bit enabled. Note that on XR16C850s, we need to
546 * reset LCR to write to IER.
548 static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
550 if (p->capabilities & UART_CAP_SLEEP) {
551 if (p->capabilities & UART_CAP_EFR) {
552 serial_outp(p, UART_LCR, 0xBF);
553 serial_outp(p, UART_EFR, UART_EFR_ECB);
554 serial_outp(p, UART_LCR, 0);
556 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
557 if (p->capabilities & UART_CAP_EFR) {
558 serial_outp(p, UART_LCR, 0xBF);
559 serial_outp(p, UART_EFR, 0);
560 serial_outp(p, UART_LCR, 0);
565 #ifdef CONFIG_SERIAL_8250_RSA
567 * Attempts to turn on the RSA FIFO. Returns zero on failure.
568 * We set the port uart clock rate if we succeed.
570 static int __enable_rsa(struct uart_8250_port *up)
575 mode = serial_inp(up, UART_RSA_MSR);
576 result = mode & UART_RSA_MSR_FIFO;
579 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
580 mode = serial_inp(up, UART_RSA_MSR);
581 result = mode & UART_RSA_MSR_FIFO;
585 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
590 static void enable_rsa(struct uart_8250_port *up)
592 if (up->port.type == PORT_RSA) {
593 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
594 spin_lock_irq(&up->port.lock);
596 spin_unlock_irq(&up->port.lock);
598 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
599 serial_outp(up, UART_RSA_FRR, 0);
604 * Attempts to turn off the RSA FIFO. Returns zero on failure.
605 * It is unknown why interrupts were disabled in here. However,
606 * the caller is expected to preserve this behaviour by grabbing
607 * the spinlock before calling this function.
609 static void disable_rsa(struct uart_8250_port *up)
614 if (up->port.type == PORT_RSA &&
615 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
616 spin_lock_irq(&up->port.lock);
618 mode = serial_inp(up, UART_RSA_MSR);
619 result = !(mode & UART_RSA_MSR_FIFO);
622 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
623 mode = serial_inp(up, UART_RSA_MSR);
624 result = !(mode & UART_RSA_MSR_FIFO);
628 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
629 spin_unlock_irq(&up->port.lock);
632 #endif /* CONFIG_SERIAL_8250_RSA */
635 * This is a quickie test to see how big the FIFO is.
636 * It doesn't work at all the time, more's the pity.
638 static int size_fifo(struct uart_8250_port *up)
640 unsigned char old_fcr, old_mcr, old_lcr;
641 unsigned short old_dl;
644 old_lcr = serial_inp(up, UART_LCR);
645 serial_outp(up, UART_LCR, 0);
646 old_fcr = serial_inp(up, UART_FCR);
647 old_mcr = serial_inp(up, UART_MCR);
648 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
649 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
650 serial_outp(up, UART_MCR, UART_MCR_LOOP);
651 serial_outp(up, UART_LCR, UART_LCR_DLAB);
652 old_dl = serial_dl_read(up);
653 serial_dl_write(up, 0x0001);
654 serial_outp(up, UART_LCR, 0x03);
655 for (count = 0; count < 256; count++)
656 serial_outp(up, UART_TX, count);
657 mdelay(20);/* FIXME - schedule_timeout */
658 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
659 (count < 256); count++)
660 serial_inp(up, UART_RX);
661 serial_outp(up, UART_FCR, old_fcr);
662 serial_outp(up, UART_MCR, old_mcr);
663 serial_outp(up, UART_LCR, UART_LCR_DLAB);
664 serial_dl_write(up, old_dl);
665 serial_outp(up, UART_LCR, old_lcr);
671 * Read UART ID using the divisor method - set DLL and DLM to zero
672 * and the revision will be in DLL and device type in DLM. We
673 * preserve the device state across this.
675 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
677 unsigned char old_dll, old_dlm, old_lcr;
680 old_lcr = serial_inp(p, UART_LCR);
681 serial_outp(p, UART_LCR, UART_LCR_DLAB);
683 old_dll = serial_inp(p, UART_DLL);
684 old_dlm = serial_inp(p, UART_DLM);
686 serial_outp(p, UART_DLL, 0);
687 serial_outp(p, UART_DLM, 0);
689 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
691 serial_outp(p, UART_DLL, old_dll);
692 serial_outp(p, UART_DLM, old_dlm);
693 serial_outp(p, UART_LCR, old_lcr);
699 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
700 * When this function is called we know it is at least a StarTech
701 * 16650 V2, but it might be one of several StarTech UARTs, or one of
702 * its clones. (We treat the broken original StarTech 16650 V1 as a
703 * 16550, and why not? Startech doesn't seem to even acknowledge its
706 * What evil have men's minds wrought...
708 static void autoconfig_has_efr(struct uart_8250_port *up)
710 unsigned int id1, id2, id3, rev;
713 * Everything with an EFR has SLEEP
715 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
718 * First we check to see if it's an Oxford Semiconductor UART.
720 * If we have to do this here because some non-National
721 * Semiconductor clone chips lock up if you try writing to the
722 * LSR register (which serial_icr_read does)
726 * Check for Oxford Semiconductor 16C950.
728 * EFR [4] must be set else this test fails.
730 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
731 * claims that it's needed for 952 dual UART's (which are not
732 * recommended for new designs).
735 serial_out(up, UART_LCR, 0xBF);
736 serial_out(up, UART_EFR, UART_EFR_ECB);
737 serial_out(up, UART_LCR, 0x00);
738 id1 = serial_icr_read(up, UART_ID1);
739 id2 = serial_icr_read(up, UART_ID2);
740 id3 = serial_icr_read(up, UART_ID3);
741 rev = serial_icr_read(up, UART_REV);
743 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
745 if (id1 == 0x16 && id2 == 0xC9 &&
746 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
747 up->port.type = PORT_16C950;
750 * Enable work around for the Oxford Semiconductor 952 rev B
751 * chip which causes it to seriously miscalculate baud rates
754 if (id3 == 0x52 && rev == 0x01)
755 up->bugs |= UART_BUG_QUOT;
760 * We check for a XR16C850 by setting DLL and DLM to 0, and then
761 * reading back DLL and DLM. The chip type depends on the DLM
763 * 0x10 - XR16C850 and the DLL contains the chip revision.
767 id1 = autoconfig_read_divisor_id(up);
768 DEBUG_AUTOCONF("850id=%04x ", id1);
771 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
772 up->port.type = PORT_16850;
777 * It wasn't an XR16C850.
779 * We distinguish between the '654 and the '650 by counting
780 * how many bytes are in the FIFO. I'm using this for now,
781 * since that's the technique that was sent to me in the
782 * serial driver update, but I'm not convinced this works.
783 * I've had problems doing this in the past. -TYT
785 if (size_fifo(up) == 64)
786 up->port.type = PORT_16654;
788 up->port.type = PORT_16650V2;
792 * We detected a chip without a FIFO. Only two fall into
793 * this category - the original 8250 and the 16450. The
794 * 16450 has a scratch register (accessible with LCR=0)
796 static void autoconfig_8250(struct uart_8250_port *up)
798 unsigned char scratch, status1, status2;
800 up->port.type = PORT_8250;
802 scratch = serial_in(up, UART_SCR);
803 serial_outp(up, UART_SCR, 0xa5);
804 status1 = serial_in(up, UART_SCR);
805 serial_outp(up, UART_SCR, 0x5a);
806 status2 = serial_in(up, UART_SCR);
807 serial_outp(up, UART_SCR, scratch);
809 if (status1 == 0xa5 && status2 == 0x5a)
810 up->port.type = PORT_16450;
813 static int broken_efr(struct uart_8250_port *up)
816 * Exar ST16C2550 "A2" devices incorrectly detect as
817 * having an EFR, and report an ID of 0x0201. See
818 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
820 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
827 * We know that the chip has FIFOs. Does it have an EFR? The
828 * EFR is located in the same register position as the IIR and
829 * we know the top two bits of the IIR are currently set. The
830 * EFR should contain zero. Try to read the EFR.
832 static void autoconfig_16550a(struct uart_8250_port *up)
834 unsigned char status1, status2;
835 unsigned int iersave;
837 up->port.type = PORT_16550A;
838 up->capabilities |= UART_CAP_FIFO;
841 * Check for presence of the EFR when DLAB is set.
842 * Only ST16C650V1 UARTs pass this test.
844 serial_outp(up, UART_LCR, UART_LCR_DLAB);
845 if (serial_in(up, UART_EFR) == 0) {
846 serial_outp(up, UART_EFR, 0xA8);
847 if (serial_in(up, UART_EFR) != 0) {
848 DEBUG_AUTOCONF("EFRv1 ");
849 up->port.type = PORT_16650;
850 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
852 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
854 serial_outp(up, UART_EFR, 0);
859 * Maybe it requires 0xbf to be written to the LCR.
860 * (other ST16C650V2 UARTs, TI16C752A, etc)
862 serial_outp(up, UART_LCR, 0xBF);
863 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
864 DEBUG_AUTOCONF("EFRv2 ");
865 autoconfig_has_efr(up);
870 * Check for a National Semiconductor SuperIO chip.
871 * Attempt to switch to bank 2, read the value of the LOOP bit
872 * from EXCR1. Switch back to bank 0, change it in MCR. Then
873 * switch back to bank 2, read it from EXCR1 again and check
874 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
876 serial_outp(up, UART_LCR, 0);
877 status1 = serial_in(up, UART_MCR);
878 serial_outp(up, UART_LCR, 0xE0);
879 status2 = serial_in(up, 0x02); /* EXCR1 */
881 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
882 serial_outp(up, UART_LCR, 0);
883 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
884 serial_outp(up, UART_LCR, 0xE0);
885 status2 = serial_in(up, 0x02); /* EXCR1 */
886 serial_outp(up, UART_LCR, 0);
887 serial_outp(up, UART_MCR, status1);
889 if ((status2 ^ status1) & UART_MCR_LOOP) {
892 serial_outp(up, UART_LCR, 0xE0);
894 quot = serial_dl_read(up);
897 status1 = serial_in(up, 0x04); /* EXCR2 */
898 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
899 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
900 serial_outp(up, 0x04, status1);
902 serial_dl_write(up, quot);
904 serial_outp(up, UART_LCR, 0);
906 up->port.uartclk = 921600*16;
907 up->port.type = PORT_NS16550A;
908 up->capabilities |= UART_NATSEMI;
914 * No EFR. Try to detect a TI16750, which only sets bit 5 of
915 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
916 * Try setting it with and without DLAB set. Cheap clones
917 * set bit 5 without DLAB set.
919 serial_outp(up, UART_LCR, 0);
920 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
921 status1 = serial_in(up, UART_IIR) >> 5;
922 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
923 serial_outp(up, UART_LCR, UART_LCR_DLAB);
924 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
925 status2 = serial_in(up, UART_IIR) >> 5;
926 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
927 serial_outp(up, UART_LCR, 0);
929 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
931 if (status1 == 6 && status2 == 7) {
932 up->port.type = PORT_16750;
933 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
938 * Try writing and reading the UART_IER_UUE bit (b6).
939 * If it works, this is probably one of the Xscale platform's
941 * We're going to explicitly set the UUE bit to 0 before
942 * trying to write and read a 1 just to make sure it's not
943 * already a 1 and maybe locked there before we even start start.
945 iersave = serial_in(up, UART_IER);
946 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
947 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
949 * OK it's in a known zero state, try writing and reading
950 * without disturbing the current state of the other bits.
952 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
953 if (serial_in(up, UART_IER) & UART_IER_UUE) {
956 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
958 DEBUG_AUTOCONF("Xscale ");
959 up->port.type = PORT_XSCALE;
960 up->capabilities |= UART_CAP_UUE;
965 * If we got here we couldn't force the IER_UUE bit to 0.
966 * Log it and continue.
968 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
970 serial_outp(up, UART_IER, iersave);
974 * This routine is called by rs_init() to initialize a specific serial
975 * port. It determines what type of UART chip this serial port is
976 * using: 8250, 16450, 16550, 16550A. The important question is
977 * whether or not this UART is a 16550A or not, since this will
978 * determine whether or not we can use its FIFO features or not.
980 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
982 unsigned char status1, scratch, scratch2, scratch3;
983 unsigned char save_lcr, save_mcr;
986 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
989 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
990 up->port.line, up->port.iobase, up->port.membase);
993 * We really do need global IRQs disabled here - we're going to
994 * be frobbing the chips IRQ enable register to see if it exists.
996 spin_lock_irqsave(&up->port.lock, flags);
998 up->capabilities = 0;
1001 if (!(up->port.flags & UPF_BUGGY_UART)) {
1003 * Do a simple existence test first; if we fail this,
1004 * there's no point trying anything else.
1006 * 0x80 is used as a nonsense port to prevent against
1007 * false positives due to ISA bus float. The
1008 * assumption is that 0x80 is a non-existent port;
1009 * which should be safe since include/asm/io.h also
1010 * makes this assumption.
1012 * Note: this is safe as long as MCR bit 4 is clear
1013 * and the device is in "PC" mode.
1015 scratch = serial_inp(up, UART_IER);
1016 serial_outp(up, UART_IER, 0);
1021 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1022 * 16C754B) allow only to modify them if an EFR bit is set.
1024 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1025 serial_outp(up, UART_IER, 0x0F);
1029 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1030 serial_outp(up, UART_IER, scratch);
1031 if (scratch2 != 0 || scratch3 != 0x0F) {
1033 * We failed; there's nothing here
1035 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1036 scratch2, scratch3);
1041 save_mcr = serial_in(up, UART_MCR);
1042 save_lcr = serial_in(up, UART_LCR);
1045 * Check to see if a UART is really there. Certain broken
1046 * internal modems based on the Rockwell chipset fail this
1047 * test, because they apparently don't implement the loopback
1048 * test mode. So this test is skipped on the COM 1 through
1049 * COM 4 ports. This *should* be safe, since no board
1050 * manufacturer would be stupid enough to design a board
1051 * that conflicts with COM 1-4 --- we hope!
1053 if (!(up->port.flags & UPF_SKIP_TEST)) {
1054 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1055 status1 = serial_inp(up, UART_MSR) & 0xF0;
1056 serial_outp(up, UART_MCR, save_mcr);
1057 if (status1 != 0x90) {
1058 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1065 * We're pretty sure there's a port here. Lets find out what
1066 * type of port it is. The IIR top two bits allows us to find
1067 * out if it's 8250 or 16450, 16550, 16550A or later. This
1068 * determines what we test for next.
1070 * We also initialise the EFR (if any) to zero for later. The
1071 * EFR occupies the same register location as the FCR and IIR.
1073 serial_outp(up, UART_LCR, 0xBF);
1074 serial_outp(up, UART_EFR, 0);
1075 serial_outp(up, UART_LCR, 0);
1077 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1078 scratch = serial_in(up, UART_IIR) >> 6;
1080 DEBUG_AUTOCONF("iir=%d ", scratch);
1084 autoconfig_8250(up);
1087 up->port.type = PORT_UNKNOWN;
1090 up->port.type = PORT_16550;
1093 autoconfig_16550a(up);
1097 #ifdef CONFIG_SERIAL_8250_RSA
1099 * Only probe for RSA ports if we got the region.
1101 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1104 for (i = 0 ; i < probe_rsa_count; ++i) {
1105 if (probe_rsa[i] == up->port.iobase &&
1107 up->port.type = PORT_RSA;
1114 #ifdef CONFIG_SERIAL_8250_AU1X00
1115 /* if access method is AU, it is a 16550 with a quirk */
1116 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1117 up->bugs |= UART_BUG_NOMSR;
1120 serial_outp(up, UART_LCR, save_lcr);
1122 if (up->capabilities != uart_config[up->port.type].flags) {
1124 "ttyS%d: detected caps %08x should be %08x\n",
1125 up->port.line, up->capabilities,
1126 uart_config[up->port.type].flags);
1129 up->port.fifosize = uart_config[up->port.type].fifo_size;
1130 up->capabilities = uart_config[up->port.type].flags;
1131 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1133 if (up->port.type == PORT_UNKNOWN)
1139 #ifdef CONFIG_SERIAL_8250_RSA
1140 if (up->port.type == PORT_RSA)
1141 serial_outp(up, UART_RSA_FRR, 0);
1143 serial_outp(up, UART_MCR, save_mcr);
1144 serial8250_clear_fifos(up);
1145 serial_in(up, UART_RX);
1146 if (up->capabilities & UART_CAP_UUE)
1147 serial_outp(up, UART_IER, UART_IER_UUE);
1149 serial_outp(up, UART_IER, 0);
1152 spin_unlock_irqrestore(&up->port.lock, flags);
1153 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1156 static void autoconfig_irq(struct uart_8250_port *up)
1158 unsigned char save_mcr, save_ier;
1159 unsigned char save_ICP = 0;
1160 unsigned int ICP = 0;
1164 if (up->port.flags & UPF_FOURPORT) {
1165 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1166 save_ICP = inb_p(ICP);
1171 /* forget possible initially masked and pending IRQ */
1172 probe_irq_off(probe_irq_on());
1173 save_mcr = serial_inp(up, UART_MCR);
1174 save_ier = serial_inp(up, UART_IER);
1175 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1177 irqs = probe_irq_on();
1178 serial_outp(up, UART_MCR, 0);
1180 if (up->port.flags & UPF_FOURPORT) {
1181 serial_outp(up, UART_MCR,
1182 UART_MCR_DTR | UART_MCR_RTS);
1184 serial_outp(up, UART_MCR,
1185 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1187 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1188 (void)serial_inp(up, UART_LSR);
1189 (void)serial_inp(up, UART_RX);
1190 (void)serial_inp(up, UART_IIR);
1191 (void)serial_inp(up, UART_MSR);
1192 serial_outp(up, UART_TX, 0xFF);
1194 irq = probe_irq_off(irqs);
1196 serial_outp(up, UART_MCR, save_mcr);
1197 serial_outp(up, UART_IER, save_ier);
1199 if (up->port.flags & UPF_FOURPORT)
1200 outb_p(save_ICP, ICP);
1202 up->port.irq = (irq > 0) ? irq : 0;
1205 static inline void __stop_tx(struct uart_8250_port *p)
1207 if (p->ier & UART_IER_THRI) {
1208 p->ier &= ~UART_IER_THRI;
1209 serial_out(p, UART_IER, p->ier);
1213 static void serial8250_stop_tx(struct uart_port *port)
1215 struct uart_8250_port *up = (struct uart_8250_port *)port;
1220 * We really want to stop the transmitter from sending.
1222 if (up->port.type == PORT_16C950) {
1223 up->acr |= UART_ACR_TXDIS;
1224 serial_icr_write(up, UART_ACR, up->acr);
1228 static void transmit_chars(struct uart_8250_port *up);
1230 static void serial8250_start_tx(struct uart_port *port)
1232 struct uart_8250_port *up = (struct uart_8250_port *)port;
1234 if (!(up->ier & UART_IER_THRI)) {
1235 up->ier |= UART_IER_THRI;
1236 serial_out(up, UART_IER, up->ier);
1238 if (up->bugs & UART_BUG_TXEN) {
1239 unsigned char lsr, iir;
1240 lsr = serial_in(up, UART_LSR);
1241 iir = serial_in(up, UART_IIR) & 0x0f;
1242 if ((up->port.type == PORT_RM9000) ?
1243 (lsr & UART_LSR_THRE &&
1244 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1245 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
1251 * Re-enable the transmitter if we disabled it.
1253 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1254 up->acr &= ~UART_ACR_TXDIS;
1255 serial_icr_write(up, UART_ACR, up->acr);
1259 static void serial8250_stop_rx(struct uart_port *port)
1261 struct uart_8250_port *up = (struct uart_8250_port *)port;
1263 up->ier &= ~UART_IER_RLSI;
1264 up->port.read_status_mask &= ~UART_LSR_DR;
1265 serial_out(up, UART_IER, up->ier);
1268 static void serial8250_enable_ms(struct uart_port *port)
1270 struct uart_8250_port *up = (struct uart_8250_port *)port;
1272 /* no MSR capabilities */
1273 if (up->bugs & UART_BUG_NOMSR)
1276 up->ier |= UART_IER_MSI;
1277 serial_out(up, UART_IER, up->ier);
1281 receive_chars(struct uart_8250_port *up, unsigned int *status)
1283 struct tty_struct *tty = up->port.info->tty;
1284 unsigned char ch, lsr = *status;
1285 int max_count = 256;
1289 ch = serial_inp(up, UART_RX);
1291 up->port.icount.rx++;
1293 #ifdef CONFIG_SERIAL_8250_CONSOLE
1295 * Recover the break flag from console xmit
1297 if (up->port.line == up->port.cons->index) {
1298 lsr |= up->lsr_break_flag;
1299 up->lsr_break_flag = 0;
1303 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1304 UART_LSR_FE | UART_LSR_OE))) {
1306 * For statistics only
1308 if (lsr & UART_LSR_BI) {
1309 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1310 up->port.icount.brk++;
1312 * We do the SysRQ and SAK checking
1313 * here because otherwise the break
1314 * may get masked by ignore_status_mask
1315 * or read_status_mask.
1317 if (uart_handle_break(&up->port))
1319 } else if (lsr & UART_LSR_PE)
1320 up->port.icount.parity++;
1321 else if (lsr & UART_LSR_FE)
1322 up->port.icount.frame++;
1323 if (lsr & UART_LSR_OE)
1324 up->port.icount.overrun++;
1327 * Mask off conditions which should be ignored.
1329 lsr &= up->port.read_status_mask;
1331 if (lsr & UART_LSR_BI) {
1332 DEBUG_INTR("handling break....");
1334 } else if (lsr & UART_LSR_PE)
1336 else if (lsr & UART_LSR_FE)
1339 if (uart_handle_sysrq_char(&up->port, ch))
1342 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1345 lsr = serial_inp(up, UART_LSR);
1346 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1347 spin_unlock(&up->port.lock);
1348 tty_flip_buffer_push(tty);
1349 spin_lock(&up->port.lock);
1353 static void transmit_chars(struct uart_8250_port *up)
1355 struct circ_buf *xmit = &up->port.info->xmit;
1358 if (up->port.x_char) {
1359 serial_outp(up, UART_TX, up->port.x_char);
1360 up->port.icount.tx++;
1361 up->port.x_char = 0;
1364 if (uart_tx_stopped(&up->port)) {
1365 serial8250_stop_tx(&up->port);
1368 if (uart_circ_empty(xmit)) {
1373 count = up->tx_loadsz;
1375 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1376 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1377 up->port.icount.tx++;
1378 if (uart_circ_empty(xmit))
1380 } while (--count > 0);
1382 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1383 uart_write_wakeup(&up->port);
1385 DEBUG_INTR("THRE...");
1387 if (uart_circ_empty(xmit))
1391 static unsigned int check_modem_status(struct uart_8250_port *up)
1393 unsigned int status = serial_in(up, UART_MSR);
1395 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1396 up->port.info != NULL) {
1397 if (status & UART_MSR_TERI)
1398 up->port.icount.rng++;
1399 if (status & UART_MSR_DDSR)
1400 up->port.icount.dsr++;
1401 if (status & UART_MSR_DDCD)
1402 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1403 if (status & UART_MSR_DCTS)
1404 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1406 wake_up_interruptible(&up->port.info->delta_msr_wait);
1413 * This handles the interrupt from one port.
1416 serial8250_handle_port(struct uart_8250_port *up)
1418 unsigned int status;
1419 unsigned long flags;
1421 spin_lock_irqsave(&up->port.lock, flags);
1423 status = serial_inp(up, UART_LSR);
1425 DEBUG_INTR("status = %x...", status);
1427 if (status & UART_LSR_DR)
1428 receive_chars(up, &status);
1429 check_modem_status(up);
1430 if (status & UART_LSR_THRE)
1433 spin_unlock_irqrestore(&up->port.lock, flags);
1437 * This is the serial driver's interrupt routine.
1439 * Arjan thinks the old way was overly complex, so it got simplified.
1440 * Alan disagrees, saying that need the complexity to handle the weird
1441 * nature of ISA shared interrupts. (This is a special exception.)
1443 * In order to handle ISA shared interrupts properly, we need to check
1444 * that all ports have been serviced, and therefore the ISA interrupt
1445 * line has been de-asserted.
1447 * This means we need to loop through all ports. checking that they
1448 * don't have an interrupt pending.
1450 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1452 struct irq_info *i = dev_id;
1453 struct list_head *l, *end = NULL;
1454 int pass_counter = 0, handled = 0;
1456 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1458 spin_lock(&i->lock);
1462 struct uart_8250_port *up;
1465 up = list_entry(l, struct uart_8250_port, list);
1467 iir = serial_in(up, UART_IIR);
1468 if (!(iir & UART_IIR_NO_INT)) {
1469 serial8250_handle_port(up);
1474 } else if (up->port.iotype == UPIO_DWAPB &&
1475 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1476 /* The DesignWare APB UART has an Busy Detect (0x07)
1477 * interrupt meaning an LCR write attempt occured while the
1478 * UART was busy. The interrupt must be cleared by reading
1479 * the UART status register (USR) and the LCR re-written. */
1480 unsigned int status;
1481 status = *(volatile u32 *)up->port.private_data;
1482 serial_out(up, UART_LCR, up->lcr);
1487 } else if (end == NULL)
1492 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1493 /* If we hit this, we're dead. */
1494 printk(KERN_ERR "serial8250: too much work for "
1500 spin_unlock(&i->lock);
1502 DEBUG_INTR("end.\n");
1504 #ifdef CONFIG_ARCH_OMAP15XX
1505 return IRQ_HANDLED; /* FIXME: iir status not ready on 1510 */
1507 return IRQ_RETVAL(handled);
1512 * To support ISA shared interrupts, we need to have one interrupt
1513 * handler that ensures that the IRQ line has been deasserted
1514 * before returning. Failing to do this will result in the IRQ
1515 * line being stuck active, and, since ISA irqs are edge triggered,
1516 * no more IRQs will be seen.
1518 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1520 spin_lock_irq(&i->lock);
1522 if (!list_empty(i->head)) {
1523 if (i->head == &up->list)
1524 i->head = i->head->next;
1525 list_del(&up->list);
1527 BUG_ON(i->head != &up->list);
1531 spin_unlock_irq(&i->lock);
1534 static int serial_link_irq_chain(struct uart_8250_port *up)
1536 struct irq_info *i = irq_lists + up->port.irq;
1537 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1539 spin_lock_irq(&i->lock);
1542 list_add(&up->list, i->head);
1543 spin_unlock_irq(&i->lock);
1547 INIT_LIST_HEAD(&up->list);
1548 i->head = &up->list;
1549 spin_unlock_irq(&i->lock);
1551 ret = request_irq(up->port.irq, serial8250_interrupt,
1552 irq_flags, "serial", i);
1554 serial_do_unlink(i, up);
1560 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1562 struct irq_info *i = irq_lists + up->port.irq;
1564 BUG_ON(i->head == NULL);
1566 if (list_empty(i->head))
1567 free_irq(up->port.irq, i);
1569 serial_do_unlink(i, up);
1572 /* Base timer interval for polling */
1573 static inline int poll_timeout(int timeout)
1575 return timeout > 6 ? (timeout / 2 - 2) : 1;
1579 * This function is used to handle ports that do not have an
1580 * interrupt. This doesn't work very well for 16450's, but gives
1581 * barely passable results for a 16550A. (Although at the expense
1582 * of much CPU overhead).
1584 static void serial8250_timeout(unsigned long data)
1586 struct uart_8250_port *up = (struct uart_8250_port *)data;
1589 iir = serial_in(up, UART_IIR);
1590 if (!(iir & UART_IIR_NO_INT))
1591 serial8250_handle_port(up);
1592 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1595 static void serial8250_backup_timeout(unsigned long data)
1597 struct uart_8250_port *up = (struct uart_8250_port *)data;
1598 unsigned int iir, ier = 0;
1601 * Must disable interrupts or else we risk racing with the interrupt
1604 if (is_real_interrupt(up->port.irq)) {
1605 ier = serial_in(up, UART_IER);
1606 serial_out(up, UART_IER, 0);
1609 iir = serial_in(up, UART_IIR);
1612 * This should be a safe test for anyone who doesn't trust the
1613 * IIR bits on their UART, but it's specifically designed for
1614 * the "Diva" UART used on the management processor on many HP
1615 * ia64 and parisc boxes.
1617 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1618 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1619 (serial_in(up, UART_LSR) & UART_LSR_THRE)) {
1620 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1621 iir |= UART_IIR_THRI;
1624 if (!(iir & UART_IIR_NO_INT))
1625 serial8250_handle_port(up);
1627 if (is_real_interrupt(up->port.irq))
1628 serial_out(up, UART_IER, ier);
1630 /* Standard timer interval plus 0.2s to keep the port running */
1631 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout) + HZ/5);
1634 static unsigned int serial8250_tx_empty(struct uart_port *port)
1636 struct uart_8250_port *up = (struct uart_8250_port *)port;
1637 unsigned long flags;
1640 spin_lock_irqsave(&up->port.lock, flags);
1641 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1642 spin_unlock_irqrestore(&up->port.lock, flags);
1647 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1649 struct uart_8250_port *up = (struct uart_8250_port *)port;
1650 unsigned int status;
1653 status = check_modem_status(up);
1656 if (status & UART_MSR_DCD)
1658 if (status & UART_MSR_RI)
1660 if (status & UART_MSR_DSR)
1662 if (status & UART_MSR_CTS)
1667 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1669 struct uart_8250_port *up = (struct uart_8250_port *)port;
1670 unsigned char mcr = 0;
1672 if (mctrl & TIOCM_RTS)
1673 mcr |= UART_MCR_RTS;
1674 if (mctrl & TIOCM_DTR)
1675 mcr |= UART_MCR_DTR;
1676 if (mctrl & TIOCM_OUT1)
1677 mcr |= UART_MCR_OUT1;
1678 if (mctrl & TIOCM_OUT2)
1679 mcr |= UART_MCR_OUT2;
1680 if (mctrl & TIOCM_LOOP)
1681 mcr |= UART_MCR_LOOP;
1683 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1685 serial_out(up, UART_MCR, mcr);
1688 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1690 struct uart_8250_port *up = (struct uart_8250_port *)port;
1691 unsigned long flags;
1693 spin_lock_irqsave(&up->port.lock, flags);
1694 if (break_state == -1)
1695 up->lcr |= UART_LCR_SBC;
1697 up->lcr &= ~UART_LCR_SBC;
1698 serial_out(up, UART_LCR, up->lcr);
1699 spin_unlock_irqrestore(&up->port.lock, flags);
1702 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1705 * Wait for transmitter & holding register to empty
1707 static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1709 unsigned int status, tmout = 10000;
1711 /* Wait up to 10ms for the character(s) to be sent. */
1713 status = serial_in(up, UART_LSR);
1715 if (status & UART_LSR_BI)
1716 up->lsr_break_flag = UART_LSR_BI;
1721 } while ((status & bits) != bits);
1723 /* Wait up to 1s for flow control if necessary */
1724 if (up->port.flags & UPF_CONS_FLOW) {
1726 while (!(serial_in(up, UART_MSR) & UART_MSR_CTS) && --tmout) {
1728 touch_nmi_watchdog();
1733 static int serial8250_startup(struct uart_port *port)
1735 struct uart_8250_port *up = (struct uart_8250_port *)port;
1736 unsigned long flags;
1737 unsigned char lsr, iir;
1740 up->capabilities = uart_config[up->port.type].flags;
1743 if (up->port.type == PORT_16C950) {
1744 /* Wake up and initialize UART */
1746 serial_outp(up, UART_LCR, 0xBF);
1747 serial_outp(up, UART_EFR, UART_EFR_ECB);
1748 serial_outp(up, UART_IER, 0);
1749 serial_outp(up, UART_LCR, 0);
1750 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1751 serial_outp(up, UART_LCR, 0xBF);
1752 serial_outp(up, UART_EFR, UART_EFR_ECB);
1753 serial_outp(up, UART_LCR, 0);
1756 #ifdef CONFIG_SERIAL_8250_RSA
1758 * If this is an RSA port, see if we can kick it up to the
1759 * higher speed clock.
1765 * Clear the FIFO buffers and disable them.
1766 * (they will be reenabled in set_termios())
1768 serial8250_clear_fifos(up);
1771 * Clear the interrupt registers.
1773 (void) serial_inp(up, UART_LSR);
1774 (void) serial_inp(up, UART_RX);
1775 (void) serial_inp(up, UART_IIR);
1776 (void) serial_inp(up, UART_MSR);
1779 * At this point, there's no way the LSR could still be 0xff;
1780 * if it is, then bail out, because there's likely no UART
1783 if (!(up->port.flags & UPF_BUGGY_UART) &&
1784 (serial_inp(up, UART_LSR) == 0xff)) {
1785 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1790 * For a XR16C850, we need to set the trigger levels
1792 if (up->port.type == PORT_16850) {
1795 serial_outp(up, UART_LCR, 0xbf);
1797 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1798 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1799 serial_outp(up, UART_TRG, UART_TRG_96);
1800 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1801 serial_outp(up, UART_TRG, UART_TRG_96);
1803 serial_outp(up, UART_LCR, 0);
1806 if (is_real_interrupt(up->port.irq)) {
1808 * Test for UARTs that do not reassert THRE when the
1809 * transmitter is idle and the interrupt has already
1810 * been cleared. Real 16550s should always reassert
1811 * this interrupt whenever the transmitter is idle and
1812 * the interrupt is enabled. Delays are necessary to
1813 * allow register changes to become visible.
1815 spin_lock_irqsave(&up->port.lock, flags);
1817 wait_for_xmitr(up, UART_LSR_THRE);
1818 serial_out_sync(up, UART_IER, UART_IER_THRI);
1819 udelay(1); /* allow THRE to set */
1820 serial_in(up, UART_IIR);
1821 serial_out(up, UART_IER, 0);
1822 serial_out_sync(up, UART_IER, UART_IER_THRI);
1823 udelay(1); /* allow a working UART time to re-assert THRE */
1824 iir = serial_in(up, UART_IIR);
1825 serial_out(up, UART_IER, 0);
1827 spin_unlock_irqrestore(&up->port.lock, flags);
1830 * If the interrupt is not reasserted, setup a timer to
1831 * kick the UART on a regular basis.
1833 if (iir & UART_IIR_NO_INT) {
1834 pr_debug("ttyS%d - using backup timer\n", port->line);
1835 up->timer.function = serial8250_backup_timeout;
1836 up->timer.data = (unsigned long)up;
1837 mod_timer(&up->timer, jiffies +
1838 poll_timeout(up->port.timeout) + HZ/5);
1843 * If the "interrupt" for this port doesn't correspond with any
1844 * hardware interrupt, we use a timer-based system. The original
1845 * driver used to do this with IRQ0.
1847 if (!is_real_interrupt(up->port.irq)) {
1848 up->timer.data = (unsigned long)up;
1849 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1851 retval = serial_link_irq_chain(up);
1857 * Now, initialize the UART
1859 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1861 spin_lock_irqsave(&up->port.lock, flags);
1862 if (up->port.flags & UPF_FOURPORT) {
1863 if (!is_real_interrupt(up->port.irq))
1864 up->port.mctrl |= TIOCM_OUT1;
1867 * Most PC uarts need OUT2 raised to enable interrupts.
1869 if (is_real_interrupt(up->port.irq))
1870 up->port.mctrl |= TIOCM_OUT2;
1872 serial8250_set_mctrl(&up->port, up->port.mctrl);
1875 * Do a quick test to see if we receive an
1876 * interrupt when we enable the TX irq.
1878 serial_outp(up, UART_IER, UART_IER_THRI);
1879 lsr = serial_in(up, UART_LSR);
1880 iir = serial_in(up, UART_IIR);
1881 serial_outp(up, UART_IER, 0);
1883 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1884 if (!(up->bugs & UART_BUG_TXEN)) {
1885 up->bugs |= UART_BUG_TXEN;
1886 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1890 up->bugs &= ~UART_BUG_TXEN;
1893 spin_unlock_irqrestore(&up->port.lock, flags);
1896 * Finally, enable interrupts. Note: Modem status interrupts
1897 * are set via set_termios(), which will be occurring imminently
1898 * anyway, so we don't enable them here.
1900 up->ier = UART_IER_RLSI | UART_IER_RDI;
1901 serial_outp(up, UART_IER, up->ier);
1903 if (up->port.flags & UPF_FOURPORT) {
1906 * Enable interrupts on the AST Fourport board
1908 icp = (up->port.iobase & 0xfe0) | 0x01f;
1914 * And clear the interrupt registers again for luck.
1916 (void) serial_inp(up, UART_LSR);
1917 (void) serial_inp(up, UART_RX);
1918 (void) serial_inp(up, UART_IIR);
1919 (void) serial_inp(up, UART_MSR);
1924 static void serial8250_shutdown(struct uart_port *port)
1926 struct uart_8250_port *up = (struct uart_8250_port *)port;
1927 unsigned long flags;
1930 * Disable interrupts from this port
1933 serial_outp(up, UART_IER, 0);
1935 spin_lock_irqsave(&up->port.lock, flags);
1936 if (up->port.flags & UPF_FOURPORT) {
1937 /* reset interrupts on the AST Fourport board */
1938 inb((up->port.iobase & 0xfe0) | 0x1f);
1939 up->port.mctrl |= TIOCM_OUT1;
1941 up->port.mctrl &= ~TIOCM_OUT2;
1943 serial8250_set_mctrl(&up->port, up->port.mctrl);
1944 spin_unlock_irqrestore(&up->port.lock, flags);
1947 * Disable break condition and FIFOs
1949 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1950 serial8250_clear_fifos(up);
1952 #ifdef CONFIG_SERIAL_8250_RSA
1954 * Reset the RSA board back to 115kbps compat mode.
1960 * Read data port to reset things, and then unlink from
1963 (void) serial_in(up, UART_RX);
1965 del_timer_sync(&up->timer);
1966 up->timer.function = serial8250_timeout;
1967 if (is_real_interrupt(up->port.irq))
1968 serial_unlink_irq_chain(up);
1971 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1976 * Handle magic divisors for baud rates above baud_base on
1977 * SMSC SuperIO chips.
1979 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1980 baud == (port->uartclk/4))
1982 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1983 baud == (port->uartclk/8))
1986 quot = uart_get_divisor(port, baud);
1992 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
1993 struct ktermios *old)
1995 struct uart_8250_port *up = (struct uart_8250_port *)port;
1996 unsigned char cval, fcr = 0;
1997 unsigned long flags;
1998 unsigned int baud, quot;
2000 switch (termios->c_cflag & CSIZE) {
2002 cval = UART_LCR_WLEN5;
2005 cval = UART_LCR_WLEN6;
2008 cval = UART_LCR_WLEN7;
2012 cval = UART_LCR_WLEN8;
2016 if (termios->c_cflag & CSTOPB)
2017 cval |= UART_LCR_STOP;
2018 if (termios->c_cflag & PARENB)
2019 cval |= UART_LCR_PARITY;
2020 if (!(termios->c_cflag & PARODD))
2021 cval |= UART_LCR_EPAR;
2023 if (termios->c_cflag & CMSPAR)
2024 cval |= UART_LCR_SPAR;
2028 * Ask the core to calculate the divisor for us.
2030 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
2031 quot = serial8250_get_divisor(port, baud);
2034 * Oxford Semi 952 rev B workaround
2036 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2039 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2041 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2043 fcr = uart_config[up->port.type].fcr;
2047 * MCR-based auto flow control. When AFE is enabled, RTS will be
2048 * deasserted when the receive FIFO contains more characters than
2049 * the trigger, or the MCR RTS bit is cleared. In the case where
2050 * the remote UART is not using CTS auto flow control, we must
2051 * have sufficient FIFO entries for the latency of the remote
2052 * UART to respond. IOW, at least 32 bytes of FIFO.
2054 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2055 up->mcr &= ~UART_MCR_AFE;
2056 if (termios->c_cflag & CRTSCTS)
2057 up->mcr |= UART_MCR_AFE;
2061 * Ok, we're now changing the port state. Do it with
2062 * interrupts disabled.
2064 spin_lock_irqsave(&up->port.lock, flags);
2067 * Update the per-port timeout.
2069 uart_update_timeout(port, termios->c_cflag, baud);
2071 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2072 if (termios->c_iflag & INPCK)
2073 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2074 if (termios->c_iflag & (BRKINT | PARMRK))
2075 up->port.read_status_mask |= UART_LSR_BI;
2078 * Characteres to ignore
2080 up->port.ignore_status_mask = 0;
2081 if (termios->c_iflag & IGNPAR)
2082 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2083 if (termios->c_iflag & IGNBRK) {
2084 up->port.ignore_status_mask |= UART_LSR_BI;
2086 * If we're ignoring parity and break indicators,
2087 * ignore overruns too (for real raw support).
2089 if (termios->c_iflag & IGNPAR)
2090 up->port.ignore_status_mask |= UART_LSR_OE;
2094 * ignore all characters if CREAD is not set
2096 if ((termios->c_cflag & CREAD) == 0)
2097 up->port.ignore_status_mask |= UART_LSR_DR;
2100 * CTS flow control flag and modem status interrupts
2102 up->ier &= ~UART_IER_MSI;
2103 if (!(up->bugs & UART_BUG_NOMSR) &&
2104 UART_ENABLE_MS(&up->port, termios->c_cflag))
2105 up->ier |= UART_IER_MSI;
2106 if (up->capabilities & UART_CAP_UUE)
2107 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2109 serial_out(up, UART_IER, up->ier);
2111 if (up->capabilities & UART_CAP_EFR) {
2112 unsigned char efr = 0;
2114 * TI16C752/Startech hardware flow control. FIXME:
2115 * - TI16C752 requires control thresholds to be set.
2116 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2118 if (termios->c_cflag & CRTSCTS)
2119 efr |= UART_EFR_CTS;
2121 serial_outp(up, UART_LCR, 0xBF);
2122 serial_outp(up, UART_EFR, efr);
2125 #ifdef CONFIG_ARCH_OMAP15XX
2126 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2127 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
2128 if (baud == 115200) {
2130 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2132 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2136 if (up->capabilities & UART_NATSEMI) {
2137 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2138 serial_outp(up, UART_LCR, 0xe0);
2140 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2143 serial_dl_write(up, quot);
2146 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2147 * is written without DLAB set, this mode will be disabled.
2149 if (up->port.type == PORT_16750)
2150 serial_outp(up, UART_FCR, fcr);
2152 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2153 up->lcr = cval; /* Save LCR */
2154 if (up->port.type != PORT_16750) {
2155 if (fcr & UART_FCR_ENABLE_FIFO) {
2156 /* emulated UARTs (Lucent Venus 167x) need two steps */
2157 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2160 /* Note that we need to set ECB to access write water mark
2161 * bits. First allow FCR tx fifo write, then set fcr with
2162 * possible TX fifo settings. */
2163 if (uart_config[up->port.type].flags & UART_CAP_EFR) {
2164 serial_outp(up, UART_LCR, 0xbf); /* Access EFR */
2165 serial_outp(up, UART_EFR, UART_EFR_ECB);
2166 serial_outp(up, UART_LCR, 0x0); /* Access FCR */
2167 serial_outp(up, UART_FCR, fcr);
2168 serial_outp(up, UART_LCR, 0xbf); /* Access EFR */
2169 serial_outp(up, UART_EFR, 0);
2170 serial_outp(up, UART_LCR, cval); /* Access FCR */
2172 serial_outp(up, UART_FCR, fcr); /* set fcr */
2174 serial8250_set_mctrl(&up->port, up->port.mctrl);
2175 spin_unlock_irqrestore(&up->port.lock, flags);
2179 serial8250_pm(struct uart_port *port, unsigned int state,
2180 unsigned int oldstate)
2182 struct uart_8250_port *p = (struct uart_8250_port *)port;
2184 serial8250_set_sleep(p, state != 0);
2187 p->pm(port, state, oldstate);
2191 * Resource handling.
2193 static int serial8250_request_std_resource(struct uart_8250_port *up)
2195 unsigned int size = 8 << up->port.regshift;
2198 #ifdef CONFIG_ARCH_OMAP
2199 if (is_omap_port((unsigned int)up->port.membase))
2200 size = 0x16 << up->port.regshift;
2203 switch (up->port.iotype) {
2211 if (!up->port.mapbase)
2214 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2219 if (up->port.flags & UPF_IOREMAP) {
2220 up->port.membase = ioremap(up->port.mapbase, size);
2221 if (!up->port.membase) {
2222 release_mem_region(up->port.mapbase, size);
2230 if (!request_region(up->port.iobase, size, "serial"))
2237 static void serial8250_release_std_resource(struct uart_8250_port *up)
2239 unsigned int size = 8 << up->port.regshift;
2241 switch (up->port.iotype) {
2249 if (!up->port.mapbase)
2252 if (up->port.flags & UPF_IOREMAP) {
2253 iounmap(up->port.membase);
2254 up->port.membase = NULL;
2257 release_mem_region(up->port.mapbase, size);
2262 release_region(up->port.iobase, size);
2267 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2269 unsigned long start = UART_RSA_BASE << up->port.regshift;
2270 unsigned int size = 8 << up->port.regshift;
2273 switch (up->port.iotype) {
2276 start += up->port.iobase;
2277 if (request_region(start, size, "serial-rsa"))
2287 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2289 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2290 unsigned int size = 8 << up->port.regshift;
2292 switch (up->port.iotype) {
2295 release_region(up->port.iobase + offset, size);
2300 static void serial8250_release_port(struct uart_port *port)
2302 struct uart_8250_port *up = (struct uart_8250_port *)port;
2304 serial8250_release_std_resource(up);
2305 if (up->port.type == PORT_RSA)
2306 serial8250_release_rsa_resource(up);
2309 static int serial8250_request_port(struct uart_port *port)
2311 struct uart_8250_port *up = (struct uart_8250_port *)port;
2314 ret = serial8250_request_std_resource(up);
2315 if (ret == 0 && up->port.type == PORT_RSA) {
2316 ret = serial8250_request_rsa_resource(up);
2318 serial8250_release_std_resource(up);
2324 static void serial8250_config_port(struct uart_port *port, int flags)
2326 struct uart_8250_port *up = (struct uart_8250_port *)port;
2327 int probeflags = PROBE_ANY;
2331 * Find the region that we can probe for. This in turn
2332 * tells us whether we can probe for the type of port.
2334 ret = serial8250_request_std_resource(up);
2338 ret = serial8250_request_rsa_resource(up);
2340 probeflags &= ~PROBE_RSA;
2342 if (flags & UART_CONFIG_TYPE)
2343 autoconfig(up, probeflags);
2344 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2347 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2348 serial8250_release_rsa_resource(up);
2349 if (up->port.type == PORT_UNKNOWN)
2350 serial8250_release_std_resource(up);
2354 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2356 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2357 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2358 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2359 ser->type == PORT_STARTECH)
2365 serial8250_type(struct uart_port *port)
2367 int type = port->type;
2369 if (type >= ARRAY_SIZE(uart_config))
2371 return uart_config[type].name;
2374 static struct uart_ops serial8250_pops = {
2375 .tx_empty = serial8250_tx_empty,
2376 .set_mctrl = serial8250_set_mctrl,
2377 .get_mctrl = serial8250_get_mctrl,
2378 .stop_tx = serial8250_stop_tx,
2379 .start_tx = serial8250_start_tx,
2380 .stop_rx = serial8250_stop_rx,
2381 .enable_ms = serial8250_enable_ms,
2382 .break_ctl = serial8250_break_ctl,
2383 .startup = serial8250_startup,
2384 .shutdown = serial8250_shutdown,
2385 .set_termios = serial8250_set_termios,
2386 .pm = serial8250_pm,
2387 .type = serial8250_type,
2388 .release_port = serial8250_release_port,
2389 .request_port = serial8250_request_port,
2390 .config_port = serial8250_config_port,
2391 .verify_port = serial8250_verify_port,
2394 static struct uart_8250_port serial8250_ports[UART_NR];
2396 static void __init serial8250_isa_init_ports(void)
2398 struct uart_8250_port *up;
2399 static int first = 1;
2406 for (i = 0; i < nr_uarts; i++) {
2407 struct uart_8250_port *up = &serial8250_ports[i];
2410 spin_lock_init(&up->port.lock);
2412 init_timer(&up->timer);
2413 up->timer.function = serial8250_timeout;
2416 * ALPHA_KLUDGE_MCR needs to be killed.
2418 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2419 up->mcr_force = ALPHA_KLUDGE_MCR;
2421 up->port.ops = &serial8250_pops;
2424 for (i = 0, up = serial8250_ports;
2425 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2427 up->port.iobase = old_serial_port[i].port;
2428 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2429 up->port.uartclk = old_serial_port[i].baud_base * 16;
2430 up->port.flags = old_serial_port[i].flags;
2431 up->port.hub6 = old_serial_port[i].hub6;
2432 up->port.membase = old_serial_port[i].iomem_base;
2433 up->port.iotype = old_serial_port[i].io_type;
2434 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2436 up->port.flags |= UPF_SHARE_IRQ;
2441 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2445 serial8250_isa_init_ports();
2447 for (i = 0; i < nr_uarts; i++) {
2448 struct uart_8250_port *up = &serial8250_ports[i];
2451 uart_add_one_port(drv, &up->port);
2455 #ifdef CONFIG_SERIAL_8250_CONSOLE
2457 static void serial8250_console_putchar(struct uart_port *port, int ch)
2459 struct uart_8250_port *up = (struct uart_8250_port *)port;
2461 wait_for_xmitr(up, UART_LSR_THRE);
2462 serial_out(up, UART_TX, ch);
2466 * Print a string to the serial port trying not to disturb
2467 * any possible real use of the port...
2469 * The console_lock must be held when we get here.
2472 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2474 struct uart_8250_port *up = &serial8250_ports[co->index];
2475 unsigned long flags;
2479 touch_nmi_watchdog();
2481 local_irq_save(flags);
2482 if (up->port.sysrq) {
2483 /* serial8250_handle_port() already took the lock */
2485 } else if (oops_in_progress) {
2486 locked = spin_trylock(&up->port.lock);
2488 spin_lock(&up->port.lock);
2491 * First save the IER then disable the interrupts
2493 ier = serial_in(up, UART_IER);
2495 if (up->capabilities & UART_CAP_UUE)
2496 serial_out(up, UART_IER, UART_IER_UUE);
2498 serial_out(up, UART_IER, 0);
2500 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2503 * Finally, wait for transmitter to become empty
2504 * and restore the IER
2506 wait_for_xmitr(up, BOTH_EMPTY);
2507 serial_out(up, UART_IER, ier);
2510 spin_unlock(&up->port.lock);
2511 local_irq_restore(flags);
2514 static int __init serial8250_console_setup(struct console *co, char *options)
2516 struct uart_port *port;
2523 * Check whether an invalid uart number has been specified, and
2524 * if so, search for the first available port that does have
2527 if (co->index >= nr_uarts)
2529 port = &serial8250_ports[co->index].port;
2530 if (!port->iobase && !port->membase)
2534 uart_parse_options(options, &baud, &parity, &bits, &flow);
2536 return uart_set_options(port, co, baud, parity, bits, flow);
2539 static int serial8250_console_early_setup(void)
2541 return serial8250_find_port_for_earlycon();
2544 static struct uart_driver serial8250_reg;
2545 static struct console serial8250_console = {
2547 .write = serial8250_console_write,
2548 .device = uart_console_device,
2549 .setup = serial8250_console_setup,
2550 .early_setup = serial8250_console_early_setup,
2551 .flags = CON_PRINTBUFFER,
2553 .data = &serial8250_reg,
2556 static int __init serial8250_console_init(void)
2558 serial8250_isa_init_ports();
2559 register_console(&serial8250_console);
2562 console_initcall(serial8250_console_init);
2564 int serial8250_find_port(struct uart_port *p)
2567 struct uart_port *port;
2569 for (line = 0; line < nr_uarts; line++) {
2570 port = &serial8250_ports[line].port;
2571 if (uart_match_port(p, port))
2577 #define SERIAL8250_CONSOLE &serial8250_console
2579 #define SERIAL8250_CONSOLE NULL
2582 static struct uart_driver serial8250_reg = {
2583 .owner = THIS_MODULE,
2584 .driver_name = "serial",
2589 .cons = SERIAL8250_CONSOLE,
2593 * early_serial_setup - early registration for 8250 ports
2595 * Setup an 8250 port structure prior to console initialisation. Use
2596 * after console initialisation will cause undefined behaviour.
2598 int __init early_serial_setup(struct uart_port *port)
2600 if (port->line >= ARRAY_SIZE(serial8250_ports))
2603 serial8250_isa_init_ports();
2604 serial8250_ports[port->line].port = *port;
2605 serial8250_ports[port->line].port.ops = &serial8250_pops;
2610 * serial8250_suspend_port - suspend one serial port
2611 * @line: serial line number
2613 * Suspend one serial port.
2615 void serial8250_suspend_port(int line)
2617 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2621 * serial8250_resume_port - resume one serial port
2622 * @line: serial line number
2624 * Resume one serial port.
2626 void serial8250_resume_port(int line)
2628 struct uart_8250_port *up = &serial8250_ports[line];
2630 if (up->capabilities & UART_NATSEMI) {
2633 /* Ensure it's still in high speed mode */
2634 serial_outp(up, UART_LCR, 0xE0);
2636 tmp = serial_in(up, 0x04); /* EXCR2 */
2637 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2638 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2639 serial_outp(up, 0x04, tmp);
2641 serial_outp(up, UART_LCR, 0);
2643 uart_resume_port(&serial8250_reg, &up->port);
2647 * Register a set of serial devices attached to a platform device. The
2648 * list is terminated with a zero flags entry, which means we expect
2649 * all entries to have at least UPF_BOOT_AUTOCONF set.
2651 static int __devinit serial8250_probe(struct platform_device *dev)
2653 struct plat_serial8250_port *p = dev->dev.platform_data;
2654 struct uart_port port;
2657 memset(&port, 0, sizeof(struct uart_port));
2659 for (i = 0; p && p->flags != 0; p++, i++) {
2660 port.iobase = p->iobase;
2661 port.membase = p->membase;
2663 port.uartclk = p->uartclk;
2664 port.regshift = p->regshift;
2665 port.iotype = p->iotype;
2666 port.flags = p->flags;
2667 port.mapbase = p->mapbase;
2668 port.hub6 = p->hub6;
2669 port.dev = &dev->dev;
2671 port.flags |= UPF_SHARE_IRQ;
2672 ret = serial8250_register_port(&port);
2674 dev_err(&dev->dev, "unable to register port at index %d "
2675 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2676 p->iobase, (unsigned long long)p->mapbase,
2684 * Remove serial ports registered against a platform device.
2686 static int __devexit serial8250_remove(struct platform_device *dev)
2690 for (i = 0; i < nr_uarts; i++) {
2691 struct uart_8250_port *up = &serial8250_ports[i];
2693 if (up->port.dev == &dev->dev)
2694 serial8250_unregister_port(i);
2699 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2703 for (i = 0; i < UART_NR; i++) {
2704 struct uart_8250_port *up = &serial8250_ports[i];
2706 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2707 uart_suspend_port(&serial8250_reg, &up->port);
2713 static int serial8250_resume(struct platform_device *dev)
2717 for (i = 0; i < UART_NR; i++) {
2718 struct uart_8250_port *up = &serial8250_ports[i];
2720 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2721 serial8250_resume_port(i);
2727 static struct platform_driver serial8250_isa_driver = {
2728 .probe = serial8250_probe,
2729 .remove = __devexit_p(serial8250_remove),
2730 .suspend = serial8250_suspend,
2731 .resume = serial8250_resume,
2733 .name = "serial8250",
2734 .owner = THIS_MODULE,
2739 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2740 * in the table in include/asm/serial.h
2742 static struct platform_device *serial8250_isa_devs;
2745 * serial8250_register_port and serial8250_unregister_port allows for
2746 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2747 * modems and PCI multiport cards.
2749 static DEFINE_MUTEX(serial_mutex);
2751 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2756 * First, find a port entry which matches.
2758 for (i = 0; i < nr_uarts; i++)
2759 if (uart_match_port(&serial8250_ports[i].port, port))
2760 return &serial8250_ports[i];
2763 * We didn't find a matching entry, so look for the first
2764 * free entry. We look for one which hasn't been previously
2765 * used (indicated by zero iobase).
2767 for (i = 0; i < nr_uarts; i++)
2768 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2769 serial8250_ports[i].port.iobase == 0)
2770 return &serial8250_ports[i];
2773 * That also failed. Last resort is to find any entry which
2774 * doesn't have a real port associated with it.
2776 for (i = 0; i < nr_uarts; i++)
2777 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2778 return &serial8250_ports[i];
2784 * serial8250_register_port - register a serial port
2785 * @port: serial port template
2787 * Configure the serial port specified by the request. If the
2788 * port exists and is in use, it is hung up and unregistered
2791 * The port is then probed and if necessary the IRQ is autodetected
2792 * If this fails an error is returned.
2794 * On success the port is ready to use and the line number is returned.
2796 int serial8250_register_port(struct uart_port *port)
2798 struct uart_8250_port *uart;
2801 if (port->uartclk == 0)
2804 mutex_lock(&serial_mutex);
2806 uart = serial8250_find_match_or_unused(port);
2808 uart_remove_one_port(&serial8250_reg, &uart->port);
2810 uart->port.iobase = port->iobase;
2811 uart->port.membase = port->membase;
2812 uart->port.irq = port->irq;
2813 uart->port.uartclk = port->uartclk;
2814 uart->port.fifosize = port->fifosize;
2815 uart->port.regshift = port->regshift;
2816 uart->port.iotype = port->iotype;
2817 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2818 uart->port.mapbase = port->mapbase;
2820 uart->port.dev = port->dev;
2822 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2824 ret = uart->port.line;
2826 mutex_unlock(&serial_mutex);
2830 EXPORT_SYMBOL(serial8250_register_port);
2833 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2834 * @line: serial line number
2836 * Remove one serial port. This may not be called from interrupt
2837 * context. We hand the port back to the our control.
2839 void serial8250_unregister_port(int line)
2841 struct uart_8250_port *uart = &serial8250_ports[line];
2843 mutex_lock(&serial_mutex);
2844 uart_remove_one_port(&serial8250_reg, &uart->port);
2845 if (serial8250_isa_devs) {
2846 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2847 uart->port.type = PORT_UNKNOWN;
2848 uart->port.dev = &serial8250_isa_devs->dev;
2849 uart_add_one_port(&serial8250_reg, &uart->port);
2851 uart->port.dev = NULL;
2853 mutex_unlock(&serial_mutex);
2855 EXPORT_SYMBOL(serial8250_unregister_port);
2857 static int __init serial8250_init(void)
2861 if (nr_uarts > UART_NR)
2864 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2865 "%d ports, IRQ sharing %sabled\n", nr_uarts,
2866 share_irqs ? "en" : "dis");
2868 for (i = 0; i < NR_IRQS; i++)
2869 spin_lock_init(&irq_lists[i].lock);
2871 ret = uart_register_driver(&serial8250_reg);
2875 serial8250_isa_devs = platform_device_alloc("serial8250",
2876 PLAT8250_DEV_LEGACY);
2877 if (!serial8250_isa_devs) {
2879 goto unreg_uart_drv;
2882 ret = platform_device_add(serial8250_isa_devs);
2886 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2888 ret = platform_driver_register(&serial8250_isa_driver);
2892 platform_device_del(serial8250_isa_devs);
2894 platform_device_put(serial8250_isa_devs);
2896 uart_unregister_driver(&serial8250_reg);
2901 static void __exit serial8250_exit(void)
2903 struct platform_device *isa_dev = serial8250_isa_devs;
2906 * This tells serial8250_unregister_port() not to re-register
2907 * the ports (thereby making serial8250_isa_driver permanently
2910 serial8250_isa_devs = NULL;
2912 platform_driver_unregister(&serial8250_isa_driver);
2913 platform_device_unregister(isa_dev);
2915 uart_unregister_driver(&serial8250_reg);
2918 module_init(serial8250_init);
2919 module_exit(serial8250_exit);
2921 EXPORT_SYMBOL(serial8250_suspend_port);
2922 EXPORT_SYMBOL(serial8250_resume_port);
2924 MODULE_LICENSE("GPL");
2925 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2927 module_param(share_irqs, uint, 0644);
2928 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2931 module_param(nr_uarts, uint, 0644);
2932 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2934 #ifdef CONFIG_SERIAL_8250_RSA
2935 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2936 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2938 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);