2 * linux/drivers/char/8250.c
4 * Driver for 8250/16550-type serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * A note about mapbase / membase
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
21 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/ioport.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_reg.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_8250.h>
39 #include <linux/nmi.h>
40 #include <linux/mutex.h>
49 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
50 * is unsafe when used on edge-triggered interrupts.
52 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
54 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
60 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
62 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
66 #define DEBUG_INTR(fmt...) printk(fmt)
68 #define DEBUG_INTR(fmt...) do { } while (0)
71 #define PASS_LIMIT 256
74 * We default to IRQ0 for the "no irq" hack. Some
75 * machine types want others as well - they're free
76 * to redefine this in their header file.
78 #define is_real_interrupt(irq) ((irq) != 0)
80 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
81 #define CONFIG_SERIAL_DETECT_IRQ 1
83 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
84 #define CONFIG_SERIAL_MANY_PORTS 1
88 * HUB6 is always on. This will be removed once the header
89 * files have been cleaned.
93 #include <asm/serial.h>
95 * SERIAL_PORT_DFNS tells us about built-in ports that have no
96 * standard enumeration mechanism. Platforms that can find all
97 * serial ports via mechanisms like ACPI or PCI need not supply it.
99 #ifndef SERIAL_PORT_DFNS
100 #define SERIAL_PORT_DFNS
103 static const struct old_serial_port old_serial_port[] = {
104 SERIAL_PORT_DFNS /* defined in asm/serial.h */
107 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
109 #ifdef CONFIG_SERIAL_8250_RSA
111 #define PORT_RSA_MAX 4
112 static unsigned long probe_rsa[PORT_RSA_MAX];
113 static unsigned int probe_rsa_count;
114 #endif /* CONFIG_SERIAL_8250_RSA */
116 struct uart_8250_port {
117 struct uart_port port;
118 struct timer_list timer; /* "no irq" timer */
119 struct list_head list; /* ports on this IRQ */
120 unsigned short capabilities; /* port capabilities */
121 unsigned short bugs; /* port bugs */
122 unsigned int tx_loadsz; /* transmit fifo load size */
127 unsigned char mcr_mask; /* mask of user bits */
128 unsigned char mcr_force; /* mask of forced bits */
131 * Some bits in registers are cleared on a read, so they must
132 * be saved whenever the register is read but the bits will not
133 * be immediately processed.
135 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
136 unsigned char lsr_saved_flags;
137 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
138 unsigned char msr_saved_flags;
141 * We provide a per-port pm hook.
143 void (*pm)(struct uart_port *port,
144 unsigned int state, unsigned int old);
149 struct list_head *head;
152 static struct irq_info irq_lists[NR_IRQS];
155 * Here we define the default xmit fifo size used for each type of UART.
157 static const struct serial8250_config uart_config[] = {
182 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
183 .flags = UART_CAP_FIFO,
194 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
200 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
202 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
208 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
210 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
218 .name = "16C950/954",
221 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
222 .flags = UART_CAP_FIFO,
228 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
230 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
244 .flags = UART_CAP_FIFO,
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .flags = UART_CAP_FIFO | UART_NATSEMI,
257 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
258 .flags = UART_CAP_FIFO | UART_CAP_UUE,
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
265 .flags = UART_CAP_FIFO,
269 #if defined (CONFIG_SERIAL_8250_AU1X00)
271 /* Au1x00 UART hardware has a weird register layout */
272 static const u8 au_io_in_map[] = {
282 static const u8 au_io_out_map[] = {
290 /* sane hardware needs no mapping */
291 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
293 if (up->port.iotype != UPIO_AU)
295 return au_io_in_map[offset];
298 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
300 if (up->port.iotype != UPIO_AU)
302 return au_io_out_map[offset];
305 #elif defined(CONFIG_SERIAL_8250_RM9K)
329 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
331 if (up->port.iotype != UPIO_RM9000)
333 return regmap_in[offset];
336 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
338 if (up->port.iotype != UPIO_RM9000)
340 return regmap_out[offset];
345 /* sane hardware needs no mapping */
346 #define map_8250_in_reg(up, offset) (offset)
347 #define map_8250_out_reg(up, offset) (offset)
351 static unsigned int serial_in(struct uart_8250_port *up, int offset)
354 offset = map_8250_in_reg(up, offset) << up->port.regshift;
356 switch (up->port.iotype) {
358 outb(up->port.hub6 - 1 + offset, up->port.iobase);
359 return inb(up->port.iobase + 1);
363 return readb(up->port.membase + offset);
367 return readl(up->port.membase + offset);
369 #ifdef CONFIG_SERIAL_8250_AU1X00
371 return __raw_readl(up->port.membase + offset);
375 if (offset == UART_IIR) {
376 tmp = readl(up->port.membase + (UART_IIR & ~3));
377 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
379 return readb(up->port.membase + offset);
382 return inb(up->port.iobase + offset);
387 serial_out(struct uart_8250_port *up, int offset, int value)
389 /* Save the offset before it's remapped */
390 int save_offset = offset;
391 offset = map_8250_out_reg(up, offset) << up->port.regshift;
393 switch (up->port.iotype) {
395 outb(up->port.hub6 - 1 + offset, up->port.iobase);
396 outb(value, up->port.iobase + 1);
400 writeb(value, up->port.membase + offset);
405 writel(value, up->port.membase + offset);
408 #ifdef CONFIG_SERIAL_8250_AU1X00
410 __raw_writel(value, up->port.membase + offset);
414 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
415 writeb(value, up->port.membase + offset);
419 /* Save the LCR value so it can be re-written when a
420 * Busy Detect interrupt occurs. */
421 if (save_offset == UART_LCR)
423 writeb(value, up->port.membase + offset);
424 /* Read the IER to ensure any interrupt is cleared before
425 * returning from ISR. */
426 if (save_offset == UART_TX || save_offset == UART_IER)
427 value = serial_in(up, UART_IER);
431 outb(value, up->port.iobase + offset);
436 serial_out_sync(struct uart_8250_port *up, int offset, int value)
438 switch (up->port.iotype) {
441 #ifdef CONFIG_SERIAL_8250_AU1X00
445 serial_out(up, offset, value);
446 serial_in(up, UART_LCR); /* safe, no side-effects */
449 serial_out(up, offset, value);
454 * We used to support using pause I/O for certain machines. We
455 * haven't supported this for a while, but just in case it's badly
456 * needed for certain old 386 machines, I've left these #define's
459 #define serial_inp(up, offset) serial_in(up, offset)
460 #define serial_outp(up, offset, value) serial_out(up, offset, value)
462 /* Uart divisor latch read */
463 static inline int _serial_dl_read(struct uart_8250_port *up)
465 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
468 /* Uart divisor latch write */
469 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
471 serial_outp(up, UART_DLL, value & 0xff);
472 serial_outp(up, UART_DLM, value >> 8 & 0xff);
475 #if defined(CONFIG_SERIAL_8250_AU1X00)
476 /* Au1x00 haven't got a standard divisor latch */
477 static int serial_dl_read(struct uart_8250_port *up)
479 if (up->port.iotype == UPIO_AU)
480 return __raw_readl(up->port.membase + 0x28);
482 return _serial_dl_read(up);
485 static void serial_dl_write(struct uart_8250_port *up, int value)
487 if (up->port.iotype == UPIO_AU)
488 __raw_writel(value, up->port.membase + 0x28);
490 _serial_dl_write(up, value);
492 #elif defined(CONFIG_SERIAL_8250_RM9K)
493 static int serial_dl_read(struct uart_8250_port *up)
495 return (up->port.iotype == UPIO_RM9000) ?
496 (((__raw_readl(up->port.membase + 0x10) << 8) |
497 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
501 static void serial_dl_write(struct uart_8250_port *up, int value)
503 if (up->port.iotype == UPIO_RM9000) {
504 __raw_writel(value, up->port.membase + 0x08);
505 __raw_writel(value >> 8, up->port.membase + 0x10);
507 _serial_dl_write(up, value);
511 #define serial_dl_read(up) _serial_dl_read(up)
512 #define serial_dl_write(up, value) _serial_dl_write(up, value)
518 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
520 serial_out(up, UART_SCR, offset);
521 serial_out(up, UART_ICR, value);
524 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
528 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
529 serial_out(up, UART_SCR, offset);
530 value = serial_in(up, UART_ICR);
531 serial_icr_write(up, UART_ACR, up->acr);
539 static inline void serial8250_clear_fifos(struct uart_8250_port *p)
541 if (p->capabilities & UART_CAP_FIFO) {
542 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
543 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
544 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
545 serial_outp(p, UART_FCR, 0);
550 * IER sleep support. UARTs which have EFRs need the "extended
551 * capability" bit enabled. Note that on XR16C850s, we need to
552 * reset LCR to write to IER.
554 static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
556 if (p->capabilities & UART_CAP_SLEEP) {
557 if (p->capabilities & UART_CAP_EFR) {
558 serial_outp(p, UART_LCR, 0xBF);
559 serial_outp(p, UART_EFR, UART_EFR_ECB);
560 serial_outp(p, UART_LCR, 0);
562 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
563 if (p->capabilities & UART_CAP_EFR) {
564 serial_outp(p, UART_LCR, 0xBF);
565 serial_outp(p, UART_EFR, 0);
566 serial_outp(p, UART_LCR, 0);
571 #ifdef CONFIG_SERIAL_8250_RSA
573 * Attempts to turn on the RSA FIFO. Returns zero on failure.
574 * We set the port uart clock rate if we succeed.
576 static int __enable_rsa(struct uart_8250_port *up)
581 mode = serial_inp(up, UART_RSA_MSR);
582 result = mode & UART_RSA_MSR_FIFO;
585 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
586 mode = serial_inp(up, UART_RSA_MSR);
587 result = mode & UART_RSA_MSR_FIFO;
591 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
596 static void enable_rsa(struct uart_8250_port *up)
598 if (up->port.type == PORT_RSA) {
599 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
600 spin_lock_irq(&up->port.lock);
602 spin_unlock_irq(&up->port.lock);
604 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
605 serial_outp(up, UART_RSA_FRR, 0);
610 * Attempts to turn off the RSA FIFO. Returns zero on failure.
611 * It is unknown why interrupts were disabled in here. However,
612 * the caller is expected to preserve this behaviour by grabbing
613 * the spinlock before calling this function.
615 static void disable_rsa(struct uart_8250_port *up)
620 if (up->port.type == PORT_RSA &&
621 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
622 spin_lock_irq(&up->port.lock);
624 mode = serial_inp(up, UART_RSA_MSR);
625 result = !(mode & UART_RSA_MSR_FIFO);
628 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
629 mode = serial_inp(up, UART_RSA_MSR);
630 result = !(mode & UART_RSA_MSR_FIFO);
634 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
635 spin_unlock_irq(&up->port.lock);
638 #endif /* CONFIG_SERIAL_8250_RSA */
641 * This is a quickie test to see how big the FIFO is.
642 * It doesn't work at all the time, more's the pity.
644 static int size_fifo(struct uart_8250_port *up)
646 unsigned char old_fcr, old_mcr, old_lcr;
647 unsigned short old_dl;
650 old_lcr = serial_inp(up, UART_LCR);
651 serial_outp(up, UART_LCR, 0);
652 old_fcr = serial_inp(up, UART_FCR);
653 old_mcr = serial_inp(up, UART_MCR);
654 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
655 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
656 serial_outp(up, UART_MCR, UART_MCR_LOOP);
657 serial_outp(up, UART_LCR, UART_LCR_DLAB);
658 old_dl = serial_dl_read(up);
659 serial_dl_write(up, 0x0001);
660 serial_outp(up, UART_LCR, 0x03);
661 for (count = 0; count < 256; count++)
662 serial_outp(up, UART_TX, count);
663 mdelay(20);/* FIXME - schedule_timeout */
664 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
665 (count < 256); count++)
666 serial_inp(up, UART_RX);
667 serial_outp(up, UART_FCR, old_fcr);
668 serial_outp(up, UART_MCR, old_mcr);
669 serial_outp(up, UART_LCR, UART_LCR_DLAB);
670 serial_dl_write(up, old_dl);
671 serial_outp(up, UART_LCR, old_lcr);
677 * Read UART ID using the divisor method - set DLL and DLM to zero
678 * and the revision will be in DLL and device type in DLM. We
679 * preserve the device state across this.
681 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
683 unsigned char old_dll, old_dlm, old_lcr;
686 old_lcr = serial_inp(p, UART_LCR);
687 serial_outp(p, UART_LCR, UART_LCR_DLAB);
689 old_dll = serial_inp(p, UART_DLL);
690 old_dlm = serial_inp(p, UART_DLM);
692 serial_outp(p, UART_DLL, 0);
693 serial_outp(p, UART_DLM, 0);
695 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
697 serial_outp(p, UART_DLL, old_dll);
698 serial_outp(p, UART_DLM, old_dlm);
699 serial_outp(p, UART_LCR, old_lcr);
705 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
706 * When this function is called we know it is at least a StarTech
707 * 16650 V2, but it might be one of several StarTech UARTs, or one of
708 * its clones. (We treat the broken original StarTech 16650 V1 as a
709 * 16550, and why not? Startech doesn't seem to even acknowledge its
712 * What evil have men's minds wrought...
714 static void autoconfig_has_efr(struct uart_8250_port *up)
716 unsigned int id1, id2, id3, rev;
719 * Everything with an EFR has SLEEP
721 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
724 * First we check to see if it's an Oxford Semiconductor UART.
726 * If we have to do this here because some non-National
727 * Semiconductor clone chips lock up if you try writing to the
728 * LSR register (which serial_icr_read does)
732 * Check for Oxford Semiconductor 16C950.
734 * EFR [4] must be set else this test fails.
736 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
737 * claims that it's needed for 952 dual UART's (which are not
738 * recommended for new designs).
741 serial_out(up, UART_LCR, 0xBF);
742 serial_out(up, UART_EFR, UART_EFR_ECB);
743 serial_out(up, UART_LCR, 0x00);
744 id1 = serial_icr_read(up, UART_ID1);
745 id2 = serial_icr_read(up, UART_ID2);
746 id3 = serial_icr_read(up, UART_ID3);
747 rev = serial_icr_read(up, UART_REV);
749 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
751 if (id1 == 0x16 && id2 == 0xC9 &&
752 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
753 up->port.type = PORT_16C950;
756 * Enable work around for the Oxford Semiconductor 952 rev B
757 * chip which causes it to seriously miscalculate baud rates
760 if (id3 == 0x52 && rev == 0x01)
761 up->bugs |= UART_BUG_QUOT;
766 * We check for a XR16C850 by setting DLL and DLM to 0, and then
767 * reading back DLL and DLM. The chip type depends on the DLM
769 * 0x10 - XR16C850 and the DLL contains the chip revision.
773 id1 = autoconfig_read_divisor_id(up);
774 DEBUG_AUTOCONF("850id=%04x ", id1);
777 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
778 up->port.type = PORT_16850;
783 * It wasn't an XR16C850.
785 * We distinguish between the '654 and the '650 by counting
786 * how many bytes are in the FIFO. I'm using this for now,
787 * since that's the technique that was sent to me in the
788 * serial driver update, but I'm not convinced this works.
789 * I've had problems doing this in the past. -TYT
791 if (size_fifo(up) == 64)
792 up->port.type = PORT_16654;
794 up->port.type = PORT_16650V2;
798 * We detected a chip without a FIFO. Only two fall into
799 * this category - the original 8250 and the 16450. The
800 * 16450 has a scratch register (accessible with LCR=0)
802 static void autoconfig_8250(struct uart_8250_port *up)
804 unsigned char scratch, status1, status2;
806 up->port.type = PORT_8250;
808 scratch = serial_in(up, UART_SCR);
809 serial_outp(up, UART_SCR, 0xa5);
810 status1 = serial_in(up, UART_SCR);
811 serial_outp(up, UART_SCR, 0x5a);
812 status2 = serial_in(up, UART_SCR);
813 serial_outp(up, UART_SCR, scratch);
815 if (status1 == 0xa5 && status2 == 0x5a)
816 up->port.type = PORT_16450;
819 static int broken_efr(struct uart_8250_port *up)
822 * Exar ST16C2550 "A2" devices incorrectly detect as
823 * having an EFR, and report an ID of 0x0201. See
824 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
826 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
833 * We know that the chip has FIFOs. Does it have an EFR? The
834 * EFR is located in the same register position as the IIR and
835 * we know the top two bits of the IIR are currently set. The
836 * EFR should contain zero. Try to read the EFR.
838 static void autoconfig_16550a(struct uart_8250_port *up)
840 unsigned char status1, status2;
841 unsigned int iersave;
843 up->port.type = PORT_16550A;
844 up->capabilities |= UART_CAP_FIFO;
847 * Check for presence of the EFR when DLAB is set.
848 * Only ST16C650V1 UARTs pass this test.
850 serial_outp(up, UART_LCR, UART_LCR_DLAB);
851 if (serial_in(up, UART_EFR) == 0) {
852 serial_outp(up, UART_EFR, 0xA8);
853 if (serial_in(up, UART_EFR) != 0) {
854 DEBUG_AUTOCONF("EFRv1 ");
855 up->port.type = PORT_16650;
856 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
858 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
860 serial_outp(up, UART_EFR, 0);
865 * Maybe it requires 0xbf to be written to the LCR.
866 * (other ST16C650V2 UARTs, TI16C752A, etc)
868 serial_outp(up, UART_LCR, 0xBF);
869 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
870 DEBUG_AUTOCONF("EFRv2 ");
871 autoconfig_has_efr(up);
876 * Check for a National Semiconductor SuperIO chip.
877 * Attempt to switch to bank 2, read the value of the LOOP bit
878 * from EXCR1. Switch back to bank 0, change it in MCR. Then
879 * switch back to bank 2, read it from EXCR1 again and check
880 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
882 serial_outp(up, UART_LCR, 0);
883 status1 = serial_in(up, UART_MCR);
884 serial_outp(up, UART_LCR, 0xE0);
885 status2 = serial_in(up, 0x02); /* EXCR1 */
887 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
888 serial_outp(up, UART_LCR, 0);
889 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
890 serial_outp(up, UART_LCR, 0xE0);
891 status2 = serial_in(up, 0x02); /* EXCR1 */
892 serial_outp(up, UART_LCR, 0);
893 serial_outp(up, UART_MCR, status1);
895 if ((status2 ^ status1) & UART_MCR_LOOP) {
898 serial_outp(up, UART_LCR, 0xE0);
900 quot = serial_dl_read(up);
903 status1 = serial_in(up, 0x04); /* EXCR2 */
904 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
905 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
906 serial_outp(up, 0x04, status1);
908 serial_dl_write(up, quot);
910 serial_outp(up, UART_LCR, 0);
912 up->port.uartclk = 921600*16;
913 up->port.type = PORT_NS16550A;
914 up->capabilities |= UART_NATSEMI;
920 * No EFR. Try to detect a TI16750, which only sets bit 5 of
921 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
922 * Try setting it with and without DLAB set. Cheap clones
923 * set bit 5 without DLAB set.
925 serial_outp(up, UART_LCR, 0);
926 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
927 status1 = serial_in(up, UART_IIR) >> 5;
928 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
929 serial_outp(up, UART_LCR, UART_LCR_DLAB);
930 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
931 status2 = serial_in(up, UART_IIR) >> 5;
932 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
933 serial_outp(up, UART_LCR, 0);
935 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
937 if (status1 == 6 && status2 == 7) {
938 up->port.type = PORT_16750;
939 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
944 * Try writing and reading the UART_IER_UUE bit (b6).
945 * If it works, this is probably one of the Xscale platform's
947 * We're going to explicitly set the UUE bit to 0 before
948 * trying to write and read a 1 just to make sure it's not
949 * already a 1 and maybe locked there before we even start start.
951 iersave = serial_in(up, UART_IER);
952 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
953 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
955 * OK it's in a known zero state, try writing and reading
956 * without disturbing the current state of the other bits.
958 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
959 if (serial_in(up, UART_IER) & UART_IER_UUE) {
962 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
964 DEBUG_AUTOCONF("Xscale ");
965 up->port.type = PORT_XSCALE;
966 up->capabilities |= UART_CAP_UUE;
971 * If we got here we couldn't force the IER_UUE bit to 0.
972 * Log it and continue.
974 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
976 serial_outp(up, UART_IER, iersave);
980 * This routine is called by rs_init() to initialize a specific serial
981 * port. It determines what type of UART chip this serial port is
982 * using: 8250, 16450, 16550, 16550A. The important question is
983 * whether or not this UART is a 16550A or not, since this will
984 * determine whether or not we can use its FIFO features or not.
986 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
988 unsigned char status1, scratch, scratch2, scratch3;
989 unsigned char save_lcr, save_mcr;
992 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
995 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
996 up->port.line, up->port.iobase, up->port.membase);
999 * We really do need global IRQs disabled here - we're going to
1000 * be frobbing the chips IRQ enable register to see if it exists.
1002 spin_lock_irqsave(&up->port.lock, flags);
1004 up->capabilities = 0;
1007 if (!(up->port.flags & UPF_BUGGY_UART)) {
1009 * Do a simple existence test first; if we fail this,
1010 * there's no point trying anything else.
1012 * 0x80 is used as a nonsense port to prevent against
1013 * false positives due to ISA bus float. The
1014 * assumption is that 0x80 is a non-existent port;
1015 * which should be safe since include/asm/io.h also
1016 * makes this assumption.
1018 * Note: this is safe as long as MCR bit 4 is clear
1019 * and the device is in "PC" mode.
1021 scratch = serial_inp(up, UART_IER);
1022 serial_outp(up, UART_IER, 0);
1027 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1028 * 16C754B) allow only to modify them if an EFR bit is set.
1030 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1031 serial_outp(up, UART_IER, 0x0F);
1035 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1036 serial_outp(up, UART_IER, scratch);
1037 if (scratch2 != 0 || scratch3 != 0x0F) {
1039 * We failed; there's nothing here
1041 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1042 scratch2, scratch3);
1047 save_mcr = serial_in(up, UART_MCR);
1048 save_lcr = serial_in(up, UART_LCR);
1051 * Check to see if a UART is really there. Certain broken
1052 * internal modems based on the Rockwell chipset fail this
1053 * test, because they apparently don't implement the loopback
1054 * test mode. So this test is skipped on the COM 1 through
1055 * COM 4 ports. This *should* be safe, since no board
1056 * manufacturer would be stupid enough to design a board
1057 * that conflicts with COM 1-4 --- we hope!
1059 if (!(up->port.flags & UPF_SKIP_TEST)) {
1060 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1061 status1 = serial_inp(up, UART_MSR) & 0xF0;
1062 serial_outp(up, UART_MCR, save_mcr);
1063 if (status1 != 0x90) {
1064 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1071 * We're pretty sure there's a port here. Lets find out what
1072 * type of port it is. The IIR top two bits allows us to find
1073 * out if it's 8250 or 16450, 16550, 16550A or later. This
1074 * determines what we test for next.
1076 * We also initialise the EFR (if any) to zero for later. The
1077 * EFR occupies the same register location as the FCR and IIR.
1079 serial_outp(up, UART_LCR, 0xBF);
1080 serial_outp(up, UART_EFR, 0);
1081 serial_outp(up, UART_LCR, 0);
1083 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1084 scratch = serial_in(up, UART_IIR) >> 6;
1086 DEBUG_AUTOCONF("iir=%d ", scratch);
1090 autoconfig_8250(up);
1093 up->port.type = PORT_UNKNOWN;
1096 up->port.type = PORT_16550;
1099 autoconfig_16550a(up);
1103 #ifdef CONFIG_SERIAL_8250_RSA
1105 * Only probe for RSA ports if we got the region.
1107 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1110 for (i = 0 ; i < probe_rsa_count; ++i) {
1111 if (probe_rsa[i] == up->port.iobase &&
1113 up->port.type = PORT_RSA;
1120 #ifdef CONFIG_SERIAL_8250_AU1X00
1121 /* if access method is AU, it is a 16550 with a quirk */
1122 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1123 up->bugs |= UART_BUG_NOMSR;
1126 serial_outp(up, UART_LCR, save_lcr);
1128 if (up->capabilities != uart_config[up->port.type].flags) {
1130 "ttyS%d: detected caps %08x should be %08x\n",
1131 up->port.line, up->capabilities,
1132 uart_config[up->port.type].flags);
1135 up->port.fifosize = uart_config[up->port.type].fifo_size;
1136 up->capabilities = uart_config[up->port.type].flags;
1137 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1139 if (up->port.type == PORT_UNKNOWN)
1145 #ifdef CONFIG_SERIAL_8250_RSA
1146 if (up->port.type == PORT_RSA)
1147 serial_outp(up, UART_RSA_FRR, 0);
1149 serial_outp(up, UART_MCR, save_mcr);
1150 serial8250_clear_fifos(up);
1151 serial_in(up, UART_RX);
1152 if (up->capabilities & UART_CAP_UUE)
1153 serial_outp(up, UART_IER, UART_IER_UUE);
1155 serial_outp(up, UART_IER, 0);
1158 spin_unlock_irqrestore(&up->port.lock, flags);
1159 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1162 static void autoconfig_irq(struct uart_8250_port *up)
1164 unsigned char save_mcr, save_ier;
1165 unsigned char save_ICP = 0;
1166 unsigned int ICP = 0;
1170 if (up->port.flags & UPF_FOURPORT) {
1171 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1172 save_ICP = inb_p(ICP);
1177 /* forget possible initially masked and pending IRQ */
1178 probe_irq_off(probe_irq_on());
1179 save_mcr = serial_inp(up, UART_MCR);
1180 save_ier = serial_inp(up, UART_IER);
1181 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1183 irqs = probe_irq_on();
1184 serial_outp(up, UART_MCR, 0);
1186 if (up->port.flags & UPF_FOURPORT) {
1187 serial_outp(up, UART_MCR,
1188 UART_MCR_DTR | UART_MCR_RTS);
1190 serial_outp(up, UART_MCR,
1191 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1193 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1194 (void)serial_inp(up, UART_LSR);
1195 (void)serial_inp(up, UART_RX);
1196 (void)serial_inp(up, UART_IIR);
1197 (void)serial_inp(up, UART_MSR);
1198 serial_outp(up, UART_TX, 0xFF);
1200 irq = probe_irq_off(irqs);
1202 serial_outp(up, UART_MCR, save_mcr);
1203 serial_outp(up, UART_IER, save_ier);
1205 if (up->port.flags & UPF_FOURPORT)
1206 outb_p(save_ICP, ICP);
1208 up->port.irq = (irq > 0) ? irq : 0;
1211 static inline void __stop_tx(struct uart_8250_port *p)
1213 if (p->ier & UART_IER_THRI) {
1214 p->ier &= ~UART_IER_THRI;
1215 serial_out(p, UART_IER, p->ier);
1219 static void serial8250_stop_tx(struct uart_port *port)
1221 struct uart_8250_port *up = (struct uart_8250_port *)port;
1226 * We really want to stop the transmitter from sending.
1228 if (up->port.type == PORT_16C950) {
1229 up->acr |= UART_ACR_TXDIS;
1230 serial_icr_write(up, UART_ACR, up->acr);
1234 static void transmit_chars(struct uart_8250_port *up);
1236 static void serial8250_start_tx(struct uart_port *port)
1238 struct uart_8250_port *up = (struct uart_8250_port *)port;
1240 if (!(up->ier & UART_IER_THRI)) {
1241 up->ier |= UART_IER_THRI;
1242 serial_out(up, UART_IER, up->ier);
1244 if (up->bugs & UART_BUG_TXEN) {
1245 unsigned char lsr, iir;
1246 lsr = serial_in(up, UART_LSR);
1247 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1248 iir = serial_in(up, UART_IIR) & 0x0f;
1249 if ((up->port.type == PORT_RM9000) ?
1250 (lsr & UART_LSR_THRE &&
1251 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1252 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
1258 * Re-enable the transmitter if we disabled it.
1260 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1261 up->acr &= ~UART_ACR_TXDIS;
1262 serial_icr_write(up, UART_ACR, up->acr);
1266 static void serial8250_stop_rx(struct uart_port *port)
1268 struct uart_8250_port *up = (struct uart_8250_port *)port;
1270 up->ier &= ~UART_IER_RLSI;
1271 up->port.read_status_mask &= ~UART_LSR_DR;
1272 serial_out(up, UART_IER, up->ier);
1275 static void serial8250_enable_ms(struct uart_port *port)
1277 struct uart_8250_port *up = (struct uart_8250_port *)port;
1279 /* no MSR capabilities */
1280 if (up->bugs & UART_BUG_NOMSR)
1283 up->ier |= UART_IER_MSI;
1284 serial_out(up, UART_IER, up->ier);
1288 receive_chars(struct uart_8250_port *up, unsigned int *status)
1290 struct tty_struct *tty = up->port.info->port.tty;
1291 unsigned char ch, lsr = *status;
1292 int max_count = 256;
1296 if (likely(lsr & UART_LSR_DR))
1297 ch = serial_inp(up, UART_RX);
1300 * Intel 82571 has a Serial Over Lan device that will
1301 * set UART_LSR_BI without setting UART_LSR_DR when
1302 * it receives a break. To avoid reading from the
1303 * receive buffer without UART_LSR_DR bit set, we
1304 * just force the read character to be 0
1309 up->port.icount.rx++;
1311 lsr |= up->lsr_saved_flags;
1312 up->lsr_saved_flags = 0;
1314 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1316 * For statistics only
1318 if (lsr & UART_LSR_BI) {
1319 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1320 up->port.icount.brk++;
1322 * We do the SysRQ and SAK checking
1323 * here because otherwise the break
1324 * may get masked by ignore_status_mask
1325 * or read_status_mask.
1327 if (uart_handle_break(&up->port))
1329 } else if (lsr & UART_LSR_PE)
1330 up->port.icount.parity++;
1331 else if (lsr & UART_LSR_FE)
1332 up->port.icount.frame++;
1333 if (lsr & UART_LSR_OE)
1334 up->port.icount.overrun++;
1337 * Mask off conditions which should be ignored.
1339 lsr &= up->port.read_status_mask;
1341 if (lsr & UART_LSR_BI) {
1342 DEBUG_INTR("handling break....");
1344 } else if (lsr & UART_LSR_PE)
1346 else if (lsr & UART_LSR_FE)
1349 if (uart_handle_sysrq_char(&up->port, ch))
1352 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1355 lsr = serial_inp(up, UART_LSR);
1356 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1357 spin_unlock(&up->port.lock);
1358 tty_flip_buffer_push(tty);
1359 spin_lock(&up->port.lock);
1363 static void transmit_chars(struct uart_8250_port *up)
1365 struct circ_buf *xmit = &up->port.info->xmit;
1368 if (up->port.x_char) {
1369 serial_outp(up, UART_TX, up->port.x_char);
1370 up->port.icount.tx++;
1371 up->port.x_char = 0;
1374 if (uart_tx_stopped(&up->port)) {
1375 serial8250_stop_tx(&up->port);
1378 if (uart_circ_empty(xmit)) {
1383 count = up->tx_loadsz;
1385 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1386 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1387 up->port.icount.tx++;
1388 if (uart_circ_empty(xmit))
1390 } while (--count > 0);
1392 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1393 uart_write_wakeup(&up->port);
1395 DEBUG_INTR("THRE...");
1397 if (uart_circ_empty(xmit))
1401 static unsigned int check_modem_status(struct uart_8250_port *up)
1403 unsigned int status = serial_in(up, UART_MSR);
1405 status |= up->msr_saved_flags;
1406 up->msr_saved_flags = 0;
1407 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1408 up->port.info != NULL) {
1409 if (status & UART_MSR_TERI)
1410 up->port.icount.rng++;
1411 if (status & UART_MSR_DDSR)
1412 up->port.icount.dsr++;
1413 if (status & UART_MSR_DDCD)
1414 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1415 if (status & UART_MSR_DCTS)
1416 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1418 wake_up_interruptible(&up->port.info->delta_msr_wait);
1425 * This handles the interrupt from one port.
1428 serial8250_handle_port(struct uart_8250_port *up)
1430 unsigned int status;
1431 unsigned long flags;
1433 spin_lock_irqsave(&up->port.lock, flags);
1435 status = serial_inp(up, UART_LSR);
1437 DEBUG_INTR("status = %x...", status);
1439 if (status & (UART_LSR_DR | UART_LSR_BI))
1440 receive_chars(up, &status);
1441 check_modem_status(up);
1442 if (status & UART_LSR_THRE)
1445 spin_unlock_irqrestore(&up->port.lock, flags);
1449 * This is the serial driver's interrupt routine.
1451 * Arjan thinks the old way was overly complex, so it got simplified.
1452 * Alan disagrees, saying that need the complexity to handle the weird
1453 * nature of ISA shared interrupts. (This is a special exception.)
1455 * In order to handle ISA shared interrupts properly, we need to check
1456 * that all ports have been serviced, and therefore the ISA interrupt
1457 * line has been de-asserted.
1459 * This means we need to loop through all ports. checking that they
1460 * don't have an interrupt pending.
1462 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1464 struct irq_info *i = dev_id;
1465 struct list_head *l, *end = NULL;
1466 int pass_counter = 0, handled = 0;
1468 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1470 spin_lock(&i->lock);
1474 struct uart_8250_port *up;
1477 up = list_entry(l, struct uart_8250_port, list);
1479 iir = serial_in(up, UART_IIR);
1480 if (!(iir & UART_IIR_NO_INT)) {
1481 serial8250_handle_port(up);
1486 } else if (up->port.iotype == UPIO_DWAPB &&
1487 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1488 /* The DesignWare APB UART has an Busy Detect (0x07)
1489 * interrupt meaning an LCR write attempt occured while the
1490 * UART was busy. The interrupt must be cleared by reading
1491 * the UART status register (USR) and the LCR re-written. */
1492 unsigned int status;
1493 status = *(volatile u32 *)up->port.private_data;
1494 serial_out(up, UART_LCR, up->lcr);
1499 } else if (end == NULL)
1504 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1505 /* If we hit this, we're dead. */
1506 printk(KERN_ERR "serial8250: too much work for "
1512 spin_unlock(&i->lock);
1514 DEBUG_INTR("end.\n");
1516 #ifdef CONFIG_ARCH_OMAP15XX
1517 return IRQ_HANDLED; /* FIXME: iir status not ready on 1510 */
1519 return IRQ_RETVAL(handled);
1524 * To support ISA shared interrupts, we need to have one interrupt
1525 * handler that ensures that the IRQ line has been deasserted
1526 * before returning. Failing to do this will result in the IRQ
1527 * line being stuck active, and, since ISA irqs are edge triggered,
1528 * no more IRQs will be seen.
1530 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1532 spin_lock_irq(&i->lock);
1534 if (!list_empty(i->head)) {
1535 if (i->head == &up->list)
1536 i->head = i->head->next;
1537 list_del(&up->list);
1539 BUG_ON(i->head != &up->list);
1543 spin_unlock_irq(&i->lock);
1546 static int serial_link_irq_chain(struct uart_8250_port *up)
1548 struct irq_info *i = irq_lists + up->port.irq;
1549 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1551 spin_lock_irq(&i->lock);
1554 list_add(&up->list, i->head);
1555 spin_unlock_irq(&i->lock);
1559 INIT_LIST_HEAD(&up->list);
1560 i->head = &up->list;
1561 spin_unlock_irq(&i->lock);
1563 ret = request_irq(up->port.irq, serial8250_interrupt,
1564 irq_flags, "serial", i);
1566 serial_do_unlink(i, up);
1572 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1574 struct irq_info *i = irq_lists + up->port.irq;
1576 BUG_ON(i->head == NULL);
1578 if (list_empty(i->head))
1579 free_irq(up->port.irq, i);
1581 serial_do_unlink(i, up);
1584 /* Base timer interval for polling */
1585 static inline int poll_timeout(int timeout)
1587 return timeout > 6 ? (timeout / 2 - 2) : 1;
1591 * This function is used to handle ports that do not have an
1592 * interrupt. This doesn't work very well for 16450's, but gives
1593 * barely passable results for a 16550A. (Although at the expense
1594 * of much CPU overhead).
1596 static void serial8250_timeout(unsigned long data)
1598 struct uart_8250_port *up = (struct uart_8250_port *)data;
1601 iir = serial_in(up, UART_IIR);
1602 if (!(iir & UART_IIR_NO_INT))
1603 serial8250_handle_port(up);
1604 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1607 static void serial8250_backup_timeout(unsigned long data)
1609 struct uart_8250_port *up = (struct uart_8250_port *)data;
1610 unsigned int iir, ier = 0, lsr;
1611 unsigned long flags;
1614 * Must disable interrupts or else we risk racing with the interrupt
1617 if (is_real_interrupt(up->port.irq)) {
1618 ier = serial_in(up, UART_IER);
1619 serial_out(up, UART_IER, 0);
1622 iir = serial_in(up, UART_IIR);
1625 * This should be a safe test for anyone who doesn't trust the
1626 * IIR bits on their UART, but it's specifically designed for
1627 * the "Diva" UART used on the management processor on many HP
1628 * ia64 and parisc boxes.
1630 spin_lock_irqsave(&up->port.lock, flags);
1631 lsr = serial_in(up, UART_LSR);
1632 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1633 spin_unlock_irqrestore(&up->port.lock, flags);
1634 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1635 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1636 (lsr & UART_LSR_THRE)) {
1637 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1638 iir |= UART_IIR_THRI;
1641 if (!(iir & UART_IIR_NO_INT))
1642 serial8250_handle_port(up);
1644 if (is_real_interrupt(up->port.irq))
1645 serial_out(up, UART_IER, ier);
1647 /* Standard timer interval plus 0.2s to keep the port running */
1648 mod_timer(&up->timer,
1649 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1652 static unsigned int serial8250_tx_empty(struct uart_port *port)
1654 struct uart_8250_port *up = (struct uart_8250_port *)port;
1655 unsigned long flags;
1658 spin_lock_irqsave(&up->port.lock, flags);
1659 lsr = serial_in(up, UART_LSR);
1660 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1661 spin_unlock_irqrestore(&up->port.lock, flags);
1663 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1666 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1668 struct uart_8250_port *up = (struct uart_8250_port *)port;
1669 unsigned int status;
1672 status = check_modem_status(up);
1675 if (status & UART_MSR_DCD)
1677 if (status & UART_MSR_RI)
1679 if (status & UART_MSR_DSR)
1681 if (status & UART_MSR_CTS)
1686 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1688 struct uart_8250_port *up = (struct uart_8250_port *)port;
1689 unsigned char mcr = 0;
1691 if (mctrl & TIOCM_RTS)
1692 mcr |= UART_MCR_RTS;
1693 if (mctrl & TIOCM_DTR)
1694 mcr |= UART_MCR_DTR;
1695 if (mctrl & TIOCM_OUT1)
1696 mcr |= UART_MCR_OUT1;
1697 if (mctrl & TIOCM_OUT2)
1698 mcr |= UART_MCR_OUT2;
1699 if (mctrl & TIOCM_LOOP)
1700 mcr |= UART_MCR_LOOP;
1702 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1704 serial_out(up, UART_MCR, mcr);
1707 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1709 struct uart_8250_port *up = (struct uart_8250_port *)port;
1710 unsigned long flags;
1712 spin_lock_irqsave(&up->port.lock, flags);
1713 if (break_state == -1)
1714 up->lcr |= UART_LCR_SBC;
1716 up->lcr &= ~UART_LCR_SBC;
1717 serial_out(up, UART_LCR, up->lcr);
1718 spin_unlock_irqrestore(&up->port.lock, flags);
1721 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1724 * Wait for transmitter & holding register to empty
1726 static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1728 unsigned int status, tmout = 10000;
1730 /* Wait up to 10ms for the character(s) to be sent. */
1732 status = serial_in(up, UART_LSR);
1734 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1739 } while ((status & bits) != bits);
1741 /* Wait up to 1s for flow control if necessary */
1742 if (up->port.flags & UPF_CONS_FLOW) {
1744 for (tmout = 1000000; tmout; tmout--) {
1745 unsigned int msr = serial_in(up, UART_MSR);
1746 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1747 if (msr & UART_MSR_CTS)
1750 touch_nmi_watchdog();
1755 #ifdef CONFIG_CONSOLE_POLL
1757 * Console polling routines for writing and reading from the uart while
1758 * in an interrupt or debug context.
1761 static int serial8250_get_poll_char(struct uart_port *port)
1763 struct uart_8250_port *up = (struct uart_8250_port *)port;
1764 unsigned char lsr = serial_inp(up, UART_LSR);
1766 while (!(lsr & UART_LSR_DR))
1767 lsr = serial_inp(up, UART_LSR);
1769 return serial_inp(up, UART_RX);
1773 static void serial8250_put_poll_char(struct uart_port *port,
1777 struct uart_8250_port *up = (struct uart_8250_port *)port;
1780 * First save the IER then disable the interrupts
1782 ier = serial_in(up, UART_IER);
1783 if (up->capabilities & UART_CAP_UUE)
1784 serial_out(up, UART_IER, UART_IER_UUE);
1786 serial_out(up, UART_IER, 0);
1788 wait_for_xmitr(up, BOTH_EMPTY);
1790 * Send the character out.
1791 * If a LF, also do CR...
1793 serial_out(up, UART_TX, c);
1795 wait_for_xmitr(up, BOTH_EMPTY);
1796 serial_out(up, UART_TX, 13);
1800 * Finally, wait for transmitter to become empty
1801 * and restore the IER
1803 wait_for_xmitr(up, BOTH_EMPTY);
1804 serial_out(up, UART_IER, ier);
1807 #endif /* CONFIG_CONSOLE_POLL */
1809 static int serial8250_startup(struct uart_port *port)
1811 struct uart_8250_port *up = (struct uart_8250_port *)port;
1812 unsigned long flags;
1813 unsigned char lsr, iir;
1816 up->capabilities = uart_config[up->port.type].flags;
1819 if (up->port.type == PORT_16C950) {
1820 /* Wake up and initialize UART */
1822 serial_outp(up, UART_LCR, 0xBF);
1823 serial_outp(up, UART_EFR, UART_EFR_ECB);
1824 serial_outp(up, UART_IER, 0);
1825 serial_outp(up, UART_LCR, 0);
1826 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1827 serial_outp(up, UART_LCR, 0xBF);
1828 serial_outp(up, UART_EFR, UART_EFR_ECB);
1829 serial_outp(up, UART_LCR, 0);
1832 #ifdef CONFIG_SERIAL_8250_RSA
1834 * If this is an RSA port, see if we can kick it up to the
1835 * higher speed clock.
1841 * Clear the FIFO buffers and disable them.
1842 * (they will be reenabled in set_termios())
1844 serial8250_clear_fifos(up);
1847 * Clear the interrupt registers.
1849 (void) serial_inp(up, UART_LSR);
1850 (void) serial_inp(up, UART_RX);
1851 (void) serial_inp(up, UART_IIR);
1852 (void) serial_inp(up, UART_MSR);
1855 * At this point, there's no way the LSR could still be 0xff;
1856 * if it is, then bail out, because there's likely no UART
1859 if (!(up->port.flags & UPF_BUGGY_UART) &&
1860 (serial_inp(up, UART_LSR) == 0xff)) {
1861 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1866 * For a XR16C850, we need to set the trigger levels
1868 if (up->port.type == PORT_16850) {
1871 serial_outp(up, UART_LCR, 0xbf);
1873 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1874 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1875 serial_outp(up, UART_TRG, UART_TRG_96);
1876 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1877 serial_outp(up, UART_TRG, UART_TRG_96);
1879 serial_outp(up, UART_LCR, 0);
1882 if (is_real_interrupt(up->port.irq)) {
1885 * Test for UARTs that do not reassert THRE when the
1886 * transmitter is idle and the interrupt has already
1887 * been cleared. Real 16550s should always reassert
1888 * this interrupt whenever the transmitter is idle and
1889 * the interrupt is enabled. Delays are necessary to
1890 * allow register changes to become visible.
1892 spin_lock_irqsave(&up->port.lock, flags);
1893 if (up->port.flags & UPF_SHARE_IRQ)
1894 disable_irq_nosync(up->port.irq);
1896 wait_for_xmitr(up, UART_LSR_THRE);
1897 serial_out_sync(up, UART_IER, UART_IER_THRI);
1898 udelay(1); /* allow THRE to set */
1899 iir1 = serial_in(up, UART_IIR);
1900 serial_out(up, UART_IER, 0);
1901 serial_out_sync(up, UART_IER, UART_IER_THRI);
1902 udelay(1); /* allow a working UART time to re-assert THRE */
1903 iir = serial_in(up, UART_IIR);
1904 serial_out(up, UART_IER, 0);
1906 if (up->port.flags & UPF_SHARE_IRQ)
1907 enable_irq(up->port.irq);
1908 spin_unlock_irqrestore(&up->port.lock, flags);
1911 * If the interrupt is not reasserted, setup a timer to
1912 * kick the UART on a regular basis.
1914 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
1915 up->bugs |= UART_BUG_THRE;
1916 pr_debug("ttyS%d - using backup timer\n", port->line);
1921 * The above check will only give an accurate result the first time
1922 * the port is opened so this value needs to be preserved.
1924 if (up->bugs & UART_BUG_THRE) {
1925 up->timer.function = serial8250_backup_timeout;
1926 up->timer.data = (unsigned long)up;
1927 mod_timer(&up->timer, jiffies +
1928 poll_timeout(up->port.timeout) + HZ / 5);
1932 * If the "interrupt" for this port doesn't correspond with any
1933 * hardware interrupt, we use a timer-based system. The original
1934 * driver used to do this with IRQ0.
1936 if (!is_real_interrupt(up->port.irq)) {
1937 up->timer.data = (unsigned long)up;
1938 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1940 retval = serial_link_irq_chain(up);
1946 * Now, initialize the UART
1948 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1950 spin_lock_irqsave(&up->port.lock, flags);
1951 if (up->port.flags & UPF_FOURPORT) {
1952 if (!is_real_interrupt(up->port.irq))
1953 up->port.mctrl |= TIOCM_OUT1;
1956 * Most PC uarts need OUT2 raised to enable interrupts.
1958 if (is_real_interrupt(up->port.irq))
1959 up->port.mctrl |= TIOCM_OUT2;
1961 serial8250_set_mctrl(&up->port, up->port.mctrl);
1964 * Do a quick test to see if we receive an
1965 * interrupt when we enable the TX irq.
1967 serial_outp(up, UART_IER, UART_IER_THRI);
1968 lsr = serial_in(up, UART_LSR);
1969 iir = serial_in(up, UART_IIR);
1970 serial_outp(up, UART_IER, 0);
1972 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1973 if (!(up->bugs & UART_BUG_TXEN)) {
1974 up->bugs |= UART_BUG_TXEN;
1975 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1979 up->bugs &= ~UART_BUG_TXEN;
1982 spin_unlock_irqrestore(&up->port.lock, flags);
1985 * Clear the interrupt registers again for luck, and clear the
1986 * saved flags to avoid getting false values from polling
1987 * routines or the previous session.
1989 serial_inp(up, UART_LSR);
1990 serial_inp(up, UART_RX);
1991 serial_inp(up, UART_IIR);
1992 serial_inp(up, UART_MSR);
1993 up->lsr_saved_flags = 0;
1994 up->msr_saved_flags = 0;
1997 * Finally, enable interrupts. Note: Modem status interrupts
1998 * are set via set_termios(), which will be occurring imminently
1999 * anyway, so we don't enable them here.
2001 up->ier = UART_IER_RLSI | UART_IER_RDI;
2002 serial_outp(up, UART_IER, up->ier);
2004 if (up->port.flags & UPF_FOURPORT) {
2007 * Enable interrupts on the AST Fourport board
2009 icp = (up->port.iobase & 0xfe0) | 0x01f;
2017 static void serial8250_shutdown(struct uart_port *port)
2019 struct uart_8250_port *up = (struct uart_8250_port *)port;
2020 unsigned long flags;
2023 * Disable interrupts from this port
2026 serial_outp(up, UART_IER, 0);
2028 spin_lock_irqsave(&up->port.lock, flags);
2029 if (up->port.flags & UPF_FOURPORT) {
2030 /* reset interrupts on the AST Fourport board */
2031 inb((up->port.iobase & 0xfe0) | 0x1f);
2032 up->port.mctrl |= TIOCM_OUT1;
2034 up->port.mctrl &= ~TIOCM_OUT2;
2036 serial8250_set_mctrl(&up->port, up->port.mctrl);
2037 spin_unlock_irqrestore(&up->port.lock, flags);
2040 * Disable break condition and FIFOs
2042 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2043 serial8250_clear_fifos(up);
2045 #ifdef CONFIG_SERIAL_8250_RSA
2047 * Reset the RSA board back to 115kbps compat mode.
2053 * Read data port to reset things, and then unlink from
2056 (void) serial_in(up, UART_RX);
2058 del_timer_sync(&up->timer);
2059 up->timer.function = serial8250_timeout;
2060 if (is_real_interrupt(up->port.irq))
2061 serial_unlink_irq_chain(up);
2064 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2069 * Handle magic divisors for baud rates above baud_base on
2070 * SMSC SuperIO chips.
2072 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2073 baud == (port->uartclk/4))
2075 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2076 baud == (port->uartclk/8))
2079 quot = uart_get_divisor(port, baud);
2085 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2086 struct ktermios *old)
2088 struct uart_8250_port *up = (struct uart_8250_port *)port;
2089 unsigned char cval, fcr = 0;
2090 unsigned long flags;
2091 unsigned int baud, quot;
2093 switch (termios->c_cflag & CSIZE) {
2095 cval = UART_LCR_WLEN5;
2098 cval = UART_LCR_WLEN6;
2101 cval = UART_LCR_WLEN7;
2105 cval = UART_LCR_WLEN8;
2109 if (termios->c_cflag & CSTOPB)
2110 cval |= UART_LCR_STOP;
2111 if (termios->c_cflag & PARENB)
2112 cval |= UART_LCR_PARITY;
2113 if (!(termios->c_cflag & PARODD))
2114 cval |= UART_LCR_EPAR;
2116 if (termios->c_cflag & CMSPAR)
2117 cval |= UART_LCR_SPAR;
2121 * Ask the core to calculate the divisor for us.
2123 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
2124 quot = serial8250_get_divisor(port, baud);
2127 * Oxford Semi 952 rev B workaround
2129 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2132 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2134 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2136 fcr = uart_config[up->port.type].fcr;
2140 * MCR-based auto flow control. When AFE is enabled, RTS will be
2141 * deasserted when the receive FIFO contains more characters than
2142 * the trigger, or the MCR RTS bit is cleared. In the case where
2143 * the remote UART is not using CTS auto flow control, we must
2144 * have sufficient FIFO entries for the latency of the remote
2145 * UART to respond. IOW, at least 32 bytes of FIFO.
2147 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2148 up->mcr &= ~UART_MCR_AFE;
2149 if (termios->c_cflag & CRTSCTS)
2150 up->mcr |= UART_MCR_AFE;
2154 * Ok, we're now changing the port state. Do it with
2155 * interrupts disabled.
2157 spin_lock_irqsave(&up->port.lock, flags);
2160 * Update the per-port timeout.
2162 uart_update_timeout(port, termios->c_cflag, baud);
2164 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2165 if (termios->c_iflag & INPCK)
2166 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2167 if (termios->c_iflag & (BRKINT | PARMRK))
2168 up->port.read_status_mask |= UART_LSR_BI;
2171 * Characteres to ignore
2173 up->port.ignore_status_mask = 0;
2174 if (termios->c_iflag & IGNPAR)
2175 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2176 if (termios->c_iflag & IGNBRK) {
2177 up->port.ignore_status_mask |= UART_LSR_BI;
2179 * If we're ignoring parity and break indicators,
2180 * ignore overruns too (for real raw support).
2182 if (termios->c_iflag & IGNPAR)
2183 up->port.ignore_status_mask |= UART_LSR_OE;
2187 * ignore all characters if CREAD is not set
2189 if ((termios->c_cflag & CREAD) == 0)
2190 up->port.ignore_status_mask |= UART_LSR_DR;
2193 * CTS flow control flag and modem status interrupts
2195 up->ier &= ~UART_IER_MSI;
2196 if (!(up->bugs & UART_BUG_NOMSR) &&
2197 UART_ENABLE_MS(&up->port, termios->c_cflag))
2198 up->ier |= UART_IER_MSI;
2199 if (up->capabilities & UART_CAP_UUE)
2200 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2202 serial_out(up, UART_IER, up->ier);
2204 if (up->capabilities & UART_CAP_EFR) {
2205 unsigned char efr = 0;
2207 * TI16C752/Startech hardware flow control. FIXME:
2208 * - TI16C752 requires control thresholds to be set.
2209 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2211 if (termios->c_cflag & CRTSCTS)
2212 efr |= UART_EFR_CTS;
2214 serial_outp(up, UART_LCR, 0xBF);
2215 serial_outp(up, UART_EFR, efr);
2218 #ifdef CONFIG_ARCH_OMAP
2219 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2220 if (cpu_is_omap1510() && is_omap_port(up)) {
2221 if (baud == 115200) {
2223 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2225 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2229 if (up->capabilities & UART_NATSEMI) {
2230 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2231 serial_outp(up, UART_LCR, 0xe0);
2233 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2236 serial_dl_write(up, quot);
2239 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2240 * is written without DLAB set, this mode will be disabled.
2242 if (up->port.type == PORT_16750)
2243 serial_outp(up, UART_FCR, fcr);
2245 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2246 up->lcr = cval; /* Save LCR */
2247 if (up->port.type != PORT_16750) {
2248 if (fcr & UART_FCR_ENABLE_FIFO) {
2249 /* emulated UARTs (Lucent Venus 167x) need two steps */
2250 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2253 /* Note that we need to set ECB to access write water mark
2254 * bits. First allow FCR tx fifo write, then set fcr with
2255 * possible TX fifo settings. */
2256 if (uart_config[up->port.type].flags & UART_CAP_EFR) {
2257 serial_outp(up, UART_LCR, 0xbf); /* Access EFR */
2258 serial_outp(up, UART_EFR, UART_EFR_ECB);
2259 serial_outp(up, UART_LCR, 0x0); /* Access FCR */
2260 serial_outp(up, UART_FCR, fcr);
2261 serial_outp(up, UART_LCR, 0xbf); /* Access EFR */
2262 serial_outp(up, UART_EFR, 0);
2263 serial_outp(up, UART_LCR, cval); /* Access FCR */
2265 serial_outp(up, UART_FCR, fcr); /* set fcr */
2267 serial8250_set_mctrl(&up->port, up->port.mctrl);
2268 spin_unlock_irqrestore(&up->port.lock, flags);
2269 /* Don't rewrite B0 */
2270 if (tty_termios_baud_rate(termios))
2271 tty_termios_encode_baud_rate(termios, baud, baud);
2275 serial8250_pm(struct uart_port *port, unsigned int state,
2276 unsigned int oldstate)
2278 struct uart_8250_port *p = (struct uart_8250_port *)port;
2280 serial8250_set_sleep(p, state != 0);
2283 p->pm(port, state, oldstate);
2286 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2288 if (pt->port.iotype == UPIO_AU)
2290 #ifdef CONFIG_ARCH_OMAP
2291 if (is_omap_port(pt))
2292 return 0x16 << pt->port.regshift;
2294 return 8 << pt->port.regshift;
2298 * Resource handling.
2300 static int serial8250_request_std_resource(struct uart_8250_port *up)
2302 unsigned int size = serial8250_port_size(up);
2305 switch (up->port.iotype) {
2311 if (!up->port.mapbase)
2314 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2319 if (up->port.flags & UPF_IOREMAP) {
2320 up->port.membase = ioremap_nocache(up->port.mapbase,
2322 if (!up->port.membase) {
2323 release_mem_region(up->port.mapbase, size);
2331 if (!request_region(up->port.iobase, size, "serial"))
2338 static void serial8250_release_std_resource(struct uart_8250_port *up)
2340 unsigned int size = serial8250_port_size(up);
2342 switch (up->port.iotype) {
2348 if (!up->port.mapbase)
2351 if (up->port.flags & UPF_IOREMAP) {
2352 iounmap(up->port.membase);
2353 up->port.membase = NULL;
2356 release_mem_region(up->port.mapbase, size);
2361 release_region(up->port.iobase, size);
2366 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2368 unsigned long start = UART_RSA_BASE << up->port.regshift;
2369 unsigned int size = 8 << up->port.regshift;
2372 switch (up->port.iotype) {
2375 start += up->port.iobase;
2376 if (request_region(start, size, "serial-rsa"))
2386 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2388 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2389 unsigned int size = 8 << up->port.regshift;
2391 switch (up->port.iotype) {
2394 release_region(up->port.iobase + offset, size);
2399 static void serial8250_release_port(struct uart_port *port)
2401 struct uart_8250_port *up = (struct uart_8250_port *)port;
2403 serial8250_release_std_resource(up);
2404 if (up->port.type == PORT_RSA)
2405 serial8250_release_rsa_resource(up);
2408 static int serial8250_request_port(struct uart_port *port)
2410 struct uart_8250_port *up = (struct uart_8250_port *)port;
2413 ret = serial8250_request_std_resource(up);
2414 if (ret == 0 && up->port.type == PORT_RSA) {
2415 ret = serial8250_request_rsa_resource(up);
2417 serial8250_release_std_resource(up);
2423 static void serial8250_config_port(struct uart_port *port, int flags)
2425 struct uart_8250_port *up = (struct uart_8250_port *)port;
2426 int probeflags = PROBE_ANY;
2430 * Find the region that we can probe for. This in turn
2431 * tells us whether we can probe for the type of port.
2433 ret = serial8250_request_std_resource(up);
2437 ret = serial8250_request_rsa_resource(up);
2439 probeflags &= ~PROBE_RSA;
2441 if (flags & UART_CONFIG_TYPE)
2442 autoconfig(up, probeflags);
2443 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2446 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2447 serial8250_release_rsa_resource(up);
2448 if (up->port.type == PORT_UNKNOWN)
2449 serial8250_release_std_resource(up);
2453 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2455 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2456 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2457 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2458 ser->type == PORT_STARTECH)
2464 serial8250_type(struct uart_port *port)
2466 int type = port->type;
2468 if (type >= ARRAY_SIZE(uart_config))
2470 return uart_config[type].name;
2473 static struct uart_ops serial8250_pops = {
2474 .tx_empty = serial8250_tx_empty,
2475 .set_mctrl = serial8250_set_mctrl,
2476 .get_mctrl = serial8250_get_mctrl,
2477 .stop_tx = serial8250_stop_tx,
2478 .start_tx = serial8250_start_tx,
2479 .stop_rx = serial8250_stop_rx,
2480 .enable_ms = serial8250_enable_ms,
2481 .break_ctl = serial8250_break_ctl,
2482 .startup = serial8250_startup,
2483 .shutdown = serial8250_shutdown,
2484 .set_termios = serial8250_set_termios,
2485 .pm = serial8250_pm,
2486 .type = serial8250_type,
2487 .release_port = serial8250_release_port,
2488 .request_port = serial8250_request_port,
2489 .config_port = serial8250_config_port,
2490 .verify_port = serial8250_verify_port,
2491 #ifdef CONFIG_CONSOLE_POLL
2492 .poll_get_char = serial8250_get_poll_char,
2493 .poll_put_char = serial8250_put_poll_char,
2497 static struct uart_8250_port serial8250_ports[UART_NR];
2499 static void __init serial8250_isa_init_ports(void)
2501 struct uart_8250_port *up;
2502 static int first = 1;
2509 for (i = 0; i < nr_uarts; i++) {
2510 struct uart_8250_port *up = &serial8250_ports[i];
2513 spin_lock_init(&up->port.lock);
2515 init_timer(&up->timer);
2516 up->timer.function = serial8250_timeout;
2519 * ALPHA_KLUDGE_MCR needs to be killed.
2521 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2522 up->mcr_force = ALPHA_KLUDGE_MCR;
2524 up->port.ops = &serial8250_pops;
2527 for (i = 0, up = serial8250_ports;
2528 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2530 up->port.iobase = old_serial_port[i].port;
2531 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2532 up->port.uartclk = old_serial_port[i].baud_base * 16;
2533 up->port.flags = old_serial_port[i].flags;
2534 up->port.hub6 = old_serial_port[i].hub6;
2535 up->port.membase = old_serial_port[i].iomem_base;
2536 up->port.iotype = old_serial_port[i].io_type;
2537 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2539 up->port.flags |= UPF_SHARE_IRQ;
2544 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2548 serial8250_isa_init_ports();
2550 for (i = 0; i < nr_uarts; i++) {
2551 struct uart_8250_port *up = &serial8250_ports[i];
2554 uart_add_one_port(drv, &up->port);
2558 #ifdef CONFIG_SERIAL_8250_CONSOLE
2560 static void serial8250_console_putchar(struct uart_port *port, int ch)
2562 struct uart_8250_port *up = (struct uart_8250_port *)port;
2564 wait_for_xmitr(up, UART_LSR_THRE);
2565 serial_out(up, UART_TX, ch);
2569 * Print a string to the serial port trying not to disturb
2570 * any possible real use of the port...
2572 * The console_lock must be held when we get here.
2575 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2577 struct uart_8250_port *up = &serial8250_ports[co->index];
2578 unsigned long flags;
2582 touch_nmi_watchdog();
2584 local_irq_save(flags);
2585 if (up->port.sysrq) {
2586 /* serial8250_handle_port() already took the lock */
2588 } else if (oops_in_progress) {
2589 locked = spin_trylock(&up->port.lock);
2591 spin_lock(&up->port.lock);
2594 * First save the IER then disable the interrupts
2596 ier = serial_in(up, UART_IER);
2598 if (up->capabilities & UART_CAP_UUE)
2599 serial_out(up, UART_IER, UART_IER_UUE);
2601 serial_out(up, UART_IER, 0);
2603 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2606 * Finally, wait for transmitter to become empty
2607 * and restore the IER
2609 wait_for_xmitr(up, BOTH_EMPTY);
2610 serial_out(up, UART_IER, ier);
2613 * The receive handling will happen properly because the
2614 * receive ready bit will still be set; it is not cleared
2615 * on read. However, modem control will not, we must
2616 * call it if we have saved something in the saved flags
2617 * while processing with interrupts off.
2619 if (up->msr_saved_flags)
2620 check_modem_status(up);
2623 spin_unlock(&up->port.lock);
2624 local_irq_restore(flags);
2627 static int __init serial8250_console_setup(struct console *co, char *options)
2629 struct uart_port *port;
2636 * Check whether an invalid uart number has been specified, and
2637 * if so, search for the first available port that does have
2640 if (co->index >= nr_uarts)
2642 port = &serial8250_ports[co->index].port;
2643 if (!port->iobase && !port->membase)
2647 uart_parse_options(options, &baud, &parity, &bits, &flow);
2649 return uart_set_options(port, co, baud, parity, bits, flow);
2652 static int serial8250_console_early_setup(void)
2654 return serial8250_find_port_for_earlycon();
2657 static struct uart_driver serial8250_reg;
2658 static struct console serial8250_console = {
2660 .write = serial8250_console_write,
2661 .device = uart_console_device,
2662 .setup = serial8250_console_setup,
2663 .early_setup = serial8250_console_early_setup,
2664 .flags = CON_PRINTBUFFER,
2666 .data = &serial8250_reg,
2669 static int __init serial8250_console_init(void)
2671 if (nr_uarts > UART_NR)
2674 serial8250_isa_init_ports();
2675 register_console(&serial8250_console);
2678 console_initcall(serial8250_console_init);
2680 int serial8250_find_port(struct uart_port *p)
2683 struct uart_port *port;
2685 for (line = 0; line < nr_uarts; line++) {
2686 port = &serial8250_ports[line].port;
2687 if (uart_match_port(p, port))
2693 #define SERIAL8250_CONSOLE &serial8250_console
2695 #define SERIAL8250_CONSOLE NULL
2698 static struct uart_driver serial8250_reg = {
2699 .owner = THIS_MODULE,
2700 .driver_name = "serial",
2705 .cons = SERIAL8250_CONSOLE,
2709 * early_serial_setup - early registration for 8250 ports
2711 * Setup an 8250 port structure prior to console initialisation. Use
2712 * after console initialisation will cause undefined behaviour.
2714 int __init early_serial_setup(struct uart_port *port)
2716 if (port->line >= ARRAY_SIZE(serial8250_ports))
2719 serial8250_isa_init_ports();
2720 serial8250_ports[port->line].port = *port;
2721 serial8250_ports[port->line].port.ops = &serial8250_pops;
2726 * serial8250_suspend_port - suspend one serial port
2727 * @line: serial line number
2729 * Suspend one serial port.
2731 void serial8250_suspend_port(int line)
2733 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2737 * serial8250_resume_port - resume one serial port
2738 * @line: serial line number
2740 * Resume one serial port.
2742 void serial8250_resume_port(int line)
2744 struct uart_8250_port *up = &serial8250_ports[line];
2746 if (up->capabilities & UART_NATSEMI) {
2749 /* Ensure it's still in high speed mode */
2750 serial_outp(up, UART_LCR, 0xE0);
2752 tmp = serial_in(up, 0x04); /* EXCR2 */
2753 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2754 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2755 serial_outp(up, 0x04, tmp);
2757 serial_outp(up, UART_LCR, 0);
2759 uart_resume_port(&serial8250_reg, &up->port);
2763 * Register a set of serial devices attached to a platform device. The
2764 * list is terminated with a zero flags entry, which means we expect
2765 * all entries to have at least UPF_BOOT_AUTOCONF set.
2767 static int __devinit serial8250_probe(struct platform_device *dev)
2769 struct plat_serial8250_port *p = dev->dev.platform_data;
2770 struct uart_port port;
2773 memset(&port, 0, sizeof(struct uart_port));
2775 for (i = 0; p && p->flags != 0; p++, i++) {
2776 port.iobase = p->iobase;
2777 port.membase = p->membase;
2779 port.uartclk = p->uartclk;
2780 port.regshift = p->regshift;
2781 port.iotype = p->iotype;
2782 port.flags = p->flags;
2783 port.mapbase = p->mapbase;
2784 port.hub6 = p->hub6;
2785 port.private_data = p->private_data;
2786 port.dev = &dev->dev;
2788 port.flags |= UPF_SHARE_IRQ;
2789 ret = serial8250_register_port(&port);
2791 dev_err(&dev->dev, "unable to register port at index %d "
2792 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2793 p->iobase, (unsigned long long)p->mapbase,
2801 * Remove serial ports registered against a platform device.
2803 static int __devexit serial8250_remove(struct platform_device *dev)
2807 for (i = 0; i < nr_uarts; i++) {
2808 struct uart_8250_port *up = &serial8250_ports[i];
2810 if (up->port.dev == &dev->dev)
2811 serial8250_unregister_port(i);
2816 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2820 for (i = 0; i < UART_NR; i++) {
2821 struct uart_8250_port *up = &serial8250_ports[i];
2823 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2824 uart_suspend_port(&serial8250_reg, &up->port);
2830 static int serial8250_resume(struct platform_device *dev)
2834 for (i = 0; i < UART_NR; i++) {
2835 struct uart_8250_port *up = &serial8250_ports[i];
2837 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2838 serial8250_resume_port(i);
2844 static struct platform_driver serial8250_isa_driver = {
2845 .probe = serial8250_probe,
2846 .remove = __devexit_p(serial8250_remove),
2847 .suspend = serial8250_suspend,
2848 .resume = serial8250_resume,
2850 .name = "serial8250",
2851 .owner = THIS_MODULE,
2856 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2857 * in the table in include/asm/serial.h
2859 static struct platform_device *serial8250_isa_devs;
2862 * serial8250_register_port and serial8250_unregister_port allows for
2863 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2864 * modems and PCI multiport cards.
2866 static DEFINE_MUTEX(serial_mutex);
2868 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2873 * First, find a port entry which matches.
2875 for (i = 0; i < nr_uarts; i++)
2876 if (uart_match_port(&serial8250_ports[i].port, port))
2877 return &serial8250_ports[i];
2880 * We didn't find a matching entry, so look for the first
2881 * free entry. We look for one which hasn't been previously
2882 * used (indicated by zero iobase).
2884 for (i = 0; i < nr_uarts; i++)
2885 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2886 serial8250_ports[i].port.iobase == 0)
2887 return &serial8250_ports[i];
2890 * That also failed. Last resort is to find any entry which
2891 * doesn't have a real port associated with it.
2893 for (i = 0; i < nr_uarts; i++)
2894 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2895 return &serial8250_ports[i];
2901 * serial8250_register_port - register a serial port
2902 * @port: serial port template
2904 * Configure the serial port specified by the request. If the
2905 * port exists and is in use, it is hung up and unregistered
2908 * The port is then probed and if necessary the IRQ is autodetected
2909 * If this fails an error is returned.
2911 * On success the port is ready to use and the line number is returned.
2913 int serial8250_register_port(struct uart_port *port)
2915 struct uart_8250_port *uart;
2918 if (port->uartclk == 0)
2921 mutex_lock(&serial_mutex);
2923 uart = serial8250_find_match_or_unused(port);
2925 uart_remove_one_port(&serial8250_reg, &uart->port);
2927 uart->port.iobase = port->iobase;
2928 uart->port.membase = port->membase;
2929 uart->port.irq = port->irq;
2930 uart->port.uartclk = port->uartclk;
2931 uart->port.fifosize = port->fifosize;
2932 uart->port.regshift = port->regshift;
2933 uart->port.iotype = port->iotype;
2934 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2935 uart->port.mapbase = port->mapbase;
2936 uart->port.private_data = port->private_data;
2938 uart->port.dev = port->dev;
2940 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2942 ret = uart->port.line;
2944 mutex_unlock(&serial_mutex);
2948 EXPORT_SYMBOL(serial8250_register_port);
2951 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2952 * @line: serial line number
2954 * Remove one serial port. This may not be called from interrupt
2955 * context. We hand the port back to the our control.
2957 void serial8250_unregister_port(int line)
2959 struct uart_8250_port *uart = &serial8250_ports[line];
2961 mutex_lock(&serial_mutex);
2962 uart_remove_one_port(&serial8250_reg, &uart->port);
2963 if (serial8250_isa_devs) {
2964 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2965 uart->port.type = PORT_UNKNOWN;
2966 uart->port.dev = &serial8250_isa_devs->dev;
2967 uart_add_one_port(&serial8250_reg, &uart->port);
2969 uart->port.dev = NULL;
2971 mutex_unlock(&serial_mutex);
2973 EXPORT_SYMBOL(serial8250_unregister_port);
2975 static int __init serial8250_init(void)
2979 if (nr_uarts > UART_NR)
2982 printk(KERN_INFO "Serial: 8250/16550 driver"
2983 "%d ports, IRQ sharing %sabled\n", nr_uarts,
2984 share_irqs ? "en" : "dis");
2986 for (i = 0; i < NR_IRQS; i++)
2987 spin_lock_init(&irq_lists[i].lock);
2989 ret = uart_register_driver(&serial8250_reg);
2993 serial8250_isa_devs = platform_device_alloc("serial8250",
2994 PLAT8250_DEV_LEGACY);
2995 if (!serial8250_isa_devs) {
2997 goto unreg_uart_drv;
3000 ret = platform_device_add(serial8250_isa_devs);
3004 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3006 ret = platform_driver_register(&serial8250_isa_driver);
3010 platform_device_del(serial8250_isa_devs);
3012 platform_device_put(serial8250_isa_devs);
3014 uart_unregister_driver(&serial8250_reg);
3019 static void __exit serial8250_exit(void)
3021 struct platform_device *isa_dev = serial8250_isa_devs;
3024 * This tells serial8250_unregister_port() not to re-register
3025 * the ports (thereby making serial8250_isa_driver permanently
3028 serial8250_isa_devs = NULL;
3030 platform_driver_unregister(&serial8250_isa_driver);
3031 platform_device_unregister(isa_dev);
3033 uart_unregister_driver(&serial8250_reg);
3036 module_init(serial8250_init);
3037 module_exit(serial8250_exit);
3039 EXPORT_SYMBOL(serial8250_suspend_port);
3040 EXPORT_SYMBOL(serial8250_resume_port);
3042 MODULE_LICENSE("GPL");
3043 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3045 module_param(share_irqs, uint, 0644);
3046 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3049 module_param(nr_uarts, uint, 0644);
3050 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3052 #ifdef CONFIG_SERIAL_8250_RSA
3053 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3054 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3056 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);