drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <linux/vmalloc.h>
  11 #include <asm/uaccess.h>
  12
  13 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
  14 static void qla2x00_nv_deselect(scsi_qla_host_t *);
  15 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
  16
  17 /*
  18  * NVRAM support routines
  19  */
  20
  21 /**
  22  * qla2x00_lock_nvram_access() -
  23  * @ha: HA context
  24  */
  25 static void
  26 qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
  27 {
  28         uint16_t data;
  29         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  30
  31         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  32                 data = RD_REG_WORD(&reg->nvram);
  33                 while (data & NVR_BUSY) {
  34                         udelay(100);
  35                         data = RD_REG_WORD(&reg->nvram);
  36                 }
  37
  38                 /* Lock resource */
  39                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  40                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  41                 udelay(5);
  42                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  43                 while ((data & BIT_0) == 0) {
  44                         /* Lock failed */
  45                         udelay(100);
  46                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  47                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  48                         udelay(5);
  49                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  50                 }
  51         }
  52 }
  53
  54 /**
  55  * qla2x00_unlock_nvram_access() -
  56  * @ha: HA context
  57  */
  58 static void
  59 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
  60 {
  61         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  62
  63         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  64                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  65                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  66         }
  67 }
  68
  69 /**
  70  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
  71  *      request routine to get the word from NVRAM.
  72  * @ha: HA context
  73  * @addr: Address in NVRAM to read
  74  *
  75  * Returns the word read from nvram @addr.
  76  */
  77 static uint16_t
  78 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
  79 {
  80         uint16_t        data;
  81         uint32_t        nv_cmd;
  82
  83         nv_cmd = addr << 16;
  84         nv_cmd |= NV_READ_OP;
  85         data = qla2x00_nvram_request(ha, nv_cmd);
  86
  87         return (data);
  88 }
  89
  90 /**
  91  * qla2x00_write_nvram_word() - Write NVRAM data.
  92  * @ha: HA context
  93  * @addr: Address in NVRAM to write
  94  * @data: word to program
  95  */
  96 static void
  97 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
  98 {
  99         int count;
 100         uint16_t word;
 101         uint32_t nv_cmd, wait_cnt;
 102         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 103
 104         qla2x00_nv_write(ha, NVR_DATA_OUT);
 105         qla2x00_nv_write(ha, 0);
 106         qla2x00_nv_write(ha, 0);
 107
 108         for (word = 0; word < 8; word++)
 109                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 110
 111         qla2x00_nv_deselect(ha);
 112
 113         /* Write data */
 114         nv_cmd = (addr << 16) | NV_WRITE_OP;
 115         nv_cmd |= data;
 116         nv_cmd <<= 5;
 117         for (count = 0; count < 27; count++) {
 118                 if (nv_cmd & BIT_31)
 119                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 120                 else
 121                         qla2x00_nv_write(ha, 0);
 122
 123                 nv_cmd <<= 1;
 124         }
 125
 126         qla2x00_nv_deselect(ha);
 127
 128         /* Wait for NVRAM to become ready */
 129         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 130         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 131         wait_cnt = NVR_WAIT_CNT;
 132         do {
 133                 if (!--wait_cnt) {
 134                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
 135                             __func__, ha->host_no));
 136                         break;
 137                 }
 138                 NVRAM_DELAY();
 139                 word = RD_REG_WORD(&reg->nvram);
 140         } while ((word & NVR_DATA_IN) == 0);
 141
 142         qla2x00_nv_deselect(ha);
 143
 144         /* Disable writes */
 145         qla2x00_nv_write(ha, NVR_DATA_OUT);
 146         for (count = 0; count < 10; count++)
 147                 qla2x00_nv_write(ha, 0);
 148
 149         qla2x00_nv_deselect(ha);
 150 }
 151
 152 static int
 153 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
 154     uint32_t tmo)
 155 {
 156         int ret, count;
 157         uint16_t word;
 158         uint32_t nv_cmd;
 159         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 160
 161         ret = QLA_SUCCESS;
 162
 163         qla2x00_nv_write(ha, NVR_DATA_OUT);
 164         qla2x00_nv_write(ha, 0);
 165         qla2x00_nv_write(ha, 0);
 166
 167         for (word = 0; word < 8; word++)
 168                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 169
 170         qla2x00_nv_deselect(ha);
 171
 172         /* Write data */
 173         nv_cmd = (addr << 16) | NV_WRITE_OP;
 174         nv_cmd |= data;
 175         nv_cmd <<= 5;
 176         for (count = 0; count < 27; count++) {
 177                 if (nv_cmd & BIT_31)
 178                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 179                 else
 180                         qla2x00_nv_write(ha, 0);
 181
 182                 nv_cmd <<= 1;
 183         }
 184
 185         qla2x00_nv_deselect(ha);
 186
 187         /* Wait for NVRAM to become ready */
 188         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 189         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 190         do {
 191                 NVRAM_DELAY();
 192                 word = RD_REG_WORD(&reg->nvram);
 193                 if (!--tmo) {
 194                         ret = QLA_FUNCTION_FAILED;
 195                         break;
 196                 }
 197         } while ((word & NVR_DATA_IN) == 0);
 198
 199         qla2x00_nv_deselect(ha);
 200
 201         /* Disable writes */
 202         qla2x00_nv_write(ha, NVR_DATA_OUT);
 203         for (count = 0; count < 10; count++)
 204                 qla2x00_nv_write(ha, 0);
 205
 206         qla2x00_nv_deselect(ha);
 207
 208         return ret;
 209 }
 210
 211 /**
 212  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
 213  *      NVRAM.
 214  * @ha: HA context
 215  * @nv_cmd: NVRAM command
 216  *
 217  * Bit definitions for NVRAM command:
 218  *
 219  *      Bit 26     = start bit
 220  *      Bit 25, 24 = opcode
 221  *      Bit 23-16  = address
 222  *      Bit 15-0   = write data
 223  *
 224  * Returns the word read from nvram @addr.
 225  */
 226 static uint16_t
 227 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
 228 {
 229         uint8_t         cnt;
 230         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 231         uint16_t        data = 0;
 232         uint16_t        reg_data;
 233
 234         /* Send command to NVRAM. */
 235         nv_cmd <<= 5;
 236         for (cnt = 0; cnt < 11; cnt++) {
 237                 if (nv_cmd & BIT_31)
 238                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 239                 else
 240                         qla2x00_nv_write(ha, 0);
 241                 nv_cmd <<= 1;
 242         }
 243
 244         /* Read data from NVRAM. */
 245         for (cnt = 0; cnt < 16; cnt++) {
 246                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 247                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 248                 NVRAM_DELAY();
 249                 data <<= 1;
 250                 reg_data = RD_REG_WORD(&reg->nvram);
 251                 if (reg_data & NVR_DATA_IN)
 252                         data |= BIT_0;
 253                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 254                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 255                 NVRAM_DELAY();
 256         }
 257
 258         /* Deselect chip. */
 259         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 260         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 261         NVRAM_DELAY();
 262
 263         return (data);
 264 }
 265
 266 /**
 267  * qla2x00_nv_write() - Clean NVRAM operations.
 268  * @ha: HA context
 269  */
 270 static void
 271 qla2x00_nv_deselect(scsi_qla_host_t *ha)
 272 {
 273         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 274
 275         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 276         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 277         NVRAM_DELAY();
 278 }
 279
 280 /**
 281  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
 282  * @ha: HA context
 283  * @data: Serial interface selector
 284  */
 285 static void
 286 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
 287 {
 288         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 289
 290         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
 291         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 292         NVRAM_DELAY();
 293         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
 294             NVR_WRT_ENABLE);
 295         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 296         NVRAM_DELAY();
 297         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
 298         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 299         NVRAM_DELAY();
 300 }
 301
 302 /**
 303  * qla2x00_clear_nvram_protection() -
 304  * @ha: HA context
 305  */
 306 static int
 307 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
 308 {
 309         int ret, stat;
 310         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 311         uint32_t word, wait_cnt;
 312         uint16_t wprot, wprot_old;
 313
 314         /* Clear NVRAM write protection. */
 315         ret = QLA_FUNCTION_FAILED;
 316
 317         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 318         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 319             __constant_cpu_to_le16(0x1234), 100000);
 320         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 321         if (stat != QLA_SUCCESS || wprot != 0x1234) {
 322                 /* Write enable. */
 323                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 324                 qla2x00_nv_write(ha, 0);
 325                 qla2x00_nv_write(ha, 0);
 326                 for (word = 0; word < 8; word++)
 327                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 328
 329                 qla2x00_nv_deselect(ha);
 330
 331                 /* Enable protection register. */
 332                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 333                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 334                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 335                 for (word = 0; word < 8; word++)
 336                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 337
 338                 qla2x00_nv_deselect(ha);
 339
 340                 /* Clear protection register (ffff is cleared). */
 341                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 342                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 343                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 344                 for (word = 0; word < 8; word++)
 345                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 346
 347                 qla2x00_nv_deselect(ha);
 348
 349                 /* Wait for NVRAM to become ready. */
 350                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 351                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 352                 wait_cnt = NVR_WAIT_CNT;
 353                 do {
 354                         if (!--wait_cnt) {
 355                                 DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
 356                                     "ready...\n", __func__,
 357                                     ha->host_no));
 358                                 break;
 359                         }
 360                         NVRAM_DELAY();
 361                         word = RD_REG_WORD(&reg->nvram);
 362                 } while ((word & NVR_DATA_IN) == 0);
 363
 364                 if (wait_cnt)
 365                         ret = QLA_SUCCESS;
 366         } else
 367                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 368
 369         return ret;
 370 }
 371
 372 static void
 373 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
 374 {
 375         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 376         uint32_t word, wait_cnt;
 377
 378         if (stat != QLA_SUCCESS)
 379                 return;
 380
 381         /* Set NVRAM write protection. */
 382         /* Write enable. */
 383         qla2x00_nv_write(ha, NVR_DATA_OUT);
 384         qla2x00_nv_write(ha, 0);
 385         qla2x00_nv_write(ha, 0);
 386         for (word = 0; word < 8; word++)
 387                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 388
 389         qla2x00_nv_deselect(ha);
 390
 391         /* Enable protection register. */
 392         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 393         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 394         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 395         for (word = 0; word < 8; word++)
 396                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 397
 398         qla2x00_nv_deselect(ha);
 399
 400         /* Enable protection register. */
 401         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 402         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 403         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 404         for (word = 0; word < 8; word++)
 405                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 406
 407         qla2x00_nv_deselect(ha);
 408
 409         /* Wait for NVRAM to become ready. */
 410         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 411         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 412         wait_cnt = NVR_WAIT_CNT;
 413         do {
 414                 if (!--wait_cnt) {
 415                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
 416                             __func__, ha->host_no));
 417                         break;
 418                 }
 419                 NVRAM_DELAY();
 420                 word = RD_REG_WORD(&reg->nvram);
 421         } while ((word & NVR_DATA_IN) == 0);
 422 }
 423
 424
 425 /*****************************************************************************/
 426 /* Flash Manipulation Routines                                               */
 427 /*****************************************************************************/
 428
 429 #define OPTROM_BURST_SIZE       0x1000
 430 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
 431
 432 static inline uint32_t
 433 flash_conf_to_access_addr(uint32_t faddr)
 434 {
 435         return FARX_ACCESS_FLASH_CONF | faddr;
 436 }
 437
 438 static inline uint32_t
 439 flash_data_to_access_addr(uint32_t faddr)
 440 {
 441         return FARX_ACCESS_FLASH_DATA | faddr;
 442 }
 443
 444 static inline uint32_t
 445 nvram_conf_to_access_addr(uint32_t naddr)
 446 {
 447         return FARX_ACCESS_NVRAM_CONF | naddr;
 448 }
 449
 450 static inline uint32_t
 451 nvram_data_to_access_addr(uint32_t naddr)
 452 {
 453         return FARX_ACCESS_NVRAM_DATA | naddr;
 454 }
 455
 456 static uint32_t
 457 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
 458 {
 459         int rval;
 460         uint32_t cnt, data;
 461         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 462
 463         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 464         /* Wait for READ cycle to complete. */
 465         rval = QLA_SUCCESS;
 466         for (cnt = 3000;
 467             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 468             rval == QLA_SUCCESS; cnt--) {
 469                 if (cnt)
 470                         udelay(10);
 471                 else
 472                         rval = QLA_FUNCTION_TIMEOUT;
 473                 cond_resched();
 474         }
 475
 476         /* TODO: What happens if we time out? */
 477         data = 0xDEADDEAD;
 478         if (rval == QLA_SUCCESS)
 479                 data = RD_REG_DWORD(&reg->flash_data);
 480
 481         return data;
 482 }
 483
 484 uint32_t *
 485 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 486     uint32_t dwords)
 487 {
 488         uint32_t i;
 489
 490         /* Dword reads to flash. */
 491         for (i = 0; i < dwords; i++, faddr++)
 492                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 493                     flash_data_to_access_addr(faddr)));
 494
 495         return dwptr;
 496 }
 497
 498 static int
 499 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
 500 {
 501         int rval;
 502         uint32_t cnt;
 503         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 504
 505         WRT_REG_DWORD(&reg->flash_data, data);
 506         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 507         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 508         /* Wait for Write cycle to complete. */
 509         rval = QLA_SUCCESS;
 510         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 511             rval == QLA_SUCCESS; cnt--) {
 512                 if (cnt)
 513                         udelay(10);
 514                 else
 515                         rval = QLA_FUNCTION_TIMEOUT;
 516                 cond_resched();
 517         }
 518         return rval;
 519 }
 520
 521 static void
 522 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
 523     uint8_t *flash_id)
 524 {
 525         uint32_t ids;
 526
 527         ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
 528         *man_id = LSB(ids);
 529         *flash_id = MSB(ids);
 530
 531         /* Check if man_id and flash_id are valid. */
 532         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 533                 /* Read information using 0x9f opcode
 534                  * Device ID, Mfg ID would be read in the format:
 535                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 536                  * Example: ATMEL 0x00 01 45 1F
 537                  * Extract MFG and Dev ID from last two bytes.
 538                  */
 539                 ids = qla24xx_read_flash_dword(ha,
 540                     flash_data_to_access_addr(0xd009f));
 541                 *man_id = LSB(ids);
 542                 *flash_id = MSB(ids);
 543         }
 544 }
 545
 546 static int
 547 qla2xxx_find_flt_start(scsi_qla_host_t *ha, uint32_t *start)
 548 {
 549         const char *loc, *locations[] = { "DEF", "PCI" };
 550         uint32_t pcihdr, pcids;
 551         uint32_t *dcode;
 552         uint8_t *buf, *bcode, last_image;
 553         uint16_t cnt, chksum, *wptr;
 554         struct qla_flt_location *fltl;
 555
 556         /*
 557          * FLT-location structure resides after the last PCI region.
 558          */
 559
 560         /* Begin with sane defaults. */
 561         loc = locations[0];
 562         *start = IS_QLA24XX_TYPE(ha) ? FA_FLASH_LAYOUT_ADDR_24:
 563             FA_FLASH_LAYOUT_ADDR;
 564
 565         /* Begin with first PCI expansion ROM header. */
 566         buf = (uint8_t *)ha->request_ring;
 567         dcode = (uint32_t *)ha->request_ring;
 568         pcihdr = 0;
 569         last_image = 1;
 570         do {
 571                 /* Verify PCI expansion ROM header. */
 572                 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20);
 573                 bcode = buf + (pcihdr % 4);
 574                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
 575                         goto end;
 576
 577                 /* Locate PCI data structure. */
 578                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
 579                 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20);
 580                 bcode = buf + (pcihdr % 4);
 581
 582                 /* Validate signature of PCI data structure. */
 583                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
 584                     bcode[0x2] != 'I' || bcode[0x3] != 'R')
 585                         goto end;
 586
 587                 last_image = bcode[0x15] & BIT_7;
 588
 589                 /* Locate next PCI expansion ROM. */
 590                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
 591         } while (!last_image);
 592
 593         /* Now verify FLT-location structure. */
 594         fltl = (struct qla_flt_location *)ha->request_ring;
 595         qla24xx_read_flash_data(ha, dcode, pcihdr >> 2,
 596             sizeof(struct qla_flt_location) >> 2);
 597         if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
 598             fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
 599                 goto end;
 600
 601         wptr = (uint16_t *)ha->request_ring;
 602         cnt = sizeof(struct qla_flt_location) >> 1;
 603         for (chksum = 0; cnt; cnt--)
 604                 chksum += le16_to_cpu(*wptr++);
 605         if (chksum) {
 606                 qla_printk(KERN_ERR, ha,
 607                     "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
 608                 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
 609                 return QLA_FUNCTION_FAILED;
 610         }
 611
 612         /* Good data.  Use specified location. */
 613         loc = locations[1];
 614         *start = le16_to_cpu(fltl->start_hi) << 16 |
 615             le16_to_cpu(fltl->start_lo);
 616 end:
 617         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
 618         return QLA_SUCCESS;
 619 }
 620
 621 static void
 622 qla2xxx_get_flt_info(scsi_qla_host_t *ha, uint32_t flt_addr)
 623 {
 624         const char *loc, *locations[] = { "DEF", "FLT" };
 625         uint16_t *wptr;
 626         uint16_t cnt, chksum;
 627         uint32_t start;
 628         struct qla_flt_header *flt;
 629         struct qla_flt_region *region;
 630
 631         ha->flt_region_flt = flt_addr;
 632         wptr = (uint16_t *)ha->request_ring;
 633         flt = (struct qla_flt_header *)ha->request_ring;
 634         region = (struct qla_flt_region *)&flt[1];
 635         ha->isp_ops->read_optrom(ha, (uint8_t *)ha->request_ring,
 636             flt_addr << 2, OPTROM_BURST_SIZE);
 637         if (*wptr == __constant_cpu_to_le16(0xffff))
 638                 goto no_flash_data;
 639         if (flt->version != __constant_cpu_to_le16(1)) {
 640                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
 641                     "version=0x%x length=0x%x checksum=0x%x.\n",
 642                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 643                     le16_to_cpu(flt->checksum)));
 644                 goto no_flash_data;
 645         }
 646
 647         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
 648         for (chksum = 0; cnt; cnt--)
 649                 chksum += le16_to_cpu(*wptr++);
 650         if (chksum) {
 651                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
 652                     "version=0x%x length=0x%x checksum=0x%x.\n",
 653                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 654                     chksum));
 655                 goto no_flash_data;
 656         }
 657
 658         loc = locations[1];
 659         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
 660         for ( ; cnt; cnt--, region++) {
 661                 /* Store addresses as DWORD offsets. */
 662                 start = le32_to_cpu(region->start) >> 2;
 663
 664                 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
 665                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
 666                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
 667
 668                 switch (le32_to_cpu(region->code)) {
 669                 case FLT_REG_FW:
 670                         ha->flt_region_fw = start;
 671                         break;
 672                 case FLT_REG_BOOT_CODE:
 673                         ha->flt_region_boot = start;
 674                         break;
 675                 case FLT_REG_VPD_0:
 676                         ha->flt_region_vpd_nvram = start;
 677                         break;
 678                 case FLT_REG_FDT:
 679                         ha->flt_region_fdt = start;
 680                         break;
 681                 case FLT_REG_HW_EVENT_0:
 682                         if (!PCI_FUNC(ha->pdev->devfn))
 683                                 ha->flt_region_hw_event = start;
 684                         break;
 685                 case FLT_REG_HW_EVENT_1:
 686                         if (PCI_FUNC(ha->pdev->devfn))
 687                                 ha->flt_region_hw_event = start;
 688                         break;
 689                 case FLT_REG_NPIV_CONF_0:
 690                         if (!PCI_FUNC(ha->pdev->devfn))
 691                                 ha->flt_region_npiv_conf = start;
 692                         break;
 693                 case FLT_REG_NPIV_CONF_1:
 694                         if (PCI_FUNC(ha->pdev->devfn))
 695                                 ha->flt_region_npiv_conf = start;
 696                         break;
 697                 }
 698         }
 699         goto done;
 700
 701 no_flash_data:
 702         /* Use hardcoded defaults. */
 703         loc = locations[0];
 704         ha->flt_region_fw = FA_RISC_CODE_ADDR;
 705         ha->flt_region_boot = FA_BOOT_CODE_ADDR;
 706         ha->flt_region_vpd_nvram = FA_VPD_NVRAM_ADDR;
 707         ha->flt_region_fdt = IS_QLA24XX_TYPE(ha) ? FA_FLASH_DESCR_ADDR_24:
 708             FA_FLASH_DESCR_ADDR;
 709         ha->flt_region_hw_event = !PCI_FUNC(ha->pdev->devfn) ?
 710             FA_HW_EVENT0_ADDR: FA_HW_EVENT1_ADDR;
 711         ha->flt_region_npiv_conf = !PCI_FUNC(ha->pdev->devfn) ?
 712             (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF0_ADDR_24: FA_NPIV_CONF0_ADDR):
 713             (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF1_ADDR_24: FA_NPIV_CONF1_ADDR);
 714 done:
 715         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
 716             "vpd_nvram=0x%x fdt=0x%x flt=0x%x hwe=0x%x npiv=0x%x.\n", loc,
 717             ha->flt_region_boot, ha->flt_region_fw, ha->flt_region_vpd_nvram,
 718             ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_hw_event,
 719             ha->flt_region_npiv_conf));
 720 }
 721
 722 static void
 723 qla2xxx_get_fdt_info(scsi_qla_host_t *ha)
 724 {
 725 #define FLASH_BLK_SIZE_32K      0x8000
 726 #define FLASH_BLK_SIZE_64K      0x10000
 727         const char *loc, *locations[] = { "MID", "FDT" };
 728         uint16_t cnt, chksum;
 729         uint16_t *wptr;
 730         struct qla_fdt_layout *fdt;
 731         uint8_t man_id, flash_id;
 732         uint16_t mid, fid;
 733
 734         wptr = (uint16_t *)ha->request_ring;
 735         fdt = (struct qla_fdt_layout *)ha->request_ring;
 736         ha->isp_ops->read_optrom(ha, (uint8_t *)ha->request_ring,
 737             ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
 738         if (*wptr == __constant_cpu_to_le16(0xffff))
 739                 goto no_flash_data;
 740         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
 741             fdt->sig[3] != 'D')
 742                 goto no_flash_data;
 743
 744         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
 745             cnt++)
 746                 chksum += le16_to_cpu(*wptr++);
 747         if (chksum) {
 748                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
 749                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
 750                     le16_to_cpu(fdt->version)));
 751                 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
 752                 goto no_flash_data;
 753         }
 754
 755         loc = locations[1];
 756         mid = le16_to_cpu(fdt->man_id);
 757         fid = le16_to_cpu(fdt->id);
 758         ha->fdt_odd_index = mid == 0x1f;
 759         ha->fdt_wrt_disable = fdt->wrt_disable_bits;
 760         ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0300 | fdt->erase_cmd);
 761         ha->fdt_block_size = le32_to_cpu(fdt->block_size);
 762         if (fdt->unprotect_sec_cmd) {
 763                 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0300 |
 764                     fdt->unprotect_sec_cmd);
 765                 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
 766                     flash_conf_to_access_addr(0x0300 | fdt->protect_sec_cmd):
 767                     flash_conf_to_access_addr(0x0336);
 768         }
 769         goto done;
 770 no_flash_data:
 771         loc = locations[0];
 772         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 773         mid = man_id;
 774         fid = flash_id;
 775         ha->fdt_wrt_disable = 0x9c;
 776         ha->fdt_erase_cmd = flash_conf_to_access_addr(0x03d8);
 777         switch (man_id) {
 778         case 0xbf: /* STT flash. */
 779                 if (flash_id == 0x8e)
 780                         ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 781                 else
 782                         ha->fdt_block_size = FLASH_BLK_SIZE_32K;
 783
 784                 if (flash_id == 0x80)
 785                         ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0352);
 786                 break;
 787         case 0x13: /* ST M25P80. */
 788                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 789                 break;
 790         case 0x1f: /* Atmel 26DF081A. */
 791                 ha->fdt_odd_index = 1;
 792                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 793                 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0320);
 794                 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0339);
 795                 ha->fdt_protect_sec_cmd = flash_conf_to_access_addr(0x0336);
 796                 break;
 797         default:
 798                 /* Default to 64 kb sector size. */
 799                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 800                 break;
 801         }
 802 done:
 803         DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
 804             "pro=%x upro=%x idx=%d wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
 805             ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
 806             ha->fdt_unprotect_sec_cmd, ha->fdt_odd_index, ha->fdt_wrt_disable,
 807             ha->fdt_block_size));
 808 }
 809
 810 int
 811 qla2xxx_get_flash_info(scsi_qla_host_t *ha)
 812 {
 813         int ret;
 814         uint32_t flt_addr;
 815
 816         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
 817                 return QLA_SUCCESS;
 818
 819         ret = qla2xxx_find_flt_start(ha, &flt_addr);
 820         if (ret != QLA_SUCCESS)
 821                 return ret;
 822
 823         qla2xxx_get_flt_info(ha, flt_addr);
 824         qla2xxx_get_fdt_info(ha);
 825
 826         return QLA_SUCCESS;
 827 }
 828
 829 void
 830 qla2xxx_flash_npiv_conf(scsi_qla_host_t *ha)
 831 {
 832 #define NPIV_CONFIG_SIZE        (16*1024)
 833         void *data;
 834         uint16_t *wptr;
 835         uint16_t cnt, chksum;
 836         struct qla_npiv_header hdr;
 837         struct qla_npiv_entry *entry;
 838
 839         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
 840                 return;
 841
 842         ha->isp_ops->read_optrom(ha, (uint8_t *)&hdr,
 843             ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
 844         if (hdr.version == __constant_cpu_to_le16(0xffff))
 845                 return;
 846         if (hdr.version != __constant_cpu_to_le16(1)) {
 847                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
 848                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 849                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 850                     le16_to_cpu(hdr.checksum)));
 851                 return;
 852         }
 853
 854         data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
 855         if (!data) {
 856                 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
 857                     "allocate memory.\n"));
 858                 return;
 859         }
 860
 861         ha->isp_ops->read_optrom(ha, (uint8_t *)data,
 862             ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
 863
 864         cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
 865             sizeof(struct qla_npiv_entry)) >> 1;
 866         for (wptr = data, chksum = 0; cnt; cnt--)
 867                 chksum += le16_to_cpu(*wptr++);
 868         if (chksum) {
 869                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
 870                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 871                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 872                     chksum));
 873                 goto done;
 874         }
 875
 876         entry = data + sizeof(struct qla_npiv_header);
 877         cnt = le16_to_cpu(hdr.entries);
 878         for ( ; cnt; cnt--, entry++) {
 879                 uint16_t flags;
 880                 struct fc_vport_identifiers vid;
 881                 struct fc_vport *vport;
 882
 883                 flags = le16_to_cpu(entry->flags);
 884                 if (flags == 0xffff)
 885                         continue;
 886                 if ((flags & BIT_0) == 0)
 887                         continue;
 888
 889                 memset(&vid, 0, sizeof(vid));
 890                 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
 891                 vid.vport_type = FC_PORTTYPE_NPIV;
 892                 vid.disable = false;
 893                 vid.port_name = wwn_to_u64(entry->port_name);
 894                 vid.node_name = wwn_to_u64(entry->node_name);
 895
 896                 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx "
 897                     "wwnn=%llx vf_id=0x%x qos=0x%x.\n", cnt, vid.port_name,
 898                     vid.node_name, le16_to_cpu(entry->vf_id),
 899                     le16_to_cpu(entry->qos)));
 900
 901                 vport = fc_vport_create(ha->host, 0, &vid);
 902                 if (!vport)
 903                         qla_printk(KERN_INFO, ha, "NPIV-Config: Failed to "
 904                             "create vport [%02x]: wwpn=%llx wwnn=%llx.\n", cnt,
 905                             vid.port_name, vid.node_name);
 906         }
 907 done:
 908         kfree(data);
 909 }
 910
 911 static void
 912 qla24xx_unprotect_flash(scsi_qla_host_t *ha)
 913 {
 914         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 915
 916         /* Enable flash write. */
 917         WRT_REG_DWORD(&reg->ctrl_status,
 918             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 919         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 920
 921         if (!ha->fdt_wrt_disable)
 922                 return;
 923
 924         /* Disable flash write-protection. */
 925         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
 926         /* Some flash parts need an additional zero-write to clear bits.*/
 927         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
 928 }
 929
 930 static void
 931 qla24xx_protect_flash(scsi_qla_host_t *ha)
 932 {
 933         uint32_t cnt;
 934         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 935
 936         if (!ha->fdt_wrt_disable)
 937                 goto skip_wrt_protect;
 938
 939         /* Enable flash write-protection and wait for completion. */
 940         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101),
 941             ha->fdt_wrt_disable);
 942         for (cnt = 300; cnt &&
 943             qla24xx_read_flash_dword(ha,
 944                     flash_conf_to_access_addr(0x005)) & BIT_0;
 945             cnt--) {
 946                 udelay(10);
 947         }
 948
 949 skip_wrt_protect:
 950         /* Disable flash write. */
 951         WRT_REG_DWORD(&reg->ctrl_status,
 952             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
 953         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 954 }
 955
 956 static int
 957 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 958     uint32_t dwords)
 959 {
 960         int ret;
 961         uint32_t liter, miter;
 962         uint32_t sec_mask, rest_addr;
 963         uint32_t fdata, findex;
 964         dma_addr_t optrom_dma;
 965         void *optrom = NULL;
 966         uint32_t *s, *d;
 967
 968         ret = QLA_SUCCESS;
 969
 970         /* Prepare burst-capable write on supported ISPs. */
 971         if (IS_QLA25XX(ha) && !(faddr & 0xfff) &&
 972             dwords > OPTROM_BURST_DWORDS) {
 973                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
 974                     &optrom_dma, GFP_KERNEL);
 975                 if (!optrom) {
 976                         qla_printk(KERN_DEBUG, ha,
 977                             "Unable to allocate memory for optrom burst write "
 978                             "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
 979                 }
 980         }
 981
 982         rest_addr = (ha->fdt_block_size >> 2) - 1;
 983         sec_mask = 0x80000 - (ha->fdt_block_size >> 2);
 984
 985         qla24xx_unprotect_flash(ha);
 986
 987         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
 988                 if (ha->fdt_odd_index) {
 989                         findex = faddr << 2;
 990                         fdata = findex & sec_mask;
 991                 } else {
 992                         findex = faddr;
 993                         fdata = (findex & sec_mask) << 2;
 994                 }
 995
 996                 /* Are we at the beginning of a sector? */
 997                 if ((findex & rest_addr) == 0) {
 998                         /* Do sector unprotect. */
 999                         if (ha->fdt_unprotect_sec_cmd)
1000                                 qla24xx_write_flash_dword(ha,
1001                                     ha->fdt_unprotect_sec_cmd,
1002                                     (fdata & 0xff00) | ((fdata << 16) &
1003                                     0xff0000) | ((fdata >> 16) & 0xff));
1004                         ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1005                             (fdata & 0xff00) |((fdata << 16) &
1006                             0xff0000) | ((fdata >> 16) & 0xff));
1007                         if (ret != QLA_SUCCESS) {
1008                                 DEBUG9(printk("%s(%ld) Unable to flash "
1009                                     "sector: address=%x.\n", __func__,
1010                                     ha->host_no, faddr));
1011                                 break;
1012                         }
1013                 }
1014
1015                 /* Go with burst-write. */
1016                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1017                         /* Copy data to DMA'ble buffer. */
1018                         for (miter = 0, s = optrom, d = dwptr;
1019                             miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
1020                                 *s = cpu_to_le32(*d);
1021
1022                         ret = qla2x00_load_ram(ha, optrom_dma,
1023                             flash_data_to_access_addr(faddr),
1024                             OPTROM_BURST_DWORDS);
1025                         if (ret != QLA_SUCCESS) {
1026                                 qla_printk(KERN_WARNING, ha,
1027                                     "Unable to burst-write optrom segment "
1028                                     "(%x/%x/%llx).\n", ret,
1029                                     flash_data_to_access_addr(faddr),
1030                                     (unsigned long long)optrom_dma);
1031                                 qla_printk(KERN_WARNING, ha,
1032                                     "Reverting to slow-write.\n");
1033
1034                                 dma_free_coherent(&ha->pdev->dev,
1035                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1036                                 optrom = NULL;
1037                         } else {
1038                                 liter += OPTROM_BURST_DWORDS - 1;
1039                                 faddr += OPTROM_BURST_DWORDS - 1;
1040                                 dwptr += OPTROM_BURST_DWORDS - 1;
1041                                 continue;
1042                         }
1043                 }
1044
1045                 ret = qla24xx_write_flash_dword(ha,
1046                     flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr));
1047                 if (ret != QLA_SUCCESS) {
1048                         DEBUG9(printk("%s(%ld) Unable to program flash "
1049                             "address=%x data=%x.\n", __func__,
1050                             ha->host_no, faddr, *dwptr));
1051                         break;
1052                 }
1053
1054                 /* Do sector protect. */
1055                 if (ha->fdt_unprotect_sec_cmd &&
1056                     ((faddr & rest_addr) == rest_addr))
1057                         qla24xx_write_flash_dword(ha,
1058                             ha->fdt_protect_sec_cmd,
1059                             (fdata & 0xff00) | ((fdata << 16) &
1060                             0xff0000) | ((fdata >> 16) & 0xff));
1061         }
1062
1063         qla24xx_protect_flash(ha);
1064
1065         if (optrom)
1066                 dma_free_coherent(&ha->pdev->dev,
1067                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1068
1069         return ret;
1070 }
1071
1072 uint8_t *
1073 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
1074     uint32_t bytes)
1075 {
1076         uint32_t i;
1077         uint16_t *wptr;
1078
1079         /* Word reads to NVRAM via registers. */
1080         wptr = (uint16_t *)buf;
1081         qla2x00_lock_nvram_access(ha);
1082         for (i = 0; i < bytes >> 1; i++, naddr++)
1083                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1084                     naddr));
1085         qla2x00_unlock_nvram_access(ha);
1086
1087         return buf;
1088 }
1089
1090 uint8_t *
1091 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
1092     uint32_t bytes)
1093 {
1094         uint32_t i;
1095         uint32_t *dwptr;
1096
1097         /* Dword reads to flash. */
1098         dwptr = (uint32_t *)buf;
1099         for (i = 0; i < bytes >> 2; i++, naddr++)
1100                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1101                     nvram_data_to_access_addr(naddr)));
1102
1103         return buf;
1104 }
1105
1106 int
1107 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
1108     uint32_t bytes)
1109 {
1110         int ret, stat;
1111         uint32_t i;
1112         uint16_t *wptr;
1113         unsigned long flags;
1114
1115         ret = QLA_SUCCESS;
1116
1117         spin_lock_irqsave(&ha->hardware_lock, flags);
1118         qla2x00_lock_nvram_access(ha);
1119
1120         /* Disable NVRAM write-protection. */
1121         stat = qla2x00_clear_nvram_protection(ha);
1122
1123         wptr = (uint16_t *)buf;
1124         for (i = 0; i < bytes >> 1; i++, naddr++) {
1125                 qla2x00_write_nvram_word(ha, naddr,
1126                     cpu_to_le16(*wptr));
1127                 wptr++;
1128         }
1129
1130         /* Enable NVRAM write-protection. */
1131         qla2x00_set_nvram_protection(ha, stat);
1132
1133         qla2x00_unlock_nvram_access(ha);
1134         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1135
1136         return ret;
1137 }
1138
1139 int
1140 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
1141     uint32_t bytes)
1142 {
1143         int ret;
1144         uint32_t i;
1145         uint32_t *dwptr;
1146         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1147
1148         ret = QLA_SUCCESS;
1149
1150         /* Enable flash write. */
1151         WRT_REG_DWORD(&reg->ctrl_status,
1152             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1153         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1154
1155         /* Disable NVRAM write-protection. */
1156         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1157             0);
1158         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1159             0);
1160
1161         /* Dword writes to flash. */
1162         dwptr = (uint32_t *)buf;
1163         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1164                 ret = qla24xx_write_flash_dword(ha,
1165                     nvram_data_to_access_addr(naddr),
1166                     cpu_to_le32(*dwptr));
1167                 if (ret != QLA_SUCCESS) {
1168                         DEBUG9(printk("%s(%ld) Unable to program "
1169                             "nvram address=%x data=%x.\n", __func__,
1170                             ha->host_no, naddr, *dwptr));
1171                         break;
1172                 }
1173         }
1174
1175         /* Enable NVRAM write-protection. */
1176         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1177             0x8c);
1178
1179         /* Disable flash write. */
1180         WRT_REG_DWORD(&reg->ctrl_status,
1181             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1182         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1183
1184         return ret;
1185 }
1186
1187 uint8_t *
1188 qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
1189     uint32_t bytes)
1190 {
1191         uint32_t i;
1192         uint32_t *dwptr;
1193
1194         /* Dword reads to flash. */
1195         dwptr = (uint32_t *)buf;
1196         for (i = 0; i < bytes >> 2; i++, naddr++)
1197                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1198                     flash_data_to_access_addr(ha->flt_region_vpd_nvram |
1199                     naddr)));
1200
1201         return buf;
1202 }
1203
1204 int
1205 qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
1206     uint32_t bytes)
1207 {
1208 #define RMW_BUFFER_SIZE (64 * 1024)
1209         uint8_t *dbuf;
1210
1211         dbuf = vmalloc(RMW_BUFFER_SIZE);
1212         if (!dbuf)
1213                 return QLA_MEMORY_ALLOC_FAILED;
1214         ha->isp_ops->read_optrom(ha, dbuf, ha->flt_region_vpd_nvram << 2,
1215             RMW_BUFFER_SIZE);
1216         memcpy(dbuf + (naddr << 2), buf, bytes);
1217         ha->isp_ops->write_optrom(ha, dbuf, ha->flt_region_vpd_nvram << 2,
1218             RMW_BUFFER_SIZE);
1219         vfree(dbuf);
1220
1221         return QLA_SUCCESS;
1222 }
1223
1224 static inline void
1225 qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
1226 {
1227         if (IS_QLA2322(ha)) {
1228                 /* Flip all colors. */
1229                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1230                         /* Turn off. */
1231                         ha->beacon_color_state = 0;
1232                         *pflags = GPIO_LED_ALL_OFF;
1233                 } else {
1234                         /* Turn on. */
1235                         ha->beacon_color_state = QLA_LED_ALL_ON;
1236                         *pflags = GPIO_LED_RGA_ON;
1237                 }
1238         } else {
1239                 /* Flip green led only. */
1240                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1241                         /* Turn off. */
1242                         ha->beacon_color_state = 0;
1243                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1244                 } else {
1245                         /* Turn on. */
1246                         ha->beacon_color_state = QLA_LED_GRN_ON;
1247                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1248                 }
1249         }
1250 }
1251
1252 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1253
1254 void
1255 qla2x00_beacon_blink(struct scsi_qla_host *ha)
1256 {
1257         uint16_t gpio_enable;
1258         uint16_t gpio_data;
1259         uint16_t led_color = 0;
1260         unsigned long flags;
1261         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1262
1263         spin_lock_irqsave(&ha->hardware_lock, flags);
1264
1265         /* Save the Original GPIOE. */
1266         if (ha->pio_address) {
1267                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1268                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1269         } else {
1270                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1271                 gpio_data = RD_REG_WORD(&reg->gpiod);
1272         }
1273
1274         /* Set the modified gpio_enable values */
1275         gpio_enable |= GPIO_LED_MASK;
1276
1277         if (ha->pio_address) {
1278                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1279         } else {
1280                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1281                 RD_REG_WORD(&reg->gpioe);
1282         }
1283
1284         qla2x00_flip_colors(ha, &led_color);
1285
1286         /* Clear out any previously set LED color. */
1287         gpio_data &= ~GPIO_LED_MASK;
1288
1289         /* Set the new input LED color to GPIOD. */
1290         gpio_data |= led_color;
1291
1292         /* Set the modified gpio_data values */
1293         if (ha->pio_address) {
1294                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1295         } else {
1296                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1297                 RD_REG_WORD(&reg->gpiod);
1298         }
1299
1300         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1301 }
1302
1303 int
1304 qla2x00_beacon_on(struct scsi_qla_host *ha)
1305 {
1306         uint16_t gpio_enable;
1307         uint16_t gpio_data;
1308         unsigned long flags;
1309         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1310
1311         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1312         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1313
1314         if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1315                 qla_printk(KERN_WARNING, ha,
1316                     "Unable to update fw options (beacon on).\n");
1317                 return QLA_FUNCTION_FAILED;
1318         }
1319
1320         /* Turn off LEDs. */
1321         spin_lock_irqsave(&ha->hardware_lock, flags);
1322         if (ha->pio_address) {
1323                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1324                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1325         } else {
1326                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1327                 gpio_data = RD_REG_WORD(&reg->gpiod);
1328         }
1329         gpio_enable |= GPIO_LED_MASK;
1330
1331         /* Set the modified gpio_enable values. */
1332         if (ha->pio_address) {
1333                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1334         } else {
1335                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1336                 RD_REG_WORD(&reg->gpioe);
1337         }
1338
1339         /* Clear out previously set LED colour. */
1340         gpio_data &= ~GPIO_LED_MASK;
1341         if (ha->pio_address) {
1342                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1343         } else {
1344                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1345                 RD_REG_WORD(&reg->gpiod);
1346         }
1347         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1348
1349         /*
1350          * Let the per HBA timer kick off the blinking process based on
1351          * the following flags. No need to do anything else now.
1352          */
1353         ha->beacon_blink_led = 1;
1354         ha->beacon_color_state = 0;
1355
1356         return QLA_SUCCESS;
1357 }
1358
1359 int
1360 qla2x00_beacon_off(struct scsi_qla_host *ha)
1361 {
1362         int rval = QLA_SUCCESS;
1363
1364         ha->beacon_blink_led = 0;
1365
1366         /* Set the on flag so when it gets flipped it will be off. */
1367         if (IS_QLA2322(ha))
1368                 ha->beacon_color_state = QLA_LED_ALL_ON;
1369         else
1370                 ha->beacon_color_state = QLA_LED_GRN_ON;
1371
1372         ha->isp_ops->beacon_blink(ha);  /* This turns green LED off */
1373
1374         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1375         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1376
1377         rval = qla2x00_set_fw_options(ha, ha->fw_options);
1378         if (rval != QLA_SUCCESS)
1379                 qla_printk(KERN_WARNING, ha,
1380                     "Unable to update fw options (beacon off).\n");
1381         return rval;
1382 }
1383
1384
1385 static inline void
1386 qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
1387 {
1388         /* Flip all colors. */
1389         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1390                 /* Turn off. */
1391                 ha->beacon_color_state = 0;
1392                 *pflags = 0;
1393         } else {
1394                 /* Turn on. */
1395                 ha->beacon_color_state = QLA_LED_ALL_ON;
1396                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1397         }
1398 }
1399
1400 void
1401 qla24xx_beacon_blink(struct scsi_qla_host *ha)
1402 {
1403         uint16_t led_color = 0;
1404         uint32_t gpio_data;
1405         unsigned long flags;
1406         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1407
1408         /* Save the Original GPIOD. */
1409         spin_lock_irqsave(&ha->hardware_lock, flags);
1410         gpio_data = RD_REG_DWORD(&reg->gpiod);
1411
1412         /* Enable the gpio_data reg for update. */
1413         gpio_data |= GPDX_LED_UPDATE_MASK;
1414
1415         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1416         gpio_data = RD_REG_DWORD(&reg->gpiod);
1417
1418         /* Set the color bits. */
1419         qla24xx_flip_colors(ha, &led_color);
1420
1421         /* Clear out any previously set LED color. */
1422         gpio_data &= ~GPDX_LED_COLOR_MASK;
1423
1424         /* Set the new input LED color to GPIOD. */
1425         gpio_data |= led_color;
1426
1427         /* Set the modified gpio_data values. */
1428         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1429         gpio_data = RD_REG_DWORD(&reg->gpiod);
1430         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1431 }
1432
1433 int
1434 qla24xx_beacon_on(struct scsi_qla_host *ha)
1435 {
1436         uint32_t gpio_data;
1437         unsigned long flags;
1438         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1439
1440         if (ha->beacon_blink_led == 0) {
1441                 /* Enable firmware for update */
1442                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1443
1444                 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
1445                         return QLA_FUNCTION_FAILED;
1446
1447                 if (qla2x00_get_fw_options(ha, ha->fw_options) !=
1448                     QLA_SUCCESS) {
1449                         qla_printk(KERN_WARNING, ha,
1450                             "Unable to update fw options (beacon on).\n");
1451                         return QLA_FUNCTION_FAILED;
1452                 }
1453
1454                 spin_lock_irqsave(&ha->hardware_lock, flags);
1455                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1456
1457                 /* Enable the gpio_data reg for update. */
1458                 gpio_data |= GPDX_LED_UPDATE_MASK;
1459                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1460                 RD_REG_DWORD(&reg->gpiod);
1461
1462                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1463         }
1464
1465         /* So all colors blink together. */
1466         ha->beacon_color_state = 0;
1467
1468         /* Let the per HBA timer kick off the blinking process. */
1469         ha->beacon_blink_led = 1;
1470
1471         return QLA_SUCCESS;
1472 }
1473
1474 int
1475 qla24xx_beacon_off(struct scsi_qla_host *ha)
1476 {
1477         uint32_t gpio_data;
1478         unsigned long flags;
1479         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1480
1481         ha->beacon_blink_led = 0;
1482         ha->beacon_color_state = QLA_LED_ALL_ON;
1483
1484         ha->isp_ops->beacon_blink(ha);  /* Will flip to all off. */
1485
1486         /* Give control back to firmware. */
1487         spin_lock_irqsave(&ha->hardware_lock, flags);
1488         gpio_data = RD_REG_DWORD(&reg->gpiod);
1489
1490         /* Disable the gpio_data reg for update. */
1491         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1492         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1493         RD_REG_DWORD(&reg->gpiod);
1494         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1495
1496         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1497
1498         if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1499                 qla_printk(KERN_WARNING, ha,
1500                     "Unable to update fw options (beacon off).\n");
1501                 return QLA_FUNCTION_FAILED;
1502         }
1503
1504         if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1505                 qla_printk(KERN_WARNING, ha,
1506                     "Unable to get fw options (beacon off).\n");
1507                 return QLA_FUNCTION_FAILED;
1508         }
1509
1510         return QLA_SUCCESS;
1511 }
1512
1513
1514 /*
1515  * Flash support routines
1516  */
1517
1518 /**
1519  * qla2x00_flash_enable() - Setup flash for reading and writing.
1520  * @ha: HA context
1521  */
1522 static void
1523 qla2x00_flash_enable(scsi_qla_host_t *ha)
1524 {
1525         uint16_t data;
1526         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1527
1528         data = RD_REG_WORD(&reg->ctrl_status);
1529         data |= CSR_FLASH_ENABLE;
1530         WRT_REG_WORD(&reg->ctrl_status, data);
1531         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1532 }
1533
1534 /**
1535  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1536  * @ha: HA context
1537  */
1538 static void
1539 qla2x00_flash_disable(scsi_qla_host_t *ha)
1540 {
1541         uint16_t data;
1542         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1543
1544         data = RD_REG_WORD(&reg->ctrl_status);
1545         data &= ~(CSR_FLASH_ENABLE);
1546         WRT_REG_WORD(&reg->ctrl_status, data);
1547         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1548 }
1549
1550 /**
1551  * qla2x00_read_flash_byte() - Reads a byte from flash
1552  * @ha: HA context
1553  * @addr: Address in flash to read
1554  *
1555  * A word is read from the chip, but, only the lower byte is valid.
1556  *
1557  * Returns the byte read from flash @addr.
1558  */
1559 static uint8_t
1560 qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
1561 {
1562         uint16_t data;
1563         uint16_t bank_select;
1564         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1565
1566         bank_select = RD_REG_WORD(&reg->ctrl_status);
1567
1568         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1569                 /* Specify 64K address range: */
1570                 /*  clear out Module Select and Flash Address bits [19:16]. */
1571                 bank_select &= ~0xf8;
1572                 bank_select |= addr >> 12 & 0xf0;
1573                 bank_select |= CSR_FLASH_64K_BANK;
1574                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1575                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1576
1577                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1578                 data = RD_REG_WORD(&reg->flash_data);
1579
1580                 return (uint8_t)data;
1581         }
1582
1583         /* Setup bit 16 of flash address. */
1584         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1585                 bank_select |= CSR_FLASH_64K_BANK;
1586                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1587                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1588         } else if (((addr & BIT_16) == 0) &&
1589             (bank_select & CSR_FLASH_64K_BANK)) {
1590                 bank_select &= ~(CSR_FLASH_64K_BANK);
1591                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1592                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1593         }
1594
1595         /* Always perform IO mapped accesses to the FLASH registers. */
1596         if (ha->pio_address) {
1597                 uint16_t data2;
1598
1599                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1600                 do {
1601                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1602                         barrier();
1603                         cpu_relax();
1604                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1605                 } while (data != data2);
1606         } else {
1607                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1608                 data = qla2x00_debounce_register(&reg->flash_data);
1609         }
1610
1611         return (uint8_t)data;
1612 }
1613
1614 /**
1615  * qla2x00_write_flash_byte() - Write a byte to flash
1616  * @ha: HA context
1617  * @addr: Address in flash to write
1618  * @data: Data to write
1619  */
1620 static void
1621 qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
1622 {
1623         uint16_t bank_select;
1624         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1625
1626         bank_select = RD_REG_WORD(&reg->ctrl_status);
1627         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1628                 /* Specify 64K address range: */
1629                 /*  clear out Module Select and Flash Address bits [19:16]. */
1630                 bank_select &= ~0xf8;
1631                 bank_select |= addr >> 12 & 0xf0;
1632                 bank_select |= CSR_FLASH_64K_BANK;
1633                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1634                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1635
1636                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1637                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1638                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1639                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1640
1641                 return;
1642         }
1643
1644         /* Setup bit 16 of flash address. */
1645         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1646                 bank_select |= CSR_FLASH_64K_BANK;
1647                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1648                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1649         } else if (((addr & BIT_16) == 0) &&
1650             (bank_select & CSR_FLASH_64K_BANK)) {
1651                 bank_select &= ~(CSR_FLASH_64K_BANK);
1652                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1653                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1654         }
1655
1656         /* Always perform IO mapped accesses to the FLASH registers. */
1657         if (ha->pio_address) {
1658                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1659                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1660         } else {
1661                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1662                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1663                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1664                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1665         }
1666 }
1667
1668 /**
1669  * qla2x00_poll_flash() - Polls flash for completion.
1670  * @ha: HA context
1671  * @addr: Address in flash to poll
1672  * @poll_data: Data to be polled
1673  * @man_id: Flash manufacturer ID
1674  * @flash_id: Flash ID
1675  *
1676  * This function polls the device until bit 7 of what is read matches data
1677  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1678  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1679  * reading bit 5 as a 1.
1680  *
1681  * Returns 0 on success, else non-zero.
1682  */
1683 static int
1684 qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
1685     uint8_t man_id, uint8_t flash_id)
1686 {
1687         int status;
1688         uint8_t flash_data;
1689         uint32_t cnt;
1690
1691         status = 1;
1692
1693         /* Wait for 30 seconds for command to finish. */
1694         poll_data &= BIT_7;
1695         for (cnt = 3000000; cnt; cnt--) {
1696                 flash_data = qla2x00_read_flash_byte(ha, addr);
1697                 if ((flash_data & BIT_7) == poll_data) {
1698                         status = 0;
1699                         break;
1700                 }
1701
1702                 if (man_id != 0x40 && man_id != 0xda) {
1703                         if ((flash_data & BIT_5) && cnt > 2)
1704                                 cnt = 2;
1705                 }
1706                 udelay(10);
1707                 barrier();
1708                 cond_resched();
1709         }
1710         return status;
1711 }
1712
1713 /**
1714  * qla2x00_program_flash_address() - Programs a flash address
1715  * @ha: HA context
1716  * @addr: Address in flash to program
1717  * @data: Data to be written in flash
1718  * @man_id: Flash manufacturer ID
1719  * @flash_id: Flash ID
1720  *
1721  * Returns 0 on success, else non-zero.
1722  */
1723 static int
1724 qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
1725     uint8_t man_id, uint8_t flash_id)
1726 {
1727         /* Write Program Command Sequence. */
1728         if (IS_OEM_001(ha)) {
1729                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1730                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1731                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1732                 qla2x00_write_flash_byte(ha, addr, data);
1733         } else {
1734                 if (man_id == 0xda && flash_id == 0xc1) {
1735                         qla2x00_write_flash_byte(ha, addr, data);
1736                         if (addr & 0x7e)
1737                                 return 0;
1738                 } else {
1739                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1740                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1741                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1742                         qla2x00_write_flash_byte(ha, addr, data);
1743                 }
1744         }
1745
1746         udelay(150);
1747
1748         /* Wait for write to complete. */
1749         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1750 }
1751
1752 /**
1753  * qla2x00_erase_flash() - Erase the flash.
1754  * @ha: HA context
1755  * @man_id: Flash manufacturer ID
1756  * @flash_id: Flash ID
1757  *
1758  * Returns 0 on success, else non-zero.
1759  */
1760 static int
1761 qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
1762 {
1763         /* Individual Sector Erase Command Sequence */
1764         if (IS_OEM_001(ha)) {
1765                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1766                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1767                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1768                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1769                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1770                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1771         } else {
1772                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1773                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1774                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1775                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1776                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1777                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1778         }
1779
1780         udelay(150);
1781
1782         /* Wait for erase to complete. */
1783         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1784 }
1785
1786 /**
1787  * qla2x00_erase_flash_sector() - Erase a flash sector.
1788  * @ha: HA context
1789  * @addr: Flash sector to erase
1790  * @sec_mask: Sector address mask
1791  * @man_id: Flash manufacturer ID
1792  * @flash_id: Flash ID
1793  *
1794  * Returns 0 on success, else non-zero.
1795  */
1796 static int
1797 qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
1798     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1799 {
1800         /* Individual Sector Erase Command Sequence */
1801         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1802         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1803         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1804         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1805         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1806         if (man_id == 0x1f && flash_id == 0x13)
1807                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1808         else
1809                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1810
1811         udelay(150);
1812
1813         /* Wait for erase to complete. */
1814         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1815 }
1816
1817 /**
1818  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1819  * @man_id: Flash manufacturer ID
1820  * @flash_id: Flash ID
1821  */
1822 static void
1823 qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
1824     uint8_t *flash_id)
1825 {
1826         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1827         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1828         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1829         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1830         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1831         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1832         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1833         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1834 }
1835
1836 static void
1837 qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr,
1838         uint32_t length)
1839 {
1840         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1841         uint32_t midpoint, ilength;
1842         uint8_t data;
1843
1844         midpoint = length / 2;
1845
1846         WRT_REG_WORD(&reg->nvram, 0);
1847         RD_REG_WORD(&reg->nvram);
1848         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1849                 if (ilength == midpoint) {
1850                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1851                         RD_REG_WORD(&reg->nvram);
1852                 }
1853                 data = qla2x00_read_flash_byte(ha, saddr);
1854                 if (saddr % 100)
1855                         udelay(10);
1856                 *tmp_buf = data;
1857                 cond_resched();
1858         }
1859 }
1860
1861 static inline void
1862 qla2x00_suspend_hba(struct scsi_qla_host *ha)
1863 {
1864         int cnt;
1865         unsigned long flags;
1866         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1867
1868         /* Suspend HBA. */
1869         scsi_block_requests(ha->host);
1870         ha->isp_ops->disable_intrs(ha);
1871         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1872
1873         /* Pause RISC. */
1874         spin_lock_irqsave(&ha->hardware_lock, flags);
1875         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1876         RD_REG_WORD(&reg->hccr);
1877         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1878                 for (cnt = 0; cnt < 30000; cnt++) {
1879                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1880                                 break;
1881                         udelay(100);
1882                 }
1883         } else {
1884                 udelay(10);
1885         }
1886         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1887 }
1888
1889 static inline void
1890 qla2x00_resume_hba(struct scsi_qla_host *ha)
1891 {
1892         /* Resume HBA. */
1893         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1894         set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1895         qla2xxx_wake_dpc(ha);
1896         qla2x00_wait_for_hba_online(ha);
1897         scsi_unblock_requests(ha->host);
1898 }
1899
1900 uint8_t *
1901 qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1902     uint32_t offset, uint32_t length)
1903 {
1904         uint32_t addr, midpoint;
1905         uint8_t *data;
1906         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1907
1908         /* Suspend HBA. */
1909         qla2x00_suspend_hba(ha);
1910
1911         /* Go with read. */
1912         midpoint = ha->optrom_size / 2;
1913
1914         qla2x00_flash_enable(ha);
1915         WRT_REG_WORD(&reg->nvram, 0);
1916         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
1917         for (addr = offset, data = buf; addr < length; addr++, data++) {
1918                 if (addr == midpoint) {
1919                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1920                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
1921                 }
1922
1923                 *data = qla2x00_read_flash_byte(ha, addr);
1924         }
1925         qla2x00_flash_disable(ha);
1926
1927         /* Resume HBA. */
1928         qla2x00_resume_hba(ha);
1929
1930         return buf;
1931 }
1932
1933 int
1934 qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1935     uint32_t offset, uint32_t length)
1936 {
1937
1938         int rval;
1939         uint8_t man_id, flash_id, sec_number, data;
1940         uint16_t wd;
1941         uint32_t addr, liter, sec_mask, rest_addr;
1942         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1943
1944         /* Suspend HBA. */
1945         qla2x00_suspend_hba(ha);
1946
1947         rval = QLA_SUCCESS;
1948         sec_number = 0;
1949
1950         /* Reset ISP chip. */
1951         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1952         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1953
1954         /* Go with write. */
1955         qla2x00_flash_enable(ha);
1956         do {    /* Loop once to provide quick error exit */
1957                 /* Structure of flash memory based on manufacturer */
1958                 if (IS_OEM_001(ha)) {
1959                         /* OEM variant with special flash part. */
1960                         man_id = flash_id = 0;
1961                         rest_addr = 0xffff;
1962                         sec_mask   = 0x10000;
1963                         goto update_flash;
1964                 }
1965                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1966                 switch (man_id) {
1967                 case 0x20: /* ST flash. */
1968                         if (flash_id == 0xd2 || flash_id == 0xe3) {
1969                                 /*
1970                                  * ST m29w008at part - 64kb sector size with
1971                                  * 32kb,8kb,8kb,16kb sectors at memory address
1972                                  * 0xf0000.
1973                                  */
1974                                 rest_addr = 0xffff;
1975                                 sec_mask = 0x10000;
1976                                 break;
1977                         }
1978                         /*
1979                          * ST m29w010b part - 16kb sector size
1980                          * Default to 16kb sectors
1981                          */
1982                         rest_addr = 0x3fff;
1983                         sec_mask = 0x1c000;
1984                         break;
1985                 case 0x40: /* Mostel flash. */
1986                         /* Mostel v29c51001 part - 512 byte sector size. */
1987                         rest_addr = 0x1ff;
1988                         sec_mask = 0x1fe00;
1989                         break;
1990                 case 0xbf: /* SST flash. */
1991                         /* SST39sf10 part - 4kb sector size. */
1992                         rest_addr = 0xfff;
1993                         sec_mask = 0x1f000;
1994                         break;
1995                 case 0xda: /* Winbond flash. */
1996                         /* Winbond W29EE011 part - 256 byte sector size. */
1997                         rest_addr = 0x7f;
1998                         sec_mask = 0x1ff80;
1999                         break;
2000                 case 0xc2: /* Macronix flash. */
2001                         /* 64k sector size. */
2002                         if (flash_id == 0x38 || flash_id == 0x4f) {
2003                                 rest_addr = 0xffff;
2004                                 sec_mask = 0x10000;
2005                                 break;
2006                         }
2007                         /* Fall through... */
2008
2009                 case 0x1f: /* Atmel flash. */
2010                         /* 512k sector size. */
2011                         if (flash_id == 0x13) {
2012                                 rest_addr = 0x7fffffff;
2013                                 sec_mask =   0x80000000;
2014                                 break;
2015                         }
2016                         /* Fall through... */
2017
2018                 case 0x01: /* AMD flash. */
2019                         if (flash_id == 0x38 || flash_id == 0x40 ||
2020                             flash_id == 0x4f) {
2021                                 /* Am29LV081 part - 64kb sector size. */
2022                                 /* Am29LV002BT part - 64kb sector size. */
2023                                 rest_addr = 0xffff;
2024                                 sec_mask = 0x10000;
2025                                 break;
2026                         } else if (flash_id == 0x3e) {
2027                                 /*
2028                                  * Am29LV008b part - 64kb sector size with
2029                                  * 32kb,8kb,8kb,16kb sector at memory address
2030                                  * h0xf0000.
2031                                  */
2032                                 rest_addr = 0xffff;
2033                                 sec_mask = 0x10000;
2034                                 break;
2035                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
2036                                 /*
2037                                  * Am29LV010 part or AM29f010 - 16kb sector
2038                                  * size.
2039                                  */
2040                                 rest_addr = 0x3fff;
2041                                 sec_mask = 0x1c000;
2042                                 break;
2043                         } else if (flash_id == 0x6d) {
2044                                 /* Am29LV001 part - 8kb sector size. */
2045                                 rest_addr = 0x1fff;
2046                                 sec_mask = 0x1e000;
2047                                 break;
2048                         }
2049                 default:
2050                         /* Default to 16 kb sector size. */
2051                         rest_addr = 0x3fff;
2052                         sec_mask = 0x1c000;
2053                         break;
2054                 }
2055
2056 update_flash:
2057                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2058                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2059                                 rval = QLA_FUNCTION_FAILED;
2060                                 break;
2061                         }
2062                 }
2063
2064                 for (addr = offset, liter = 0; liter < length; liter++,
2065                     addr++) {
2066                         data = buf[liter];
2067                         /* Are we at the beginning of a sector? */
2068                         if ((addr & rest_addr) == 0) {
2069                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2070                                         if (addr >= 0x10000UL) {
2071                                                 if (((addr >> 12) & 0xf0) &&
2072                                                     ((man_id == 0x01 &&
2073                                                         flash_id == 0x3e) ||
2074                                                      (man_id == 0x20 &&
2075                                                          flash_id == 0xd2))) {
2076                                                         sec_number++;
2077                                                         if (sec_number == 1) {
2078                                                                 rest_addr =
2079                                                                     0x7fff;
2080                                                                 sec_mask =
2081                                                                     0x18000;
2082                                                         } else if (
2083                                                             sec_number == 2 ||
2084                                                             sec_number == 3) {
2085                                                                 rest_addr =
2086                                                                     0x1fff;
2087                                                                 sec_mask =
2088                                                                     0x1e000;
2089                                                         } else if (
2090                                                             sec_number == 4) {
2091                                                                 rest_addr =
2092                                                                     0x3fff;
2093                                                                 sec_mask =
2094                                                                     0x1c000;
2095                                                         }
2096                                                 }
2097                                         }
2098                                 } else if (addr == ha->optrom_size / 2) {
2099                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2100                                         RD_REG_WORD(&reg->nvram);
2101                                 }
2102
2103                                 if (flash_id == 0xda && man_id == 0xc1) {
2104                                         qla2x00_write_flash_byte(ha, 0x5555,
2105                                             0xaa);
2106                                         qla2x00_write_flash_byte(ha, 0x2aaa,
2107                                             0x55);
2108                                         qla2x00_write_flash_byte(ha, 0x5555,
2109                                             0xa0);
2110                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2111                                         /* Then erase it */
2112                                         if (qla2x00_erase_flash_sector(ha,
2113                                             addr, sec_mask, man_id,
2114                                             flash_id)) {
2115                                                 rval = QLA_FUNCTION_FAILED;
2116                                                 break;
2117                                         }
2118                                         if (man_id == 0x01 && flash_id == 0x6d)
2119                                                 sec_number++;
2120                                 }
2121                         }
2122
2123                         if (man_id == 0x01 && flash_id == 0x6d) {
2124                                 if (sec_number == 1 &&
2125                                     addr == (rest_addr - 1)) {
2126                                         rest_addr = 0x0fff;
2127                                         sec_mask   = 0x1f000;
2128                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2129                                         rest_addr = 0x3fff;
2130                                         sec_mask   = 0x1c000;
2131                                 }
2132                         }
2133
2134                         if (qla2x00_program_flash_address(ha, addr, data,
2135                             man_id, flash_id)) {
2136                                 rval = QLA_FUNCTION_FAILED;
2137                                 break;
2138                         }
2139                         cond_resched();
2140                 }
2141         } while (0);
2142         qla2x00_flash_disable(ha);
2143
2144         /* Resume HBA. */
2145         qla2x00_resume_hba(ha);
2146
2147         return rval;
2148 }
2149
2150 uint8_t *
2151 qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
2152     uint32_t offset, uint32_t length)
2153 {
2154         /* Suspend HBA. */
2155         scsi_block_requests(ha->host);
2156         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2157
2158         /* Go with read. */
2159         qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
2160
2161         /* Resume HBA. */
2162         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2163         scsi_unblock_requests(ha->host);
2164
2165         return buf;
2166 }
2167
2168 int
2169 qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
2170     uint32_t offset, uint32_t length)
2171 {
2172         int rval;
2173
2174         /* Suspend HBA. */
2175         scsi_block_requests(ha->host);
2176         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2177
2178         /* Go with write. */
2179         rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
2180             length >> 2);
2181
2182         /* Resume HBA -- RISC reset needed. */
2183         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2184         set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
2185         qla2xxx_wake_dpc(ha);
2186         qla2x00_wait_for_hba_online(ha);
2187         scsi_unblock_requests(ha->host);
2188
2189         return rval;
2190 }
2191
2192 uint8_t *
2193 qla25xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
2194     uint32_t offset, uint32_t length)
2195 {
2196         int rval;
2197         dma_addr_t optrom_dma;
2198         void *optrom;
2199         uint8_t *pbuf;
2200         uint32_t faddr, left, burst;
2201
2202         if (offset & 0xfff)
2203                 goto slow_read;
2204         if (length < OPTROM_BURST_SIZE)
2205                 goto slow_read;
2206
2207         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2208             &optrom_dma, GFP_KERNEL);
2209         if (!optrom) {
2210                 qla_printk(KERN_DEBUG, ha,
2211                     "Unable to allocate memory for optrom burst read "
2212                     "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2213
2214                 goto slow_read;
2215         }
2216
2217         pbuf = buf;
2218         faddr = offset >> 2;
2219         left = length >> 2;
2220         burst = OPTROM_BURST_DWORDS;
2221         while (left != 0) {
2222                 if (burst > left)
2223                         burst = left;
2224
2225                 rval = qla2x00_dump_ram(ha, optrom_dma,
2226                     flash_data_to_access_addr(faddr), burst);
2227                 if (rval) {
2228                         qla_printk(KERN_WARNING, ha,
2229                             "Unable to burst-read optrom segment "
2230                             "(%x/%x/%llx).\n", rval,
2231                             flash_data_to_access_addr(faddr),
2232                             (unsigned long long)optrom_dma);
2233                         qla_printk(KERN_WARNING, ha,
2234                             "Reverting to slow-read.\n");
2235
2236                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2237                             optrom, optrom_dma);
2238                         goto slow_read;
2239                 }
2240
2241                 memcpy(pbuf, optrom, burst * 4);
2242
2243                 left -= burst;
2244                 faddr += burst;
2245                 pbuf += burst * 4;
2246         }
2247
2248         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2249             optrom_dma);
2250
2251         return buf;
2252
2253 slow_read:
2254     return qla24xx_read_optrom_data(ha, buf, offset, length);
2255 }
2256
2257 /**
2258  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2259  * @ha: HA context
2260  * @pcids: Pointer to the FCODE PCI data structure
2261  *
2262  * The process of retrieving the FCODE version information is at best
2263  * described as interesting.
2264  *
2265  * Within the first 100h bytes of the image an ASCII string is present
2266  * which contains several pieces of information including the FCODE
2267  * version.  Unfortunately it seems the only reliable way to retrieve
2268  * the version is by scanning for another sentinel within the string,
2269  * the FCODE build date:
2270  *
2271  *      ... 2.00.02 10/17/02 ...
2272  *
2273  * Returns QLA_SUCCESS on successful retrieval of version.
2274  */
2275 static void
2276 qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids)
2277 {
2278         int ret = QLA_FUNCTION_FAILED;
2279         uint32_t istart, iend, iter, vend;
2280         uint8_t do_next, rbyte, *vbyte;
2281
2282         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2283
2284         /* Skip the PCI data structure. */
2285         istart = pcids +
2286             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2287                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2288         iend = istart + 0x100;
2289         do {
2290                 /* Scan for the sentinel date string...eeewww. */
2291                 do_next = 0;
2292                 iter = istart;
2293                 while ((iter < iend) && !do_next) {
2294                         iter++;
2295                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
2296                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2297                                     '/')
2298                                         do_next++;
2299                                 else if (qla2x00_read_flash_byte(ha,
2300                                     iter + 3) == '/')
2301                                         do_next++;
2302                         }
2303                 }
2304                 if (!do_next)
2305                         break;
2306
2307                 /* Backtrack to previous ' ' (space). */
2308                 do_next = 0;
2309                 while ((iter > istart) && !do_next) {
2310                         iter--;
2311                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
2312                                 do_next++;
2313                 }
2314                 if (!do_next)
2315                         break;
2316
2317                 /*
2318                  * Mark end of version tag, and find previous ' ' (space) or
2319                  * string length (recent FCODE images -- major hack ahead!!!).
2320                  */
2321                 vend = iter - 1;
2322                 do_next = 0;
2323                 while ((iter > istart) && !do_next) {
2324                         iter--;
2325                         rbyte = qla2x00_read_flash_byte(ha, iter);
2326                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2327                                 do_next++;
2328                 }
2329                 if (!do_next)
2330                         break;
2331
2332                 /* Mark beginning of version tag, and copy data. */
2333                 iter++;
2334                 if ((vend - iter) &&
2335                     ((vend - iter) < sizeof(ha->fcode_revision))) {
2336                         vbyte = ha->fcode_revision;
2337                         while (iter <= vend) {
2338                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2339                                 iter++;
2340                         }
2341                         ret = QLA_SUCCESS;
2342                 }
2343         } while (0);
2344
2345         if (ret != QLA_SUCCESS)
2346                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2347 }
2348
2349 int
2350 qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2351 {
2352         int ret = QLA_SUCCESS;
2353         uint8_t code_type, last_image;
2354         uint32_t pcihdr, pcids;
2355         uint8_t *dbyte;
2356         uint16_t *dcode;
2357
2358         if (!ha->pio_address || !mbuf)
2359                 return QLA_FUNCTION_FAILED;
2360
2361         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2362         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2363         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2364         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2365
2366         qla2x00_flash_enable(ha);
2367
2368         /* Begin with first PCI expansion ROM header. */
2369         pcihdr = 0;
2370         last_image = 1;
2371         do {
2372                 /* Verify PCI expansion ROM header. */
2373                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2374                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2375                         /* No signature */
2376                         DEBUG2(printk("scsi(%ld): No matching ROM "
2377                             "signature.\n", ha->host_no));
2378                         ret = QLA_FUNCTION_FAILED;
2379                         break;
2380                 }
2381
2382                 /* Locate PCI data structure. */
2383                 pcids = pcihdr +
2384                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2385                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2386
2387                 /* Validate signature of PCI data structure. */
2388                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2389                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2390                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2391                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2392                         /* Incorrect header. */
2393                         DEBUG2(printk("%s(): PCI data struct not found "
2394                             "pcir_adr=%x.\n", __func__, pcids));
2395                         ret = QLA_FUNCTION_FAILED;
2396                         break;
2397                 }
2398
2399                 /* Read version */
2400                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2401                 switch (code_type) {
2402                 case ROM_CODE_TYPE_BIOS:
2403                         /* Intel x86, PC-AT compatible. */
2404                         ha->bios_revision[0] =
2405                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2406                         ha->bios_revision[1] =
2407                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2408                         DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2409                             ha->bios_revision[1], ha->bios_revision[0]));
2410                         break;
2411                 case ROM_CODE_TYPE_FCODE:
2412                         /* Open Firmware standard for PCI (FCode). */
2413                         /* Eeeewww... */
2414                         qla2x00_get_fcode_version(ha, pcids);
2415                         break;
2416                 case ROM_CODE_TYPE_EFI:
2417                         /* Extensible Firmware Interface (EFI). */
2418                         ha->efi_revision[0] =
2419                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2420                         ha->efi_revision[1] =
2421                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2422                         DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2423                             ha->efi_revision[1], ha->efi_revision[0]));
2424                         break;
2425                 default:
2426                         DEBUG2(printk("%s(): Unrecognized code type %x at "
2427                             "pcids %x.\n", __func__, code_type, pcids));
2428                         break;
2429                 }
2430
2431                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2432
2433                 /* Locate next PCI expansion ROM. */
2434                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2435                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2436         } while (!last_image);
2437
2438         if (IS_QLA2322(ha)) {
2439                 /* Read firmware image information. */
2440                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2441                 dbyte = mbuf;
2442                 memset(dbyte, 0, 8);
2443                 dcode = (uint16_t *)dbyte;
2444
2445                 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2446                     8);
2447                 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n",
2448                     __func__, ha->host_no));
2449                 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2450
2451                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2452                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2453                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2454                     dcode[3] == 0)) {
2455                         DEBUG2(printk("%s(): Unrecognized fw revision at "
2456                             "%x.\n", __func__, ha->flt_region_fw * 4));
2457                 } else {
2458                         /* values are in big endian */
2459                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2460                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2461                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2462                 }
2463         }
2464
2465         qla2x00_flash_disable(ha);
2466
2467         return ret;
2468 }
2469
2470 int
2471 qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2472 {
2473         int ret = QLA_SUCCESS;
2474         uint32_t pcihdr, pcids;
2475         uint32_t *dcode;
2476         uint8_t *bcode;
2477         uint8_t code_type, last_image;
2478         int i;
2479
2480         if (!mbuf)
2481                 return QLA_FUNCTION_FAILED;
2482
2483         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2484         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2485         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2486         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2487
2488         dcode = mbuf;
2489
2490         /* Begin with first PCI expansion ROM header. */
2491         pcihdr = ha->flt_region_boot;
2492         last_image = 1;
2493         do {
2494                 /* Verify PCI expansion ROM header. */
2495                 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20);
2496                 bcode = mbuf + (pcihdr % 4);
2497                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2498                         /* No signature */
2499                         DEBUG2(printk("scsi(%ld): No matching ROM "
2500                             "signature.\n", ha->host_no));
2501                         ret = QLA_FUNCTION_FAILED;
2502                         break;
2503                 }
2504
2505                 /* Locate PCI data structure. */
2506                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2507
2508                 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20);
2509                 bcode = mbuf + (pcihdr % 4);
2510
2511                 /* Validate signature of PCI data structure. */
2512                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2513                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2514                         /* Incorrect header. */
2515                         DEBUG2(printk("%s(): PCI data struct not found "
2516                             "pcir_adr=%x.\n", __func__, pcids));
2517                         ret = QLA_FUNCTION_FAILED;
2518                         break;
2519                 }
2520
2521                 /* Read version */
2522                 code_type = bcode[0x14];
2523                 switch (code_type) {
2524                 case ROM_CODE_TYPE_BIOS:
2525                         /* Intel x86, PC-AT compatible. */
2526                         ha->bios_revision[0] = bcode[0x12];
2527                         ha->bios_revision[1] = bcode[0x13];
2528                         DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2529                             ha->bios_revision[1], ha->bios_revision[0]));
2530                         break;
2531                 case ROM_CODE_TYPE_FCODE:
2532                         /* Open Firmware standard for PCI (FCode). */
2533                         ha->fcode_revision[0] = bcode[0x12];
2534                         ha->fcode_revision[1] = bcode[0x13];
2535                         DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__,
2536                             ha->fcode_revision[1], ha->fcode_revision[0]));
2537                         break;
2538                 case ROM_CODE_TYPE_EFI:
2539                         /* Extensible Firmware Interface (EFI). */
2540                         ha->efi_revision[0] = bcode[0x12];
2541                         ha->efi_revision[1] = bcode[0x13];
2542                         DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2543                             ha->efi_revision[1], ha->efi_revision[0]));
2544                         break;
2545                 default:
2546                         DEBUG2(printk("%s(): Unrecognized code type %x at "
2547                             "pcids %x.\n", __func__, code_type, pcids));
2548                         break;
2549                 }
2550
2551                 last_image = bcode[0x15] & BIT_7;
2552
2553                 /* Locate next PCI expansion ROM. */
2554                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2555         } while (!last_image);
2556
2557         /* Read firmware image information. */
2558         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2559         dcode = mbuf;
2560
2561         qla24xx_read_flash_data(ha, dcode, ha->flt_region_fw + 4, 4);
2562         for (i = 0; i < 4; i++)
2563                 dcode[i] = be32_to_cpu(dcode[i]);
2564
2565         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2566             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2567             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2568             dcode[3] == 0)) {
2569                 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n",
2570                     __func__, ha->flt_region_fw));
2571         } else {
2572                 ha->fw_revision[0] = dcode[0];
2573                 ha->fw_revision[1] = dcode[1];
2574                 ha->fw_revision[2] = dcode[2];
2575                 ha->fw_revision[3] = dcode[3];
2576         }
2577
2578         return ret;
2579 }
2580
2581 static int
2582 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2583 {
2584         if (pos >= end || *pos != 0x82)
2585                 return 0;
2586
2587         pos += 3 + pos[1];
2588         if (pos >= end || *pos != 0x90)
2589                 return 0;
2590
2591         pos += 3 + pos[1];
2592         if (pos >= end || *pos != 0x78)
2593                 return 0;
2594
2595         return 1;
2596 }
2597
2598 int
2599 qla2xxx_get_vpd_field(scsi_qla_host_t *ha, char *key, char *str, size_t size)
2600 {
2601         uint8_t *pos = ha->vpd;
2602         uint8_t *end = pos + ha->vpd_size;
2603         int len = 0;
2604
2605         if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2606                 return 0;
2607
2608         while (pos < end && *pos != 0x78) {
2609                 len = (*pos == 0x82) ? pos[1] : pos[2];
2610
2611                 if (!strncmp(pos, key, strlen(key)))
2612                         break;
2613
2614                 if (*pos != 0x90 && *pos != 0x91)
2615                         pos += len;
2616
2617                 pos += 3;
2618         }
2619
2620         if (pos < end - len && *pos != 0x78)
2621                 return snprintf(str, size, "%.*s", len, pos + 3);
2622
2623         return 0;
2624 }
2625
2626 static int
2627 qla2xxx_hw_event_store(scsi_qla_host_t *ha, uint32_t *fdata)
2628 {
2629         uint32_t d[2], faddr;
2630
2631         /* Locate first empty entry. */
2632         for (;;) {
2633                 if (ha->hw_event_ptr >=
2634                     ha->flt_region_hw_event + FA_HW_EVENT_SIZE) {
2635                         DEBUG2(qla_printk(KERN_WARNING, ha,
2636                             "HW event -- Log Full!\n"));
2637                         return QLA_MEMORY_ALLOC_FAILED;
2638                 }
2639
2640                 qla24xx_read_flash_data(ha, d, ha->hw_event_ptr, 2);
2641                 faddr = flash_data_to_access_addr(ha->hw_event_ptr);
2642                 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2643                 if (d[0] == __constant_cpu_to_le32(0xffffffff) &&
2644                     d[1] == __constant_cpu_to_le32(0xffffffff)) {
2645                         qla24xx_unprotect_flash(ha);
2646
2647                         qla24xx_write_flash_dword(ha, faddr++,
2648                             cpu_to_le32(jiffies));
2649                         qla24xx_write_flash_dword(ha, faddr++, 0);
2650                         qla24xx_write_flash_dword(ha, faddr++, *fdata++);
2651                         qla24xx_write_flash_dword(ha, faddr++, *fdata);
2652
2653                         qla24xx_protect_flash(ha);
2654                         break;
2655                 }
2656         }
2657         return QLA_SUCCESS;
2658 }
2659
2660 int
2661 qla2xxx_hw_event_log(scsi_qla_host_t *ha, uint16_t code, uint16_t d1,
2662     uint16_t d2, uint16_t d3)
2663 {
2664 #define QMARK(a, b, c, d) \
2665     cpu_to_le32(LSB(a) << 24 | LSB(b) << 16 | LSB(c) << 8 | LSB(d))
2666
2667         int rval;
2668         uint32_t marker[2], fdata[4];
2669
2670         if (ha->flt_region_hw_event == 0)
2671                 return QLA_FUNCTION_FAILED;
2672
2673         DEBUG2(qla_printk(KERN_WARNING, ha,
2674             "HW event -- code=%x, d1=%x, d2=%x, d3=%x.\n", code, d1, d2, d3));
2675
2676         /* If marker not already found, locate or write.  */
2677         if (!ha->flags.hw_event_marker_found) {
2678                 /* Create marker. */
2679                 marker[0] = QMARK('L', ha->fw_major_version,
2680                     ha->fw_minor_version, ha->fw_subminor_version);
2681                 marker[1] = QMARK(QLA_DRIVER_MAJOR_VER, QLA_DRIVER_MINOR_VER,
2682                     QLA_DRIVER_PATCH_VER, QLA_DRIVER_BETA_VER);
2683
2684                 /* Locate marker. */
2685                 ha->hw_event_ptr = ha->flt_region_hw_event;
2686                 for (;;) {
2687                         qla24xx_read_flash_data(ha, fdata, ha->hw_event_ptr,
2688                             4);
2689                         if (fdata[0] == __constant_cpu_to_le32(0xffffffff) &&
2690                             fdata[1] == __constant_cpu_to_le32(0xffffffff))
2691                                 break;
2692                         ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2693                         if (ha->hw_event_ptr >=
2694                             ha->flt_region_hw_event + FA_HW_EVENT_SIZE) {
2695                                 DEBUG2(qla_printk(KERN_WARNING, ha,
2696                                     "HW event -- Log Full!\n"));
2697                                 return QLA_MEMORY_ALLOC_FAILED;
2698                         }
2699                         if (fdata[2] == marker[0] && fdata[3] == marker[1]) {
2700                                 ha->flags.hw_event_marker_found = 1;
2701                                 break;
2702                         }
2703                 }
2704                 /* No marker, write it. */
2705                 if (!ha->flags.hw_event_marker_found) {
2706                         rval = qla2xxx_hw_event_store(ha, marker);
2707                         if (rval != QLA_SUCCESS) {
2708                                 DEBUG2(qla_printk(KERN_WARNING, ha,
2709                                     "HW event -- Failed marker write=%x.!\n",
2710                                     rval));
2711                                 return rval;
2712                         }
2713                         ha->flags.hw_event_marker_found = 1;
2714                 }
2715         }
2716
2717         /* Store error.  */
2718         fdata[0] = cpu_to_le32(code << 16 | d1);
2719         fdata[1] = cpu_to_le32(d2 << 16 | d3);
2720         rval = qla2xxx_hw_event_store(ha, fdata);
2721         if (rval != QLA_SUCCESS) {
2722                 DEBUG2(qla_printk(KERN_WARNING, ha,
2723                     "HW event -- Failed error write=%x.!\n",
2724                     rval));
2725         }
2726
2727         return rval;
2728 }