2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "1.01"
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
58 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_CMD_TBL_HDR = 0x80,
61 AHCI_CMD_TBL_CDB = 0x40,
62 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
63 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_IRQ_ON_SG = (1 << 31),
66 AHCI_CMD_ATAPI = (1 << 5),
67 AHCI_CMD_WRITE = (1 << 6),
69 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
73 /* global controller registers */
74 HOST_CAP = 0x00, /* host capabilities */
75 HOST_CTL = 0x04, /* global host control */
76 HOST_IRQ_STAT = 0x08, /* interrupt status */
77 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
78 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
81 HOST_RESET = (1 << 0), /* reset controller; self-clear */
82 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
83 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
86 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
88 /* registers for each SATA port */
89 PORT_LST_ADDR = 0x00, /* command list DMA addr */
90 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
91 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
92 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
93 PORT_IRQ_STAT = 0x10, /* interrupt status */
94 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
95 PORT_CMD = 0x18, /* port command */
96 PORT_TFDATA = 0x20, /* taskfile data */
97 PORT_SIG = 0x24, /* device TF signature */
98 PORT_CMD_ISSUE = 0x38, /* command issue */
99 PORT_SCR = 0x28, /* SATA phy register block */
100 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
101 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
102 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
103 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
105 /* PORT_IRQ_{STAT,MASK} bits */
106 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
107 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
108 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
109 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
110 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
111 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
112 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
113 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
115 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
116 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
117 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
118 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
119 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
120 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
121 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
122 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
123 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
125 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
127 PORT_IRQ_HBUS_DATA_ERR |
129 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
130 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
131 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
132 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
133 PORT_IRQ_D2H_REG_FIS,
136 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
137 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
138 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
139 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
140 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
141 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
143 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
144 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
145 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
147 /* hpriv->flags bits */
148 AHCI_FLAG_MSI = (1 << 0),
151 struct ahci_cmd_hdr {
166 struct ahci_host_priv {
168 u32 cap; /* cache of HOST_CAP register */
169 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
172 struct ahci_port_priv {
173 struct ahci_cmd_hdr *cmd_slot;
174 dma_addr_t cmd_slot_dma;
176 dma_addr_t cmd_tbl_dma;
177 struct ahci_sg *cmd_tbl_sg;
179 dma_addr_t rx_fis_dma;
182 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
183 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
184 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
185 static int ahci_qc_issue(struct ata_queued_cmd *qc);
186 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
187 static void ahci_phy_reset(struct ata_port *ap);
188 static void ahci_irq_clear(struct ata_port *ap);
189 static void ahci_eng_timeout(struct ata_port *ap);
190 static int ahci_port_start(struct ata_port *ap);
191 static void ahci_port_stop(struct ata_port *ap);
192 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
193 static void ahci_qc_prep(struct ata_queued_cmd *qc);
194 static u8 ahci_check_status(struct ata_port *ap);
195 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
196 static void ahci_remove_one (struct pci_dev *pdev);
198 static Scsi_Host_Template ahci_sht = {
199 .module = THIS_MODULE,
201 .ioctl = ata_scsi_ioctl,
202 .queuecommand = ata_scsi_queuecmd,
203 .eh_strategy_handler = ata_scsi_error,
204 .can_queue = ATA_DEF_QUEUE,
205 .this_id = ATA_SHT_THIS_ID,
206 .sg_tablesize = AHCI_MAX_SG,
207 .max_sectors = ATA_MAX_SECTORS,
208 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
209 .emulated = ATA_SHT_EMULATED,
210 .use_clustering = AHCI_USE_CLUSTERING,
211 .proc_name = DRV_NAME,
212 .dma_boundary = AHCI_DMA_BOUNDARY,
213 .slave_configure = ata_scsi_slave_config,
214 .bios_param = ata_std_bios_param,
218 static const struct ata_port_operations ahci_ops = {
219 .port_disable = ata_port_disable,
221 .check_status = ahci_check_status,
222 .check_altstatus = ahci_check_status,
223 .dev_select = ata_noop_dev_select,
225 .tf_read = ahci_tf_read,
227 .phy_reset = ahci_phy_reset,
229 .qc_prep = ahci_qc_prep,
230 .qc_issue = ahci_qc_issue,
232 .eng_timeout = ahci_eng_timeout,
234 .irq_handler = ahci_interrupt,
235 .irq_clear = ahci_irq_clear,
237 .scr_read = ahci_scr_read,
238 .scr_write = ahci_scr_write,
240 .port_start = ahci_port_start,
241 .port_stop = ahci_port_stop,
244 static struct ata_port_info ahci_port_info[] = {
248 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
249 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
251 .pio_mask = 0x1f, /* pio0-4 */
252 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
253 .port_ops = &ahci_ops,
257 static struct pci_device_id ahci_pci_tbl[] = {
258 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
259 board_ahci }, /* ICH6 */
260 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_ahci }, /* ICH6M */
262 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ICH7 */
264 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH7M */
266 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH7R */
268 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ULi M5288 */
270 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ESB2 */
272 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ESB2 */
274 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ESB2 */
276 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ICH7-M DH */
278 { } /* terminate list */
282 static struct pci_driver ahci_pci_driver = {
284 .id_table = ahci_pci_tbl,
285 .probe = ahci_init_one,
286 .remove = ahci_remove_one,
290 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
292 return base + 0x100 + (port * 0x80);
295 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
297 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
300 static int ahci_port_start(struct ata_port *ap)
302 struct device *dev = ap->host_set->dev;
303 struct ahci_host_priv *hpriv = ap->host_set->private_data;
304 struct ahci_port_priv *pp;
305 void __iomem *mmio = ap->host_set->mmio_base;
306 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
310 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
313 memset(pp, 0, sizeof(*pp));
315 ap->pad = dma_alloc_coherent(dev, ATA_DMA_PAD_BUF_SZ, &ap->pad_dma, GFP_KERNEL);
321 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
323 dma_free_coherent(dev, ATA_DMA_PAD_BUF_SZ, ap->pad, ap->pad_dma);
327 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
330 * First item in chunk of DMA memory: 32-slot command table,
331 * 32 bytes each in size
334 pp->cmd_slot_dma = mem_dma;
336 mem += AHCI_CMD_SLOT_SZ;
337 mem_dma += AHCI_CMD_SLOT_SZ;
340 * Second item: Received-FIS area
343 pp->rx_fis_dma = mem_dma;
345 mem += AHCI_RX_FIS_SZ;
346 mem_dma += AHCI_RX_FIS_SZ;
349 * Third item: data area for storing a single command
350 * and its scatter-gather table
353 pp->cmd_tbl_dma = mem_dma;
355 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
357 ap->private_data = pp;
359 if (hpriv->cap & HOST_CAP_64)
360 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
361 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
362 readl(port_mmio + PORT_LST_ADDR); /* flush */
364 if (hpriv->cap & HOST_CAP_64)
365 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
366 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
367 readl(port_mmio + PORT_FIS_ADDR); /* flush */
369 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
370 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
371 PORT_CMD_START, port_mmio + PORT_CMD);
372 readl(port_mmio + PORT_CMD); /* flush */
378 static void ahci_port_stop(struct ata_port *ap)
380 struct device *dev = ap->host_set->dev;
381 struct ahci_port_priv *pp = ap->private_data;
382 void __iomem *mmio = ap->host_set->mmio_base;
383 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
386 tmp = readl(port_mmio + PORT_CMD);
387 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
388 writel(tmp, port_mmio + PORT_CMD);
389 readl(port_mmio + PORT_CMD); /* flush */
391 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
392 * this is slightly incorrect.
396 ap->private_data = NULL;
397 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
398 pp->cmd_slot, pp->cmd_slot_dma);
399 dma_free_coherent(dev, ATA_DMA_PAD_BUF_SZ, ap->pad, ap->pad_dma);
403 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
408 case SCR_STATUS: sc_reg = 0; break;
409 case SCR_CONTROL: sc_reg = 1; break;
410 case SCR_ERROR: sc_reg = 2; break;
411 case SCR_ACTIVE: sc_reg = 3; break;
416 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
420 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
426 case SCR_STATUS: sc_reg = 0; break;
427 case SCR_CONTROL: sc_reg = 1; break;
428 case SCR_ERROR: sc_reg = 2; break;
429 case SCR_ACTIVE: sc_reg = 3; break;
434 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
437 static void ahci_phy_reset(struct ata_port *ap)
439 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
440 struct ata_taskfile tf;
441 struct ata_device *dev = &ap->device[0];
444 __sata_phy_reset(ap);
446 if (ap->flags & ATA_FLAG_PORT_DISABLED)
449 tmp = readl(port_mmio + PORT_SIG);
450 tf.lbah = (tmp >> 24) & 0xff;
451 tf.lbam = (tmp >> 16) & 0xff;
452 tf.lbal = (tmp >> 8) & 0xff;
453 tf.nsect = (tmp) & 0xff;
455 dev->class = ata_dev_classify(&tf);
456 if (!ata_dev_present(dev))
457 ata_port_disable(ap);
460 static u8 ahci_check_status(struct ata_port *ap)
462 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
464 return readl(mmio + PORT_TFDATA) & 0xFF;
467 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
469 struct ahci_port_priv *pp = ap->private_data;
470 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
472 ata_tf_from_fis(d2h_fis, tf);
475 static void ahci_fill_sg(struct ata_queued_cmd *qc)
477 struct ahci_port_priv *pp = qc->ap->private_data;
478 struct scatterlist *sg;
479 struct ahci_sg *ahci_sg;
484 * Next, the S/G list.
486 ahci_sg = pp->cmd_tbl_sg;
487 ata_for_each_sg(sg, qc) {
488 dma_addr_t addr = sg_dma_address(sg);
489 u32 sg_len = sg_dma_len(sg);
491 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
492 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
493 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
498 static void ahci_qc_prep(struct ata_queued_cmd *qc)
500 struct ata_port *ap = qc->ap;
501 struct ahci_port_priv *pp = ap->private_data;
503 const u32 cmd_fis_len = 5; /* five dwords */
506 * Fill in command slot information (currently only one slot,
507 * slot 0, is currently since we don't do queueing)
510 opts = (qc->n_elem << 16) | cmd_fis_len;
511 if (qc->tf.flags & ATA_TFLAG_WRITE)
512 opts |= AHCI_CMD_WRITE;
513 if (is_atapi_taskfile(&qc->tf))
514 opts |= AHCI_CMD_ATAPI;
516 pp->cmd_slot[0].opts = cpu_to_le32(opts);
517 pp->cmd_slot[0].status = 0;
518 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
519 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
522 * Fill in command table information. First, the header,
523 * a SATA Register - Host to Device command FIS.
525 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
526 if (opts & AHCI_CMD_ATAPI) {
527 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
528 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
531 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
537 static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
539 void __iomem *mmio = ap->host_set->mmio_base;
540 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
545 tmp = readl(port_mmio + PORT_CMD);
546 tmp &= ~PORT_CMD_START;
547 writel(tmp, port_mmio + PORT_CMD);
549 /* wait for engine to stop. TODO: this could be
550 * as long as 500 msec
554 tmp = readl(port_mmio + PORT_CMD);
555 if ((tmp & PORT_CMD_LIST_ON) == 0)
560 /* clear SATA phy error, if any */
561 tmp = readl(port_mmio + PORT_SCR_ERR);
562 writel(tmp, port_mmio + PORT_SCR_ERR);
564 /* if DRQ/BSY is set, device needs to be reset.
565 * if so, issue COMRESET
567 tmp = readl(port_mmio + PORT_TFDATA);
568 if (tmp & (ATA_BUSY | ATA_DRQ)) {
569 writel(0x301, port_mmio + PORT_SCR_CTL);
570 readl(port_mmio + PORT_SCR_CTL); /* flush */
572 writel(0x300, port_mmio + PORT_SCR_CTL);
573 readl(port_mmio + PORT_SCR_CTL); /* flush */
577 tmp = readl(port_mmio + PORT_CMD);
578 tmp |= PORT_CMD_START;
579 writel(tmp, port_mmio + PORT_CMD);
580 readl(port_mmio + PORT_CMD); /* flush */
582 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
585 static void ahci_eng_timeout(struct ata_port *ap)
587 struct ata_host_set *host_set = ap->host_set;
588 void __iomem *mmio = host_set->mmio_base;
589 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
590 struct ata_queued_cmd *qc;
595 spin_lock_irqsave(&host_set->lock, flags);
597 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
599 qc = ata_qc_from_tag(ap, ap->active_tag);
601 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
604 /* hack alert! We cannot use the supplied completion
605 * function from inside the ->eh_strategy_handler() thread.
606 * libata is the only user of ->eh_strategy_handler() in
607 * any kernel, so the default scsi_done() assumes it is
608 * not being called from the SCSI EH.
610 qc->scsidone = scsi_finish_command;
611 ata_qc_complete(qc, ATA_ERR);
614 spin_unlock_irqrestore(&host_set->lock, flags);
617 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
619 void __iomem *mmio = ap->host_set->mmio_base;
620 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
621 u32 status, serr, ci;
623 serr = readl(port_mmio + PORT_SCR_ERR);
624 writel(serr, port_mmio + PORT_SCR_ERR);
626 status = readl(port_mmio + PORT_IRQ_STAT);
627 writel(status, port_mmio + PORT_IRQ_STAT);
629 ci = readl(port_mmio + PORT_CMD_ISSUE);
630 if (likely((ci & 0x1) == 0)) {
632 ata_qc_complete(qc, 0);
637 if (status & PORT_IRQ_FATAL) {
638 ahci_intr_error(ap, status);
640 ata_qc_complete(qc, ATA_ERR);
646 static void ahci_irq_clear(struct ata_port *ap)
651 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
653 struct ata_host_set *host_set = dev_instance;
654 struct ahci_host_priv *hpriv;
655 unsigned int i, handled = 0;
657 u32 irq_stat, irq_ack = 0;
661 hpriv = host_set->private_data;
662 mmio = host_set->mmio_base;
664 /* sigh. 0xffffffff is a valid return from h/w */
665 irq_stat = readl(mmio + HOST_IRQ_STAT);
666 irq_stat &= hpriv->port_map;
670 spin_lock(&host_set->lock);
672 for (i = 0; i < host_set->n_ports; i++) {
675 if (!(irq_stat & (1 << i)))
678 ap = host_set->ports[i];
680 struct ata_queued_cmd *qc;
681 qc = ata_qc_from_tag(ap, ap->active_tag);
682 if (!ahci_host_intr(ap, qc))
683 if (ata_ratelimit()) {
684 struct pci_dev *pdev =
685 to_pci_dev(ap->host_set->dev);
687 "ahci(%s): unhandled interrupt on port %u\n",
691 VPRINTK("port %u\n", i);
693 VPRINTK("port %u (no irq)\n", i);
694 if (ata_ratelimit()) {
695 struct pci_dev *pdev =
696 to_pci_dev(ap->host_set->dev);
698 "ahci(%s): interrupt on disabled port %u\n",
707 writel(irq_ack, mmio + HOST_IRQ_STAT);
711 spin_unlock(&host_set->lock);
715 return IRQ_RETVAL(handled);
718 static int ahci_qc_issue(struct ata_queued_cmd *qc)
720 struct ata_port *ap = qc->ap;
721 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
723 writel(1, port_mmio + PORT_CMD_ISSUE);
724 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
729 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
730 unsigned int port_idx)
732 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
733 base = ahci_port_base_ul(base, port_idx);
734 VPRINTK("base now==0x%lx\n", base);
736 port->cmd_addr = base;
737 port->scr_addr = base + PORT_SCR;
742 static int ahci_host_init(struct ata_probe_ent *probe_ent)
744 struct ahci_host_priv *hpriv = probe_ent->private_data;
745 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
746 void __iomem *mmio = probe_ent->mmio_base;
749 unsigned int i, j, using_dac;
751 void __iomem *port_mmio;
753 cap_save = readl(mmio + HOST_CAP);
754 cap_save &= ( (1<<28) | (1<<17) );
755 cap_save |= (1 << 27);
757 /* global controller reset */
758 tmp = readl(mmio + HOST_CTL);
759 if ((tmp & HOST_RESET) == 0) {
760 writel(tmp | HOST_RESET, mmio + HOST_CTL);
761 readl(mmio + HOST_CTL); /* flush */
764 /* reset must complete within 1 second, or
765 * the hardware should be considered fried.
769 tmp = readl(mmio + HOST_CTL);
770 if (tmp & HOST_RESET) {
771 printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",
772 pci_name(pdev), tmp);
776 writel(HOST_AHCI_EN, mmio + HOST_CTL);
777 (void) readl(mmio + HOST_CTL); /* flush */
778 writel(cap_save, mmio + HOST_CAP);
779 writel(0xf, mmio + HOST_PORTS_IMPL);
780 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
782 pci_read_config_word(pdev, 0x92, &tmp16);
784 pci_write_config_word(pdev, 0x92, tmp16);
786 hpriv->cap = readl(mmio + HOST_CAP);
787 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
788 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
790 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
791 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
793 using_dac = hpriv->cap & HOST_CAP_64;
795 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
796 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
798 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
800 printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",
806 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
808 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
812 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
814 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
820 for (i = 0; i < probe_ent->n_ports; i++) {
821 #if 0 /* BIOSen initialize this incorrectly */
822 if (!(hpriv->port_map & (1 << i)))
826 port_mmio = ahci_port_base(mmio, i);
827 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
829 ahci_setup_port(&probe_ent->port[i],
830 (unsigned long) mmio, i);
832 /* make sure port is not active */
833 tmp = readl(port_mmio + PORT_CMD);
834 VPRINTK("PORT_CMD 0x%x\n", tmp);
835 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
836 PORT_CMD_FIS_RX | PORT_CMD_START)) {
837 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
838 PORT_CMD_FIS_RX | PORT_CMD_START);
839 writel(tmp, port_mmio + PORT_CMD);
840 readl(port_mmio + PORT_CMD); /* flush */
842 /* spec says 500 msecs for each bit, so
843 * this is slightly incorrect.
848 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
853 tmp = readl(port_mmio + PORT_SCR_STAT);
854 if ((tmp & 0xf) == 0x3)
859 tmp = readl(port_mmio + PORT_SCR_ERR);
860 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
861 writel(tmp, port_mmio + PORT_SCR_ERR);
863 /* ack any pending irq events for this port */
864 tmp = readl(port_mmio + PORT_IRQ_STAT);
865 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
867 writel(tmp, port_mmio + PORT_IRQ_STAT);
869 writel(1 << i, mmio + HOST_IRQ_STAT);
871 /* set irq mask (enables interrupts) */
872 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
875 tmp = readl(mmio + HOST_CTL);
876 VPRINTK("HOST_CTL 0x%x\n", tmp);
877 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
878 tmp = readl(mmio + HOST_CTL);
879 VPRINTK("HOST_CTL 0x%x\n", tmp);
881 pci_set_master(pdev);
886 static void ahci_print_info(struct ata_probe_ent *probe_ent)
888 struct ahci_host_priv *hpriv = probe_ent->private_data;
889 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
890 void __iomem *mmio = probe_ent->mmio_base;
891 u32 vers, cap, impl, speed;
896 vers = readl(mmio + HOST_VERSION);
898 impl = hpriv->port_map;
900 speed = (cap >> 20) & 0xf;
908 pci_read_config_word(pdev, 0x0a, &cc);
911 else if (cc == 0x0106)
913 else if (cc == 0x0104)
918 printk(KERN_INFO DRV_NAME "(%s) AHCI %02x%02x.%02x%02x "
919 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
928 ((cap >> 8) & 0x1f) + 1,
934 printk(KERN_INFO DRV_NAME "(%s) flags: "
940 cap & (1 << 31) ? "64bit " : "",
941 cap & (1 << 30) ? "ncq " : "",
942 cap & (1 << 28) ? "ilck " : "",
943 cap & (1 << 27) ? "stag " : "",
944 cap & (1 << 26) ? "pm " : "",
945 cap & (1 << 25) ? "led " : "",
947 cap & (1 << 24) ? "clo " : "",
948 cap & (1 << 19) ? "nz " : "",
949 cap & (1 << 18) ? "only " : "",
950 cap & (1 << 17) ? "pmp " : "",
951 cap & (1 << 15) ? "pio " : "",
952 cap & (1 << 14) ? "slum " : "",
953 cap & (1 << 13) ? "part " : ""
957 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
959 static int printed_version;
960 struct ata_probe_ent *probe_ent = NULL;
961 struct ahci_host_priv *hpriv;
963 void __iomem *mmio_base;
964 unsigned int board_idx = (unsigned int) ent->driver_data;
965 int have_msi, pci_dev_busy = 0;
970 if (!printed_version++)
971 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
973 rc = pci_enable_device(pdev);
977 rc = pci_request_regions(pdev, DRV_NAME);
983 if (pci_enable_msi(pdev) == 0)
990 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
991 if (probe_ent == NULL) {
996 memset(probe_ent, 0, sizeof(*probe_ent));
997 probe_ent->dev = pci_dev_to_dev(pdev);
998 INIT_LIST_HEAD(&probe_ent->node);
1000 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1001 if (mmio_base == NULL) {
1003 goto err_out_free_ent;
1005 base = (unsigned long) mmio_base;
1007 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1010 goto err_out_iounmap;
1012 memset(hpriv, 0, sizeof(*hpriv));
1014 probe_ent->sht = ahci_port_info[board_idx].sht;
1015 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1016 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1017 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1018 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1020 probe_ent->irq = pdev->irq;
1021 probe_ent->irq_flags = SA_SHIRQ;
1022 probe_ent->mmio_base = mmio_base;
1023 probe_ent->private_data = hpriv;
1026 hpriv->flags |= AHCI_FLAG_MSI;
1028 /* initialize adapter */
1029 rc = ahci_host_init(probe_ent);
1033 ahci_print_info(probe_ent);
1035 /* FIXME: check ata_device_add return value */
1036 ata_device_add(probe_ent);
1044 pci_iounmap(pdev, mmio_base);
1049 pci_disable_msi(pdev);
1052 pci_release_regions(pdev);
1055 pci_disable_device(pdev);
1059 static void ahci_remove_one (struct pci_dev *pdev)
1061 struct device *dev = pci_dev_to_dev(pdev);
1062 struct ata_host_set *host_set = dev_get_drvdata(dev);
1063 struct ahci_host_priv *hpriv = host_set->private_data;
1064 struct ata_port *ap;
1068 for (i = 0; i < host_set->n_ports; i++) {
1069 ap = host_set->ports[i];
1071 scsi_remove_host(ap->host);
1074 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1075 free_irq(host_set->irq, host_set);
1077 for (i = 0; i < host_set->n_ports; i++) {
1078 ap = host_set->ports[i];
1080 ata_scsi_release(ap->host);
1081 scsi_host_put(ap->host);
1085 pci_iounmap(pdev, host_set->mmio_base);
1089 pci_disable_msi(pdev);
1092 pci_release_regions(pdev);
1093 pci_disable_device(pdev);
1094 dev_set_drvdata(dev, NULL);
1097 static int __init ahci_init(void)
1099 return pci_module_init(&ahci_pci_driver);
1102 static void __exit ahci_exit(void)
1104 pci_unregister_driver(&ahci_pci_driver);
1108 MODULE_AUTHOR("Jeff Garzik");
1109 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1110 MODULE_LICENSE("GPL");
1111 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1112 MODULE_VERSION(DRV_VERSION);
1114 module_init(ahci_init);
1115 module_exit(ahci_exit);