2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17 #define PCI_CFG_SPACE_SIZE 256
18 #define PCI_CFG_SPACE_EXP_SIZE 4096
20 /* Ugh. Need to stop exporting this to modules. */
21 LIST_HEAD(pci_root_buses);
22 EXPORT_SYMBOL(pci_root_buses);
25 static int find_anything(struct device *dev, void *data)
31 * Some device drivers need know if pci is initiated.
32 * Basically, we think pci is not initiated when there
33 * is no device to be found on the pci_bus_type.
35 int no_pci_devices(void)
40 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
41 no_devices = (dev == NULL);
45 EXPORT_SYMBOL(no_pci_devices);
47 #ifdef HAVE_PCI_LEGACY
49 * pci_create_legacy_files - create legacy I/O port and memory files
50 * @b: bus to create files under
52 * Some platforms allow access to legacy I/O port and ISA memory space on
53 * a per-bus basis. This routine creates the files and ties them into
54 * their associated read, write and mmap files from pci-sysfs.c
56 static void pci_create_legacy_files(struct pci_bus *b)
58 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
61 b->legacy_io->attr.name = "legacy_io";
62 b->legacy_io->size = 0xffff;
63 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
64 b->legacy_io->read = pci_read_legacy_io;
65 b->legacy_io->write = pci_write_legacy_io;
66 device_create_bin_file(&b->dev, b->legacy_io);
68 /* Allocated above after the legacy_io struct */
69 b->legacy_mem = b->legacy_io + 1;
70 b->legacy_mem->attr.name = "legacy_mem";
71 b->legacy_mem->size = 1024*1024;
72 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
73 b->legacy_mem->mmap = pci_mmap_legacy_mem;
74 device_create_bin_file(&b->dev, b->legacy_mem);
78 void pci_remove_legacy_files(struct pci_bus *b)
81 device_remove_bin_file(&b->dev, b->legacy_io);
82 device_remove_bin_file(&b->dev, b->legacy_mem);
83 kfree(b->legacy_io); /* both are allocated here */
86 #else /* !HAVE_PCI_LEGACY */
87 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
88 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
89 #endif /* HAVE_PCI_LEGACY */
92 * PCI Bus Class Devices
94 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
95 struct device_attribute *attr,
101 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
102 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
107 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
112 static void release_pcibus_dev(struct device *dev)
114 struct pci_bus *pci_bus = to_pci_bus(dev);
117 put_device(pci_bus->bridge);
121 static struct class pcibus_class = {
123 .dev_release = &release_pcibus_dev,
126 static int __init pcibus_class_init(void)
128 return class_register(&pcibus_class);
130 postcore_initcall(pcibus_class_init);
133 * Translate the low bits of the PCI base
134 * to the resource type
136 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
138 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
139 return IORESOURCE_IO;
141 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
142 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
144 return IORESOURCE_MEM;
148 * Find the extent of a PCI decode..
150 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
152 u32 size = mask & maxbase; /* Find the significant bits */
156 /* Get the lowest of them to find the decode size, and
157 from that the extent. */
158 size = (size & ~(size-1)) - 1;
160 /* base == maxbase can be valid only if the BAR has
161 already been programmed with all 1s. */
162 if (base == maxbase && ((base | size) & mask) != mask)
168 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
170 u64 size = mask & maxbase; /* Find the significant bits */
174 /* Get the lowest of them to find the decode size, and
175 from that the extent. */
176 size = (size & ~(size-1)) - 1;
178 /* base == maxbase can be valid only if the BAR has
179 already been programmed with all 1s. */
180 if (base == maxbase && ((base | size) & mask) != mask)
186 static inline int is_64bit_memory(u32 mask)
188 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
189 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
194 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
196 unsigned int pos, reg, next;
198 struct resource *res;
200 for(pos=0; pos<howmany; pos = next) {
206 res = &dev->resource[pos];
207 res->name = pci_name(dev);
208 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
209 pci_read_config_dword(dev, reg, &l);
210 pci_write_config_dword(dev, reg, ~0);
211 pci_read_config_dword(dev, reg, &sz);
212 pci_write_config_dword(dev, reg, l);
213 if (!sz || sz == 0xffffffff)
218 if ((l & PCI_BASE_ADDRESS_SPACE) ==
219 PCI_BASE_ADDRESS_SPACE_MEMORY) {
220 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
222 * For 64bit prefetchable memory sz could be 0, if the
223 * real size is bigger than 4G, so we need to check
226 if (!is_64bit_memory(l) && !sz)
228 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
229 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
231 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
234 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
235 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
237 res->end = res->start + (unsigned long) sz;
238 res->flags |= pci_calc_resource_flags(l);
239 if (is_64bit_memory(l)) {
242 pci_read_config_dword(dev, reg+4, &lhi);
243 pci_write_config_dword(dev, reg+4, ~0);
244 pci_read_config_dword(dev, reg+4, &szhi);
245 pci_write_config_dword(dev, reg+4, lhi);
246 sz64 = ((u64)szhi << 32) | raw_sz;
247 l64 = ((u64)lhi << 32) | l;
248 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
250 #if BITS_PER_LONG == 64
257 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
258 res->end = res->start + sz64;
260 if (sz64 > 0x100000000ULL) {
261 printk(KERN_ERR "PCI: Unable to handle 64-bit "
262 "BAR for device %s\n", pci_name(dev));
266 /* 64-bit wide address, treat as disabled */
267 pci_write_config_dword(dev, reg,
268 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
269 pci_write_config_dword(dev, reg+4, 0);
277 dev->rom_base_reg = rom;
278 res = &dev->resource[PCI_ROM_RESOURCE];
279 res->name = pci_name(dev);
280 pci_read_config_dword(dev, rom, &l);
281 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
282 pci_read_config_dword(dev, rom, &sz);
283 pci_write_config_dword(dev, rom, l);
286 if (sz && sz != 0xffffffff) {
287 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
289 res->flags = (l & IORESOURCE_ROM_ENABLE) |
290 IORESOURCE_MEM | IORESOURCE_PREFETCH |
291 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
292 res->start = l & PCI_ROM_ADDRESS_MASK;
293 res->end = res->start + (unsigned long) sz;
299 void __devinit pci_read_bridge_bases(struct pci_bus *child)
301 struct pci_dev *dev = child->self;
302 u8 io_base_lo, io_limit_lo;
303 u16 mem_base_lo, mem_limit_lo;
304 unsigned long base, limit;
305 struct resource *res;
308 if (!dev) /* It's a host bus, nothing to read */
311 if (dev->transparent) {
312 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
313 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
314 child->resource[i] = child->parent->resource[i - 3];
318 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
320 res = child->resource[0];
321 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
322 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
323 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
324 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
326 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
327 u16 io_base_hi, io_limit_hi;
328 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
329 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
330 base |= (io_base_hi << 16);
331 limit |= (io_limit_hi << 16);
335 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
339 res->end = limit + 0xfff;
342 res = child->resource[1];
343 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
344 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
345 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
346 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
348 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
350 res->end = limit + 0xfffff;
353 res = child->resource[2];
354 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
355 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
356 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
357 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
359 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
360 u32 mem_base_hi, mem_limit_hi;
361 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
362 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
365 * Some bridges set the base > limit by default, and some
366 * (broken) BIOSes do not initialize them. If we find
367 * this, just assume they are not being used.
369 if (mem_base_hi <= mem_limit_hi) {
370 #if BITS_PER_LONG == 64
371 base |= ((long) mem_base_hi) << 32;
372 limit |= ((long) mem_limit_hi) << 32;
374 if (mem_base_hi || mem_limit_hi) {
375 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
382 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
384 res->end = limit + 0xfffff;
388 static struct pci_bus * pci_alloc_bus(void)
392 b = kzalloc(sizeof(*b), GFP_KERNEL);
394 INIT_LIST_HEAD(&b->node);
395 INIT_LIST_HEAD(&b->children);
396 INIT_LIST_HEAD(&b->devices);
401 static struct pci_bus * __devinit
402 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
404 struct pci_bus *child;
408 * Allocate a new bus, and inherit stuff from the parent..
410 child = pci_alloc_bus();
414 child->self = bridge;
415 child->parent = parent;
416 child->ops = parent->ops;
417 child->sysdata = parent->sysdata;
418 child->bus_flags = parent->bus_flags;
419 child->bridge = get_device(&bridge->dev);
421 /* initialize some portions of the bus device, but don't register it
422 * now as the parent is not properly set up yet. This device will get
423 * registered later in pci_bus_add_devices()
425 child->dev.class = &pcibus_class;
426 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
429 * Set up the primary, secondary and subordinate
432 child->number = child->secondary = busnr;
433 child->primary = parent->secondary;
434 child->subordinate = 0xff;
436 /* Set up default resource pointers and names.. */
437 for (i = 0; i < 4; i++) {
438 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
439 child->resource[i]->name = child->name;
441 bridge->subordinate = child;
446 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
448 struct pci_bus *child;
450 child = pci_alloc_child_bus(parent, dev, busnr);
452 down_write(&pci_bus_sem);
453 list_add_tail(&child->node, &parent->children);
454 up_write(&pci_bus_sem);
459 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
461 struct pci_bus *parent = child->parent;
463 /* Attempts to fix that up are really dangerous unless
464 we're going to re-assign all bus numbers. */
465 if (!pcibios_assign_all_busses())
468 while (parent->parent && parent->subordinate < max) {
469 parent->subordinate = max;
470 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
471 parent = parent->parent;
476 * If it's a bridge, configure it and scan the bus behind it.
477 * For CardBus bridges, we don't scan behind as the devices will
478 * be handled by the bridge driver itself.
480 * We need to process bridges in two passes -- first we scan those
481 * already configured by the BIOS and after we are done with all of
482 * them, we proceed to assigning numbers to the remaining buses in
483 * order to avoid overlaps between old and new bus numbers.
485 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
487 struct pci_bus *child;
488 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
492 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
494 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
495 pci_name(dev), buses & 0xffffff, pass);
497 /* Disable MasterAbortMode during probing to avoid reporting
498 of bus errors (in some architectures) */
499 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
500 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
501 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
503 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
504 unsigned int cmax, busnr;
506 * Bus already configured by firmware, process it in the first
507 * pass and just note the configuration.
511 busnr = (buses >> 8) & 0xFF;
514 * If we already got to this bus through a different bridge,
515 * ignore it. This can happen with the i450NX chipset.
517 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
518 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
519 pci_domain_nr(bus), busnr);
523 child = pci_add_new_bus(bus, dev, busnr);
526 child->primary = buses & 0xFF;
527 child->subordinate = (buses >> 16) & 0xFF;
528 child->bridge_ctl = bctl;
530 cmax = pci_scan_child_bus(child);
533 if (child->subordinate > max)
534 max = child->subordinate;
537 * We need to assign a number to this bus which we always
538 * do in the second pass.
541 if (pcibios_assign_all_busses())
542 /* Temporarily disable forwarding of the
543 configuration cycles on all bridges in
544 this bus segment to avoid possible
545 conflicts in the second pass between two
546 bridges programmed with overlapping
548 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
554 pci_write_config_word(dev, PCI_STATUS, 0xffff);
556 /* Prevent assigning a bus number that already exists.
557 * This can happen when a bridge is hot-plugged */
558 if (pci_find_bus(pci_domain_nr(bus), max+1))
560 child = pci_add_new_bus(bus, dev, ++max);
561 buses = (buses & 0xff000000)
562 | ((unsigned int)(child->primary) << 0)
563 | ((unsigned int)(child->secondary) << 8)
564 | ((unsigned int)(child->subordinate) << 16);
567 * yenta.c forces a secondary latency timer of 176.
568 * Copy that behaviour here.
571 buses &= ~0xff000000;
572 buses |= CARDBUS_LATENCY_TIMER << 24;
576 * We need to blast all three values with a single write.
578 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
581 child->bridge_ctl = bctl;
583 * Adjust subordinate busnr in parent buses.
584 * We do this before scanning for children because
585 * some devices may not be detected if the bios
588 pci_fixup_parent_subordinate_busnr(child, max);
589 /* Now we can scan all subordinate buses... */
590 max = pci_scan_child_bus(child);
592 * now fix it up again since we have found
593 * the real value of max.
595 pci_fixup_parent_subordinate_busnr(child, max);
598 * For CardBus bridges, we leave 4 bus numbers
599 * as cards with a PCI-to-PCI bridge can be
602 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
603 struct pci_bus *parent = bus;
604 if (pci_find_bus(pci_domain_nr(bus),
607 while (parent->parent) {
608 if ((!pcibios_assign_all_busses()) &&
609 (parent->subordinate > max) &&
610 (parent->subordinate <= max+i)) {
613 parent = parent->parent;
617 * Often, there are two cardbus bridges
618 * -- try to leave one valid bus number
626 pci_fixup_parent_subordinate_busnr(child, max);
629 * Set the subordinate bus number to its real value.
631 child->subordinate = max;
632 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
636 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
637 pci_domain_nr(bus), child->number);
639 /* Has only triggered on CardBus, fixup is in yenta_socket */
640 while (bus->parent) {
641 if ((child->subordinate > bus->subordinate) ||
642 (child->number > bus->subordinate) ||
643 (child->number < bus->number) ||
644 (child->subordinate < bus->number)) {
645 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
646 "hidden behind%s bridge #%02x (-#%02x)\n",
647 child->number, child->subordinate,
648 (bus->number > child->subordinate &&
649 bus->subordinate < child->number) ?
650 "wholly" : "partially",
651 bus->self->transparent ? " transparent" : "",
652 bus->number, bus->subordinate);
658 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
664 * Read interrupt line and base address registers.
665 * The architecture-dependent code can tweak these, of course.
667 static void pci_read_irq(struct pci_dev *dev)
671 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
674 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
678 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
681 * pci_setup_device - fill in class and map information of a device
682 * @dev: the device structure to fill
684 * Initialize the device structure with information about the device's
685 * vendor,class,memory and IO-space addresses,IRQ lines etc.
686 * Called at initialisation of the PCI subsystem and by CardBus services.
687 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
690 static int pci_setup_device(struct pci_dev * dev)
694 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
695 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
697 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
698 dev->revision = class & 0xff;
699 class >>= 8; /* upper 3 bytes */
703 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
704 dev->vendor, dev->device, class, dev->hdr_type);
706 /* "Unknown power state" */
707 dev->current_state = PCI_UNKNOWN;
709 /* Early fixups, before probing the BARs */
710 pci_fixup_device(pci_fixup_early, dev);
711 class = dev->class >> 8;
713 switch (dev->hdr_type) { /* header type */
714 case PCI_HEADER_TYPE_NORMAL: /* standard header */
715 if (class == PCI_CLASS_BRIDGE_PCI)
718 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
719 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
720 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
723 * Do the ugly legacy mode stuff here rather than broken chip
724 * quirk code. Legacy mode ATA controllers have fixed
725 * addresses. These are not always echoed in BAR0-3, and
726 * BAR0-3 in a few cases contain junk!
728 if (class == PCI_CLASS_STORAGE_IDE) {
730 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
731 if ((progif & 1) == 0) {
732 dev->resource[0].start = 0x1F0;
733 dev->resource[0].end = 0x1F7;
734 dev->resource[0].flags = LEGACY_IO_RESOURCE;
735 dev->resource[1].start = 0x3F6;
736 dev->resource[1].end = 0x3F6;
737 dev->resource[1].flags = LEGACY_IO_RESOURCE;
739 if ((progif & 4) == 0) {
740 dev->resource[2].start = 0x170;
741 dev->resource[2].end = 0x177;
742 dev->resource[2].flags = LEGACY_IO_RESOURCE;
743 dev->resource[3].start = 0x376;
744 dev->resource[3].end = 0x376;
745 dev->resource[3].flags = LEGACY_IO_RESOURCE;
750 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
751 if (class != PCI_CLASS_BRIDGE_PCI)
753 /* The PCI-to-PCI bridge spec requires that subtractive
754 decoding (i.e. transparent) bridge must have programming
755 interface code of 0x01. */
757 dev->transparent = ((dev->class & 0xff) == 1);
758 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
761 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
762 if (class != PCI_CLASS_BRIDGE_CARDBUS)
765 pci_read_bases(dev, 1, 0);
766 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
767 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
770 default: /* unknown header */
771 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
772 pci_name(dev), dev->hdr_type);
776 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
777 pci_name(dev), class, dev->hdr_type);
778 dev->class = PCI_CLASS_NOT_DEFINED;
781 /* We found a fine healthy device, go go go... */
786 * pci_release_dev - free a pci device structure when all users of it are finished.
787 * @dev: device that's been disconnected
789 * Will be called only by the device core when all users of this pci device are
792 static void pci_release_dev(struct device *dev)
794 struct pci_dev *pci_dev;
796 pci_dev = to_pci_dev(dev);
800 static void set_pcie_port_type(struct pci_dev *pdev)
805 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
809 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
810 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
814 * pci_cfg_space_size - get the configuration space size of the PCI device.
817 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
818 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
819 * access it. Maybe we don't have a way to generate extended config space
820 * accesses, or the device is behind a reverse Express bridge. So we try
821 * reading the dword at 0x100 which must either be 0 or a valid extended
824 int pci_cfg_space_size(struct pci_dev *dev)
829 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
831 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
835 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
836 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
840 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
842 if (status == 0xffffffff)
845 return PCI_CFG_SPACE_EXP_SIZE;
848 return PCI_CFG_SPACE_SIZE;
851 static void pci_release_bus_bridge_dev(struct device *dev)
856 struct pci_dev *alloc_pci_dev(void)
860 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
864 INIT_LIST_HEAD(&dev->bus_list);
866 pci_msi_init_pci_dev(dev);
870 EXPORT_SYMBOL(alloc_pci_dev);
873 * Read the config data for a PCI device, sanity-check it
874 * and fill in the dev structure...
876 static struct pci_dev * __devinit
877 pci_scan_device(struct pci_bus *bus, int devfn)
884 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
887 /* some broken boards return 0 or ~0 if a slot is empty: */
888 if (l == 0xffffffff || l == 0x00000000 ||
889 l == 0x0000ffff || l == 0xffff0000)
892 /* Configuration request Retry Status */
893 while (l == 0xffff0001) {
896 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
898 /* Card hasn't responded in 60 seconds? Must be stuck. */
899 if (delay > 60 * 1000) {
900 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
901 "responding\n", pci_domain_nr(bus),
902 bus->number, PCI_SLOT(devfn),
908 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
911 dev = alloc_pci_dev();
916 dev->sysdata = bus->sysdata;
917 dev->dev.parent = bus->bridge;
918 dev->dev.bus = &pci_bus_type;
920 dev->hdr_type = hdr_type & 0x7f;
921 dev->multifunction = !!(hdr_type & 0x80);
922 dev->vendor = l & 0xffff;
923 dev->device = (l >> 16) & 0xffff;
924 dev->cfg_size = pci_cfg_space_size(dev);
925 dev->error_state = pci_channel_io_normal;
926 set_pcie_port_type(dev);
928 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
929 set this higher, assuming the system even supports it. */
930 dev->dma_mask = 0xffffffff;
931 if (pci_setup_device(dev) < 0) {
939 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
941 device_initialize(&dev->dev);
942 dev->dev.release = pci_release_dev;
945 set_dev_node(&dev->dev, pcibus_to_node(bus));
946 dev->dev.dma_mask = &dev->dma_mask;
947 dev->dev.dma_parms = &dev->dma_parms;
948 dev->dev.coherent_dma_mask = 0xffffffffull;
950 pci_set_dma_max_seg_size(dev, 65536);
951 pci_set_dma_seg_boundary(dev, 0xffffffff);
953 /* Fix up broken headers */
954 pci_fixup_device(pci_fixup_header, dev);
957 * Add the device to our list of discovered devices
958 * and the bus list for fixup functions, etc.
960 down_write(&pci_bus_sem);
961 list_add_tail(&dev->bus_list, &bus->devices);
962 up_write(&pci_bus_sem);
965 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
969 dev = pci_scan_device(bus, devfn);
973 pci_device_add(dev, bus);
977 EXPORT_SYMBOL(pci_scan_single_device);
980 * pci_scan_slot - scan a PCI slot on a bus for devices.
981 * @bus: PCI bus to scan
982 * @devfn: slot number to scan (must have zero function.)
984 * Scan a PCI slot on the specified PCI bus for devices, adding
985 * discovered devices to the @bus->devices list. New devices
986 * will not have is_added set.
988 int pci_scan_slot(struct pci_bus *bus, int devfn)
993 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
995 for (func = 0; func < 8; func++, devfn++) {
998 dev = pci_scan_single_device(bus, devfn);
1003 * If this is a single function device,
1004 * don't scan past the first function.
1006 if (!dev->multifunction) {
1008 dev->multifunction = 1;
1014 if (func == 0 && !scan_all_fns)
1020 pcie_aspm_init_link_state(bus->self);
1025 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1027 unsigned int devfn, pass, max = bus->secondary;
1028 struct pci_dev *dev;
1030 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1032 /* Go find them, Rover! */
1033 for (devfn = 0; devfn < 0x100; devfn += 8)
1034 pci_scan_slot(bus, devfn);
1037 * After performing arch-dependent fixup of the bus, look behind
1038 * all PCI-to-PCI bridges on this bus.
1040 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1041 pcibios_fixup_bus(bus);
1042 for (pass=0; pass < 2; pass++)
1043 list_for_each_entry(dev, &bus->devices, bus_list) {
1044 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1045 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1046 max = pci_scan_bridge(bus, dev, max, pass);
1050 * We've scanned the bus and so we know all about what's on
1051 * the other side of any bridges that may be on this bus plus
1054 * Return how far we've got finding sub-buses.
1056 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1057 pci_domain_nr(bus), bus->number, max);
1061 struct pci_bus * pci_create_bus(struct device *parent,
1062 int bus, struct pci_ops *ops, void *sysdata)
1068 b = pci_alloc_bus();
1072 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1078 b->sysdata = sysdata;
1081 if (pci_find_bus(pci_domain_nr(b), bus)) {
1082 /* If we already got to this bus through a different bridge, ignore it */
1083 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1087 down_write(&pci_bus_sem);
1088 list_add_tail(&b->node, &pci_root_buses);
1089 up_write(&pci_bus_sem);
1091 memset(dev, 0, sizeof(*dev));
1092 dev->parent = parent;
1093 dev->release = pci_release_bus_bridge_dev;
1094 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1095 error = device_register(dev);
1098 b->bridge = get_device(dev);
1100 b->dev.class = &pcibus_class;
1101 b->dev.parent = b->bridge;
1102 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1103 error = device_register(&b->dev);
1105 goto class_dev_reg_err;
1106 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1108 goto dev_create_file_err;
1110 /* Create legacy_io and legacy_mem files for this bus */
1111 pci_create_legacy_files(b);
1113 b->number = b->secondary = bus;
1114 b->resource[0] = &ioport_resource;
1115 b->resource[1] = &iomem_resource;
1119 dev_create_file_err:
1120 device_unregister(&b->dev);
1122 device_unregister(dev);
1124 down_write(&pci_bus_sem);
1126 up_write(&pci_bus_sem);
1133 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1134 int bus, struct pci_ops *ops, void *sysdata)
1138 b = pci_create_bus(parent, bus, ops, sysdata);
1140 b->subordinate = pci_scan_child_bus(b);
1143 EXPORT_SYMBOL(pci_scan_bus_parented);
1145 #ifdef CONFIG_HOTPLUG
1146 EXPORT_SYMBOL(pci_add_new_bus);
1147 EXPORT_SYMBOL(pci_scan_slot);
1148 EXPORT_SYMBOL(pci_scan_bridge);
1149 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1152 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1154 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1155 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1157 if (a->bus->number < b->bus->number) return -1;
1158 else if (a->bus->number > b->bus->number) return 1;
1160 if (a->devfn < b->devfn) return -1;
1161 else if (a->devfn > b->devfn) return 1;
1167 * Yes, this forcably breaks the klist abstraction temporarily. It
1168 * just wants to sort the klist, not change reference counts and
1169 * take/drop locks rapidly in the process. It does all this while
1170 * holding the lock for the list, so objects can't otherwise be
1171 * added/removed while we're swizzling.
1173 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1175 struct list_head *pos;
1176 struct klist_node *n;
1180 list_for_each(pos, list) {
1181 n = container_of(pos, struct klist_node, n_node);
1182 dev = container_of(n, struct device, knode_bus);
1183 b = to_pci_dev(dev);
1184 if (pci_sort_bf_cmp(a, b) <= 0) {
1185 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1189 list_move_tail(&a->dev.knode_bus.n_node, list);
1192 void __init pci_sort_breadthfirst(void)
1194 LIST_HEAD(sorted_devices);
1195 struct list_head *pos, *tmp;
1196 struct klist_node *n;
1198 struct pci_dev *pdev;
1199 struct klist *device_klist;
1201 device_klist = bus_get_device_klist(&pci_bus_type);
1203 spin_lock(&device_klist->k_lock);
1204 list_for_each_safe(pos, tmp, &device_klist->k_list) {
1205 n = container_of(pos, struct klist_node, n_node);
1206 dev = container_of(n, struct device, knode_bus);
1207 pdev = to_pci_dev(dev);
1208 pci_insertion_sort_klist(pdev, &sorted_devices);
1210 list_splice(&sorted_devices, &device_klist->k_list);
1211 spin_unlock(&device_klist->k_lock);