2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17 #define PCI_CFG_SPACE_SIZE 256
18 #define PCI_CFG_SPACE_EXP_SIZE 4096
20 /* Ugh. Need to stop exporting this to modules. */
21 LIST_HEAD(pci_root_buses);
22 EXPORT_SYMBOL(pci_root_buses);
25 static int find_anything(struct device *dev, void *data)
31 * Some device drivers need know if pci is initiated.
32 * Basically, we think pci is not initiated when there
33 * is no device to be found on the pci_bus_type.
35 int no_pci_devices(void)
40 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
41 no_devices = (dev == NULL);
45 EXPORT_SYMBOL(no_pci_devices);
47 #ifdef HAVE_PCI_LEGACY
49 * pci_create_legacy_files - create legacy I/O port and memory files
50 * @b: bus to create files under
52 * Some platforms allow access to legacy I/O port and ISA memory space on
53 * a per-bus basis. This routine creates the files and ties them into
54 * their associated read, write and mmap files from pci-sysfs.c
56 static void pci_create_legacy_files(struct pci_bus *b)
58 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
61 b->legacy_io->attr.name = "legacy_io";
62 b->legacy_io->size = 0xffff;
63 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
64 b->legacy_io->read = pci_read_legacy_io;
65 b->legacy_io->write = pci_write_legacy_io;
66 device_create_bin_file(&b->dev, b->legacy_io);
68 /* Allocated above after the legacy_io struct */
69 b->legacy_mem = b->legacy_io + 1;
70 b->legacy_mem->attr.name = "legacy_mem";
71 b->legacy_mem->size = 1024*1024;
72 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
73 b->legacy_mem->mmap = pci_mmap_legacy_mem;
74 device_create_bin_file(&b->dev, b->legacy_mem);
78 void pci_remove_legacy_files(struct pci_bus *b)
81 device_remove_bin_file(&b->dev, b->legacy_io);
82 device_remove_bin_file(&b->dev, b->legacy_mem);
83 kfree(b->legacy_io); /* both are allocated here */
86 #else /* !HAVE_PCI_LEGACY */
87 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
88 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
89 #endif /* HAVE_PCI_LEGACY */
92 * PCI Bus Class Devices
94 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
96 struct device_attribute *attr,
102 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
104 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask):
105 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
111 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
112 struct device_attribute *attr,
115 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
118 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
119 struct device_attribute *attr,
122 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
125 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
126 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
131 static void release_pcibus_dev(struct device *dev)
133 struct pci_bus *pci_bus = to_pci_bus(dev);
136 put_device(pci_bus->bridge);
140 static struct class pcibus_class = {
142 .dev_release = &release_pcibus_dev,
145 static int __init pcibus_class_init(void)
147 return class_register(&pcibus_class);
149 postcore_initcall(pcibus_class_init);
152 * Translate the low bits of the PCI base
153 * to the resource type
155 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
157 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
158 return IORESOURCE_IO;
160 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
161 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
163 return IORESOURCE_MEM;
167 * Find the extent of a PCI decode..
169 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
171 u32 size = mask & maxbase; /* Find the significant bits */
175 /* Get the lowest of them to find the decode size, and
176 from that the extent. */
177 size = (size & ~(size-1)) - 1;
179 /* base == maxbase can be valid only if the BAR has
180 already been programmed with all 1s. */
181 if (base == maxbase && ((base | size) & mask) != mask)
187 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
189 u64 size = mask & maxbase; /* Find the significant bits */
193 /* Get the lowest of them to find the decode size, and
194 from that the extent. */
195 size = (size & ~(size-1)) - 1;
197 /* base == maxbase can be valid only if the BAR has
198 already been programmed with all 1s. */
199 if (base == maxbase && ((base | size) & mask) != mask)
205 static inline int is_64bit_memory(u32 mask)
207 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
208 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
213 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
215 unsigned int pos, reg, next;
217 struct resource *res;
219 for(pos=0; pos<howmany; pos = next) {
225 res = &dev->resource[pos];
226 res->name = pci_name(dev);
227 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
228 pci_read_config_dword(dev, reg, &l);
229 pci_write_config_dword(dev, reg, ~0);
230 pci_read_config_dword(dev, reg, &sz);
231 pci_write_config_dword(dev, reg, l);
232 if (!sz || sz == 0xffffffff)
237 if ((l & PCI_BASE_ADDRESS_SPACE) ==
238 PCI_BASE_ADDRESS_SPACE_MEMORY) {
239 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
241 * For 64bit prefetchable memory sz could be 0, if the
242 * real size is bigger than 4G, so we need to check
245 if (!is_64bit_memory(l) && !sz)
247 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
248 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
250 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
253 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
254 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
256 res->end = res->start + (unsigned long) sz;
257 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
258 if (is_64bit_memory(l)) {
261 pci_read_config_dword(dev, reg+4, &lhi);
262 pci_write_config_dword(dev, reg+4, ~0);
263 pci_read_config_dword(dev, reg+4, &szhi);
264 pci_write_config_dword(dev, reg+4, lhi);
265 sz64 = ((u64)szhi << 32) | raw_sz;
266 l64 = ((u64)lhi << 32) | l;
267 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
269 #if BITS_PER_LONG == 64
276 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
277 res->end = res->start + sz64;
279 if (sz64 > 0x100000000ULL) {
280 dev_err(&dev->dev, "BAR %d: can't handle 64-bit"
285 /* 64-bit wide address, treat as disabled */
286 pci_write_config_dword(dev, reg,
287 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
288 pci_write_config_dword(dev, reg+4, 0);
296 dev->rom_base_reg = rom;
297 res = &dev->resource[PCI_ROM_RESOURCE];
298 res->name = pci_name(dev);
299 pci_read_config_dword(dev, rom, &l);
300 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
301 pci_read_config_dword(dev, rom, &sz);
302 pci_write_config_dword(dev, rom, l);
305 if (sz && sz != 0xffffffff) {
306 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
308 res->flags = (l & IORESOURCE_ROM_ENABLE) |
309 IORESOURCE_MEM | IORESOURCE_PREFETCH |
310 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
311 IORESOURCE_SIZEALIGN;
312 res->start = l & PCI_ROM_ADDRESS_MASK;
313 res->end = res->start + (unsigned long) sz;
319 void __devinit pci_read_bridge_bases(struct pci_bus *child)
321 struct pci_dev *dev = child->self;
322 u8 io_base_lo, io_limit_lo;
323 u16 mem_base_lo, mem_limit_lo;
324 unsigned long base, limit;
325 struct resource *res;
328 if (!dev) /* It's a host bus, nothing to read */
331 if (dev->transparent) {
332 dev_info(&dev->dev, "transparent bridge\n");
333 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
334 child->resource[i] = child->parent->resource[i - 3];
338 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
340 res = child->resource[0];
341 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
342 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
343 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
344 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
346 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
347 u16 io_base_hi, io_limit_hi;
348 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
349 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
350 base |= (io_base_hi << 16);
351 limit |= (io_limit_hi << 16);
355 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
359 res->end = limit + 0xfff;
362 res = child->resource[1];
363 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
364 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
365 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
366 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
368 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
370 res->end = limit + 0xfffff;
373 res = child->resource[2];
374 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
375 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
376 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
377 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
379 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
380 u32 mem_base_hi, mem_limit_hi;
381 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
382 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
385 * Some bridges set the base > limit by default, and some
386 * (broken) BIOSes do not initialize them. If we find
387 * this, just assume they are not being used.
389 if (mem_base_hi <= mem_limit_hi) {
390 #if BITS_PER_LONG == 64
391 base |= ((long) mem_base_hi) << 32;
392 limit |= ((long) mem_limit_hi) << 32;
394 if (mem_base_hi || mem_limit_hi) {
395 dev_err(&dev->dev, "can't handle 64-bit "
396 "address space for bridge\n");
403 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
405 res->end = limit + 0xfffff;
409 static struct pci_bus * pci_alloc_bus(void)
413 b = kzalloc(sizeof(*b), GFP_KERNEL);
415 INIT_LIST_HEAD(&b->node);
416 INIT_LIST_HEAD(&b->children);
417 INIT_LIST_HEAD(&b->devices);
418 INIT_LIST_HEAD(&b->slots);
423 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
424 struct pci_dev *bridge, int busnr)
426 struct pci_bus *child;
430 * Allocate a new bus, and inherit stuff from the parent..
432 child = pci_alloc_bus();
436 child->self = bridge;
437 child->parent = parent;
438 child->ops = parent->ops;
439 child->sysdata = parent->sysdata;
440 child->bus_flags = parent->bus_flags;
441 child->bridge = get_device(&bridge->dev);
443 /* initialize some portions of the bus device, but don't register it
444 * now as the parent is not properly set up yet. This device will get
445 * registered later in pci_bus_add_devices()
447 child->dev.class = &pcibus_class;
448 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
451 * Set up the primary, secondary and subordinate
454 child->number = child->secondary = busnr;
455 child->primary = parent->secondary;
456 child->subordinate = 0xff;
458 /* Set up default resource pointers and names.. */
459 for (i = 0; i < 4; i++) {
460 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
461 child->resource[i]->name = child->name;
463 bridge->subordinate = child;
468 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
470 struct pci_bus *child;
472 child = pci_alloc_child_bus(parent, dev, busnr);
474 down_write(&pci_bus_sem);
475 list_add_tail(&child->node, &parent->children);
476 up_write(&pci_bus_sem);
481 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
483 struct pci_bus *parent = child->parent;
485 /* Attempts to fix that up are really dangerous unless
486 we're going to re-assign all bus numbers. */
487 if (!pcibios_assign_all_busses())
490 while (parent->parent && parent->subordinate < max) {
491 parent->subordinate = max;
492 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
493 parent = parent->parent;
498 * If it's a bridge, configure it and scan the bus behind it.
499 * For CardBus bridges, we don't scan behind as the devices will
500 * be handled by the bridge driver itself.
502 * We need to process bridges in two passes -- first we scan those
503 * already configured by the BIOS and after we are done with all of
504 * them, we proceed to assigning numbers to the remaining buses in
505 * order to avoid overlaps between old and new bus numbers.
507 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
509 struct pci_bus *child;
510 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
514 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
516 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
517 buses & 0xffffff, pass);
519 /* Disable MasterAbortMode during probing to avoid reporting
520 of bus errors (in some architectures) */
521 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
522 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
523 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
525 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
526 unsigned int cmax, busnr;
528 * Bus already configured by firmware, process it in the first
529 * pass and just note the configuration.
533 busnr = (buses >> 8) & 0xFF;
536 * If we already got to this bus through a different bridge,
537 * ignore it. This can happen with the i450NX chipset.
539 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
540 dev_info(&dev->dev, "bus %04x:%02x already known\n",
541 pci_domain_nr(bus), busnr);
545 child = pci_add_new_bus(bus, dev, busnr);
548 child->primary = buses & 0xFF;
549 child->subordinate = (buses >> 16) & 0xFF;
550 child->bridge_ctl = bctl;
552 cmax = pci_scan_child_bus(child);
555 if (child->subordinate > max)
556 max = child->subordinate;
559 * We need to assign a number to this bus which we always
560 * do in the second pass.
563 if (pcibios_assign_all_busses())
564 /* Temporarily disable forwarding of the
565 configuration cycles on all bridges in
566 this bus segment to avoid possible
567 conflicts in the second pass between two
568 bridges programmed with overlapping
570 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
576 pci_write_config_word(dev, PCI_STATUS, 0xffff);
578 /* Prevent assigning a bus number that already exists.
579 * This can happen when a bridge is hot-plugged */
580 if (pci_find_bus(pci_domain_nr(bus), max+1))
582 child = pci_add_new_bus(bus, dev, ++max);
583 buses = (buses & 0xff000000)
584 | ((unsigned int)(child->primary) << 0)
585 | ((unsigned int)(child->secondary) << 8)
586 | ((unsigned int)(child->subordinate) << 16);
589 * yenta.c forces a secondary latency timer of 176.
590 * Copy that behaviour here.
593 buses &= ~0xff000000;
594 buses |= CARDBUS_LATENCY_TIMER << 24;
598 * We need to blast all three values with a single write.
600 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
603 child->bridge_ctl = bctl;
605 * Adjust subordinate busnr in parent buses.
606 * We do this before scanning for children because
607 * some devices may not be detected if the bios
610 pci_fixup_parent_subordinate_busnr(child, max);
611 /* Now we can scan all subordinate buses... */
612 max = pci_scan_child_bus(child);
614 * now fix it up again since we have found
615 * the real value of max.
617 pci_fixup_parent_subordinate_busnr(child, max);
620 * For CardBus bridges, we leave 4 bus numbers
621 * as cards with a PCI-to-PCI bridge can be
624 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
625 struct pci_bus *parent = bus;
626 if (pci_find_bus(pci_domain_nr(bus),
629 while (parent->parent) {
630 if ((!pcibios_assign_all_busses()) &&
631 (parent->subordinate > max) &&
632 (parent->subordinate <= max+i)) {
635 parent = parent->parent;
639 * Often, there are two cardbus bridges
640 * -- try to leave one valid bus number
648 pci_fixup_parent_subordinate_busnr(child, max);
651 * Set the subordinate bus number to its real value.
653 child->subordinate = max;
654 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
658 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
659 pci_domain_nr(bus), child->number);
661 /* Has only triggered on CardBus, fixup is in yenta_socket */
662 while (bus->parent) {
663 if ((child->subordinate > bus->subordinate) ||
664 (child->number > bus->subordinate) ||
665 (child->number < bus->number) ||
666 (child->subordinate < bus->number)) {
667 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
668 "hidden behind%s bridge #%02x (-#%02x)\n",
669 child->number, child->subordinate,
670 (bus->number > child->subordinate &&
671 bus->subordinate < child->number) ?
672 "wholly" : "partially",
673 bus->self->transparent ? " transparent" : "",
674 bus->number, bus->subordinate);
680 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
686 * Read interrupt line and base address registers.
687 * The architecture-dependent code can tweak these, of course.
689 static void pci_read_irq(struct pci_dev *dev)
693 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
696 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
700 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
703 * pci_setup_device - fill in class and map information of a device
704 * @dev: the device structure to fill
706 * Initialize the device structure with information about the device's
707 * vendor,class,memory and IO-space addresses,IRQ lines etc.
708 * Called at initialisation of the PCI subsystem and by CardBus services.
709 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
712 static int pci_setup_device(struct pci_dev * dev)
716 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
717 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
719 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
720 dev->revision = class & 0xff;
721 class >>= 8; /* upper 3 bytes */
725 dev_dbg(&dev->dev, "found [%04x/%04x] class %06x header type %02x\n",
726 dev->vendor, dev->device, class, dev->hdr_type);
728 /* "Unknown power state" */
729 dev->current_state = PCI_UNKNOWN;
731 /* Early fixups, before probing the BARs */
732 pci_fixup_device(pci_fixup_early, dev);
733 class = dev->class >> 8;
735 switch (dev->hdr_type) { /* header type */
736 case PCI_HEADER_TYPE_NORMAL: /* standard header */
737 if (class == PCI_CLASS_BRIDGE_PCI)
740 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
741 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
742 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
745 * Do the ugly legacy mode stuff here rather than broken chip
746 * quirk code. Legacy mode ATA controllers have fixed
747 * addresses. These are not always echoed in BAR0-3, and
748 * BAR0-3 in a few cases contain junk!
750 if (class == PCI_CLASS_STORAGE_IDE) {
752 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
753 if ((progif & 1) == 0) {
754 dev->resource[0].start = 0x1F0;
755 dev->resource[0].end = 0x1F7;
756 dev->resource[0].flags = LEGACY_IO_RESOURCE;
757 dev->resource[1].start = 0x3F6;
758 dev->resource[1].end = 0x3F6;
759 dev->resource[1].flags = LEGACY_IO_RESOURCE;
761 if ((progif & 4) == 0) {
762 dev->resource[2].start = 0x170;
763 dev->resource[2].end = 0x177;
764 dev->resource[2].flags = LEGACY_IO_RESOURCE;
765 dev->resource[3].start = 0x376;
766 dev->resource[3].end = 0x376;
767 dev->resource[3].flags = LEGACY_IO_RESOURCE;
772 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
773 if (class != PCI_CLASS_BRIDGE_PCI)
775 /* The PCI-to-PCI bridge spec requires that subtractive
776 decoding (i.e. transparent) bridge must have programming
777 interface code of 0x01. */
779 dev->transparent = ((dev->class & 0xff) == 1);
780 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
783 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
784 if (class != PCI_CLASS_BRIDGE_CARDBUS)
787 pci_read_bases(dev, 1, 0);
788 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
789 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
792 default: /* unknown header */
793 dev_err(&dev->dev, "unknown header type %02x, "
794 "ignoring device\n", dev->hdr_type);
798 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
799 "type %02x)\n", class, dev->hdr_type);
800 dev->class = PCI_CLASS_NOT_DEFINED;
803 /* We found a fine healthy device, go go go... */
808 * pci_release_dev - free a pci device structure when all users of it are finished.
809 * @dev: device that's been disconnected
811 * Will be called only by the device core when all users of this pci device are
814 static void pci_release_dev(struct device *dev)
816 struct pci_dev *pci_dev;
818 pci_dev = to_pci_dev(dev);
819 pci_vpd_release(pci_dev);
823 static void set_pcie_port_type(struct pci_dev *pdev)
828 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
832 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
833 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
837 * pci_cfg_space_size - get the configuration space size of the PCI device.
840 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
841 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
842 * access it. Maybe we don't have a way to generate extended config space
843 * accesses, or the device is behind a reverse Express bridge. So we try
844 * reading the dword at 0x100 which must either be 0 or a valid extended
847 int pci_cfg_space_size_ext(struct pci_dev *dev)
851 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
853 if (status == 0xffffffff)
856 return PCI_CFG_SPACE_EXP_SIZE;
859 return PCI_CFG_SPACE_SIZE;
863 * pci_disable_pme - Disable the PME function of PCI device
864 * @dev: PCI device affected
865 * -EINVAL is returned if PCI device doesn't support PME.
866 * Zero is returned if the PME is supported and can be disabled.
868 static int pci_disable_pme(struct pci_dev *dev)
873 /* find PCI PM capability in list */
874 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
876 /* If device doesn't support PM Capabilities, it means that PME is
881 /* Check device's ability to generate PME# */
882 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
884 value &= PCI_PM_CAP_PME_MASK;
885 /* Check if it can generate PME# */
888 * If it is zero, it means that PME is still unsupported
889 * although there exists the PM capability.
894 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
896 /* Clear PME_Status by writing 1 to it */
897 value |= PCI_PM_CTRL_PME_STATUS ;
898 /* Disable PME enable bit */
899 value &= ~PCI_PM_CTRL_PME_ENABLE;
900 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
905 int pci_cfg_space_size(struct pci_dev *dev)
910 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
912 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
916 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
917 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
921 return pci_cfg_space_size_ext(dev);
924 return PCI_CFG_SPACE_SIZE;
927 static void pci_release_bus_bridge_dev(struct device *dev)
932 struct pci_dev *alloc_pci_dev(void)
936 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
940 INIT_LIST_HEAD(&dev->bus_list);
942 pci_msi_init_pci_dev(dev);
946 EXPORT_SYMBOL(alloc_pci_dev);
949 * Read the config data for a PCI device, sanity-check it
950 * and fill in the dev structure...
952 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
959 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
962 /* some broken boards return 0 or ~0 if a slot is empty: */
963 if (l == 0xffffffff || l == 0x00000000 ||
964 l == 0x0000ffff || l == 0xffff0000)
967 /* Configuration request Retry Status */
968 while (l == 0xffff0001) {
971 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
973 /* Card hasn't responded in 60 seconds? Must be stuck. */
974 if (delay > 60 * 1000) {
975 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
976 "responding\n", pci_domain_nr(bus),
977 bus->number, PCI_SLOT(devfn),
983 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
986 dev = alloc_pci_dev();
991 dev->sysdata = bus->sysdata;
992 dev->dev.parent = bus->bridge;
993 dev->dev.bus = &pci_bus_type;
995 dev->hdr_type = hdr_type & 0x7f;
996 dev->multifunction = !!(hdr_type & 0x80);
997 dev->vendor = l & 0xffff;
998 dev->device = (l >> 16) & 0xffff;
999 dev->cfg_size = pci_cfg_space_size(dev);
1000 dev->error_state = pci_channel_io_normal;
1001 set_pcie_port_type(dev);
1003 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1004 set this higher, assuming the system even supports it. */
1005 dev->dma_mask = 0xffffffff;
1006 if (pci_setup_device(dev) < 0) {
1011 pci_vpd_pci22_init(dev);
1012 pci_disable_pme(dev);
1017 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1019 device_initialize(&dev->dev);
1020 dev->dev.release = pci_release_dev;
1023 dev->dev.dma_mask = &dev->dma_mask;
1024 dev->dev.dma_parms = &dev->dma_parms;
1025 dev->dev.coherent_dma_mask = 0xffffffffull;
1027 pci_set_dma_max_seg_size(dev, 65536);
1028 pci_set_dma_seg_boundary(dev, 0xffffffff);
1030 /* Fix up broken headers */
1031 pci_fixup_device(pci_fixup_header, dev);
1034 * Add the device to our list of discovered devices
1035 * and the bus list for fixup functions, etc.
1037 down_write(&pci_bus_sem);
1038 list_add_tail(&dev->bus_list, &bus->devices);
1039 up_write(&pci_bus_sem);
1042 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1044 struct pci_dev *dev;
1046 dev = pci_scan_device(bus, devfn);
1050 pci_device_add(dev, bus);
1054 EXPORT_SYMBOL(pci_scan_single_device);
1057 * pci_scan_slot - scan a PCI slot on a bus for devices.
1058 * @bus: PCI bus to scan
1059 * @devfn: slot number to scan (must have zero function.)
1061 * Scan a PCI slot on the specified PCI bus for devices, adding
1062 * discovered devices to the @bus->devices list. New devices
1063 * will not have is_added set.
1065 int pci_scan_slot(struct pci_bus *bus, int devfn)
1070 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
1072 for (func = 0; func < 8; func++, devfn++) {
1073 struct pci_dev *dev;
1075 dev = pci_scan_single_device(bus, devfn);
1080 * If this is a single function device,
1081 * don't scan past the first function.
1083 if (!dev->multifunction) {
1085 dev->multifunction = 1;
1091 if (func == 0 && !scan_all_fns)
1097 pcie_aspm_init_link_state(bus->self);
1102 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1104 unsigned int devfn, pass, max = bus->secondary;
1105 struct pci_dev *dev;
1107 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1109 /* Go find them, Rover! */
1110 for (devfn = 0; devfn < 0x100; devfn += 8)
1111 pci_scan_slot(bus, devfn);
1114 * After performing arch-dependent fixup of the bus, look behind
1115 * all PCI-to-PCI bridges on this bus.
1117 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1118 pcibios_fixup_bus(bus);
1119 for (pass=0; pass < 2; pass++)
1120 list_for_each_entry(dev, &bus->devices, bus_list) {
1121 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1122 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1123 max = pci_scan_bridge(bus, dev, max, pass);
1127 * We've scanned the bus and so we know all about what's on
1128 * the other side of any bridges that may be on this bus plus
1131 * Return how far we've got finding sub-buses.
1133 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1134 pci_domain_nr(bus), bus->number, max);
1138 void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b)
1142 struct pci_bus * pci_create_bus(struct device *parent,
1143 int bus, struct pci_ops *ops, void *sysdata)
1149 b = pci_alloc_bus();
1153 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1159 b->sysdata = sysdata;
1162 if (pci_find_bus(pci_domain_nr(b), bus)) {
1163 /* If we already got to this bus through a different bridge, ignore it */
1164 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1168 down_write(&pci_bus_sem);
1169 list_add_tail(&b->node, &pci_root_buses);
1170 up_write(&pci_bus_sem);
1172 memset(dev, 0, sizeof(*dev));
1173 dev->parent = parent;
1174 dev->release = pci_release_bus_bridge_dev;
1175 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1176 error = device_register(dev);
1179 b->bridge = get_device(dev);
1182 set_dev_node(b->bridge, pcibus_to_node(b));
1184 b->dev.class = &pcibus_class;
1185 b->dev.parent = b->bridge;
1186 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1187 error = device_register(&b->dev);
1189 goto class_dev_reg_err;
1190 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1192 goto dev_create_file_err;
1194 /* Create legacy_io and legacy_mem files for this bus */
1195 pci_create_legacy_files(b);
1197 b->number = b->secondary = bus;
1198 b->resource[0] = &ioport_resource;
1199 b->resource[1] = &iomem_resource;
1201 set_pci_bus_resources_arch_default(b);
1205 dev_create_file_err:
1206 device_unregister(&b->dev);
1208 device_unregister(dev);
1210 down_write(&pci_bus_sem);
1212 up_write(&pci_bus_sem);
1219 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1220 int bus, struct pci_ops *ops, void *sysdata)
1224 b = pci_create_bus(parent, bus, ops, sysdata);
1226 b->subordinate = pci_scan_child_bus(b);
1229 EXPORT_SYMBOL(pci_scan_bus_parented);
1231 #ifdef CONFIG_HOTPLUG
1232 EXPORT_SYMBOL(pci_add_new_bus);
1233 EXPORT_SYMBOL(pci_scan_slot);
1234 EXPORT_SYMBOL(pci_scan_bridge);
1235 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1238 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1240 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1241 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1243 if (a->bus->number < b->bus->number) return -1;
1244 else if (a->bus->number > b->bus->number) return 1;
1246 if (a->devfn < b->devfn) return -1;
1247 else if (a->devfn > b->devfn) return 1;
1253 * Yes, this forcably breaks the klist abstraction temporarily. It
1254 * just wants to sort the klist, not change reference counts and
1255 * take/drop locks rapidly in the process. It does all this while
1256 * holding the lock for the list, so objects can't otherwise be
1257 * added/removed while we're swizzling.
1259 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1261 struct list_head *pos;
1262 struct klist_node *n;
1266 list_for_each(pos, list) {
1267 n = container_of(pos, struct klist_node, n_node);
1268 dev = container_of(n, struct device, knode_bus);
1269 b = to_pci_dev(dev);
1270 if (pci_sort_bf_cmp(a, b) <= 0) {
1271 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1275 list_move_tail(&a->dev.knode_bus.n_node, list);
1278 void __init pci_sort_breadthfirst(void)
1280 LIST_HEAD(sorted_devices);
1281 struct list_head *pos, *tmp;
1282 struct klist_node *n;
1284 struct pci_dev *pdev;
1285 struct klist *device_klist;
1287 device_klist = bus_get_device_klist(&pci_bus_type);
1289 spin_lock(&device_klist->k_lock);
1290 list_for_each_safe(pos, tmp, &device_klist->k_list) {
1291 n = container_of(pos, struct klist_node, n_node);
1292 dev = container_of(n, struct device, knode_bus);
1293 pdev = to_pci_dev(dev);
1294 pci_insertion_sort_klist(pdev, &sorted_devices);
1296 list_splice(&sorted_devices, &device_klist->k_list);
1297 spin_unlock(&device_klist->k_lock);