2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
25 unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT;
27 #ifdef CONFIG_PCI_DOMAINS
28 int pci_domains_supported = 1;
31 #define DEFAULT_CARDBUS_IO_SIZE (256)
32 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
33 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
34 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
35 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
38 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
39 * @bus: pointer to PCI bus structure to search
41 * Given a PCI bus, returns the highest PCI bus number present in the set
42 * including the given PCI bus and its list of child PCI buses.
44 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
46 struct list_head *tmp;
49 max = bus->subordinate;
50 list_for_each(tmp, &bus->children) {
51 n = pci_bus_max_busnr(pci_bus_b(tmp));
57 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
59 #ifdef CONFIG_HAS_IOMEM
60 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
63 * Make sure the BAR is actually a memory resource, not an IO resource
65 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
69 return ioremap_nocache(pci_resource_start(pdev, bar),
70 pci_resource_len(pdev, bar));
72 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
77 * pci_max_busnr - returns maximum PCI bus number
79 * Returns the highest PCI bus number present in the system global list of
82 unsigned char __devinit
85 struct pci_bus *bus = NULL;
89 while ((bus = pci_find_next_bus(bus)) != NULL) {
90 n = pci_bus_max_busnr(bus);
99 #define PCI_FIND_CAP_TTL 48
101 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
102 u8 pos, int cap, int *ttl)
107 pci_bus_read_config_byte(bus, devfn, pos, &pos);
111 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
117 pos += PCI_CAP_LIST_NEXT;
122 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
125 int ttl = PCI_FIND_CAP_TTL;
127 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
130 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
132 return __pci_find_next_cap(dev->bus, dev->devfn,
133 pos + PCI_CAP_LIST_NEXT, cap);
135 EXPORT_SYMBOL_GPL(pci_find_next_capability);
137 static int __pci_bus_find_cap_start(struct pci_bus *bus,
138 unsigned int devfn, u8 hdr_type)
142 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
143 if (!(status & PCI_STATUS_CAP_LIST))
147 case PCI_HEADER_TYPE_NORMAL:
148 case PCI_HEADER_TYPE_BRIDGE:
149 return PCI_CAPABILITY_LIST;
150 case PCI_HEADER_TYPE_CARDBUS:
151 return PCI_CB_CAPABILITY_LIST;
160 * pci_find_capability - query for devices' capabilities
161 * @dev: PCI device to query
162 * @cap: capability code
164 * Tell if a device supports a given PCI capability.
165 * Returns the address of the requested capability structure within the
166 * device's PCI configuration space or 0 in case the device does not
167 * support it. Possible values for @cap:
169 * %PCI_CAP_ID_PM Power Management
170 * %PCI_CAP_ID_AGP Accelerated Graphics Port
171 * %PCI_CAP_ID_VPD Vital Product Data
172 * %PCI_CAP_ID_SLOTID Slot Identification
173 * %PCI_CAP_ID_MSI Message Signalled Interrupts
174 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
175 * %PCI_CAP_ID_PCIX PCI-X
176 * %PCI_CAP_ID_EXP PCI Express
178 int pci_find_capability(struct pci_dev *dev, int cap)
182 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
184 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
190 * pci_bus_find_capability - query for devices' capabilities
191 * @bus: the PCI bus to query
192 * @devfn: PCI device to query
193 * @cap: capability code
195 * Like pci_find_capability() but works for pci devices that do not have a
196 * pci_dev structure set up yet.
198 * Returns the address of the requested capability structure within the
199 * device's PCI configuration space or 0 in case the device does not
202 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
207 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
209 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
211 pos = __pci_find_next_cap(bus, devfn, pos, cap);
217 * pci_find_ext_capability - Find an extended capability
218 * @dev: PCI device to query
219 * @cap: capability code
221 * Returns the address of the requested extended capability structure
222 * within the device's PCI configuration space or 0 if the device does
223 * not support it. Possible values for @cap:
225 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
226 * %PCI_EXT_CAP_ID_VC Virtual Channel
227 * %PCI_EXT_CAP_ID_DSN Device Serial Number
228 * %PCI_EXT_CAP_ID_PWR Power Budgeting
230 int pci_find_ext_capability(struct pci_dev *dev, int cap)
234 int pos = PCI_CFG_SPACE_SIZE;
236 /* minimum 8 bytes per capability */
237 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
239 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
242 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
246 * If we have no capabilities, this is indicated by cap ID,
247 * cap version and next pointer all being 0.
253 if (PCI_EXT_CAP_ID(header) == cap)
256 pos = PCI_EXT_CAP_NEXT(header);
257 if (pos < PCI_CFG_SPACE_SIZE)
260 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
266 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
268 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
270 int rc, ttl = PCI_FIND_CAP_TTL;
273 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
274 mask = HT_3BIT_CAP_MASK;
276 mask = HT_5BIT_CAP_MASK;
278 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
279 PCI_CAP_ID_HT, &ttl);
281 rc = pci_read_config_byte(dev, pos + 3, &cap);
282 if (rc != PCIBIOS_SUCCESSFUL)
285 if ((cap & mask) == ht_cap)
288 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
289 pos + PCI_CAP_LIST_NEXT,
290 PCI_CAP_ID_HT, &ttl);
296 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
297 * @dev: PCI device to query
298 * @pos: Position from which to continue searching
299 * @ht_cap: Hypertransport capability code
301 * To be used in conjunction with pci_find_ht_capability() to search for
302 * all capabilities matching @ht_cap. @pos should always be a value returned
303 * from pci_find_ht_capability().
305 * NB. To be 100% safe against broken PCI devices, the caller should take
306 * steps to avoid an infinite loop.
308 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
310 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
312 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
315 * pci_find_ht_capability - query a device's Hypertransport capabilities
316 * @dev: PCI device to query
317 * @ht_cap: Hypertransport capability code
319 * Tell if a device supports a given Hypertransport capability.
320 * Returns an address within the device's PCI configuration space
321 * or 0 in case the device does not support the request capability.
322 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
323 * which has a Hypertransport capability matching @ht_cap.
325 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
329 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
331 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
335 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
338 * pci_find_parent_resource - return resource region of parent bus of given region
339 * @dev: PCI device structure contains resources to be searched
340 * @res: child resource record for which parent is sought
342 * For given resource region of given device, return the resource
343 * region of parent bus the given region is contained in or where
344 * it should be allocated from.
347 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
349 const struct pci_bus *bus = dev->bus;
351 struct resource *best = NULL;
353 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
354 struct resource *r = bus->resource[i];
357 if (res->start && !(res->start >= r->start && res->end <= r->end))
358 continue; /* Not contained */
359 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
360 continue; /* Wrong type */
361 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
362 return r; /* Exact match */
363 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
364 best = r; /* Approximating prefetchable by non-prefetchable */
370 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
371 * @dev: PCI device to have its BARs restored
373 * Restore the BAR values for a given device, so as to make it
374 * accessible by its driver.
377 pci_restore_bars(struct pci_dev *dev)
381 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
382 pci_update_resource(dev, i);
385 static struct pci_platform_pm_ops *pci_platform_pm;
387 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
389 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
390 || !ops->sleep_wake || !ops->can_wakeup)
392 pci_platform_pm = ops;
396 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
398 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
401 static inline int platform_pci_set_power_state(struct pci_dev *dev,
404 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
407 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
409 return pci_platform_pm ?
410 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
413 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
415 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
418 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
420 return pci_platform_pm ?
421 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
425 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
427 * @dev: PCI device to handle.
428 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
431 * -EINVAL if the requested state is invalid.
432 * -EIO if device does not support PCI PM or its PM capabilities register has a
433 * wrong version, or device doesn't support the requested state.
434 * 0 if device already is in the requested state.
435 * 0 if device's power state has been successfully changed.
437 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
440 bool need_restore = false;
445 if (state < PCI_D0 || state > PCI_D3hot)
448 /* Validate current state:
449 * Can enter D0 from any state, but if we can only go deeper
450 * to sleep if we're already in a low power state
452 if (dev->current_state == state) {
453 /* we're already there */
455 } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold
456 && dev->current_state > state) {
457 dev_err(&dev->dev, "invalid power transition "
458 "(from state %d to %d)\n", dev->current_state, state);
462 /* check if this device supports the desired state */
463 if ((state == PCI_D1 && !dev->d1_support)
464 || (state == PCI_D2 && !dev->d2_support))
467 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
469 /* If we're (effectively) in D3, force entire word to 0.
470 * This doesn't affect PME_Status, disables PME_En, and
471 * sets PowerState to 0.
473 switch (dev->current_state) {
477 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
480 case PCI_UNKNOWN: /* Boot-up */
481 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
482 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
484 /* Fall-through: force to D0 */
490 /* enter specified state */
491 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
493 /* Mandatory power management transition delays */
494 /* see PCI PM 1.1 5.6.1 table 18 */
495 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
496 msleep(pci_pm_d3_delay);
497 else if (state == PCI_D2 || dev->current_state == PCI_D2)
498 udelay(PCI_PM_D2_DELAY);
500 dev->current_state = state;
502 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
503 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
504 * from D3hot to D0 _may_ perform an internal reset, thereby
505 * going to "D0 Uninitialized" rather than "D0 Initialized".
506 * For example, at least some versions of the 3c905B and the
507 * 3c556B exhibit this behaviour.
509 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
510 * devices in a D3hot state at boot. Consequently, we need to
511 * restore at least the BARs so that the device will be
512 * accessible to its driver.
515 pci_restore_bars(dev);
518 pcie_aspm_pm_state_change(dev->bus->self);
524 * pci_update_current_state - Read PCI power state of given device from its
525 * PCI PM registers and cache it
526 * @dev: PCI device to handle.
527 * @state: State to cache in case the device doesn't have the PM capability
529 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
534 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
535 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
537 dev->current_state = state;
542 * pci_set_power_state - Set the power state of a PCI device
543 * @dev: PCI device to handle.
544 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
546 * Transition a device to a new power state, using the platform formware and/or
547 * the device's PCI PM registers.
550 * -EINVAL if the requested state is invalid.
551 * -EIO if device does not support PCI PM or its PM capabilities register has a
552 * wrong version, or device doesn't support the requested state.
553 * 0 if device already is in the requested state.
554 * 0 if device's power state has been successfully changed.
556 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
560 /* bound the state we're entering */
561 if (state > PCI_D3hot)
563 else if (state < PCI_D0)
565 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
567 * If the device or the parent bridge do not support PCI PM,
568 * ignore the request if we're doing anything other than putting
569 * it into D0 (which would only happen on boot).
573 if (state == PCI_D0 && platform_pci_power_manageable(dev)) {
575 * Allow the platform to change the state, for example via ACPI
576 * _PR0, _PS0 and some such, but do not trust it.
578 int ret = platform_pci_set_power_state(dev, PCI_D0);
580 pci_update_current_state(dev, PCI_D0);
582 /* This device is quirked not to be put into D3, so
583 don't put it in D3 */
584 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
587 error = pci_raw_set_power_state(dev, state);
589 if (state > PCI_D0 && platform_pci_power_manageable(dev)) {
590 /* Allow the platform to finalize the transition */
591 int ret = platform_pci_set_power_state(dev, state);
593 pci_update_current_state(dev, state);
602 * pci_choose_state - Choose the power state of a PCI device
603 * @dev: PCI device to be suspended
604 * @state: target sleep state for the whole system. This is the value
605 * that is passed to suspend() function.
607 * Returns PCI power state suitable for given device and given system
611 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
615 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
618 ret = platform_pci_choose_state(dev);
619 if (ret != PCI_POWER_ERROR)
622 switch (state.event) {
625 case PM_EVENT_FREEZE:
626 case PM_EVENT_PRETHAW:
627 /* REVISIT both freeze and pre-thaw "should" use D0 */
628 case PM_EVENT_SUSPEND:
629 case PM_EVENT_HIBERNATE:
632 dev_info(&dev->dev, "unrecognized suspend event %d\n",
639 EXPORT_SYMBOL(pci_choose_state);
641 static int pci_save_pcie_state(struct pci_dev *dev)
644 struct pci_cap_saved_state *save_state;
647 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
651 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
653 dev_err(&dev->dev, "buffer not found in %s\n", __FUNCTION__);
656 cap = (u16 *)&save_state->data[0];
658 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
659 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
660 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
661 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
666 static void pci_restore_pcie_state(struct pci_dev *dev)
669 struct pci_cap_saved_state *save_state;
672 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
673 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
674 if (!save_state || pos <= 0)
676 cap = (u16 *)&save_state->data[0];
678 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
679 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
680 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
681 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
685 static int pci_save_pcix_state(struct pci_dev *dev)
688 struct pci_cap_saved_state *save_state;
690 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
694 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
696 dev_err(&dev->dev, "buffer not found in %s\n", __FUNCTION__);
700 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
705 static void pci_restore_pcix_state(struct pci_dev *dev)
708 struct pci_cap_saved_state *save_state;
711 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
712 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
713 if (!save_state || pos <= 0)
715 cap = (u16 *)&save_state->data[0];
717 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
722 * pci_save_state - save the PCI configuration space of a device before suspending
723 * @dev: - PCI device that we're dealing with
726 pci_save_state(struct pci_dev *dev)
729 /* XXX: 100% dword access ok here? */
730 for (i = 0; i < 16; i++)
731 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
732 dev->state_saved = true;
733 if ((i = pci_save_pcie_state(dev)) != 0)
735 if ((i = pci_save_pcix_state(dev)) != 0)
741 * pci_restore_state - Restore the saved state of a PCI device
742 * @dev: - PCI device that we're dealing with
745 pci_restore_state(struct pci_dev *dev)
750 /* PCI Express register must be restored first */
751 pci_restore_pcie_state(dev);
754 * The Base Address register should be programmed before the command
757 for (i = 15; i >= 0; i--) {
758 pci_read_config_dword(dev, i * 4, &val);
759 if (val != dev->saved_config_space[i]) {
760 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
761 "space at offset %#x (was %#x, writing %#x)\n",
762 i, val, (int)dev->saved_config_space[i]);
763 pci_write_config_dword(dev,i * 4,
764 dev->saved_config_space[i]);
767 pci_restore_pcix_state(dev);
768 pci_restore_msi_state(dev);
773 static int do_pci_enable_device(struct pci_dev *dev, int bars)
777 err = pci_set_power_state(dev, PCI_D0);
778 if (err < 0 && err != -EIO)
780 err = pcibios_enable_device(dev, bars);
783 pci_fixup_device(pci_fixup_enable, dev);
789 * pci_reenable_device - Resume abandoned device
790 * @dev: PCI device to be resumed
792 * Note this function is a backend of pci_default_resume and is not supposed
793 * to be called by normal code, write proper resume handler and use it instead.
795 int pci_reenable_device(struct pci_dev *dev)
797 if (atomic_read(&dev->enable_cnt))
798 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
802 static int __pci_enable_device_flags(struct pci_dev *dev,
803 resource_size_t flags)
808 if (atomic_add_return(1, &dev->enable_cnt) > 1)
809 return 0; /* already enabled */
811 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
812 if (dev->resource[i].flags & flags)
815 err = do_pci_enable_device(dev, bars);
817 atomic_dec(&dev->enable_cnt);
822 * pci_enable_device_io - Initialize a device for use with IO space
823 * @dev: PCI device to be initialized
825 * Initialize device before it's used by a driver. Ask low-level code
826 * to enable I/O resources. Wake up the device if it was suspended.
827 * Beware, this function can fail.
829 int pci_enable_device_io(struct pci_dev *dev)
831 return __pci_enable_device_flags(dev, IORESOURCE_IO);
835 * pci_enable_device_mem - Initialize a device for use with Memory space
836 * @dev: PCI device to be initialized
838 * Initialize device before it's used by a driver. Ask low-level code
839 * to enable Memory resources. Wake up the device if it was suspended.
840 * Beware, this function can fail.
842 int pci_enable_device_mem(struct pci_dev *dev)
844 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
848 * pci_enable_device - Initialize device before it's used by a driver.
849 * @dev: PCI device to be initialized
851 * Initialize device before it's used by a driver. Ask low-level code
852 * to enable I/O and memory. Wake up the device if it was suspended.
853 * Beware, this function can fail.
855 * Note we don't actually enable the device many times if we call
856 * this function repeatedly (we just increment the count).
858 int pci_enable_device(struct pci_dev *dev)
860 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
864 * Managed PCI resources. This manages device on/off, intx/msi/msix
865 * on/off and BAR regions. pci_dev itself records msi/msix status, so
866 * there's no need to track it separately. pci_devres is initialized
867 * when a device is enabled using managed PCI device enable interface.
870 unsigned int enabled:1;
871 unsigned int pinned:1;
872 unsigned int orig_intx:1;
873 unsigned int restore_intx:1;
877 static void pcim_release(struct device *gendev, void *res)
879 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
880 struct pci_devres *this = res;
883 if (dev->msi_enabled)
884 pci_disable_msi(dev);
885 if (dev->msix_enabled)
886 pci_disable_msix(dev);
888 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
889 if (this->region_mask & (1 << i))
890 pci_release_region(dev, i);
892 if (this->restore_intx)
893 pci_intx(dev, this->orig_intx);
895 if (this->enabled && !this->pinned)
896 pci_disable_device(dev);
899 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
901 struct pci_devres *dr, *new_dr;
903 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
907 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
910 return devres_get(&pdev->dev, new_dr, NULL, NULL);
913 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
915 if (pci_is_managed(pdev))
916 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
921 * pcim_enable_device - Managed pci_enable_device()
922 * @pdev: PCI device to be initialized
924 * Managed pci_enable_device().
926 int pcim_enable_device(struct pci_dev *pdev)
928 struct pci_devres *dr;
931 dr = get_pci_dr(pdev);
937 rc = pci_enable_device(pdev);
939 pdev->is_managed = 1;
946 * pcim_pin_device - Pin managed PCI device
947 * @pdev: PCI device to pin
949 * Pin managed PCI device @pdev. Pinned device won't be disabled on
950 * driver detach. @pdev must have been enabled with
951 * pcim_enable_device().
953 void pcim_pin_device(struct pci_dev *pdev)
955 struct pci_devres *dr;
957 dr = find_pci_dr(pdev);
958 WARN_ON(!dr || !dr->enabled);
964 * pcibios_disable_device - disable arch specific PCI resources for device dev
965 * @dev: the PCI device to disable
967 * Disables architecture specific PCI resources for the device. This
968 * is the default implementation. Architecture implementations can
971 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
973 static void do_pci_disable_device(struct pci_dev *dev)
977 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
978 if (pci_command & PCI_COMMAND_MASTER) {
979 pci_command &= ~PCI_COMMAND_MASTER;
980 pci_write_config_word(dev, PCI_COMMAND, pci_command);
983 pcibios_disable_device(dev);
987 * pci_disable_enabled_device - Disable device without updating enable_cnt
988 * @dev: PCI device to disable
990 * NOTE: This function is a backend of PCI power management routines and is
991 * not supposed to be called drivers.
993 void pci_disable_enabled_device(struct pci_dev *dev)
995 if (atomic_read(&dev->enable_cnt))
996 do_pci_disable_device(dev);
1000 * pci_disable_device - Disable PCI device after use
1001 * @dev: PCI device to be disabled
1003 * Signal to the system that the PCI device is not in use by the system
1004 * anymore. This only involves disabling PCI bus-mastering, if active.
1006 * Note we don't actually disable the device until all callers of
1007 * pci_device_enable() have called pci_device_disable().
1010 pci_disable_device(struct pci_dev *dev)
1012 struct pci_devres *dr;
1014 dr = find_pci_dr(dev);
1018 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1021 do_pci_disable_device(dev);
1023 dev->is_busmaster = 0;
1027 * pcibios_set_pcie_reset_state - set reset state for device dev
1028 * @dev: the PCI-E device reset
1029 * @state: Reset state to enter into
1032 * Sets the PCI-E reset state for the device. This is the default
1033 * implementation. Architecture implementations can override this.
1035 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1036 enum pcie_reset_state state)
1042 * pci_set_pcie_reset_state - set reset state for device dev
1043 * @dev: the PCI-E device reset
1044 * @state: Reset state to enter into
1047 * Sets the PCI reset state for the device.
1049 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1051 return pcibios_set_pcie_reset_state(dev, state);
1055 * pci_pme_capable - check the capability of PCI device to generate PME#
1056 * @dev: PCI device to handle.
1057 * @state: PCI state from which device will issue PME#.
1059 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1064 return !!(dev->pme_support & (1 << state));
1068 * pci_pme_active - enable or disable PCI device's PME# function
1069 * @dev: PCI device to handle.
1070 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1072 * The caller must verify that the device is capable of generating PME# before
1073 * calling this function with @enable equal to 'true'.
1075 void pci_pme_active(struct pci_dev *dev, bool enable)
1082 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1083 /* Clear PME_Status by writing 1 to it and enable PME# */
1084 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1086 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1088 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1090 dev_printk(KERN_INFO, &dev->dev, "PME# %s\n",
1091 enable ? "enabled" : "disabled");
1095 * pci_enable_wake - enable PCI device as wakeup event source
1096 * @dev: PCI device affected
1097 * @state: PCI state from which device will issue wakeup events
1098 * @enable: True to enable event generation; false to disable
1100 * This enables the device as a wakeup event source, or disables it.
1101 * When such events involves platform-specific hooks, those hooks are
1102 * called automatically by this routine.
1104 * Devices with legacy power management (no standard PCI PM capabilities)
1105 * always require such platform hooks.
1108 * 0 is returned on success
1109 * -EINVAL is returned if device is not supposed to wake up the system
1110 * Error code depending on the platform is returned if both the platform and
1111 * the native mechanism fail to enable the generation of wake-up events
1113 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
1116 bool pme_done = false;
1118 if (enable && !device_may_wakeup(&dev->dev))
1122 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1123 * Anderson we should be doing PME# wake enable followed by ACPI wake
1124 * enable. To disable wake-up we call the platform first, for symmetry.
1127 if (!enable && platform_pci_can_wakeup(dev))
1128 error = platform_pci_sleep_wake(dev, false);
1130 if (!enable || pci_pme_capable(dev, state)) {
1131 pci_pme_active(dev, enable);
1135 if (enable && platform_pci_can_wakeup(dev))
1136 error = platform_pci_sleep_wake(dev, true);
1138 return pme_done ? 0 : error;
1142 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1143 * @dev: PCI device to prepare
1144 * @enable: True to enable wake-up event generation; false to disable
1146 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1147 * and this function allows them to set that up cleanly - pci_enable_wake()
1148 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1149 * ordering constraints.
1151 * This function only returns error code if the device is not capable of
1152 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1153 * enable wake-up power for it.
1155 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1157 return pci_pme_capable(dev, PCI_D3cold) ?
1158 pci_enable_wake(dev, PCI_D3cold, enable) :
1159 pci_enable_wake(dev, PCI_D3hot, enable);
1163 * pci_target_state - find an appropriate low power state for a given PCI dev
1166 * Use underlying platform code to find a supported low power state for @dev.
1167 * If the platform can't manage @dev, return the deepest state from which it
1168 * can generate wake events, based on any available PME info.
1170 pci_power_t pci_target_state(struct pci_dev *dev)
1172 pci_power_t target_state = PCI_D3hot;
1174 if (platform_pci_power_manageable(dev)) {
1176 * Call the platform to choose the target state of the device
1177 * and enable wake-up from this state if supported.
1179 pci_power_t state = platform_pci_choose_state(dev);
1182 case PCI_POWER_ERROR:
1187 if (pci_no_d1d2(dev))
1190 target_state = state;
1192 } else if (device_may_wakeup(&dev->dev)) {
1194 * Find the deepest state from which the device can generate
1195 * wake-up events, make it the target state and enable device
1199 return PCI_POWER_ERROR;
1201 if (dev->pme_support) {
1203 && !(dev->pme_support & (1 << target_state)))
1208 return target_state;
1212 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1213 * @dev: Device to handle.
1215 * Choose the power state appropriate for the device depending on whether
1216 * it can wake up the system and/or is power manageable by the platform
1217 * (PCI_D3hot is the default) and put the device into that state.
1219 int pci_prepare_to_sleep(struct pci_dev *dev)
1221 pci_power_t target_state = pci_target_state(dev);
1224 if (target_state == PCI_POWER_ERROR)
1227 pci_enable_wake(dev, target_state, true);
1229 error = pci_set_power_state(dev, target_state);
1232 pci_enable_wake(dev, target_state, false);
1238 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1239 * @dev: Device to handle.
1241 * Disable device's sytem wake-up capability and put it into D0.
1243 int pci_back_from_sleep(struct pci_dev *dev)
1245 pci_enable_wake(dev, PCI_D0, false);
1246 return pci_set_power_state(dev, PCI_D0);
1250 * pci_pm_init - Initialize PM functions of given PCI device
1251 * @dev: PCI device to handle.
1253 void pci_pm_init(struct pci_dev *dev)
1260 /* find PCI PM capability in list */
1261 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1264 /* Check device's ability to generate PME# */
1265 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1267 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1268 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1269 pmc & PCI_PM_CAP_VER_MASK);
1275 dev->d1_support = false;
1276 dev->d2_support = false;
1277 if (!pci_no_d1d2(dev)) {
1278 if (pmc & PCI_PM_CAP_D1)
1279 dev->d1_support = true;
1280 if (pmc & PCI_PM_CAP_D2)
1281 dev->d2_support = true;
1283 if (dev->d1_support || dev->d2_support)
1284 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1285 dev->d1_support ? " D1" : "",
1286 dev->d2_support ? " D2" : "");
1289 pmc &= PCI_PM_CAP_PME_MASK;
1291 dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n",
1292 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1293 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1294 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1295 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1296 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1297 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1299 * Make device's PM flags reflect the wake-up capability, but
1300 * let the user space enable it to wake up the system as needed.
1302 device_set_wakeup_capable(&dev->dev, true);
1303 device_set_wakeup_enable(&dev->dev, false);
1304 /* Disable the PME# generation functionality */
1305 pci_pme_active(dev, false);
1307 dev->pme_support = 0;
1312 * platform_pci_wakeup_init - init platform wakeup if present
1315 * Some devices don't have PCI PM caps but can still generate wakeup
1316 * events through platform methods (like ACPI events). If @dev supports
1317 * platform wakeup events, set the device flag to indicate as much. This
1318 * may be redundant if the device also supports PCI PM caps, but double
1319 * initialization should be safe in that case.
1321 void platform_pci_wakeup_init(struct pci_dev *dev)
1323 if (!platform_pci_can_wakeup(dev))
1326 device_set_wakeup_capable(&dev->dev, true);
1327 device_set_wakeup_enable(&dev->dev, false);
1328 platform_pci_sleep_wake(dev, false);
1332 * pci_add_save_buffer - allocate buffer for saving given capability registers
1333 * @dev: the PCI device
1334 * @cap: the capability to allocate the buffer for
1335 * @size: requested size of the buffer
1337 static int pci_add_cap_save_buffer(
1338 struct pci_dev *dev, char cap, unsigned int size)
1341 struct pci_cap_saved_state *save_state;
1343 pos = pci_find_capability(dev, cap);
1347 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1351 save_state->cap_nr = cap;
1352 pci_add_saved_cap(dev, save_state);
1358 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1359 * @dev: the PCI device
1361 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1365 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 4 * sizeof(u16));
1368 "unable to preallocate PCI Express save buffer\n");
1370 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1373 "unable to preallocate PCI-X save buffer\n");
1377 * pci_enable_ari - enable ARI forwarding if hardware support it
1378 * @dev: the PCI device
1380 void pci_enable_ari(struct pci_dev *dev)
1385 struct pci_dev *bridge;
1387 if (!dev->is_pcie || dev->devfn)
1390 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1394 bridge = dev->bus->self;
1395 if (!bridge || !bridge->is_pcie)
1398 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
1402 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1403 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1406 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1407 ctrl |= PCI_EXP_DEVCTL2_ARI;
1408 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1410 bridge->ari_enabled = 1;
1414 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1415 * @dev: the PCI device
1416 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1418 * Perform INTx swizzling for a device behind one level of bridge. This is
1419 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1420 * behind bridges on add-in cards.
1422 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1424 return (((pin - 1) + PCI_SLOT(dev->devfn)) % 4) + 1;
1428 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1436 while (dev->bus->self) {
1437 pin = pci_swizzle_interrupt_pin(dev, pin);
1438 dev = dev->bus->self;
1445 * pci_common_swizzle - swizzle INTx all the way to root bridge
1446 * @dev: the PCI device
1447 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1449 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1450 * bridges all the way up to a PCI root bus.
1452 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1456 while (dev->bus->self) {
1457 pin = pci_swizzle_interrupt_pin(dev, pin);
1458 dev = dev->bus->self;
1461 return PCI_SLOT(dev->devfn);
1465 * pci_release_region - Release a PCI bar
1466 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1467 * @bar: BAR to release
1469 * Releases the PCI I/O and memory resources previously reserved by a
1470 * successful call to pci_request_region. Call this function only
1471 * after all use of the PCI regions has ceased.
1473 void pci_release_region(struct pci_dev *pdev, int bar)
1475 struct pci_devres *dr;
1477 if (pci_resource_len(pdev, bar) == 0)
1479 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1480 release_region(pci_resource_start(pdev, bar),
1481 pci_resource_len(pdev, bar));
1482 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1483 release_mem_region(pci_resource_start(pdev, bar),
1484 pci_resource_len(pdev, bar));
1486 dr = find_pci_dr(pdev);
1488 dr->region_mask &= ~(1 << bar);
1492 * __pci_request_region - Reserved PCI I/O and memory resource
1493 * @pdev: PCI device whose resources are to be reserved
1494 * @bar: BAR to be reserved
1495 * @res_name: Name to be associated with resource.
1496 * @exclusive: whether the region access is exclusive or not
1498 * Mark the PCI region associated with PCI device @pdev BR @bar as
1499 * being reserved by owner @res_name. Do not access any
1500 * address inside the PCI regions unless this call returns
1503 * If @exclusive is set, then the region is marked so that userspace
1504 * is explicitly not allowed to map the resource via /dev/mem or
1505 * sysfs MMIO access.
1507 * Returns 0 on success, or %EBUSY on error. A warning
1508 * message is also printed on failure.
1510 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1513 struct pci_devres *dr;
1515 if (pci_resource_len(pdev, bar) == 0)
1518 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1519 if (!request_region(pci_resource_start(pdev, bar),
1520 pci_resource_len(pdev, bar), res_name))
1523 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1524 if (!__request_mem_region(pci_resource_start(pdev, bar),
1525 pci_resource_len(pdev, bar), res_name,
1530 dr = find_pci_dr(pdev);
1532 dr->region_mask |= 1 << bar;
1537 dev_warn(&pdev->dev, "BAR %d: can't reserve %s region %pR\n",
1539 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1540 &pdev->resource[bar]);
1545 * pci_request_region - Reserve PCI I/O and memory resource
1546 * @pdev: PCI device whose resources are to be reserved
1547 * @bar: BAR to be reserved
1548 * @res_name: Name to be associated with resource
1550 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1551 * being reserved by owner @res_name. Do not access any
1552 * address inside the PCI regions unless this call returns
1555 * Returns 0 on success, or %EBUSY on error. A warning
1556 * message is also printed on failure.
1558 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1560 return __pci_request_region(pdev, bar, res_name, 0);
1564 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1565 * @pdev: PCI device whose resources are to be reserved
1566 * @bar: BAR to be reserved
1567 * @res_name: Name to be associated with resource.
1569 * Mark the PCI region associated with PCI device @pdev BR @bar as
1570 * being reserved by owner @res_name. Do not access any
1571 * address inside the PCI regions unless this call returns
1574 * Returns 0 on success, or %EBUSY on error. A warning
1575 * message is also printed on failure.
1577 * The key difference that _exclusive makes it that userspace is
1578 * explicitly not allowed to map the resource via /dev/mem or
1581 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1583 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1586 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1587 * @pdev: PCI device whose resources were previously reserved
1588 * @bars: Bitmask of BARs to be released
1590 * Release selected PCI I/O and memory resources previously reserved.
1591 * Call this function only after all use of the PCI regions has ceased.
1593 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1597 for (i = 0; i < 6; i++)
1598 if (bars & (1 << i))
1599 pci_release_region(pdev, i);
1602 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1603 const char *res_name, int excl)
1607 for (i = 0; i < 6; i++)
1608 if (bars & (1 << i))
1609 if (__pci_request_region(pdev, i, res_name, excl))
1615 if (bars & (1 << i))
1616 pci_release_region(pdev, i);
1623 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1624 * @pdev: PCI device whose resources are to be reserved
1625 * @bars: Bitmask of BARs to be requested
1626 * @res_name: Name to be associated with resource
1628 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1629 const char *res_name)
1631 return __pci_request_selected_regions(pdev, bars, res_name, 0);
1634 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
1635 int bars, const char *res_name)
1637 return __pci_request_selected_regions(pdev, bars, res_name,
1638 IORESOURCE_EXCLUSIVE);
1642 * pci_release_regions - Release reserved PCI I/O and memory resources
1643 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1645 * Releases all PCI I/O and memory resources previously reserved by a
1646 * successful call to pci_request_regions. Call this function only
1647 * after all use of the PCI regions has ceased.
1650 void pci_release_regions(struct pci_dev *pdev)
1652 pci_release_selected_regions(pdev, (1 << 6) - 1);
1656 * pci_request_regions - Reserved PCI I/O and memory resources
1657 * @pdev: PCI device whose resources are to be reserved
1658 * @res_name: Name to be associated with resource.
1660 * Mark all PCI regions associated with PCI device @pdev as
1661 * being reserved by owner @res_name. Do not access any
1662 * address inside the PCI regions unless this call returns
1665 * Returns 0 on success, or %EBUSY on error. A warning
1666 * message is also printed on failure.
1668 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1670 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1674 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1675 * @pdev: PCI device whose resources are to be reserved
1676 * @res_name: Name to be associated with resource.
1678 * Mark all PCI regions associated with PCI device @pdev as
1679 * being reserved by owner @res_name. Do not access any
1680 * address inside the PCI regions unless this call returns
1683 * pci_request_regions_exclusive() will mark the region so that
1684 * /dev/mem and the sysfs MMIO access will not be allowed.
1686 * Returns 0 on success, or %EBUSY on error. A warning
1687 * message is also printed on failure.
1689 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
1691 return pci_request_selected_regions_exclusive(pdev,
1692 ((1 << 6) - 1), res_name);
1695 static void __pci_set_master(struct pci_dev *dev, bool enable)
1699 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
1701 cmd = old_cmd | PCI_COMMAND_MASTER;
1703 cmd = old_cmd & ~PCI_COMMAND_MASTER;
1704 if (cmd != old_cmd) {
1705 dev_dbg(&dev->dev, "%s bus mastering\n",
1706 enable ? "enabling" : "disabling");
1707 pci_write_config_word(dev, PCI_COMMAND, cmd);
1709 dev->is_busmaster = enable;
1713 * pci_set_master - enables bus-mastering for device dev
1714 * @dev: the PCI device to enable
1716 * Enables bus-mastering on the device and calls pcibios_set_master()
1717 * to do the needed arch specific settings.
1719 void pci_set_master(struct pci_dev *dev)
1721 __pci_set_master(dev, true);
1722 pcibios_set_master(dev);
1726 * pci_clear_master - disables bus-mastering for device dev
1727 * @dev: the PCI device to disable
1729 void pci_clear_master(struct pci_dev *dev)
1731 __pci_set_master(dev, false);
1734 #ifdef PCI_DISABLE_MWI
1735 int pci_set_mwi(struct pci_dev *dev)
1740 int pci_try_set_mwi(struct pci_dev *dev)
1745 void pci_clear_mwi(struct pci_dev *dev)
1751 #ifndef PCI_CACHE_LINE_BYTES
1752 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1755 /* This can be overridden by arch code. */
1756 /* Don't forget this is measured in 32-bit words, not bytes */
1757 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1760 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1761 * @dev: the PCI device for which MWI is to be enabled
1763 * Helper function for pci_set_mwi.
1764 * Originally copied from drivers/net/acenic.c.
1765 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1767 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1770 pci_set_cacheline_size(struct pci_dev *dev)
1774 if (!pci_cache_line_size)
1775 return -EINVAL; /* The system doesn't support MWI. */
1777 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1778 equal to or multiple of the right value. */
1779 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1780 if (cacheline_size >= pci_cache_line_size &&
1781 (cacheline_size % pci_cache_line_size) == 0)
1784 /* Write the correct value. */
1785 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1787 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1788 if (cacheline_size == pci_cache_line_size)
1791 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1792 "supported\n", pci_cache_line_size << 2);
1798 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1799 * @dev: the PCI device for which MWI is enabled
1801 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1803 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1806 pci_set_mwi(struct pci_dev *dev)
1811 rc = pci_set_cacheline_size(dev);
1815 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1816 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1817 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1818 cmd |= PCI_COMMAND_INVALIDATE;
1819 pci_write_config_word(dev, PCI_COMMAND, cmd);
1826 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1827 * @dev: the PCI device for which MWI is enabled
1829 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1830 * Callers are not required to check the return value.
1832 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1834 int pci_try_set_mwi(struct pci_dev *dev)
1836 int rc = pci_set_mwi(dev);
1841 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1842 * @dev: the PCI device to disable
1844 * Disables PCI Memory-Write-Invalidate transaction on the device
1847 pci_clear_mwi(struct pci_dev *dev)
1851 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1852 if (cmd & PCI_COMMAND_INVALIDATE) {
1853 cmd &= ~PCI_COMMAND_INVALIDATE;
1854 pci_write_config_word(dev, PCI_COMMAND, cmd);
1857 #endif /* ! PCI_DISABLE_MWI */
1860 * pci_intx - enables/disables PCI INTx for device dev
1861 * @pdev: the PCI device to operate on
1862 * @enable: boolean: whether to enable or disable PCI INTx
1864 * Enables/disables PCI INTx for device dev
1867 pci_intx(struct pci_dev *pdev, int enable)
1869 u16 pci_command, new;
1871 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1874 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1876 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1879 if (new != pci_command) {
1880 struct pci_devres *dr;
1882 pci_write_config_word(pdev, PCI_COMMAND, new);
1884 dr = find_pci_dr(pdev);
1885 if (dr && !dr->restore_intx) {
1886 dr->restore_intx = 1;
1887 dr->orig_intx = !enable;
1893 * pci_msi_off - disables any msi or msix capabilities
1894 * @dev: the PCI device to operate on
1896 * If you want to use msi see pci_enable_msi and friends.
1897 * This is a lower level primitive that allows us to disable
1898 * msi operation at the device level.
1900 void pci_msi_off(struct pci_dev *dev)
1905 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1907 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1908 control &= ~PCI_MSI_FLAGS_ENABLE;
1909 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1911 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1913 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1914 control &= ~PCI_MSIX_FLAGS_ENABLE;
1915 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1919 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1921 * These can be overridden by arch-specific implementations
1924 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1926 if (!pci_dma_supported(dev, mask))
1929 dev->dma_mask = mask;
1935 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1937 if (!pci_dma_supported(dev, mask))
1940 dev->dev.coherent_dma_mask = mask;
1946 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1947 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
1949 return dma_set_max_seg_size(&dev->dev, size);
1951 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
1954 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1955 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
1957 return dma_set_seg_boundary(&dev->dev, mask);
1959 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
1962 static int __pcie_flr(struct pci_dev *dev, int probe)
1966 int exppos = pci_find_capability(dev, PCI_CAP_ID_EXP);
1970 pci_read_config_dword(dev, exppos + PCI_EXP_DEVCAP, &cap);
1971 if (!(cap & PCI_EXP_DEVCAP_FLR))
1977 pci_block_user_cfg_access(dev);
1979 /* Wait for Transaction Pending bit clean */
1981 pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status);
1982 if (status & PCI_EXP_DEVSTA_TRPND) {
1983 dev_info(&dev->dev, "Busy after 100ms while trying to reset; "
1984 "sleeping for 1 second\n");
1986 pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status);
1987 if (status & PCI_EXP_DEVSTA_TRPND)
1988 dev_info(&dev->dev, "Still busy after 1s; "
1989 "proceeding with reset anyway\n");
1992 pci_write_config_word(dev, exppos + PCI_EXP_DEVCTL,
1993 PCI_EXP_DEVCTL_BCR_FLR);
1996 pci_unblock_user_cfg_access(dev);
2000 static int __pci_af_flr(struct pci_dev *dev, int probe)
2002 int cappos = pci_find_capability(dev, PCI_CAP_ID_AF);
2008 pci_read_config_byte(dev, cappos + PCI_AF_CAP, &cap);
2009 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2015 pci_block_user_cfg_access(dev);
2017 /* Wait for Transaction Pending bit clean */
2019 pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status);
2020 if (status & PCI_AF_STATUS_TP) {
2021 dev_info(&dev->dev, "Busy after 100ms while trying to"
2022 " reset; sleeping for 1 second\n");
2024 pci_read_config_byte(dev,
2025 cappos + PCI_AF_STATUS, &status);
2026 if (status & PCI_AF_STATUS_TP)
2027 dev_info(&dev->dev, "Still busy after 1s; "
2028 "proceeding with reset anyway\n");
2030 pci_write_config_byte(dev, cappos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2033 pci_unblock_user_cfg_access(dev);
2037 static int __pci_reset_function(struct pci_dev *pdev, int probe)
2041 res = __pcie_flr(pdev, probe);
2045 res = __pci_af_flr(pdev, probe);
2053 * pci_execute_reset_function() - Reset a PCI device function
2054 * @dev: Device function to reset
2056 * Some devices allow an individual function to be reset without affecting
2057 * other functions in the same device. The PCI device must be responsive
2058 * to PCI config space in order to use this function.
2060 * The device function is presumed to be unused when this function is called.
2061 * Resetting the device will make the contents of PCI configuration space
2062 * random, so any caller of this must be prepared to reinitialise the
2063 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2066 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2067 * device doesn't support resetting a single function.
2069 int pci_execute_reset_function(struct pci_dev *dev)
2071 return __pci_reset_function(dev, 0);
2073 EXPORT_SYMBOL_GPL(pci_execute_reset_function);
2076 * pci_reset_function() - quiesce and reset a PCI device function
2077 * @dev: Device function to reset
2079 * Some devices allow an individual function to be reset without affecting
2080 * other functions in the same device. The PCI device must be responsive
2081 * to PCI config space in order to use this function.
2083 * This function does not just reset the PCI portion of a device, but
2084 * clears all the state associated with the device. This function differs
2085 * from pci_execute_reset_function in that it saves and restores device state
2088 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2089 * device doesn't support resetting a single function.
2091 int pci_reset_function(struct pci_dev *dev)
2093 int r = __pci_reset_function(dev, 1);
2098 if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0)
2099 disable_irq(dev->irq);
2100 pci_save_state(dev);
2102 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2104 r = pci_execute_reset_function(dev);
2106 pci_restore_state(dev);
2107 if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0)
2108 enable_irq(dev->irq);
2112 EXPORT_SYMBOL_GPL(pci_reset_function);
2115 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2116 * @dev: PCI device to query
2118 * Returns mmrbc: maximum designed memory read count in bytes
2119 * or appropriate error value.
2121 int pcix_get_max_mmrbc(struct pci_dev *dev)
2126 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2130 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2134 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
2136 EXPORT_SYMBOL(pcix_get_max_mmrbc);
2139 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2140 * @dev: PCI device to query
2142 * Returns mmrbc: maximum memory read count in bytes
2143 * or appropriate error value.
2145 int pcix_get_mmrbc(struct pci_dev *dev)
2150 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2154 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2156 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2160 EXPORT_SYMBOL(pcix_get_mmrbc);
2163 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2164 * @dev: PCI device to query
2165 * @mmrbc: maximum memory read count in bytes
2166 * valid values are 512, 1024, 2048, 4096
2168 * If possible sets maximum memory read byte count, some bridges have erratas
2169 * that prevent this.
2171 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2173 int cap, err = -EINVAL;
2174 u32 stat, cmd, v, o;
2176 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2179 v = ffs(mmrbc) - 10;
2181 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2185 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2189 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2192 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2196 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2198 if (v > o && dev->bus &&
2199 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2202 cmd &= ~PCI_X_CMD_MAX_READ;
2204 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
2209 EXPORT_SYMBOL(pcix_set_mmrbc);
2212 * pcie_get_readrq - get PCI Express read request size
2213 * @dev: PCI device to query
2215 * Returns maximum memory read request in bytes
2216 * or appropriate error value.
2218 int pcie_get_readrq(struct pci_dev *dev)
2223 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
2227 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2229 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2233 EXPORT_SYMBOL(pcie_get_readrq);
2236 * pcie_set_readrq - set PCI Express maximum memory read request
2237 * @dev: PCI device to query
2238 * @rq: maximum memory read count in bytes
2239 * valid values are 128, 256, 512, 1024, 2048, 4096
2241 * If possible sets maximum read byte count
2243 int pcie_set_readrq(struct pci_dev *dev, int rq)
2245 int cap, err = -EINVAL;
2248 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2251 v = (ffs(rq) - 8) << 12;
2253 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
2257 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2261 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2262 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2264 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2270 EXPORT_SYMBOL(pcie_set_readrq);
2273 * pci_select_bars - Make BAR mask from the type of resource
2274 * @dev: the PCI device for which BAR mask is made
2275 * @flags: resource type mask to be selected
2277 * This helper routine makes bar mask from the type of resource.
2279 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2282 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2283 if (pci_resource_flags(dev, i) & flags)
2289 * pci_resource_bar - get position of the BAR associated with a resource
2290 * @dev: the PCI device
2291 * @resno: the resource number
2292 * @type: the BAR type to be filled in
2294 * Returns BAR position in config space, or 0 if the BAR is invalid.
2296 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2298 if (resno < PCI_ROM_RESOURCE) {
2299 *type = pci_bar_unknown;
2300 return PCI_BASE_ADDRESS_0 + 4 * resno;
2301 } else if (resno == PCI_ROM_RESOURCE) {
2302 *type = pci_bar_mem32;
2303 return dev->rom_base_reg;
2306 dev_err(&dev->dev, "BAR: invalid resource #%d\n", resno);
2310 static void __devinit pci_no_domains(void)
2312 #ifdef CONFIG_PCI_DOMAINS
2313 pci_domains_supported = 0;
2318 * pci_ext_cfg_enabled - can we access extended PCI config space?
2319 * @dev: The PCI device of the root bridge.
2321 * Returns 1 if we can access PCI extended config space (offsets
2322 * greater than 0xff). This is the default implementation. Architecture
2323 * implementations can override this.
2325 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2330 static int __devinit pci_init(void)
2332 struct pci_dev *dev = NULL;
2334 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2335 pci_fixup_device(pci_fixup_final, dev);
2341 static int __init pci_setup(char *str)
2344 char *k = strchr(str, ',');
2347 if (*str && (str = pcibios_setup(str)) && *str) {
2348 if (!strcmp(str, "nomsi")) {
2350 } else if (!strcmp(str, "noaer")) {
2352 } else if (!strcmp(str, "nodomains")) {
2354 } else if (!strncmp(str, "cbiosize=", 9)) {
2355 pci_cardbus_io_size = memparse(str + 9, &str);
2356 } else if (!strncmp(str, "cbmemsize=", 10)) {
2357 pci_cardbus_mem_size = memparse(str + 10, &str);
2359 printk(KERN_ERR "PCI: Unknown option `%s'\n",
2367 early_param("pci", pci_setup);
2369 device_initcall(pci_init);
2371 EXPORT_SYMBOL(pci_reenable_device);
2372 EXPORT_SYMBOL(pci_enable_device_io);
2373 EXPORT_SYMBOL(pci_enable_device_mem);
2374 EXPORT_SYMBOL(pci_enable_device);
2375 EXPORT_SYMBOL(pcim_enable_device);
2376 EXPORT_SYMBOL(pcim_pin_device);
2377 EXPORT_SYMBOL(pci_disable_device);
2378 EXPORT_SYMBOL(pci_find_capability);
2379 EXPORT_SYMBOL(pci_bus_find_capability);
2380 EXPORT_SYMBOL(pci_release_regions);
2381 EXPORT_SYMBOL(pci_request_regions);
2382 EXPORT_SYMBOL(pci_request_regions_exclusive);
2383 EXPORT_SYMBOL(pci_release_region);
2384 EXPORT_SYMBOL(pci_request_region);
2385 EXPORT_SYMBOL(pci_request_region_exclusive);
2386 EXPORT_SYMBOL(pci_release_selected_regions);
2387 EXPORT_SYMBOL(pci_request_selected_regions);
2388 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2389 EXPORT_SYMBOL(pci_set_master);
2390 EXPORT_SYMBOL(pci_clear_master);
2391 EXPORT_SYMBOL(pci_set_mwi);
2392 EXPORT_SYMBOL(pci_try_set_mwi);
2393 EXPORT_SYMBOL(pci_clear_mwi);
2394 EXPORT_SYMBOL_GPL(pci_intx);
2395 EXPORT_SYMBOL(pci_set_dma_mask);
2396 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
2397 EXPORT_SYMBOL(pci_assign_resource);
2398 EXPORT_SYMBOL(pci_find_parent_resource);
2399 EXPORT_SYMBOL(pci_select_bars);
2401 EXPORT_SYMBOL(pci_set_power_state);
2402 EXPORT_SYMBOL(pci_save_state);
2403 EXPORT_SYMBOL(pci_restore_state);
2404 EXPORT_SYMBOL(pci_pme_capable);
2405 EXPORT_SYMBOL(pci_pme_active);
2406 EXPORT_SYMBOL(pci_enable_wake);
2407 EXPORT_SYMBOL(pci_wake_from_d3);
2408 EXPORT_SYMBOL(pci_target_state);
2409 EXPORT_SYMBOL(pci_prepare_to_sleep);
2410 EXPORT_SYMBOL(pci_back_from_sleep);
2411 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);