2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 unsigned int pci_pm_d3_delay = 10;
25 #ifdef CONFIG_PCI_DOMAINS
26 int pci_domains_supported = 1;
29 #define DEFAULT_CARDBUS_IO_SIZE (256)
30 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
31 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
32 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
33 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
36 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
37 * @bus: pointer to PCI bus structure to search
39 * Given a PCI bus, returns the highest PCI bus number present in the set
40 * including the given PCI bus and its list of child PCI buses.
42 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
44 struct list_head *tmp;
47 max = bus->subordinate;
48 list_for_each(tmp, &bus->children) {
49 n = pci_bus_max_busnr(pci_bus_b(tmp));
55 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
59 * pci_max_busnr - returns maximum PCI bus number
61 * Returns the highest PCI bus number present in the system global list of
64 unsigned char __devinit
67 struct pci_bus *bus = NULL;
71 while ((bus = pci_find_next_bus(bus)) != NULL) {
72 n = pci_bus_max_busnr(bus);
81 #define PCI_FIND_CAP_TTL 48
83 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
84 u8 pos, int cap, int *ttl)
89 pci_bus_read_config_byte(bus, devfn, pos, &pos);
93 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
99 pos += PCI_CAP_LIST_NEXT;
104 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
107 int ttl = PCI_FIND_CAP_TTL;
109 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
112 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
114 return __pci_find_next_cap(dev->bus, dev->devfn,
115 pos + PCI_CAP_LIST_NEXT, cap);
117 EXPORT_SYMBOL_GPL(pci_find_next_capability);
119 static int __pci_bus_find_cap_start(struct pci_bus *bus,
120 unsigned int devfn, u8 hdr_type)
124 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
125 if (!(status & PCI_STATUS_CAP_LIST))
129 case PCI_HEADER_TYPE_NORMAL:
130 case PCI_HEADER_TYPE_BRIDGE:
131 return PCI_CAPABILITY_LIST;
132 case PCI_HEADER_TYPE_CARDBUS:
133 return PCI_CB_CAPABILITY_LIST;
142 * pci_find_capability - query for devices' capabilities
143 * @dev: PCI device to query
144 * @cap: capability code
146 * Tell if a device supports a given PCI capability.
147 * Returns the address of the requested capability structure within the
148 * device's PCI configuration space or 0 in case the device does not
149 * support it. Possible values for @cap:
151 * %PCI_CAP_ID_PM Power Management
152 * %PCI_CAP_ID_AGP Accelerated Graphics Port
153 * %PCI_CAP_ID_VPD Vital Product Data
154 * %PCI_CAP_ID_SLOTID Slot Identification
155 * %PCI_CAP_ID_MSI Message Signalled Interrupts
156 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
157 * %PCI_CAP_ID_PCIX PCI-X
158 * %PCI_CAP_ID_EXP PCI Express
160 int pci_find_capability(struct pci_dev *dev, int cap)
164 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
166 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
172 * pci_bus_find_capability - query for devices' capabilities
173 * @bus: the PCI bus to query
174 * @devfn: PCI device to query
175 * @cap: capability code
177 * Like pci_find_capability() but works for pci devices that do not have a
178 * pci_dev structure set up yet.
180 * Returns the address of the requested capability structure within the
181 * device's PCI configuration space or 0 in case the device does not
184 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
189 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
191 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
193 pos = __pci_find_next_cap(bus, devfn, pos, cap);
199 * pci_find_ext_capability - Find an extended capability
200 * @dev: PCI device to query
201 * @cap: capability code
203 * Returns the address of the requested extended capability structure
204 * within the device's PCI configuration space or 0 if the device does
205 * not support it. Possible values for @cap:
207 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
208 * %PCI_EXT_CAP_ID_VC Virtual Channel
209 * %PCI_EXT_CAP_ID_DSN Device Serial Number
210 * %PCI_EXT_CAP_ID_PWR Power Budgeting
212 int pci_find_ext_capability(struct pci_dev *dev, int cap)
215 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
218 if (dev->cfg_size <= 256)
221 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
225 * If we have no capabilities, this is indicated by cap ID,
226 * cap version and next pointer all being 0.
232 if (PCI_EXT_CAP_ID(header) == cap)
235 pos = PCI_EXT_CAP_NEXT(header);
239 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
245 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
247 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
249 int rc, ttl = PCI_FIND_CAP_TTL;
252 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
253 mask = HT_3BIT_CAP_MASK;
255 mask = HT_5BIT_CAP_MASK;
257 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
258 PCI_CAP_ID_HT, &ttl);
260 rc = pci_read_config_byte(dev, pos + 3, &cap);
261 if (rc != PCIBIOS_SUCCESSFUL)
264 if ((cap & mask) == ht_cap)
267 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
268 pos + PCI_CAP_LIST_NEXT,
269 PCI_CAP_ID_HT, &ttl);
275 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
276 * @dev: PCI device to query
277 * @pos: Position from which to continue searching
278 * @ht_cap: Hypertransport capability code
280 * To be used in conjunction with pci_find_ht_capability() to search for
281 * all capabilities matching @ht_cap. @pos should always be a value returned
282 * from pci_find_ht_capability().
284 * NB. To be 100% safe against broken PCI devices, the caller should take
285 * steps to avoid an infinite loop.
287 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
289 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
291 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
294 * pci_find_ht_capability - query a device's Hypertransport capabilities
295 * @dev: PCI device to query
296 * @ht_cap: Hypertransport capability code
298 * Tell if a device supports a given Hypertransport capability.
299 * Returns an address within the device's PCI configuration space
300 * or 0 in case the device does not support the request capability.
301 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
302 * which has a Hypertransport capability matching @ht_cap.
304 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
308 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
310 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
314 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
317 * pci_find_parent_resource - return resource region of parent bus of given region
318 * @dev: PCI device structure contains resources to be searched
319 * @res: child resource record for which parent is sought
321 * For given resource region of given device, return the resource
322 * region of parent bus the given region is contained in or where
323 * it should be allocated from.
326 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
328 const struct pci_bus *bus = dev->bus;
330 struct resource *best = NULL;
332 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
333 struct resource *r = bus->resource[i];
336 if (res->start && !(res->start >= r->start && res->end <= r->end))
337 continue; /* Not contained */
338 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
339 continue; /* Wrong type */
340 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
341 return r; /* Exact match */
342 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
343 best = r; /* Approximating prefetchable by non-prefetchable */
349 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
350 * @dev: PCI device to have its BARs restored
352 * Restore the BAR values for a given device, so as to make it
353 * accessible by its driver.
356 pci_restore_bars(struct pci_dev *dev)
360 switch (dev->hdr_type) {
361 case PCI_HEADER_TYPE_NORMAL:
364 case PCI_HEADER_TYPE_BRIDGE:
367 case PCI_HEADER_TYPE_CARDBUS:
371 /* Should never get here, but just in case... */
375 for (i = 0; i < numres; i ++)
376 pci_update_resource(dev, &dev->resource[i], i);
379 static struct pci_platform_pm_ops *pci_platform_pm;
381 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
383 if (!ops->is_manageable || !ops->set_state || !ops->choose_state)
385 pci_platform_pm = ops;
389 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
391 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
394 static inline int platform_pci_set_power_state(struct pci_dev *dev,
397 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
400 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
402 return pci_platform_pm ?
403 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
407 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
409 * @dev: PCI device to handle.
410 * @pm: PCI PM capability offset of the device.
411 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
414 * -EINVAL if the requested state is invalid.
415 * -EIO if device does not support PCI PM or its PM capabilities register has a
416 * wrong version, or device doesn't support the requested state.
417 * 0 if device already is in the requested state.
418 * 0 if device's power state has been successfully changed.
421 pci_raw_set_power_state(struct pci_dev *dev, int pm, pci_power_t state)
424 bool need_restore = false;
429 if (state < PCI_D0 || state > PCI_D3hot)
432 /* Validate current state:
433 * Can enter D0 from any state, but if we can only go deeper
434 * to sleep if we're already in a low power state
436 if (dev->current_state == state) {
437 /* we're already there */
439 } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold
440 && dev->current_state > state) {
441 dev_err(&dev->dev, "invalid power transition "
442 "(from state %d to %d)\n", dev->current_state, state);
446 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
448 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
449 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
450 pmc & PCI_PM_CAP_VER_MASK);
454 /* check if this device supports the desired state */
455 if ((state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
456 || (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)))
459 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
461 /* If we're (effectively) in D3, force entire word to 0.
462 * This doesn't affect PME_Status, disables PME_En, and
463 * sets PowerState to 0.
465 switch (dev->current_state) {
469 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
472 case PCI_UNKNOWN: /* Boot-up */
473 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
474 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
476 /* Fall-through: force to D0 */
482 /* enter specified state */
483 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
485 /* Mandatory power management transition delays */
486 /* see PCI PM 1.1 5.6.1 table 18 */
487 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
488 msleep(pci_pm_d3_delay);
489 else if (state == PCI_D2 || dev->current_state == PCI_D2)
492 dev->current_state = state;
494 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
495 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
496 * from D3hot to D0 _may_ perform an internal reset, thereby
497 * going to "D0 Uninitialized" rather than "D0 Initialized".
498 * For example, at least some versions of the 3c905B and the
499 * 3c556B exhibit this behaviour.
501 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
502 * devices in a D3hot state at boot. Consequently, we need to
503 * restore at least the BARs so that the device will be
504 * accessible to its driver.
507 pci_restore_bars(dev);
510 pcie_aspm_pm_state_change(dev->bus->self);
516 * pci_update_current_state - Read PCI power state of given device from its
517 * PCI PM registers and cache it
518 * @dev: PCI device to handle.
519 * @pm: PCI PM capability offset of the device.
521 static void pci_update_current_state(struct pci_dev *dev, int pm)
526 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
527 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
532 * pci_set_power_state - Set the power state of a PCI device
533 * @dev: PCI device to handle.
534 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
536 * Transition a device to a new power state, using the platform formware and/or
537 * the device's PCI PM registers.
540 * -EINVAL if the requested state is invalid.
541 * -EIO if device does not support PCI PM or its PM capabilities register has a
542 * wrong version, or device doesn't support the requested state.
543 * 0 if device already is in the requested state.
544 * 0 if device's power state has been successfully changed.
546 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
550 /* bound the state we're entering */
551 if (state > PCI_D3hot)
553 else if (state < PCI_D0)
555 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
557 * If the device or the parent bridge do not support PCI PM,
558 * ignore the request if we're doing anything other than putting
559 * it into D0 (which would only happen on boot).
563 /* Find PCI PM capability in the list */
564 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
566 if (state == PCI_D0 && platform_pci_power_manageable(dev)) {
568 * Allow the platform to change the state, for example via ACPI
569 * _PR0, _PS0 and some such, but do not trust it.
571 int ret = platform_pci_set_power_state(dev, PCI_D0);
573 pci_update_current_state(dev, pm);
576 error = pci_raw_set_power_state(dev, pm, state);
578 if (state > PCI_D0 && platform_pci_power_manageable(dev)) {
579 /* Allow the platform to finalize the transition */
580 int ret = platform_pci_set_power_state(dev, state);
582 pci_update_current_state(dev, pm);
591 * pci_choose_state - Choose the power state of a PCI device
592 * @dev: PCI device to be suspended
593 * @state: target sleep state for the whole system. This is the value
594 * that is passed to suspend() function.
596 * Returns PCI power state suitable for given device and given system
600 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
604 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
607 ret = platform_pci_choose_state(dev);
608 if (ret != PCI_POWER_ERROR)
611 switch (state.event) {
614 case PM_EVENT_FREEZE:
615 case PM_EVENT_PRETHAW:
616 /* REVISIT both freeze and pre-thaw "should" use D0 */
617 case PM_EVENT_SUSPEND:
618 case PM_EVENT_HIBERNATE:
621 dev_info(&dev->dev, "unrecognized suspend event %d\n",
628 EXPORT_SYMBOL(pci_choose_state);
630 static int pci_save_pcie_state(struct pci_dev *dev)
633 struct pci_cap_saved_state *save_state;
637 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
641 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
643 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
647 dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
650 cap = (u16 *)&save_state->data[0];
652 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
653 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
654 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
655 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
656 save_state->cap_nr = PCI_CAP_ID_EXP;
658 pci_add_saved_cap(dev, save_state);
662 static void pci_restore_pcie_state(struct pci_dev *dev)
665 struct pci_cap_saved_state *save_state;
668 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
669 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
670 if (!save_state || pos <= 0)
672 cap = (u16 *)&save_state->data[0];
674 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
675 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
676 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
677 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
681 static int pci_save_pcix_state(struct pci_dev *dev)
684 struct pci_cap_saved_state *save_state;
688 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
692 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
694 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
698 dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
701 cap = (u16 *)&save_state->data[0];
703 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
704 save_state->cap_nr = PCI_CAP_ID_PCIX;
706 pci_add_saved_cap(dev, save_state);
710 static void pci_restore_pcix_state(struct pci_dev *dev)
713 struct pci_cap_saved_state *save_state;
716 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
717 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
718 if (!save_state || pos <= 0)
720 cap = (u16 *)&save_state->data[0];
722 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
727 * pci_save_state - save the PCI configuration space of a device before suspending
728 * @dev: - PCI device that we're dealing with
731 pci_save_state(struct pci_dev *dev)
734 /* XXX: 100% dword access ok here? */
735 for (i = 0; i < 16; i++)
736 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
737 if ((i = pci_save_pcie_state(dev)) != 0)
739 if ((i = pci_save_pcix_state(dev)) != 0)
745 * pci_restore_state - Restore the saved state of a PCI device
746 * @dev: - PCI device that we're dealing with
749 pci_restore_state(struct pci_dev *dev)
754 /* PCI Express register must be restored first */
755 pci_restore_pcie_state(dev);
758 * The Base Address register should be programmed before the command
761 for (i = 15; i >= 0; i--) {
762 pci_read_config_dword(dev, i * 4, &val);
763 if (val != dev->saved_config_space[i]) {
764 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
765 "space at offset %#x (was %#x, writing %#x)\n",
766 i, val, (int)dev->saved_config_space[i]);
767 pci_write_config_dword(dev,i * 4,
768 dev->saved_config_space[i]);
771 pci_restore_pcix_state(dev);
772 pci_restore_msi_state(dev);
777 static int do_pci_enable_device(struct pci_dev *dev, int bars)
781 err = pci_set_power_state(dev, PCI_D0);
782 if (err < 0 && err != -EIO)
784 err = pcibios_enable_device(dev, bars);
787 pci_fixup_device(pci_fixup_enable, dev);
793 * pci_reenable_device - Resume abandoned device
794 * @dev: PCI device to be resumed
796 * Note this function is a backend of pci_default_resume and is not supposed
797 * to be called by normal code, write proper resume handler and use it instead.
799 int pci_reenable_device(struct pci_dev *dev)
801 if (atomic_read(&dev->enable_cnt))
802 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
806 static int __pci_enable_device_flags(struct pci_dev *dev,
807 resource_size_t flags)
812 if (atomic_add_return(1, &dev->enable_cnt) > 1)
813 return 0; /* already enabled */
815 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
816 if (dev->resource[i].flags & flags)
819 err = do_pci_enable_device(dev, bars);
821 atomic_dec(&dev->enable_cnt);
826 * pci_enable_device_io - Initialize a device for use with IO space
827 * @dev: PCI device to be initialized
829 * Initialize device before it's used by a driver. Ask low-level code
830 * to enable I/O resources. Wake up the device if it was suspended.
831 * Beware, this function can fail.
833 int pci_enable_device_io(struct pci_dev *dev)
835 return __pci_enable_device_flags(dev, IORESOURCE_IO);
839 * pci_enable_device_mem - Initialize a device for use with Memory space
840 * @dev: PCI device to be initialized
842 * Initialize device before it's used by a driver. Ask low-level code
843 * to enable Memory resources. Wake up the device if it was suspended.
844 * Beware, this function can fail.
846 int pci_enable_device_mem(struct pci_dev *dev)
848 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
852 * pci_enable_device - Initialize device before it's used by a driver.
853 * @dev: PCI device to be initialized
855 * Initialize device before it's used by a driver. Ask low-level code
856 * to enable I/O and memory. Wake up the device if it was suspended.
857 * Beware, this function can fail.
859 * Note we don't actually enable the device many times if we call
860 * this function repeatedly (we just increment the count).
862 int pci_enable_device(struct pci_dev *dev)
864 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
868 * Managed PCI resources. This manages device on/off, intx/msi/msix
869 * on/off and BAR regions. pci_dev itself records msi/msix status, so
870 * there's no need to track it separately. pci_devres is initialized
871 * when a device is enabled using managed PCI device enable interface.
874 unsigned int enabled:1;
875 unsigned int pinned:1;
876 unsigned int orig_intx:1;
877 unsigned int restore_intx:1;
881 static void pcim_release(struct device *gendev, void *res)
883 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
884 struct pci_devres *this = res;
887 if (dev->msi_enabled)
888 pci_disable_msi(dev);
889 if (dev->msix_enabled)
890 pci_disable_msix(dev);
892 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
893 if (this->region_mask & (1 << i))
894 pci_release_region(dev, i);
896 if (this->restore_intx)
897 pci_intx(dev, this->orig_intx);
899 if (this->enabled && !this->pinned)
900 pci_disable_device(dev);
903 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
905 struct pci_devres *dr, *new_dr;
907 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
911 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
914 return devres_get(&pdev->dev, new_dr, NULL, NULL);
917 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
919 if (pci_is_managed(pdev))
920 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
925 * pcim_enable_device - Managed pci_enable_device()
926 * @pdev: PCI device to be initialized
928 * Managed pci_enable_device().
930 int pcim_enable_device(struct pci_dev *pdev)
932 struct pci_devres *dr;
935 dr = get_pci_dr(pdev);
941 rc = pci_enable_device(pdev);
943 pdev->is_managed = 1;
950 * pcim_pin_device - Pin managed PCI device
951 * @pdev: PCI device to pin
953 * Pin managed PCI device @pdev. Pinned device won't be disabled on
954 * driver detach. @pdev must have been enabled with
955 * pcim_enable_device().
957 void pcim_pin_device(struct pci_dev *pdev)
959 struct pci_devres *dr;
961 dr = find_pci_dr(pdev);
962 WARN_ON(!dr || !dr->enabled);
968 * pcibios_disable_device - disable arch specific PCI resources for device dev
969 * @dev: the PCI device to disable
971 * Disables architecture specific PCI resources for the device. This
972 * is the default implementation. Architecture implementations can
975 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
978 * pci_disable_device - Disable PCI device after use
979 * @dev: PCI device to be disabled
981 * Signal to the system that the PCI device is not in use by the system
982 * anymore. This only involves disabling PCI bus-mastering, if active.
984 * Note we don't actually disable the device until all callers of
985 * pci_device_enable() have called pci_device_disable().
988 pci_disable_device(struct pci_dev *dev)
990 struct pci_devres *dr;
993 dr = find_pci_dr(dev);
997 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1000 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1001 if (pci_command & PCI_COMMAND_MASTER) {
1002 pci_command &= ~PCI_COMMAND_MASTER;
1003 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1005 dev->is_busmaster = 0;
1007 pcibios_disable_device(dev);
1011 * pcibios_set_pcie_reset_state - set reset state for device dev
1012 * @dev: the PCI-E device reset
1013 * @state: Reset state to enter into
1016 * Sets the PCI-E reset state for the device. This is the default
1017 * implementation. Architecture implementations can override this.
1019 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1020 enum pcie_reset_state state)
1026 * pci_set_pcie_reset_state - set reset state for device dev
1027 * @dev: the PCI-E device reset
1028 * @state: Reset state to enter into
1031 * Sets the PCI reset state for the device.
1033 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1035 return pcibios_set_pcie_reset_state(dev, state);
1039 * pci_enable_wake - enable PCI device as wakeup event source
1040 * @dev: PCI device affected
1041 * @state: PCI state from which device will issue wakeup events
1042 * @enable: True to enable event generation; false to disable
1044 * This enables the device as a wakeup event source, or disables it.
1045 * When such events involves platform-specific hooks, those hooks are
1046 * called automatically by this routine.
1048 * Devices with legacy power management (no standard PCI PM capabilities)
1049 * always require such platform hooks. Depending on the platform, devices
1050 * supporting the standard PCI PME# signal may require such platform hooks;
1051 * they always update bits in config space to allow PME# generation.
1053 * -EIO is returned if the device can't ever be a wakeup event source.
1054 * -EINVAL is returned if the device can't generate wakeup events from
1055 * the specified PCI state. Returns zero if the operation is successful.
1057 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
1063 /* Note that drivers should verify device_may_wakeup(&dev->dev)
1064 * before calling this function. Platform code should report
1065 * errors when drivers try to enable wakeup on devices that
1066 * can't issue wakeups, or on which wakeups were disabled by
1067 * userspace updating the /sys/devices.../power/wakeup file.
1070 status = call_platform_enable_wakeup(&dev->dev, enable);
1072 /* find PCI PM capability in list */
1073 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1075 /* If device doesn't support PM Capabilities, but caller wants to
1076 * disable wake events, it's a NOP. Otherwise fail unless the
1077 * platform hooks handled this legacy device already.
1080 return enable ? status : 0;
1082 /* Check device's ability to generate PME# */
1083 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
1085 value &= PCI_PM_CAP_PME_MASK;
1086 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
1088 /* Check if it can generate PME# from requested state. */
1089 if (!value || !(value & (1 << state))) {
1090 /* if it can't, revert what the platform hook changed,
1091 * always reporting the base "EINVAL, can't PME#" error
1094 call_platform_enable_wakeup(&dev->dev, 0);
1095 return enable ? -EINVAL : 0;
1098 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
1100 /* Clear PME_Status by writing 1 to it and enable PME# */
1101 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1104 value &= ~PCI_PM_CTRL_PME_ENABLE;
1106 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
1112 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1120 while (dev->bus->self) {
1121 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1122 dev = dev->bus->self;
1129 * pci_release_region - Release a PCI bar
1130 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1131 * @bar: BAR to release
1133 * Releases the PCI I/O and memory resources previously reserved by a
1134 * successful call to pci_request_region. Call this function only
1135 * after all use of the PCI regions has ceased.
1137 void pci_release_region(struct pci_dev *pdev, int bar)
1139 struct pci_devres *dr;
1141 if (pci_resource_len(pdev, bar) == 0)
1143 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1144 release_region(pci_resource_start(pdev, bar),
1145 pci_resource_len(pdev, bar));
1146 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1147 release_mem_region(pci_resource_start(pdev, bar),
1148 pci_resource_len(pdev, bar));
1150 dr = find_pci_dr(pdev);
1152 dr->region_mask &= ~(1 << bar);
1156 * pci_request_region - Reserved PCI I/O and memory resource
1157 * @pdev: PCI device whose resources are to be reserved
1158 * @bar: BAR to be reserved
1159 * @res_name: Name to be associated with resource.
1161 * Mark the PCI region associated with PCI device @pdev BR @bar as
1162 * being reserved by owner @res_name. Do not access any
1163 * address inside the PCI regions unless this call returns
1166 * Returns 0 on success, or %EBUSY on error. A warning
1167 * message is also printed on failure.
1169 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1171 struct pci_devres *dr;
1173 if (pci_resource_len(pdev, bar) == 0)
1176 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1177 if (!request_region(pci_resource_start(pdev, bar),
1178 pci_resource_len(pdev, bar), res_name))
1181 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1182 if (!request_mem_region(pci_resource_start(pdev, bar),
1183 pci_resource_len(pdev, bar), res_name))
1187 dr = find_pci_dr(pdev);
1189 dr->region_mask |= 1 << bar;
1194 dev_warn(&pdev->dev, "BAR %d: can't reserve %s region [%#llx-%#llx]\n",
1196 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1197 (unsigned long long)pci_resource_start(pdev, bar),
1198 (unsigned long long)pci_resource_end(pdev, bar));
1203 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1204 * @pdev: PCI device whose resources were previously reserved
1205 * @bars: Bitmask of BARs to be released
1207 * Release selected PCI I/O and memory resources previously reserved.
1208 * Call this function only after all use of the PCI regions has ceased.
1210 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1214 for (i = 0; i < 6; i++)
1215 if (bars & (1 << i))
1216 pci_release_region(pdev, i);
1220 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1221 * @pdev: PCI device whose resources are to be reserved
1222 * @bars: Bitmask of BARs to be requested
1223 * @res_name: Name to be associated with resource
1225 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1226 const char *res_name)
1230 for (i = 0; i < 6; i++)
1231 if (bars & (1 << i))
1232 if(pci_request_region(pdev, i, res_name))
1238 if (bars & (1 << i))
1239 pci_release_region(pdev, i);
1245 * pci_release_regions - Release reserved PCI I/O and memory resources
1246 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1248 * Releases all PCI I/O and memory resources previously reserved by a
1249 * successful call to pci_request_regions. Call this function only
1250 * after all use of the PCI regions has ceased.
1253 void pci_release_regions(struct pci_dev *pdev)
1255 pci_release_selected_regions(pdev, (1 << 6) - 1);
1259 * pci_request_regions - Reserved PCI I/O and memory resources
1260 * @pdev: PCI device whose resources are to be reserved
1261 * @res_name: Name to be associated with resource.
1263 * Mark all PCI regions associated with PCI device @pdev as
1264 * being reserved by owner @res_name. Do not access any
1265 * address inside the PCI regions unless this call returns
1268 * Returns 0 on success, or %EBUSY on error. A warning
1269 * message is also printed on failure.
1271 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1273 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1277 * pci_set_master - enables bus-mastering for device dev
1278 * @dev: the PCI device to enable
1280 * Enables bus-mastering on the device and calls pcibios_set_master()
1281 * to do the needed arch specific settings.
1284 pci_set_master(struct pci_dev *dev)
1288 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1289 if (! (cmd & PCI_COMMAND_MASTER)) {
1290 dev_dbg(&dev->dev, "enabling bus mastering\n");
1291 cmd |= PCI_COMMAND_MASTER;
1292 pci_write_config_word(dev, PCI_COMMAND, cmd);
1294 dev->is_busmaster = 1;
1295 pcibios_set_master(dev);
1298 #ifdef PCI_DISABLE_MWI
1299 int pci_set_mwi(struct pci_dev *dev)
1304 int pci_try_set_mwi(struct pci_dev *dev)
1309 void pci_clear_mwi(struct pci_dev *dev)
1315 #ifndef PCI_CACHE_LINE_BYTES
1316 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1319 /* This can be overridden by arch code. */
1320 /* Don't forget this is measured in 32-bit words, not bytes */
1321 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1324 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1325 * @dev: the PCI device for which MWI is to be enabled
1327 * Helper function for pci_set_mwi.
1328 * Originally copied from drivers/net/acenic.c.
1329 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1331 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1334 pci_set_cacheline_size(struct pci_dev *dev)
1338 if (!pci_cache_line_size)
1339 return -EINVAL; /* The system doesn't support MWI. */
1341 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1342 equal to or multiple of the right value. */
1343 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1344 if (cacheline_size >= pci_cache_line_size &&
1345 (cacheline_size % pci_cache_line_size) == 0)
1348 /* Write the correct value. */
1349 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1351 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1352 if (cacheline_size == pci_cache_line_size)
1355 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1356 "supported\n", pci_cache_line_size << 2);
1362 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1363 * @dev: the PCI device for which MWI is enabled
1365 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1367 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1370 pci_set_mwi(struct pci_dev *dev)
1375 rc = pci_set_cacheline_size(dev);
1379 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1380 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1381 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1382 cmd |= PCI_COMMAND_INVALIDATE;
1383 pci_write_config_word(dev, PCI_COMMAND, cmd);
1390 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1391 * @dev: the PCI device for which MWI is enabled
1393 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1394 * Callers are not required to check the return value.
1396 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1398 int pci_try_set_mwi(struct pci_dev *dev)
1400 int rc = pci_set_mwi(dev);
1405 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1406 * @dev: the PCI device to disable
1408 * Disables PCI Memory-Write-Invalidate transaction on the device
1411 pci_clear_mwi(struct pci_dev *dev)
1415 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1416 if (cmd & PCI_COMMAND_INVALIDATE) {
1417 cmd &= ~PCI_COMMAND_INVALIDATE;
1418 pci_write_config_word(dev, PCI_COMMAND, cmd);
1421 #endif /* ! PCI_DISABLE_MWI */
1424 * pci_intx - enables/disables PCI INTx for device dev
1425 * @pdev: the PCI device to operate on
1426 * @enable: boolean: whether to enable or disable PCI INTx
1428 * Enables/disables PCI INTx for device dev
1431 pci_intx(struct pci_dev *pdev, int enable)
1433 u16 pci_command, new;
1435 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1438 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1440 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1443 if (new != pci_command) {
1444 struct pci_devres *dr;
1446 pci_write_config_word(pdev, PCI_COMMAND, new);
1448 dr = find_pci_dr(pdev);
1449 if (dr && !dr->restore_intx) {
1450 dr->restore_intx = 1;
1451 dr->orig_intx = !enable;
1457 * pci_msi_off - disables any msi or msix capabilities
1458 * @dev: the PCI device to operate on
1460 * If you want to use msi see pci_enable_msi and friends.
1461 * This is a lower level primitive that allows us to disable
1462 * msi operation at the device level.
1464 void pci_msi_off(struct pci_dev *dev)
1469 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1471 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1472 control &= ~PCI_MSI_FLAGS_ENABLE;
1473 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1475 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1477 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1478 control &= ~PCI_MSIX_FLAGS_ENABLE;
1479 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1483 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1485 * These can be overridden by arch-specific implementations
1488 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1490 if (!pci_dma_supported(dev, mask))
1493 dev->dma_mask = mask;
1499 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1501 if (!pci_dma_supported(dev, mask))
1504 dev->dev.coherent_dma_mask = mask;
1510 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1511 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
1513 return dma_set_max_seg_size(&dev->dev, size);
1515 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
1518 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1519 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
1521 return dma_set_seg_boundary(&dev->dev, mask);
1523 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
1527 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1528 * @dev: PCI device to query
1530 * Returns mmrbc: maximum designed memory read count in bytes
1531 * or appropriate error value.
1533 int pcix_get_max_mmrbc(struct pci_dev *dev)
1538 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1542 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1546 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
1548 EXPORT_SYMBOL(pcix_get_max_mmrbc);
1551 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1552 * @dev: PCI device to query
1554 * Returns mmrbc: maximum memory read count in bytes
1555 * or appropriate error value.
1557 int pcix_get_mmrbc(struct pci_dev *dev)
1562 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1566 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1568 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
1572 EXPORT_SYMBOL(pcix_get_mmrbc);
1575 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1576 * @dev: PCI device to query
1577 * @mmrbc: maximum memory read count in bytes
1578 * valid values are 512, 1024, 2048, 4096
1580 * If possible sets maximum memory read byte count, some bridges have erratas
1581 * that prevent this.
1583 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
1585 int cap, err = -EINVAL;
1586 u32 stat, cmd, v, o;
1588 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
1591 v = ffs(mmrbc) - 10;
1593 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1597 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1601 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
1604 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1608 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
1610 if (v > o && dev->bus &&
1611 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
1614 cmd &= ~PCI_X_CMD_MAX_READ;
1616 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
1621 EXPORT_SYMBOL(pcix_set_mmrbc);
1624 * pcie_get_readrq - get PCI Express read request size
1625 * @dev: PCI device to query
1627 * Returns maximum memory read request in bytes
1628 * or appropriate error value.
1630 int pcie_get_readrq(struct pci_dev *dev)
1635 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1639 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1641 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
1645 EXPORT_SYMBOL(pcie_get_readrq);
1648 * pcie_set_readrq - set PCI Express maximum memory read request
1649 * @dev: PCI device to query
1650 * @rq: maximum memory read count in bytes
1651 * valid values are 128, 256, 512, 1024, 2048, 4096
1653 * If possible sets maximum read byte count
1655 int pcie_set_readrq(struct pci_dev *dev, int rq)
1657 int cap, err = -EINVAL;
1660 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
1663 v = (ffs(rq) - 8) << 12;
1665 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1669 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1673 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
1674 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1676 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
1682 EXPORT_SYMBOL(pcie_set_readrq);
1685 * pci_select_bars - Make BAR mask from the type of resource
1686 * @dev: the PCI device for which BAR mask is made
1687 * @flags: resource type mask to be selected
1689 * This helper routine makes bar mask from the type of resource.
1691 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1694 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1695 if (pci_resource_flags(dev, i) & flags)
1700 static void __devinit pci_no_domains(void)
1702 #ifdef CONFIG_PCI_DOMAINS
1703 pci_domains_supported = 0;
1707 static int __devinit pci_init(void)
1709 struct pci_dev *dev = NULL;
1711 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1712 pci_fixup_device(pci_fixup_final, dev);
1717 static int __devinit pci_setup(char *str)
1720 char *k = strchr(str, ',');
1723 if (*str && (str = pcibios_setup(str)) && *str) {
1724 if (!strcmp(str, "nomsi")) {
1726 } else if (!strcmp(str, "noaer")) {
1728 } else if (!strcmp(str, "nodomains")) {
1730 } else if (!strncmp(str, "cbiosize=", 9)) {
1731 pci_cardbus_io_size = memparse(str + 9, &str);
1732 } else if (!strncmp(str, "cbmemsize=", 10)) {
1733 pci_cardbus_mem_size = memparse(str + 10, &str);
1735 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1743 early_param("pci", pci_setup);
1745 device_initcall(pci_init);
1747 EXPORT_SYMBOL(pci_reenable_device);
1748 EXPORT_SYMBOL(pci_enable_device_io);
1749 EXPORT_SYMBOL(pci_enable_device_mem);
1750 EXPORT_SYMBOL(pci_enable_device);
1751 EXPORT_SYMBOL(pcim_enable_device);
1752 EXPORT_SYMBOL(pcim_pin_device);
1753 EXPORT_SYMBOL(pci_disable_device);
1754 EXPORT_SYMBOL(pci_find_capability);
1755 EXPORT_SYMBOL(pci_bus_find_capability);
1756 EXPORT_SYMBOL(pci_release_regions);
1757 EXPORT_SYMBOL(pci_request_regions);
1758 EXPORT_SYMBOL(pci_release_region);
1759 EXPORT_SYMBOL(pci_request_region);
1760 EXPORT_SYMBOL(pci_release_selected_regions);
1761 EXPORT_SYMBOL(pci_request_selected_regions);
1762 EXPORT_SYMBOL(pci_set_master);
1763 EXPORT_SYMBOL(pci_set_mwi);
1764 EXPORT_SYMBOL(pci_try_set_mwi);
1765 EXPORT_SYMBOL(pci_clear_mwi);
1766 EXPORT_SYMBOL_GPL(pci_intx);
1767 EXPORT_SYMBOL(pci_set_dma_mask);
1768 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1769 EXPORT_SYMBOL(pci_assign_resource);
1770 EXPORT_SYMBOL(pci_find_parent_resource);
1771 EXPORT_SYMBOL(pci_select_bars);
1773 EXPORT_SYMBOL(pci_set_power_state);
1774 EXPORT_SYMBOL(pci_save_state);
1775 EXPORT_SYMBOL(pci_restore_state);
1776 EXPORT_SYMBOL(pci_enable_wake);
1777 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);