2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 unsigned int pci_pm_d3_delay = 10;
25 #ifdef CONFIG_PCI_DOMAINS
26 int pci_domains_supported = 1;
29 #define DEFAULT_CARDBUS_IO_SIZE (256)
30 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
31 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
32 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
33 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
36 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
37 * @bus: pointer to PCI bus structure to search
39 * Given a PCI bus, returns the highest PCI bus number present in the set
40 * including the given PCI bus and its list of child PCI buses.
42 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
44 struct list_head *tmp;
47 max = bus->subordinate;
48 list_for_each(tmp, &bus->children) {
49 n = pci_bus_max_busnr(pci_bus_b(tmp));
55 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
59 * pci_max_busnr - returns maximum PCI bus number
61 * Returns the highest PCI bus number present in the system global list of
64 unsigned char __devinit
67 struct pci_bus *bus = NULL;
71 while ((bus = pci_find_next_bus(bus)) != NULL) {
72 n = pci_bus_max_busnr(bus);
81 #define PCI_FIND_CAP_TTL 48
83 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
84 u8 pos, int cap, int *ttl)
89 pci_bus_read_config_byte(bus, devfn, pos, &pos);
93 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
99 pos += PCI_CAP_LIST_NEXT;
104 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
107 int ttl = PCI_FIND_CAP_TTL;
109 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
112 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
114 return __pci_find_next_cap(dev->bus, dev->devfn,
115 pos + PCI_CAP_LIST_NEXT, cap);
117 EXPORT_SYMBOL_GPL(pci_find_next_capability);
119 static int __pci_bus_find_cap_start(struct pci_bus *bus,
120 unsigned int devfn, u8 hdr_type)
124 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
125 if (!(status & PCI_STATUS_CAP_LIST))
129 case PCI_HEADER_TYPE_NORMAL:
130 case PCI_HEADER_TYPE_BRIDGE:
131 return PCI_CAPABILITY_LIST;
132 case PCI_HEADER_TYPE_CARDBUS:
133 return PCI_CB_CAPABILITY_LIST;
142 * pci_find_capability - query for devices' capabilities
143 * @dev: PCI device to query
144 * @cap: capability code
146 * Tell if a device supports a given PCI capability.
147 * Returns the address of the requested capability structure within the
148 * device's PCI configuration space or 0 in case the device does not
149 * support it. Possible values for @cap:
151 * %PCI_CAP_ID_PM Power Management
152 * %PCI_CAP_ID_AGP Accelerated Graphics Port
153 * %PCI_CAP_ID_VPD Vital Product Data
154 * %PCI_CAP_ID_SLOTID Slot Identification
155 * %PCI_CAP_ID_MSI Message Signalled Interrupts
156 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
157 * %PCI_CAP_ID_PCIX PCI-X
158 * %PCI_CAP_ID_EXP PCI Express
160 int pci_find_capability(struct pci_dev *dev, int cap)
164 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
166 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
172 * pci_bus_find_capability - query for devices' capabilities
173 * @bus: the PCI bus to query
174 * @devfn: PCI device to query
175 * @cap: capability code
177 * Like pci_find_capability() but works for pci devices that do not have a
178 * pci_dev structure set up yet.
180 * Returns the address of the requested capability structure within the
181 * device's PCI configuration space or 0 in case the device does not
184 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
189 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
191 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
193 pos = __pci_find_next_cap(bus, devfn, pos, cap);
199 * pci_find_ext_capability - Find an extended capability
200 * @dev: PCI device to query
201 * @cap: capability code
203 * Returns the address of the requested extended capability structure
204 * within the device's PCI configuration space or 0 if the device does
205 * not support it. Possible values for @cap:
207 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
208 * %PCI_EXT_CAP_ID_VC Virtual Channel
209 * %PCI_EXT_CAP_ID_DSN Device Serial Number
210 * %PCI_EXT_CAP_ID_PWR Power Budgeting
212 int pci_find_ext_capability(struct pci_dev *dev, int cap)
215 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
218 if (dev->cfg_size <= 256)
221 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
225 * If we have no capabilities, this is indicated by cap ID,
226 * cap version and next pointer all being 0.
232 if (PCI_EXT_CAP_ID(header) == cap)
235 pos = PCI_EXT_CAP_NEXT(header);
239 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
245 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
247 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
249 int rc, ttl = PCI_FIND_CAP_TTL;
252 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
253 mask = HT_3BIT_CAP_MASK;
255 mask = HT_5BIT_CAP_MASK;
257 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
258 PCI_CAP_ID_HT, &ttl);
260 rc = pci_read_config_byte(dev, pos + 3, &cap);
261 if (rc != PCIBIOS_SUCCESSFUL)
264 if ((cap & mask) == ht_cap)
267 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
268 pos + PCI_CAP_LIST_NEXT,
269 PCI_CAP_ID_HT, &ttl);
275 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
276 * @dev: PCI device to query
277 * @pos: Position from which to continue searching
278 * @ht_cap: Hypertransport capability code
280 * To be used in conjunction with pci_find_ht_capability() to search for
281 * all capabilities matching @ht_cap. @pos should always be a value returned
282 * from pci_find_ht_capability().
284 * NB. To be 100% safe against broken PCI devices, the caller should take
285 * steps to avoid an infinite loop.
287 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
289 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
291 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
294 * pci_find_ht_capability - query a device's Hypertransport capabilities
295 * @dev: PCI device to query
296 * @ht_cap: Hypertransport capability code
298 * Tell if a device supports a given Hypertransport capability.
299 * Returns an address within the device's PCI configuration space
300 * or 0 in case the device does not support the request capability.
301 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
302 * which has a Hypertransport capability matching @ht_cap.
304 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
308 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
310 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
314 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
317 * pci_find_parent_resource - return resource region of parent bus of given region
318 * @dev: PCI device structure contains resources to be searched
319 * @res: child resource record for which parent is sought
321 * For given resource region of given device, return the resource
322 * region of parent bus the given region is contained in or where
323 * it should be allocated from.
326 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
328 const struct pci_bus *bus = dev->bus;
330 struct resource *best = NULL;
332 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
333 struct resource *r = bus->resource[i];
336 if (res->start && !(res->start >= r->start && res->end <= r->end))
337 continue; /* Not contained */
338 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
339 continue; /* Wrong type */
340 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
341 return r; /* Exact match */
342 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
343 best = r; /* Approximating prefetchable by non-prefetchable */
349 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
350 * @dev: PCI device to have its BARs restored
352 * Restore the BAR values for a given device, so as to make it
353 * accessible by its driver.
356 pci_restore_bars(struct pci_dev *dev)
360 switch (dev->hdr_type) {
361 case PCI_HEADER_TYPE_NORMAL:
364 case PCI_HEADER_TYPE_BRIDGE:
367 case PCI_HEADER_TYPE_CARDBUS:
371 /* Should never get here, but just in case... */
375 for (i = 0; i < numres; i ++)
376 pci_update_resource(dev, &dev->resource[i], i);
379 static struct pci_platform_pm_ops *pci_platform_pm;
381 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
383 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
384 || !ops->sleep_wake || !ops->can_wakeup)
386 pci_platform_pm = ops;
390 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
392 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
395 static inline int platform_pci_set_power_state(struct pci_dev *dev,
398 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
401 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
403 return pci_platform_pm ?
404 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
407 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
409 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
412 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
414 return pci_platform_pm ?
415 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
419 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
421 * @dev: PCI device to handle.
422 * @pm: PCI PM capability offset of the device.
423 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
426 * -EINVAL if the requested state is invalid.
427 * -EIO if device does not support PCI PM or its PM capabilities register has a
428 * wrong version, or device doesn't support the requested state.
429 * 0 if device already is in the requested state.
430 * 0 if device's power state has been successfully changed.
433 pci_raw_set_power_state(struct pci_dev *dev, int pm, pci_power_t state)
436 bool need_restore = false;
441 if (state < PCI_D0 || state > PCI_D3hot)
444 /* Validate current state:
445 * Can enter D0 from any state, but if we can only go deeper
446 * to sleep if we're already in a low power state
448 if (dev->current_state == state) {
449 /* we're already there */
451 } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold
452 && dev->current_state > state) {
453 dev_err(&dev->dev, "invalid power transition "
454 "(from state %d to %d)\n", dev->current_state, state);
458 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
460 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
461 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
462 pmc & PCI_PM_CAP_VER_MASK);
466 /* check if this device supports the desired state */
467 if ((state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
468 || (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)))
471 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
473 /* If we're (effectively) in D3, force entire word to 0.
474 * This doesn't affect PME_Status, disables PME_En, and
475 * sets PowerState to 0.
477 switch (dev->current_state) {
481 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
484 case PCI_UNKNOWN: /* Boot-up */
485 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
486 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
488 /* Fall-through: force to D0 */
494 /* enter specified state */
495 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
497 /* Mandatory power management transition delays */
498 /* see PCI PM 1.1 5.6.1 table 18 */
499 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
500 msleep(pci_pm_d3_delay);
501 else if (state == PCI_D2 || dev->current_state == PCI_D2)
504 dev->current_state = state;
506 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
507 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
508 * from D3hot to D0 _may_ perform an internal reset, thereby
509 * going to "D0 Uninitialized" rather than "D0 Initialized".
510 * For example, at least some versions of the 3c905B and the
511 * 3c556B exhibit this behaviour.
513 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
514 * devices in a D3hot state at boot. Consequently, we need to
515 * restore at least the BARs so that the device will be
516 * accessible to its driver.
519 pci_restore_bars(dev);
522 pcie_aspm_pm_state_change(dev->bus->self);
528 * pci_update_current_state - Read PCI power state of given device from its
529 * PCI PM registers and cache it
530 * @dev: PCI device to handle.
531 * @pm: PCI PM capability offset of the device.
533 static void pci_update_current_state(struct pci_dev *dev, int pm)
538 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
539 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
544 * pci_set_power_state - Set the power state of a PCI device
545 * @dev: PCI device to handle.
546 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
548 * Transition a device to a new power state, using the platform formware and/or
549 * the device's PCI PM registers.
552 * -EINVAL if the requested state is invalid.
553 * -EIO if device does not support PCI PM or its PM capabilities register has a
554 * wrong version, or device doesn't support the requested state.
555 * 0 if device already is in the requested state.
556 * 0 if device's power state has been successfully changed.
558 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
562 /* bound the state we're entering */
563 if (state > PCI_D3hot)
565 else if (state < PCI_D0)
567 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
569 * If the device or the parent bridge do not support PCI PM,
570 * ignore the request if we're doing anything other than putting
571 * it into D0 (which would only happen on boot).
575 /* Find PCI PM capability in the list */
576 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
578 if (state == PCI_D0 && platform_pci_power_manageable(dev)) {
580 * Allow the platform to change the state, for example via ACPI
581 * _PR0, _PS0 and some such, but do not trust it.
583 int ret = platform_pci_set_power_state(dev, PCI_D0);
585 pci_update_current_state(dev, pm);
588 error = pci_raw_set_power_state(dev, pm, state);
590 if (state > PCI_D0 && platform_pci_power_manageable(dev)) {
591 /* Allow the platform to finalize the transition */
592 int ret = platform_pci_set_power_state(dev, state);
594 pci_update_current_state(dev, pm);
603 * pci_choose_state - Choose the power state of a PCI device
604 * @dev: PCI device to be suspended
605 * @state: target sleep state for the whole system. This is the value
606 * that is passed to suspend() function.
608 * Returns PCI power state suitable for given device and given system
612 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
616 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
619 ret = platform_pci_choose_state(dev);
620 if (ret != PCI_POWER_ERROR)
623 switch (state.event) {
626 case PM_EVENT_FREEZE:
627 case PM_EVENT_PRETHAW:
628 /* REVISIT both freeze and pre-thaw "should" use D0 */
629 case PM_EVENT_SUSPEND:
630 case PM_EVENT_HIBERNATE:
633 dev_info(&dev->dev, "unrecognized suspend event %d\n",
640 EXPORT_SYMBOL(pci_choose_state);
642 static int pci_save_pcie_state(struct pci_dev *dev)
645 struct pci_cap_saved_state *save_state;
649 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
653 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
655 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
659 dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
662 cap = (u16 *)&save_state->data[0];
664 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
665 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
666 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
667 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
668 save_state->cap_nr = PCI_CAP_ID_EXP;
670 pci_add_saved_cap(dev, save_state);
674 static void pci_restore_pcie_state(struct pci_dev *dev)
677 struct pci_cap_saved_state *save_state;
680 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
681 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
682 if (!save_state || pos <= 0)
684 cap = (u16 *)&save_state->data[0];
686 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
687 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
688 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
689 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
693 static int pci_save_pcix_state(struct pci_dev *dev)
696 struct pci_cap_saved_state *save_state;
700 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
704 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
706 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
710 dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n");
713 cap = (u16 *)&save_state->data[0];
715 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
716 save_state->cap_nr = PCI_CAP_ID_PCIX;
718 pci_add_saved_cap(dev, save_state);
722 static void pci_restore_pcix_state(struct pci_dev *dev)
725 struct pci_cap_saved_state *save_state;
728 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
729 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
730 if (!save_state || pos <= 0)
732 cap = (u16 *)&save_state->data[0];
734 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
739 * pci_save_state - save the PCI configuration space of a device before suspending
740 * @dev: - PCI device that we're dealing with
743 pci_save_state(struct pci_dev *dev)
746 /* XXX: 100% dword access ok here? */
747 for (i = 0; i < 16; i++)
748 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
749 if ((i = pci_save_pcie_state(dev)) != 0)
751 if ((i = pci_save_pcix_state(dev)) != 0)
757 * pci_restore_state - Restore the saved state of a PCI device
758 * @dev: - PCI device that we're dealing with
761 pci_restore_state(struct pci_dev *dev)
766 /* PCI Express register must be restored first */
767 pci_restore_pcie_state(dev);
770 * The Base Address register should be programmed before the command
773 for (i = 15; i >= 0; i--) {
774 pci_read_config_dword(dev, i * 4, &val);
775 if (val != dev->saved_config_space[i]) {
776 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
777 "space at offset %#x (was %#x, writing %#x)\n",
778 i, val, (int)dev->saved_config_space[i]);
779 pci_write_config_dword(dev,i * 4,
780 dev->saved_config_space[i]);
783 pci_restore_pcix_state(dev);
784 pci_restore_msi_state(dev);
789 static int do_pci_enable_device(struct pci_dev *dev, int bars)
793 err = pci_set_power_state(dev, PCI_D0);
794 if (err < 0 && err != -EIO)
796 err = pcibios_enable_device(dev, bars);
799 pci_fixup_device(pci_fixup_enable, dev);
805 * pci_reenable_device - Resume abandoned device
806 * @dev: PCI device to be resumed
808 * Note this function is a backend of pci_default_resume and is not supposed
809 * to be called by normal code, write proper resume handler and use it instead.
811 int pci_reenable_device(struct pci_dev *dev)
813 if (atomic_read(&dev->enable_cnt))
814 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
818 static int __pci_enable_device_flags(struct pci_dev *dev,
819 resource_size_t flags)
824 if (atomic_add_return(1, &dev->enable_cnt) > 1)
825 return 0; /* already enabled */
827 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
828 if (dev->resource[i].flags & flags)
831 err = do_pci_enable_device(dev, bars);
833 atomic_dec(&dev->enable_cnt);
838 * pci_enable_device_io - Initialize a device for use with IO space
839 * @dev: PCI device to be initialized
841 * Initialize device before it's used by a driver. Ask low-level code
842 * to enable I/O resources. Wake up the device if it was suspended.
843 * Beware, this function can fail.
845 int pci_enable_device_io(struct pci_dev *dev)
847 return __pci_enable_device_flags(dev, IORESOURCE_IO);
851 * pci_enable_device_mem - Initialize a device for use with Memory space
852 * @dev: PCI device to be initialized
854 * Initialize device before it's used by a driver. Ask low-level code
855 * to enable Memory resources. Wake up the device if it was suspended.
856 * Beware, this function can fail.
858 int pci_enable_device_mem(struct pci_dev *dev)
860 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
864 * pci_enable_device - Initialize device before it's used by a driver.
865 * @dev: PCI device to be initialized
867 * Initialize device before it's used by a driver. Ask low-level code
868 * to enable I/O and memory. Wake up the device if it was suspended.
869 * Beware, this function can fail.
871 * Note we don't actually enable the device many times if we call
872 * this function repeatedly (we just increment the count).
874 int pci_enable_device(struct pci_dev *dev)
876 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
880 * Managed PCI resources. This manages device on/off, intx/msi/msix
881 * on/off and BAR regions. pci_dev itself records msi/msix status, so
882 * there's no need to track it separately. pci_devres is initialized
883 * when a device is enabled using managed PCI device enable interface.
886 unsigned int enabled:1;
887 unsigned int pinned:1;
888 unsigned int orig_intx:1;
889 unsigned int restore_intx:1;
893 static void pcim_release(struct device *gendev, void *res)
895 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
896 struct pci_devres *this = res;
899 if (dev->msi_enabled)
900 pci_disable_msi(dev);
901 if (dev->msix_enabled)
902 pci_disable_msix(dev);
904 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
905 if (this->region_mask & (1 << i))
906 pci_release_region(dev, i);
908 if (this->restore_intx)
909 pci_intx(dev, this->orig_intx);
911 if (this->enabled && !this->pinned)
912 pci_disable_device(dev);
915 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
917 struct pci_devres *dr, *new_dr;
919 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
923 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
926 return devres_get(&pdev->dev, new_dr, NULL, NULL);
929 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
931 if (pci_is_managed(pdev))
932 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
937 * pcim_enable_device - Managed pci_enable_device()
938 * @pdev: PCI device to be initialized
940 * Managed pci_enable_device().
942 int pcim_enable_device(struct pci_dev *pdev)
944 struct pci_devres *dr;
947 dr = get_pci_dr(pdev);
953 rc = pci_enable_device(pdev);
955 pdev->is_managed = 1;
962 * pcim_pin_device - Pin managed PCI device
963 * @pdev: PCI device to pin
965 * Pin managed PCI device @pdev. Pinned device won't be disabled on
966 * driver detach. @pdev must have been enabled with
967 * pcim_enable_device().
969 void pcim_pin_device(struct pci_dev *pdev)
971 struct pci_devres *dr;
973 dr = find_pci_dr(pdev);
974 WARN_ON(!dr || !dr->enabled);
980 * pcibios_disable_device - disable arch specific PCI resources for device dev
981 * @dev: the PCI device to disable
983 * Disables architecture specific PCI resources for the device. This
984 * is the default implementation. Architecture implementations can
987 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
990 * pci_disable_device - Disable PCI device after use
991 * @dev: PCI device to be disabled
993 * Signal to the system that the PCI device is not in use by the system
994 * anymore. This only involves disabling PCI bus-mastering, if active.
996 * Note we don't actually disable the device until all callers of
997 * pci_device_enable() have called pci_device_disable().
1000 pci_disable_device(struct pci_dev *dev)
1002 struct pci_devres *dr;
1005 dr = find_pci_dr(dev);
1009 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1012 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1013 if (pci_command & PCI_COMMAND_MASTER) {
1014 pci_command &= ~PCI_COMMAND_MASTER;
1015 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1017 dev->is_busmaster = 0;
1019 pcibios_disable_device(dev);
1023 * pcibios_set_pcie_reset_state - set reset state for device dev
1024 * @dev: the PCI-E device reset
1025 * @state: Reset state to enter into
1028 * Sets the PCI-E reset state for the device. This is the default
1029 * implementation. Architecture implementations can override this.
1031 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1032 enum pcie_reset_state state)
1038 * pci_set_pcie_reset_state - set reset state for device dev
1039 * @dev: the PCI-E device reset
1040 * @state: Reset state to enter into
1043 * Sets the PCI reset state for the device.
1045 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1047 return pcibios_set_pcie_reset_state(dev, state);
1051 * pci_pme_capable - check the capability of PCI device to generate PME#
1052 * @dev: PCI device to handle.
1053 * @pm: PCI PM capability offset of the device.
1054 * @state: PCI state from which device will issue PME#.
1056 static bool pci_pme_capable(struct pci_dev *dev, int pm, pci_power_t state)
1063 /* Check device's ability to generate PME# from given state */
1064 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1066 pmc &= PCI_PM_CAP_PME_MASK;
1067 pmc >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
1069 return !!(pmc & (1 << state));
1073 * pci_pme_active - enable or disable PCI device's PME# function
1074 * @dev: PCI device to handle.
1075 * @pm: PCI PM capability offset of the device.
1076 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1078 * The caller must verify that the device is capable of generating PME# before
1079 * calling this function with @enable equal to 'true'.
1081 static void pci_pme_active(struct pci_dev *dev, int pm, bool enable)
1088 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1089 /* Clear PME_Status by writing 1 to it and enable PME# */
1090 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1092 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1094 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
1096 dev_printk(KERN_INFO, &dev->dev, "PME# %s\n",
1097 enable ? "enabled" : "disabled");
1101 * pci_enable_wake - enable PCI device as wakeup event source
1102 * @dev: PCI device affected
1103 * @state: PCI state from which device will issue wakeup events
1104 * @enable: True to enable event generation; false to disable
1106 * This enables the device as a wakeup event source, or disables it.
1107 * When such events involves platform-specific hooks, those hooks are
1108 * called automatically by this routine.
1110 * Devices with legacy power management (no standard PCI PM capabilities)
1111 * always require such platform hooks.
1114 * 0 is returned on success
1115 * -EINVAL is returned if device is not supposed to wake up the system
1116 * Error code depending on the platform is returned if both the platform and
1117 * the native mechanism fail to enable the generation of wake-up events
1119 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
1123 bool pme_done = false;
1125 if (!device_may_wakeup(&dev->dev))
1129 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1130 * Anderson we should be doing PME# wake enable followed by ACPI wake
1131 * enable. To disable wake-up we call the platform first, for symmetry.
1134 if (!enable && platform_pci_can_wakeup(dev))
1135 error = platform_pci_sleep_wake(dev, false);
1137 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1138 if (!enable || pci_pme_capable(dev, pm, state)) {
1139 pci_pme_active(dev, pm, enable);
1143 if (enable && platform_pci_can_wakeup(dev))
1144 error = platform_pci_sleep_wake(dev, true);
1146 return pme_done ? 0 : error;
1150 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into
1152 * @dev: Device to handle.
1154 * Choose the power state appropriate for the device depending on whether
1155 * it can wake up the system and/or is power manageable by the platform
1156 * (PCI_D3hot is the default) and put the device into that state.
1158 int pci_prepare_to_sleep(struct pci_dev *dev)
1160 pci_power_t target_state = PCI_D3hot;
1161 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1164 if (platform_pci_power_manageable(dev)) {
1166 * Call the platform to choose the target state of the device
1167 * and enable wake-up from this state if supported.
1169 pci_power_t state = platform_pci_choose_state(dev);
1172 case PCI_POWER_ERROR:
1177 if (pci_no_d1d2(dev))
1180 target_state = state;
1181 pci_enable_wake(dev, target_state, true);
1183 } else if (device_may_wakeup(&dev->dev)) {
1185 * Find the deepest state from which the device can generate
1186 * wake-up events, make it the target state and enable device
1194 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1195 if (pmc & PCI_PM_CAP_PME_MASK) {
1196 if (!(pmc & PCI_PM_CAP_PME_D3)) {
1197 /* Device cannot generate PME# from D3_hot */
1198 if (pmc & PCI_PM_CAP_PME_D2)
1199 target_state = PCI_D2;
1200 else if (pmc & PCI_PM_CAP_PME_D1)
1201 target_state = PCI_D1;
1203 target_state = PCI_D0;
1205 pci_pme_active(dev, pm, true);
1209 error = pci_set_power_state(dev, target_state);
1212 pci_enable_wake(dev, target_state, false);
1218 * pci_back_from_sleep - turn PCI device on during system-wide transition into
1219 * the working state a sleep state
1220 * @dev: Device to handle.
1222 * Disable device's sytem wake-up capability and put it into D0.
1224 int pci_back_from_sleep(struct pci_dev *dev)
1226 pci_enable_wake(dev, PCI_D0, false);
1227 return pci_set_power_state(dev, PCI_D0);
1231 * pci_pm_init - Initialize PM functions of given PCI device
1232 * @dev: PCI device to handle.
1234 void pci_pm_init(struct pci_dev *dev)
1239 /* find PCI PM capability in list */
1240 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1243 /* Check device's ability to generate PME# */
1244 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1246 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1247 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1248 pmc & PCI_PM_CAP_VER_MASK);
1252 if (pmc & PCI_PM_CAP_PME_MASK) {
1253 dev_printk(KERN_INFO, &dev->dev,
1254 "PME# supported from%s%s%s%s%s\n",
1255 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1256 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1257 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1258 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1259 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1261 * Make device's PM flags reflect the wake-up capability, but
1262 * let the user space enable it to wake up the system as needed.
1264 device_set_wakeup_capable(&dev->dev, true);
1265 device_set_wakeup_enable(&dev->dev, false);
1266 /* Disable the PME# generation functionality */
1267 pci_pme_active(dev, pm, false);
1272 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1280 while (dev->bus->self) {
1281 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1282 dev = dev->bus->self;
1289 * pci_release_region - Release a PCI bar
1290 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1291 * @bar: BAR to release
1293 * Releases the PCI I/O and memory resources previously reserved by a
1294 * successful call to pci_request_region. Call this function only
1295 * after all use of the PCI regions has ceased.
1297 void pci_release_region(struct pci_dev *pdev, int bar)
1299 struct pci_devres *dr;
1301 if (pci_resource_len(pdev, bar) == 0)
1303 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1304 release_region(pci_resource_start(pdev, bar),
1305 pci_resource_len(pdev, bar));
1306 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1307 release_mem_region(pci_resource_start(pdev, bar),
1308 pci_resource_len(pdev, bar));
1310 dr = find_pci_dr(pdev);
1312 dr->region_mask &= ~(1 << bar);
1316 * pci_request_region - Reserved PCI I/O and memory resource
1317 * @pdev: PCI device whose resources are to be reserved
1318 * @bar: BAR to be reserved
1319 * @res_name: Name to be associated with resource.
1321 * Mark the PCI region associated with PCI device @pdev BR @bar as
1322 * being reserved by owner @res_name. Do not access any
1323 * address inside the PCI regions unless this call returns
1326 * Returns 0 on success, or %EBUSY on error. A warning
1327 * message is also printed on failure.
1329 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1331 struct pci_devres *dr;
1333 if (pci_resource_len(pdev, bar) == 0)
1336 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1337 if (!request_region(pci_resource_start(pdev, bar),
1338 pci_resource_len(pdev, bar), res_name))
1341 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1342 if (!request_mem_region(pci_resource_start(pdev, bar),
1343 pci_resource_len(pdev, bar), res_name))
1347 dr = find_pci_dr(pdev);
1349 dr->region_mask |= 1 << bar;
1354 dev_warn(&pdev->dev, "BAR %d: can't reserve %s region [%#llx-%#llx]\n",
1356 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1357 (unsigned long long)pci_resource_start(pdev, bar),
1358 (unsigned long long)pci_resource_end(pdev, bar));
1363 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1364 * @pdev: PCI device whose resources were previously reserved
1365 * @bars: Bitmask of BARs to be released
1367 * Release selected PCI I/O and memory resources previously reserved.
1368 * Call this function only after all use of the PCI regions has ceased.
1370 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1374 for (i = 0; i < 6; i++)
1375 if (bars & (1 << i))
1376 pci_release_region(pdev, i);
1380 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1381 * @pdev: PCI device whose resources are to be reserved
1382 * @bars: Bitmask of BARs to be requested
1383 * @res_name: Name to be associated with resource
1385 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1386 const char *res_name)
1390 for (i = 0; i < 6; i++)
1391 if (bars & (1 << i))
1392 if(pci_request_region(pdev, i, res_name))
1398 if (bars & (1 << i))
1399 pci_release_region(pdev, i);
1405 * pci_release_regions - Release reserved PCI I/O and memory resources
1406 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1408 * Releases all PCI I/O and memory resources previously reserved by a
1409 * successful call to pci_request_regions. Call this function only
1410 * after all use of the PCI regions has ceased.
1413 void pci_release_regions(struct pci_dev *pdev)
1415 pci_release_selected_regions(pdev, (1 << 6) - 1);
1419 * pci_request_regions - Reserved PCI I/O and memory resources
1420 * @pdev: PCI device whose resources are to be reserved
1421 * @res_name: Name to be associated with resource.
1423 * Mark all PCI regions associated with PCI device @pdev as
1424 * being reserved by owner @res_name. Do not access any
1425 * address inside the PCI regions unless this call returns
1428 * Returns 0 on success, or %EBUSY on error. A warning
1429 * message is also printed on failure.
1431 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1433 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1437 * pci_set_master - enables bus-mastering for device dev
1438 * @dev: the PCI device to enable
1440 * Enables bus-mastering on the device and calls pcibios_set_master()
1441 * to do the needed arch specific settings.
1444 pci_set_master(struct pci_dev *dev)
1448 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1449 if (! (cmd & PCI_COMMAND_MASTER)) {
1450 dev_dbg(&dev->dev, "enabling bus mastering\n");
1451 cmd |= PCI_COMMAND_MASTER;
1452 pci_write_config_word(dev, PCI_COMMAND, cmd);
1454 dev->is_busmaster = 1;
1455 pcibios_set_master(dev);
1458 #ifdef PCI_DISABLE_MWI
1459 int pci_set_mwi(struct pci_dev *dev)
1464 int pci_try_set_mwi(struct pci_dev *dev)
1469 void pci_clear_mwi(struct pci_dev *dev)
1475 #ifndef PCI_CACHE_LINE_BYTES
1476 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1479 /* This can be overridden by arch code. */
1480 /* Don't forget this is measured in 32-bit words, not bytes */
1481 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1484 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1485 * @dev: the PCI device for which MWI is to be enabled
1487 * Helper function for pci_set_mwi.
1488 * Originally copied from drivers/net/acenic.c.
1489 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1491 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1494 pci_set_cacheline_size(struct pci_dev *dev)
1498 if (!pci_cache_line_size)
1499 return -EINVAL; /* The system doesn't support MWI. */
1501 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1502 equal to or multiple of the right value. */
1503 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1504 if (cacheline_size >= pci_cache_line_size &&
1505 (cacheline_size % pci_cache_line_size) == 0)
1508 /* Write the correct value. */
1509 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1511 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1512 if (cacheline_size == pci_cache_line_size)
1515 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1516 "supported\n", pci_cache_line_size << 2);
1522 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1523 * @dev: the PCI device for which MWI is enabled
1525 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1527 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1530 pci_set_mwi(struct pci_dev *dev)
1535 rc = pci_set_cacheline_size(dev);
1539 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1540 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1541 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1542 cmd |= PCI_COMMAND_INVALIDATE;
1543 pci_write_config_word(dev, PCI_COMMAND, cmd);
1550 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1551 * @dev: the PCI device for which MWI is enabled
1553 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1554 * Callers are not required to check the return value.
1556 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1558 int pci_try_set_mwi(struct pci_dev *dev)
1560 int rc = pci_set_mwi(dev);
1565 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1566 * @dev: the PCI device to disable
1568 * Disables PCI Memory-Write-Invalidate transaction on the device
1571 pci_clear_mwi(struct pci_dev *dev)
1575 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1576 if (cmd & PCI_COMMAND_INVALIDATE) {
1577 cmd &= ~PCI_COMMAND_INVALIDATE;
1578 pci_write_config_word(dev, PCI_COMMAND, cmd);
1581 #endif /* ! PCI_DISABLE_MWI */
1584 * pci_intx - enables/disables PCI INTx for device dev
1585 * @pdev: the PCI device to operate on
1586 * @enable: boolean: whether to enable or disable PCI INTx
1588 * Enables/disables PCI INTx for device dev
1591 pci_intx(struct pci_dev *pdev, int enable)
1593 u16 pci_command, new;
1595 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1598 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1600 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1603 if (new != pci_command) {
1604 struct pci_devres *dr;
1606 pci_write_config_word(pdev, PCI_COMMAND, new);
1608 dr = find_pci_dr(pdev);
1609 if (dr && !dr->restore_intx) {
1610 dr->restore_intx = 1;
1611 dr->orig_intx = !enable;
1617 * pci_msi_off - disables any msi or msix capabilities
1618 * @dev: the PCI device to operate on
1620 * If you want to use msi see pci_enable_msi and friends.
1621 * This is a lower level primitive that allows us to disable
1622 * msi operation at the device level.
1624 void pci_msi_off(struct pci_dev *dev)
1629 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1631 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1632 control &= ~PCI_MSI_FLAGS_ENABLE;
1633 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1635 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1637 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1638 control &= ~PCI_MSIX_FLAGS_ENABLE;
1639 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1643 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1645 * These can be overridden by arch-specific implementations
1648 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1650 if (!pci_dma_supported(dev, mask))
1653 dev->dma_mask = mask;
1659 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1661 if (!pci_dma_supported(dev, mask))
1664 dev->dev.coherent_dma_mask = mask;
1670 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1671 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
1673 return dma_set_max_seg_size(&dev->dev, size);
1675 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
1678 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1679 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
1681 return dma_set_seg_boundary(&dev->dev, mask);
1683 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
1687 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1688 * @dev: PCI device to query
1690 * Returns mmrbc: maximum designed memory read count in bytes
1691 * or appropriate error value.
1693 int pcix_get_max_mmrbc(struct pci_dev *dev)
1698 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1702 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1706 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
1708 EXPORT_SYMBOL(pcix_get_max_mmrbc);
1711 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1712 * @dev: PCI device to query
1714 * Returns mmrbc: maximum memory read count in bytes
1715 * or appropriate error value.
1717 int pcix_get_mmrbc(struct pci_dev *dev)
1722 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1726 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1728 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
1732 EXPORT_SYMBOL(pcix_get_mmrbc);
1735 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1736 * @dev: PCI device to query
1737 * @mmrbc: maximum memory read count in bytes
1738 * valid values are 512, 1024, 2048, 4096
1740 * If possible sets maximum memory read byte count, some bridges have erratas
1741 * that prevent this.
1743 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
1745 int cap, err = -EINVAL;
1746 u32 stat, cmd, v, o;
1748 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
1751 v = ffs(mmrbc) - 10;
1753 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1757 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1761 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
1764 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1768 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
1770 if (v > o && dev->bus &&
1771 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
1774 cmd &= ~PCI_X_CMD_MAX_READ;
1776 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
1781 EXPORT_SYMBOL(pcix_set_mmrbc);
1784 * pcie_get_readrq - get PCI Express read request size
1785 * @dev: PCI device to query
1787 * Returns maximum memory read request in bytes
1788 * or appropriate error value.
1790 int pcie_get_readrq(struct pci_dev *dev)
1795 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1799 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1801 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
1805 EXPORT_SYMBOL(pcie_get_readrq);
1808 * pcie_set_readrq - set PCI Express maximum memory read request
1809 * @dev: PCI device to query
1810 * @rq: maximum memory read count in bytes
1811 * valid values are 128, 256, 512, 1024, 2048, 4096
1813 * If possible sets maximum read byte count
1815 int pcie_set_readrq(struct pci_dev *dev, int rq)
1817 int cap, err = -EINVAL;
1820 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
1823 v = (ffs(rq) - 8) << 12;
1825 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1829 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1833 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
1834 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1836 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
1842 EXPORT_SYMBOL(pcie_set_readrq);
1845 * pci_select_bars - Make BAR mask from the type of resource
1846 * @dev: the PCI device for which BAR mask is made
1847 * @flags: resource type mask to be selected
1849 * This helper routine makes bar mask from the type of resource.
1851 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1854 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1855 if (pci_resource_flags(dev, i) & flags)
1860 static void __devinit pci_no_domains(void)
1862 #ifdef CONFIG_PCI_DOMAINS
1863 pci_domains_supported = 0;
1867 static int __devinit pci_init(void)
1869 struct pci_dev *dev = NULL;
1871 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1872 pci_fixup_device(pci_fixup_final, dev);
1877 static int __devinit pci_setup(char *str)
1880 char *k = strchr(str, ',');
1883 if (*str && (str = pcibios_setup(str)) && *str) {
1884 if (!strcmp(str, "nomsi")) {
1886 } else if (!strcmp(str, "noaer")) {
1888 } else if (!strcmp(str, "nodomains")) {
1890 } else if (!strncmp(str, "cbiosize=", 9)) {
1891 pci_cardbus_io_size = memparse(str + 9, &str);
1892 } else if (!strncmp(str, "cbmemsize=", 10)) {
1893 pci_cardbus_mem_size = memparse(str + 10, &str);
1895 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1903 early_param("pci", pci_setup);
1905 device_initcall(pci_init);
1907 EXPORT_SYMBOL(pci_reenable_device);
1908 EXPORT_SYMBOL(pci_enable_device_io);
1909 EXPORT_SYMBOL(pci_enable_device_mem);
1910 EXPORT_SYMBOL(pci_enable_device);
1911 EXPORT_SYMBOL(pcim_enable_device);
1912 EXPORT_SYMBOL(pcim_pin_device);
1913 EXPORT_SYMBOL(pci_disable_device);
1914 EXPORT_SYMBOL(pci_find_capability);
1915 EXPORT_SYMBOL(pci_bus_find_capability);
1916 EXPORT_SYMBOL(pci_release_regions);
1917 EXPORT_SYMBOL(pci_request_regions);
1918 EXPORT_SYMBOL(pci_release_region);
1919 EXPORT_SYMBOL(pci_request_region);
1920 EXPORT_SYMBOL(pci_release_selected_regions);
1921 EXPORT_SYMBOL(pci_request_selected_regions);
1922 EXPORT_SYMBOL(pci_set_master);
1923 EXPORT_SYMBOL(pci_set_mwi);
1924 EXPORT_SYMBOL(pci_try_set_mwi);
1925 EXPORT_SYMBOL(pci_clear_mwi);
1926 EXPORT_SYMBOL_GPL(pci_intx);
1927 EXPORT_SYMBOL(pci_set_dma_mask);
1928 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1929 EXPORT_SYMBOL(pci_assign_resource);
1930 EXPORT_SYMBOL(pci_find_parent_resource);
1931 EXPORT_SYMBOL(pci_select_bars);
1933 EXPORT_SYMBOL(pci_set_power_state);
1934 EXPORT_SYMBOL(pci_save_state);
1935 EXPORT_SYMBOL(pci_restore_state);
1936 EXPORT_SYMBOL(pci_enable_wake);
1937 EXPORT_SYMBOL(pci_prepare_to_sleep);
1938 EXPORT_SYMBOL(pci_back_from_sleep);
1939 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);