drivers/pci/intr_remapping.c

   1 #include <linux/dmar.h>
   2 #include <linux/spinlock.h>
   3 #include <linux/jiffies.h>
   4 #include <linux/pci.h>
   5 #include <linux/irq.h>
   6 #include <asm/io_apic.h>
   7 #include "intel-iommu.h"
   8 #include "intr_remapping.h"
   9
  10 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
  11 static int ir_ioapic_num;
  12 int intr_remapping_enabled;
  13
  14 static struct {
  15         struct intel_iommu *iommu;
  16         u16 irte_index;
  17         u16 sub_handle;
  18         u8  irte_mask;
  19 } irq_2_iommu[NR_IRQS];
  20
  21 static DEFINE_SPINLOCK(irq_2_ir_lock);
  22
  23 int irq_remapped(int irq)
  24 {
  25         if (irq > NR_IRQS)
  26                 return 0;
  27
  28         if (!irq_2_iommu[irq].iommu)
  29                 return 0;
  30
  31         return 1;
  32 }
  33
  34 int get_irte(int irq, struct irte *entry)
  35 {
  36         int index;
  37
  38         if (!entry || irq > NR_IRQS)
  39                 return -1;
  40
  41         spin_lock(&irq_2_ir_lock);
  42         if (!irq_2_iommu[irq].iommu) {
  43                 spin_unlock(&irq_2_ir_lock);
  44                 return -1;
  45         }
  46
  47         index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle;
  48         *entry = *(irq_2_iommu[irq].iommu->ir_table->base + index);
  49
  50         spin_unlock(&irq_2_ir_lock);
  51         return 0;
  52 }
  53
  54 int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
  55 {
  56         struct ir_table *table = iommu->ir_table;
  57         u16 index, start_index;
  58         unsigned int mask = 0;
  59         int i;
  60
  61         if (!count)
  62                 return -1;
  63
  64         /*
  65          * start the IRTE search from index 0.
  66          */
  67         index = start_index = 0;
  68
  69         if (count > 1) {
  70                 count = __roundup_pow_of_two(count);
  71                 mask = ilog2(count);
  72         }
  73
  74         if (mask > ecap_max_handle_mask(iommu->ecap)) {
  75                 printk(KERN_ERR
  76                        "Requested mask %x exceeds the max invalidation handle"
  77                        " mask value %Lx\n", mask,
  78                        ecap_max_handle_mask(iommu->ecap));
  79                 return -1;
  80         }
  81
  82         spin_lock(&irq_2_ir_lock);
  83         do {
  84                 for (i = index; i < index + count; i++)
  85                         if  (table->base[i].present)
  86                                 break;
  87                 /* empty index found */
  88                 if (i == index + count)
  89                         break;
  90
  91                 index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
  92
  93                 if (index == start_index) {
  94                         spin_unlock(&irq_2_ir_lock);
  95                         printk(KERN_ERR "can't allocate an IRTE\n");
  96                         return -1;
  97                 }
  98         } while (1);
  99
 100         for (i = index; i < index + count; i++)
 101                 table->base[i].present = 1;
 102
 103         irq_2_iommu[irq].iommu = iommu;
 104         irq_2_iommu[irq].irte_index =  index;
 105         irq_2_iommu[irq].sub_handle = 0;
 106         irq_2_iommu[irq].irte_mask = mask;
 107
 108         spin_unlock(&irq_2_ir_lock);
 109
 110         return index;
 111 }
 112
 113 static void qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
 114 {
 115         struct qi_desc desc;
 116
 117         desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
 118                    | QI_IEC_SELECTIVE;
 119         desc.high = 0;
 120
 121         qi_submit_sync(&desc, iommu);
 122 }
 123
 124 int map_irq_to_irte_handle(int irq, u16 *sub_handle)
 125 {
 126         int index;
 127
 128         spin_lock(&irq_2_ir_lock);
 129         if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
 130                 spin_unlock(&irq_2_ir_lock);
 131                 return -1;
 132         }
 133
 134         *sub_handle = irq_2_iommu[irq].sub_handle;
 135         index = irq_2_iommu[irq].irte_index;
 136         spin_unlock(&irq_2_ir_lock);
 137         return index;
 138 }
 139
 140 int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
 141 {
 142         spin_lock(&irq_2_ir_lock);
 143         if (irq >= NR_IRQS || irq_2_iommu[irq].iommu) {
 144                 spin_unlock(&irq_2_ir_lock);
 145                 return -1;
 146         }
 147
 148         irq_2_iommu[irq].iommu = iommu;
 149         irq_2_iommu[irq].irte_index = index;
 150         irq_2_iommu[irq].sub_handle = subhandle;
 151         irq_2_iommu[irq].irte_mask = 0;
 152
 153         spin_unlock(&irq_2_ir_lock);
 154
 155         return 0;
 156 }
 157
 158 int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
 159 {
 160         spin_lock(&irq_2_ir_lock);
 161         if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
 162                 spin_unlock(&irq_2_ir_lock);
 163                 return -1;
 164         }
 165
 166         irq_2_iommu[irq].iommu = NULL;
 167         irq_2_iommu[irq].irte_index = 0;
 168         irq_2_iommu[irq].sub_handle = 0;
 169         irq_2_iommu[irq].irte_mask = 0;
 170
 171         spin_unlock(&irq_2_ir_lock);
 172
 173         return 0;
 174 }
 175
 176 int modify_irte(int irq, struct irte *irte_modified)
 177 {
 178         int index;
 179         struct irte *irte;
 180         struct intel_iommu *iommu;
 181
 182         spin_lock(&irq_2_ir_lock);
 183         if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
 184                 spin_unlock(&irq_2_ir_lock);
 185                 return -1;
 186         }
 187
 188         iommu = irq_2_iommu[irq].iommu;
 189
 190         index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle;
 191         irte = &iommu->ir_table->base[index];
 192
 193         set_64bit((unsigned long *)irte, irte_modified->low | (1 << 1));
 194         __iommu_flush_cache(iommu, irte, sizeof(*irte));
 195
 196         qi_flush_iec(iommu, index, 0);
 197
 198         spin_unlock(&irq_2_ir_lock);
 199         return 0;
 200 }
 201
 202 int flush_irte(int irq)
 203 {
 204         int index;
 205         struct intel_iommu *iommu;
 206
 207         spin_lock(&irq_2_ir_lock);
 208         if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
 209                 spin_unlock(&irq_2_ir_lock);
 210                 return -1;
 211         }
 212
 213         iommu = irq_2_iommu[irq].iommu;
 214
 215         index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle;
 216
 217         qi_flush_iec(iommu, index, irq_2_iommu[irq].irte_mask);
 218         spin_unlock(&irq_2_ir_lock);
 219
 220         return 0;
 221 }
 222
 223 struct intel_iommu *map_ioapic_to_ir(int apic)
 224 {
 225         int i;
 226
 227         for (i = 0; i < MAX_IO_APICS; i++)
 228                 if (ir_ioapic[i].id == apic)
 229                         return ir_ioapic[i].iommu;
 230         return NULL;
 231 }
 232
 233 int free_irte(int irq)
 234 {
 235         int index, i;
 236         struct irte *irte;
 237         struct intel_iommu *iommu;
 238
 239         spin_lock(&irq_2_ir_lock);
 240         if (irq >= NR_IRQS || !irq_2_iommu[irq].iommu) {
 241                 spin_unlock(&irq_2_ir_lock);
 242                 return -1;
 243         }
 244
 245         iommu = irq_2_iommu[irq].iommu;
 246
 247         index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle;
 248         irte = &iommu->ir_table->base[index];
 249
 250         if (!irq_2_iommu[irq].sub_handle) {
 251                 for (i = 0; i < (1 << irq_2_iommu[irq].irte_mask); i++)
 252                         set_64bit((unsigned long *)irte, 0);
 253                 qi_flush_iec(iommu, index, irq_2_iommu[irq].irte_mask);
 254         }
 255
 256         irq_2_iommu[irq].iommu = NULL;
 257         irq_2_iommu[irq].irte_index = 0;
 258         irq_2_iommu[irq].sub_handle = 0;
 259         irq_2_iommu[irq].irte_mask = 0;
 260
 261         spin_unlock(&irq_2_ir_lock);
 262
 263         return 0;
 264 }
 265
 266 static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 267 {
 268         u64 addr;
 269         u32 cmd, sts;
 270         unsigned long flags;
 271
 272         addr = virt_to_phys((void *)iommu->ir_table->base);
 273
 274         spin_lock_irqsave(&iommu->register_lock, flags);
 275
 276         dmar_writeq(iommu->reg + DMAR_IRTA_REG,
 277                     (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
 278
 279         /* Set interrupt-remapping table pointer */
 280         cmd = iommu->gcmd | DMA_GCMD_SIRTP;
 281         writel(cmd, iommu->reg + DMAR_GCMD_REG);
 282
 283         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 284                       readl, (sts & DMA_GSTS_IRTPS), sts);
 285         spin_unlock_irqrestore(&iommu->register_lock, flags);
 286
 287         /*
 288          * global invalidation of interrupt entry cache before enabling
 289          * interrupt-remapping.
 290          */
 291         qi_global_iec(iommu);
 292
 293         spin_lock_irqsave(&iommu->register_lock, flags);
 294
 295         /* Enable interrupt-remapping */
 296         cmd = iommu->gcmd | DMA_GCMD_IRE;
 297         iommu->gcmd |= DMA_GCMD_IRE;
 298         writel(cmd, iommu->reg + DMAR_GCMD_REG);
 299
 300         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 301                       readl, (sts & DMA_GSTS_IRES), sts);
 302
 303         spin_unlock_irqrestore(&iommu->register_lock, flags);
 304 }
 305
 306
 307 static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
 308 {
 309         struct ir_table *ir_table;
 310         struct page *pages;
 311
 312         ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
 313                                              GFP_KERNEL);
 314
 315         if (!iommu->ir_table)
 316                 return -ENOMEM;
 317
 318         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
 319
 320         if (!pages) {
 321                 printk(KERN_ERR "failed to allocate pages of order %d\n",
 322                        INTR_REMAP_PAGE_ORDER);
 323                 kfree(iommu->ir_table);
 324                 return -ENOMEM;
 325         }
 326
 327         ir_table->base = page_address(pages);
 328
 329         iommu_set_intr_remapping(iommu, mode);
 330         return 0;
 331 }
 332
 333 int __init enable_intr_remapping(int eim)
 334 {
 335         struct dmar_drhd_unit *drhd;
 336         int setup = 0;
 337
 338         /*
 339          * check for the Interrupt-remapping support
 340          */
 341         for_each_drhd_unit(drhd) {
 342                 struct intel_iommu *iommu = drhd->iommu;
 343
 344                 if (!ecap_ir_support(iommu->ecap))
 345                         continue;
 346
 347                 if (eim && !ecap_eim_support(iommu->ecap)) {
 348                         printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
 349                                " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
 350                         return -1;
 351                 }
 352         }
 353
 354         /*
 355          * Enable queued invalidation for all the DRHD's.
 356          */
 357         for_each_drhd_unit(drhd) {
 358                 int ret;
 359                 struct intel_iommu *iommu = drhd->iommu;
 360                 ret = dmar_enable_qi(iommu);
 361
 362                 if (ret) {
 363                         printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
 364                                " invalidation, ecap %Lx, ret %d\n",
 365                                drhd->reg_base_addr, iommu->ecap, ret);
 366                         return -1;
 367                 }
 368         }
 369
 370         /*
 371          * Setup Interrupt-remapping for all the DRHD's now.
 372          */
 373         for_each_drhd_unit(drhd) {
 374                 struct intel_iommu *iommu = drhd->iommu;
 375
 376                 if (!ecap_ir_support(iommu->ecap))
 377                         continue;
 378
 379                 if (setup_intr_remapping(iommu, eim))
 380                         goto error;
 381
 382                 setup = 1;
 383         }
 384
 385         if (!setup)
 386                 goto error;
 387
 388         intr_remapping_enabled = 1;
 389
 390         return 0;
 391
 392 error:
 393         /*
 394          * handle error condition gracefully here!
 395          */
 396         return -1;
 397 }
 398
 399 static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
 400                                  struct intel_iommu *iommu)
 401 {
 402         struct acpi_dmar_hardware_unit *drhd;
 403         struct acpi_dmar_device_scope *scope;
 404         void *start, *end;
 405
 406         drhd = (struct acpi_dmar_hardware_unit *)header;
 407
 408         start = (void *)(drhd + 1);
 409         end = ((void *)drhd) + header->length;
 410
 411         while (start < end) {
 412                 scope = start;
 413                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
 414                         if (ir_ioapic_num == MAX_IO_APICS) {
 415                                 printk(KERN_WARNING "Exceeded Max IO APICS\n");
 416                                 return -1;
 417                         }
 418
 419                         printk(KERN_INFO "IOAPIC id %d under DRHD base"
 420                                " 0x%Lx\n", scope->enumeration_id,
 421                                drhd->address);
 422
 423                         ir_ioapic[ir_ioapic_num].iommu = iommu;
 424                         ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
 425                         ir_ioapic_num++;
 426                 }
 427                 start += scope->length;
 428         }
 429
 430         return 0;
 431 }
 432
 433 /*
 434  * Finds the assocaition between IOAPIC's and its Interrupt-remapping
 435  * hardware unit.
 436  */
 437 int __init parse_ioapics_under_ir(void)
 438 {
 439         struct dmar_drhd_unit *drhd;
 440         int ir_supported = 0;
 441
 442         for_each_drhd_unit(drhd) {
 443                 struct intel_iommu *iommu = drhd->iommu;
 444
 445                 if (ecap_ir_support(iommu->ecap)) {
 446                         if (ir_parse_ioapic_scope(drhd->hdr, iommu))
 447                                 return -1;
 448
 449                         ir_supported = 1;
 450                 }
 451         }
 452
 453         if (ir_supported && ir_ioapic_num != nr_ioapics) {
 454                 printk(KERN_WARNING
 455                        "Not all IO-APIC's listed under remapping hardware\n");
 456                 return -1;
 457         }
 458
 459         return ir_supported;
 460 }