1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/jiffies.h>
7 #include <asm/io_apic.h>
8 #include "intel-iommu.h"
9 #include "intr_remapping.h"
11 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
12 static int ir_ioapic_num;
13 int intr_remapping_enabled;
16 struct intel_iommu *iommu;
22 #ifdef CONFIG_HAVE_SPARSE_IRQ
23 static struct irq_2_iommu *irq_2_iommuX;
25 static int nr_irq_2_iommu = 0x100;
26 static int irq_2_iommu_index;
27 DEFINE_DYN_ARRAY(irq_2_iommuX, sizeof(struct irq_2_iommu), nr_irq_2_iommu, PAGE_SIZE, NULL);
29 extern void *__alloc_bootmem_nopanic(unsigned long size,
33 static struct irq_2_iommu *get_one_free_irq_2_iommu(int not_used)
35 struct irq_2_iommu *iommu;
36 unsigned long total_bytes;
38 if (irq_2_iommu_index >= nr_irq_2_iommu) {
40 * we run out of pre-allocate ones, allocate more
42 printk(KERN_DEBUG "try to get more irq_2_iommu %d\n", nr_irq_2_iommu);
44 total_bytes = sizeof(struct irq_2_iommu)*nr_irq_2_iommu;
47 iommu = kzalloc(total_bytes, GFP_ATOMIC);
49 iommu = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
52 panic("can not get more irq_2_iommu\n");
55 irq_2_iommu_index = 0;
58 iommu = &irq_2_iommuX[irq_2_iommu_index];
63 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
65 struct irq_desc *desc;
67 desc = irq_to_desc(irq);
71 return desc->irq_2_iommu;
74 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
76 struct irq_desc *desc;
77 struct irq_2_iommu *irq_iommu;
79 desc = irq_to_desc(irq);
83 irq_iommu = desc->irq_2_iommu;
86 desc->irq_2_iommu = get_one_free_irq_2_iommu(irq);
88 return desc->irq_2_iommu;
91 #else /* !CONFIG_HAVE_SPARSE_IRQ */
93 #ifdef CONFIG_HAVE_DYN_ARRAY
94 static struct irq_2_iommu *irq_2_iommuX;
95 DEFINE_DYN_ARRAY(irq_2_iommuX, sizeof(struct irq_2_iommu), nr_irqs, PAGE_SIZE, NULL);
97 static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
100 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
103 return &irq_2_iommuX[irq];
107 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
109 return irq_2_iommu(irq);
113 static DEFINE_SPINLOCK(irq_2_ir_lock);
115 static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
117 struct irq_2_iommu *irq_iommu;
119 irq_iommu = irq_2_iommu(irq);
124 if (!irq_iommu->iommu)
130 int irq_remapped(int irq)
132 return valid_irq_2_iommu(irq) != NULL;
135 int get_irte(int irq, struct irte *entry)
138 struct irq_2_iommu *irq_iommu;
143 spin_lock(&irq_2_ir_lock);
144 irq_iommu = valid_irq_2_iommu(irq);
146 spin_unlock(&irq_2_ir_lock);
150 index = irq_iommu->irte_index + irq_iommu->sub_handle;
151 *entry = *(irq_iommu->iommu->ir_table->base + index);
153 spin_unlock(&irq_2_ir_lock);
157 int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
159 struct ir_table *table = iommu->ir_table;
160 struct irq_2_iommu *irq_iommu;
161 u16 index, start_index;
162 unsigned int mask = 0;
168 #ifndef CONFIG_HAVE_SPARSE_IRQ
169 /* protect irq_2_iommu_alloc later */
175 * start the IRTE search from index 0.
177 index = start_index = 0;
180 count = __roundup_pow_of_two(count);
184 if (mask > ecap_max_handle_mask(iommu->ecap)) {
186 "Requested mask %x exceeds the max invalidation handle"
187 " mask value %Lx\n", mask,
188 ecap_max_handle_mask(iommu->ecap));
192 spin_lock(&irq_2_ir_lock);
194 for (i = index; i < index + count; i++)
195 if (table->base[i].present)
197 /* empty index found */
198 if (i == index + count)
201 index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
203 if (index == start_index) {
204 spin_unlock(&irq_2_ir_lock);
205 printk(KERN_ERR "can't allocate an IRTE\n");
210 for (i = index; i < index + count; i++)
211 table->base[i].present = 1;
213 irq_iommu = irq_2_iommu_alloc(irq);
214 irq_iommu->iommu = iommu;
215 irq_iommu->irte_index = index;
216 irq_iommu->sub_handle = 0;
217 irq_iommu->irte_mask = mask;
219 spin_unlock(&irq_2_ir_lock);
224 static void qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
228 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
232 qi_submit_sync(&desc, iommu);
235 int map_irq_to_irte_handle(int irq, u16 *sub_handle)
238 struct irq_2_iommu *irq_iommu;
240 spin_lock(&irq_2_ir_lock);
241 irq_iommu = valid_irq_2_iommu(irq);
243 spin_unlock(&irq_2_ir_lock);
247 *sub_handle = irq_iommu->sub_handle;
248 index = irq_iommu->irte_index;
249 spin_unlock(&irq_2_ir_lock);
253 int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
255 struct irq_2_iommu *irq_iommu;
257 spin_lock(&irq_2_ir_lock);
258 irq_iommu = valid_irq_2_iommu(irq);
260 spin_unlock(&irq_2_ir_lock);
264 irq_iommu->iommu = iommu;
265 irq_iommu->irte_index = index;
266 irq_iommu->sub_handle = subhandle;
267 irq_iommu->irte_mask = 0;
269 spin_unlock(&irq_2_ir_lock);
274 int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
276 struct irq_2_iommu *irq_iommu;
278 spin_lock(&irq_2_ir_lock);
279 irq_iommu = valid_irq_2_iommu(irq);
281 spin_unlock(&irq_2_ir_lock);
285 irq_iommu->iommu = NULL;
286 irq_iommu->irte_index = 0;
287 irq_iommu->sub_handle = 0;
288 irq_2_iommu(irq)->irte_mask = 0;
290 spin_unlock(&irq_2_ir_lock);
295 int modify_irte(int irq, struct irte *irte_modified)
299 struct intel_iommu *iommu;
300 struct irq_2_iommu *irq_iommu;
302 spin_lock(&irq_2_ir_lock);
303 irq_iommu = valid_irq_2_iommu(irq);
305 spin_unlock(&irq_2_ir_lock);
309 iommu = irq_iommu->iommu;
311 index = irq_iommu->irte_index + irq_iommu->sub_handle;
312 irte = &iommu->ir_table->base[index];
314 set_64bit((unsigned long *)irte, irte_modified->low | (1 << 1));
315 __iommu_flush_cache(iommu, irte, sizeof(*irte));
317 qi_flush_iec(iommu, index, 0);
319 spin_unlock(&irq_2_ir_lock);
323 int flush_irte(int irq)
326 struct intel_iommu *iommu;
327 struct irq_2_iommu *irq_iommu;
329 spin_lock(&irq_2_ir_lock);
330 irq_iommu = valid_irq_2_iommu(irq);
332 spin_unlock(&irq_2_ir_lock);
336 iommu = irq_iommu->iommu;
338 index = irq_iommu->irte_index + irq_iommu->sub_handle;
340 qi_flush_iec(iommu, index, irq_iommu->irte_mask);
341 spin_unlock(&irq_2_ir_lock);
346 struct intel_iommu *map_ioapic_to_ir(int apic)
350 for (i = 0; i < MAX_IO_APICS; i++)
351 if (ir_ioapic[i].id == apic)
352 return ir_ioapic[i].iommu;
356 struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
358 struct dmar_drhd_unit *drhd;
360 drhd = dmar_find_matched_drhd_unit(dev);
367 int free_irte(int irq)
371 struct intel_iommu *iommu;
372 struct irq_2_iommu *irq_iommu;
374 spin_lock(&irq_2_ir_lock);
375 irq_iommu = valid_irq_2_iommu(irq);
377 spin_unlock(&irq_2_ir_lock);
381 iommu = irq_iommu->iommu;
383 index = irq_iommu->irte_index + irq_iommu->sub_handle;
384 irte = &iommu->ir_table->base[index];
386 if (!irq_iommu->sub_handle) {
387 for (i = 0; i < (1 << irq_iommu->irte_mask); i++)
388 set_64bit((unsigned long *)irte, 0);
389 qi_flush_iec(iommu, index, irq_iommu->irte_mask);
392 irq_iommu->iommu = NULL;
393 irq_iommu->irte_index = 0;
394 irq_iommu->sub_handle = 0;
395 irq_iommu->irte_mask = 0;
397 spin_unlock(&irq_2_ir_lock);
402 static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
408 addr = virt_to_phys((void *)iommu->ir_table->base);
410 spin_lock_irqsave(&iommu->register_lock, flags);
412 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
413 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
415 /* Set interrupt-remapping table pointer */
416 cmd = iommu->gcmd | DMA_GCMD_SIRTP;
417 writel(cmd, iommu->reg + DMAR_GCMD_REG);
419 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
420 readl, (sts & DMA_GSTS_IRTPS), sts);
421 spin_unlock_irqrestore(&iommu->register_lock, flags);
424 * global invalidation of interrupt entry cache before enabling
425 * interrupt-remapping.
427 qi_global_iec(iommu);
429 spin_lock_irqsave(&iommu->register_lock, flags);
431 /* Enable interrupt-remapping */
432 cmd = iommu->gcmd | DMA_GCMD_IRE;
433 iommu->gcmd |= DMA_GCMD_IRE;
434 writel(cmd, iommu->reg + DMAR_GCMD_REG);
436 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
437 readl, (sts & DMA_GSTS_IRES), sts);
439 spin_unlock_irqrestore(&iommu->register_lock, flags);
443 static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
445 struct ir_table *ir_table;
448 ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
451 if (!iommu->ir_table)
454 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
457 printk(KERN_ERR "failed to allocate pages of order %d\n",
458 INTR_REMAP_PAGE_ORDER);
459 kfree(iommu->ir_table);
463 ir_table->base = page_address(pages);
465 iommu_set_intr_remapping(iommu, mode);
469 int __init enable_intr_remapping(int eim)
471 struct dmar_drhd_unit *drhd;
475 * check for the Interrupt-remapping support
477 for_each_drhd_unit(drhd) {
478 struct intel_iommu *iommu = drhd->iommu;
480 if (!ecap_ir_support(iommu->ecap))
483 if (eim && !ecap_eim_support(iommu->ecap)) {
484 printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
485 " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
491 * Enable queued invalidation for all the DRHD's.
493 for_each_drhd_unit(drhd) {
495 struct intel_iommu *iommu = drhd->iommu;
496 ret = dmar_enable_qi(iommu);
499 printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
500 " invalidation, ecap %Lx, ret %d\n",
501 drhd->reg_base_addr, iommu->ecap, ret);
507 * Setup Interrupt-remapping for all the DRHD's now.
509 for_each_drhd_unit(drhd) {
510 struct intel_iommu *iommu = drhd->iommu;
512 if (!ecap_ir_support(iommu->ecap))
515 if (setup_intr_remapping(iommu, eim))
524 intr_remapping_enabled = 1;
530 * handle error condition gracefully here!
535 static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
536 struct intel_iommu *iommu)
538 struct acpi_dmar_hardware_unit *drhd;
539 struct acpi_dmar_device_scope *scope;
542 drhd = (struct acpi_dmar_hardware_unit *)header;
544 start = (void *)(drhd + 1);
545 end = ((void *)drhd) + header->length;
547 while (start < end) {
549 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
550 if (ir_ioapic_num == MAX_IO_APICS) {
551 printk(KERN_WARNING "Exceeded Max IO APICS\n");
555 printk(KERN_INFO "IOAPIC id %d under DRHD base"
556 " 0x%Lx\n", scope->enumeration_id,
559 ir_ioapic[ir_ioapic_num].iommu = iommu;
560 ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
563 start += scope->length;
570 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
573 int __init parse_ioapics_under_ir(void)
575 struct dmar_drhd_unit *drhd;
576 int ir_supported = 0;
578 for_each_drhd_unit(drhd) {
579 struct intel_iommu *iommu = drhd->iommu;
581 if (ecap_ir_support(iommu->ecap)) {
582 if (ir_parse_ioapic_scope(drhd->hdr, iommu))
589 if (ir_supported && ir_ioapic_num != nr_ioapics) {
591 "Not all IO-APIC's listed under remapping hardware\n");