2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
22 #ifndef _INTEL_IOMMU_H_
23 #define _INTEL_IOMMU_H_
25 #include <linux/types.h>
26 #include <linux/msi.h>
27 #include <linux/sysdev.h>
30 #include "dma_remapping.h"
33 * Intel IOMMU register specification per version 1.0 public spec.
36 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
37 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
38 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
39 #define DMAR_GCMD_REG 0x18 /* Global command register */
40 #define DMAR_GSTS_REG 0x1c /* Global status register */
41 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
42 #define DMAR_CCMD_REG 0x28 /* Context command reg */
43 #define DMAR_FSTS_REG 0x34 /* Fault Status register */
44 #define DMAR_FECTL_REG 0x38 /* Fault control register */
45 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
46 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
47 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */
48 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
49 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
50 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
51 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
52 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
53 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
55 #define OFFSET_STRIDE (9)
57 #define dmar_readl(dmar, reg) readl(dmar + reg)
58 #define dmar_readq(dmar, reg) ({ \
60 lo = readl(dmar + reg); \
61 hi = readl(dmar + reg + 4); \
62 (((u64) hi) << 32) + lo; })
64 static inline u64 dmar_readq(void __iomem *addr)
69 return (((u64) hi) << 32) + lo;
72 static inline void dmar_writeq(void __iomem *addr, u64 val)
74 writel((u32)val, addr);
75 writel((u32)(val >> 32), addr + 4);
78 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
79 #define DMAR_VER_MINOR(v) ((v) & 0x0f)
82 * Decoding Capability Register
84 #define cap_read_drain(c) (((c) >> 55) & 1)
85 #define cap_write_drain(c) (((c) >> 54) & 1)
86 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
87 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
88 #define cap_pgsel_inv(c) (((c) >> 39) & 1)
90 #define cap_super_page_val(c) (((c) >> 34) & 0xf)
91 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
92 * OFFSET_STRIDE) + 21)
94 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
95 #define cap_max_fault_reg_offset(c) \
96 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
98 #define cap_zlr(c) (((c) >> 22) & 1)
99 #define cap_isoch(c) (((c) >> 23) & 1)
100 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
101 #define cap_sagaw(c) (((c) >> 8) & 0x1f)
102 #define cap_caching_mode(c) (((c) >> 7) & 1)
103 #define cap_phmr(c) (((c) >> 6) & 1)
104 #define cap_plmr(c) (((c) >> 5) & 1)
105 #define cap_rwbf(c) (((c) >> 4) & 1)
106 #define cap_afl(c) (((c) >> 3) & 1)
107 #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
109 * Extended Capability Register
112 #define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1)
113 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
114 #define ecap_max_iotlb_offset(e) \
115 (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
116 #define ecap_coherent(e) ((e) & 0x1)
117 #define ecap_eim_support(e) ((e >> 4) & 0x1)
118 #define ecap_ir_support(e) ((e >> 3) & 0x1)
122 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
123 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
124 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
125 #define DMA_TLB_IIRG(type) ((type >> 60) & 7)
126 #define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
127 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
128 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
129 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
130 #define DMA_TLB_IVT (((u64)1) << 63)
131 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
132 #define DMA_TLB_MAX_SIZE (0x3f)
135 #define DMA_PMEN_EPM (((u32)1)<<31)
136 #define DMA_PMEN_PRS (((u32)1)<<0)
139 #define DMA_GCMD_TE (((u32)1) << 31)
140 #define DMA_GCMD_SRTP (((u32)1) << 30)
141 #define DMA_GCMD_SFL (((u32)1) << 29)
142 #define DMA_GCMD_EAFL (((u32)1) << 28)
143 #define DMA_GCMD_WBF (((u32)1) << 27)
146 #define DMA_GSTS_TES (((u32)1) << 31)
147 #define DMA_GSTS_RTPS (((u32)1) << 30)
148 #define DMA_GSTS_FLS (((u32)1) << 29)
149 #define DMA_GSTS_AFLS (((u32)1) << 28)
150 #define DMA_GSTS_WBFS (((u32)1) << 27)
153 #define DMA_CCMD_ICC (((u64)1) << 63)
154 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
155 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
156 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
157 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
158 #define DMA_CCMD_MASK_NOBIT 0
159 #define DMA_CCMD_MASK_1BIT 1
160 #define DMA_CCMD_MASK_2BIT 2
161 #define DMA_CCMD_MASK_3BIT 3
162 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
163 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
166 #define DMA_FECTL_IM (((u32)1) << 31)
169 #define DMA_FSTS_PPF ((u32)2)
170 #define DMA_FSTS_PFO ((u32)1)
171 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
173 /* FRCD_REG, 32 bits access */
174 #define DMA_FRCD_F (((u32)1) << 31)
175 #define dma_frcd_type(d) ((d >> 30) & 1)
176 #define dma_frcd_fault_reason(c) (c & 0xff)
177 #define dma_frcd_source_id(c) (c & 0xffff)
178 #define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */
180 #define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) /* 10sec */
182 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
184 cycles_t start_time = get_cycles();\
186 sts = op (iommu->reg + offset);\
189 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
190 panic("DMAR hardware is malfunctioning\n");\
196 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
200 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
201 spinlock_t register_lock; /* protect register handling */
202 int seq_id; /* sequence id of the iommu */
205 unsigned long *domain_ids; /* bitmap of domains */
206 struct dmar_domain **domains; /* ptr to domains */
207 spinlock_t lock; /* protect context, domain ids */
208 struct root_entry *root_entry; /* virtual address */
211 unsigned char name[7]; /* Device Name */
212 struct msi_msg saved_msg;
213 struct sys_device sysdev;
217 extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
219 extern int alloc_iommu(struct dmar_drhd_unit *drhd);
220 extern void free_iommu(struct intel_iommu *iommu);