2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
61 } __attribute__ ((packed));
63 /* offsets to the controller registers based on the above structure layout */
65 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
66 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
67 CAPREG = offsetof(struct ctrl_reg, cap_reg),
68 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
69 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
70 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
71 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
72 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
73 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
74 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
75 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
76 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
77 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
78 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
83 struct pci_dev *dev = ctrl->pci_dev;
84 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
89 struct pci_dev *dev = ctrl->pci_dev;
90 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
95 struct pci_dev *dev = ctrl->pci_dev;
96 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
101 struct pci_dev *dev = ctrl->pci_dev;
102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
105 /* Field definitions in PCI Express Capabilities Register */
106 #define CAP_VER 0x000F
107 #define DEV_PORT_TYPE 0x00F0
108 #define SLOT_IMPL 0x0100
109 #define MSG_NUM 0x3E00
111 /* Device or Port Type */
112 #define NAT_ENDPT 0x00
113 #define LEG_ENDPT 0x01
114 #define ROOT_PORT 0x04
115 #define UP_STREAM 0x05
116 #define DN_STREAM 0x06
117 #define PCIE_PCI_BRDG 0x07
118 #define PCI_PCIE_BRDG 0x10
120 /* Field definitions in Device Capabilities Register */
121 #define DATTN_BUTTN_PRSN 0x1000
122 #define DATTN_LED_PRSN 0x2000
123 #define DPWR_LED_PRSN 0x4000
125 /* Field definitions in Link Capabilities Register */
126 #define MAX_LNK_SPEED 0x000F
127 #define MAX_LNK_WIDTH 0x03F0
129 /* Link Width Encoding */
138 /*Field definitions of Link Status Register */
139 #define LNK_SPEED 0x000F
140 #define NEG_LINK_WD 0x03F0
141 #define LNK_TRN_ERR 0x0400
142 #define LNK_TRN 0x0800
143 #define SLOT_CLK_CONF 0x1000
145 /* Field definitions in Slot Capabilities Register */
146 #define ATTN_BUTTN_PRSN 0x00000001
147 #define PWR_CTRL_PRSN 0x00000002
148 #define MRL_SENS_PRSN 0x00000004
149 #define ATTN_LED_PRSN 0x00000008
150 #define PWR_LED_PRSN 0x00000010
151 #define HP_SUPR_RM_SUP 0x00000020
152 #define HP_CAP 0x00000040
153 #define SLOT_PWR_VALUE 0x000003F8
154 #define SLOT_PWR_LIMIT 0x00000C00
155 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
157 /* Field definitions in Slot Control Register */
158 #define ATTN_BUTTN_ENABLE 0x0001
159 #define PWR_FAULT_DETECT_ENABLE 0x0002
160 #define MRL_DETECT_ENABLE 0x0004
161 #define PRSN_DETECT_ENABLE 0x0008
162 #define CMD_CMPL_INTR_ENABLE 0x0010
163 #define HP_INTR_ENABLE 0x0020
164 #define ATTN_LED_CTRL 0x00C0
165 #define PWR_LED_CTRL 0x0300
166 #define PWR_CTRL 0x0400
167 #define EMI_CTRL 0x0800
169 /* Attention indicator and Power indicator states */
171 #define LED_BLINK 0x10
174 /* Power Control Command */
176 #define POWER_OFF 0x0400
178 /* EMI Status defines */
179 #define EMI_DISENGAGED 0
180 #define EMI_ENGAGED 1
182 /* Field definitions in Slot Status Register */
183 #define ATTN_BUTTN_PRESSED 0x0001
184 #define PWR_FAULT_DETECTED 0x0002
185 #define MRL_SENS_CHANGED 0x0004
186 #define PRSN_DETECT_CHANGED 0x0008
187 #define CMD_COMPLETED 0x0010
188 #define MRL_STATE 0x0020
189 #define PRSN_STATE 0x0040
190 #define EMI_STATE 0x0080
191 #define EMI_STATUS_BIT 7
193 static irqreturn_t pcie_isr(int irq, void *dev_id);
194 static void start_int_poll_timer(struct controller *ctrl, int sec);
196 /* This is the interrupt polling timeout function. */
197 static void int_poll_timeout(unsigned long data)
199 struct controller *ctrl = (struct controller *)data;
201 /* Poll for interrupt events. regs == NULL => polling */
204 init_timer(&ctrl->poll_timer);
205 if (!pciehp_poll_time)
206 pciehp_poll_time = 2; /* default polling interval is 2 sec */
208 start_int_poll_timer(ctrl, pciehp_poll_time);
211 /* This function starts the interrupt polling timer. */
212 static void start_int_poll_timer(struct controller *ctrl, int sec)
214 /* Clamp to sane value */
215 if ((sec <= 0) || (sec > 60))
218 ctrl->poll_timer.function = &int_poll_timeout;
219 ctrl->poll_timer.data = (unsigned long)ctrl;
220 ctrl->poll_timer.expires = jiffies + sec * HZ;
221 add_timer(&ctrl->poll_timer);
224 static inline int pciehp_request_irq(struct controller *ctrl)
226 int retval, irq = ctrl->pci_dev->irq;
228 /* Install interrupt polling timer. Start with 10 sec delay */
229 if (pciehp_poll_mode) {
230 init_timer(&ctrl->poll_timer);
231 start_int_poll_timer(ctrl, 10);
235 /* Installs the interrupt handler */
236 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
238 err("Cannot get irq %d for the hotplug controller\n", irq);
242 static inline void pciehp_free_irq(struct controller *ctrl)
244 if (pciehp_poll_mode)
245 del_timer_sync(&ctrl->poll_timer);
247 free_irq(ctrl->pci_dev->irq, ctrl);
250 static inline int pcie_wait_cmd(struct controller *ctrl)
253 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
254 unsigned long timeout = msecs_to_jiffies(msecs);
257 rc = wait_event_interruptible_timeout(ctrl->queue,
258 !ctrl->cmd_busy, timeout);
260 dbg("Command not completed in 1000 msec\n");
263 info("Command was interrupted by a signal\n");
270 * pcie_write_cmd - Issue controller command
271 * @ctrl: controller to which the command is issued
272 * @cmd: command value written to slot control register
273 * @mask: bitmask of slot control register to be modified
275 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
281 mutex_lock(&ctrl->ctrl_lock);
283 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
285 err("%s: Cannot read SLOTSTATUS register\n", __func__);
289 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
290 /* After 1 sec and CMD_COMPLETED still not set, just
291 proceed forward to issue the next command according
292 to spec. Just print out the error message */
293 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
297 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
299 err("%s: Cannot read SLOTCTRL register\n", __func__);
304 slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
308 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
310 err("%s: Cannot write to SLOTCTRL register\n", __func__);
313 * Wait for command completion.
316 retval = pcie_wait_cmd(ctrl);
318 mutex_unlock(&ctrl->ctrl_lock);
322 static int hpc_check_lnk_status(struct controller *ctrl)
327 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
329 err("%s: Cannot read LNKSTATUS register\n", __func__);
333 dbg("%s: lnk_status = %x\n", __func__, lnk_status);
334 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
335 !(lnk_status & NEG_LINK_WD)) {
336 err("%s : Link Training Error occurs \n", __func__);
344 static int hpc_get_attention_status(struct slot *slot, u8 *status)
346 struct controller *ctrl = slot->ctrl;
351 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
353 err("%s: Cannot read SLOTCTRL register\n", __func__);
357 dbg("%s: SLOTCTRL %x, value read %x\n",
358 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
360 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
362 switch (atten_led_state) {
364 *status = 0xFF; /* Reserved */
367 *status = 1; /* On */
370 *status = 2; /* Blink */
373 *status = 0; /* Off */
383 static int hpc_get_power_status(struct slot *slot, u8 *status)
385 struct controller *ctrl = slot->ctrl;
390 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
392 err("%s: Cannot read SLOTCTRL register\n", __func__);
395 dbg("%s: SLOTCTRL %x value read %x\n",
396 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
398 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
415 static int hpc_get_latch_status(struct slot *slot, u8 *status)
417 struct controller *ctrl = slot->ctrl;
421 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
423 err("%s: Cannot read SLOTSTATUS register\n", __func__);
427 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
432 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
434 struct controller *ctrl = slot->ctrl;
439 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
441 err("%s: Cannot read SLOTSTATUS register\n", __func__);
444 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
445 *status = (card_state == 1) ? 1 : 0;
450 static int hpc_query_power_fault(struct slot *slot)
452 struct controller *ctrl = slot->ctrl;
457 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
459 err("%s: Cannot check for power fault\n", __func__);
462 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
467 static int hpc_get_emi_status(struct slot *slot, u8 *status)
469 struct controller *ctrl = slot->ctrl;
473 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
475 err("%s : Cannot check EMI status\n", __func__);
478 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
483 static int hpc_toggle_emi(struct slot *slot)
491 rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
492 slot->last_emi_toggle = get_seconds();
497 static int hpc_set_attention_status(struct slot *slot, u8 value)
499 struct controller *ctrl = slot->ctrl;
504 cmd_mask = ATTN_LED_CTRL;
506 case 0 : /* turn off */
509 case 1: /* turn on */
512 case 2: /* turn blink */
518 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
519 dbg("%s: SLOTCTRL %x write cmd %x\n",
520 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
525 static void hpc_set_green_led_on(struct slot *slot)
527 struct controller *ctrl = slot->ctrl;
532 cmd_mask = PWR_LED_CTRL;
533 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
534 dbg("%s: SLOTCTRL %x write cmd %x\n",
535 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
538 static void hpc_set_green_led_off(struct slot *slot)
540 struct controller *ctrl = slot->ctrl;
545 cmd_mask = PWR_LED_CTRL;
546 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
547 dbg("%s: SLOTCTRL %x write cmd %x\n",
548 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
551 static void hpc_set_green_led_blink(struct slot *slot)
553 struct controller *ctrl = slot->ctrl;
558 cmd_mask = PWR_LED_CTRL;
559 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
560 dbg("%s: SLOTCTRL %x write cmd %x\n",
561 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
564 static void hpc_release_ctlr(struct controller *ctrl)
566 /* Mask Hot-plug Interrupt Enable */
567 if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE))
568 err("%s: Cannot mask hotplut interrupt enable\n", __func__);
570 /* Free interrupt handler or interrupt polling timer */
571 pciehp_free_irq(ctrl);
574 * If this is the last controller to be released, destroy the
577 if (atomic_dec_and_test(&pciehp_num_controllers))
578 destroy_workqueue(pciehp_wq);
581 static int hpc_power_on_slot(struct slot * slot)
583 struct controller *ctrl = slot->ctrl;
589 dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
591 /* Clear sticky power-fault bit from previous power failures */
592 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
594 err("%s: Cannot read SLOTSTATUS register\n", __func__);
597 slot_status &= PWR_FAULT_DETECTED;
599 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
601 err("%s: Cannot write to SLOTSTATUS register\n",
609 /* Enable detection that we turned off at slot power-off time */
610 if (!pciehp_poll_mode) {
611 slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
613 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
617 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
620 err("%s: Write %x command failed!\n", __func__, slot_cmd);
623 dbg("%s: SLOTCTRL %x write cmd %x\n",
624 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
629 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
631 struct pci_dev *dev = ctrl->pci_dev;
635 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
638 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®);
639 if (reg & PCI_ERR_COR_BAD_DLLP)
641 reg |= PCI_ERR_COR_BAD_DLLP;
642 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
646 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
648 struct pci_dev *dev = ctrl->pci_dev;
652 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
655 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®);
656 if (!(reg & PCI_ERR_COR_BAD_DLLP))
658 reg &= ~PCI_ERR_COR_BAD_DLLP;
659 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
662 static int hpc_power_off_slot(struct slot * slot)
664 struct controller *ctrl = slot->ctrl;
670 dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
673 * Set Bad DLLP Mask bit in Correctable Error Mask
674 * Register. This is the workaround against Bad DLLP error
675 * that sometimes happens during turning power off the slot
676 * which conforms to PCI Express 1.0a spec.
678 changed = pcie_mask_bad_dllp(ctrl);
680 slot_cmd = POWER_OFF;
683 * If we get MRL or presence detect interrupts now, the isr
684 * will notice the sticky power-fault bit too and issue power
685 * indicator change commands. This will lead to an endless loop
686 * of command completions, since the power-fault bit remains on
687 * till the slot is powered on again.
689 if (!pciehp_poll_mode) {
690 slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
692 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
696 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
698 err("%s: Write command failed!\n", __func__);
702 dbg("%s: SLOTCTRL %x write cmd %x\n",
703 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
706 * After turning power off, we must wait for at least 1 second
707 * before taking any action that relies on power having been
708 * removed from the slot/adapter.
713 pcie_unmask_bad_dllp(ctrl);
718 static irqreturn_t pcie_isr(int irq, void *dev_id)
720 struct controller *ctrl = (struct controller *)dev_id;
721 u16 detected, intr_loc;
724 * In order to guarantee that all interrupt events are
725 * serviced, we need to re-inspect Slot Status register after
726 * clearing what is presumed to be the last pending interrupt.
730 if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) {
731 err("%s: Cannot read SLOTSTATUS\n", __func__);
735 detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
736 MRL_SENS_CHANGED | PRSN_DETECT_CHANGED |
738 intr_loc |= detected;
741 if (pciehp_writew(ctrl, SLOTSTATUS, detected)) {
742 err("%s: Cannot write to SLOTSTATUS\n", __func__);
747 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
749 /* Check Command Complete Interrupt Pending */
750 if (intr_loc & CMD_COMPLETED) {
753 wake_up_interruptible(&ctrl->queue);
756 /* Check MRL Sensor Changed */
757 if (intr_loc & MRL_SENS_CHANGED)
758 pciehp_handle_switch_change(0, ctrl);
760 /* Check Attention Button Pressed */
761 if (intr_loc & ATTN_BUTTN_PRESSED)
762 pciehp_handle_attention_button(0, ctrl);
764 /* Check Presence Detect Changed */
765 if (intr_loc & PRSN_DETECT_CHANGED)
766 pciehp_handle_presence_change(0, ctrl);
768 /* Check Power Fault Detected */
769 if (intr_loc & PWR_FAULT_DETECTED)
770 pciehp_handle_power_fault(0, ctrl);
775 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
777 struct controller *ctrl = slot->ctrl;
778 enum pcie_link_speed lnk_speed;
782 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
784 err("%s: Cannot read LNKCAP register\n", __func__);
788 switch (lnk_cap & 0x000F) {
790 lnk_speed = PCIE_2PT5GB;
793 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
798 dbg("Max link speed = %d\n", lnk_speed);
803 static int hpc_get_max_lnk_width(struct slot *slot,
804 enum pcie_link_width *value)
806 struct controller *ctrl = slot->ctrl;
807 enum pcie_link_width lnk_wdth;
811 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
813 err("%s: Cannot read LNKCAP register\n", __func__);
817 switch ((lnk_cap & 0x03F0) >> 4){
819 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
822 lnk_wdth = PCIE_LNK_X1;
825 lnk_wdth = PCIE_LNK_X2;
828 lnk_wdth = PCIE_LNK_X4;
831 lnk_wdth = PCIE_LNK_X8;
834 lnk_wdth = PCIE_LNK_X12;
837 lnk_wdth = PCIE_LNK_X16;
840 lnk_wdth = PCIE_LNK_X32;
843 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
848 dbg("Max link width = %d\n", lnk_wdth);
853 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
855 struct controller *ctrl = slot->ctrl;
856 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
860 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
862 err("%s: Cannot read LNKSTATUS register\n", __func__);
866 switch (lnk_status & 0x0F) {
868 lnk_speed = PCIE_2PT5GB;
871 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
876 dbg("Current link speed = %d\n", lnk_speed);
881 static int hpc_get_cur_lnk_width(struct slot *slot,
882 enum pcie_link_width *value)
884 struct controller *ctrl = slot->ctrl;
885 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
889 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
891 err("%s: Cannot read LNKSTATUS register\n", __func__);
895 switch ((lnk_status & 0x03F0) >> 4){
897 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
900 lnk_wdth = PCIE_LNK_X1;
903 lnk_wdth = PCIE_LNK_X2;
906 lnk_wdth = PCIE_LNK_X4;
909 lnk_wdth = PCIE_LNK_X8;
912 lnk_wdth = PCIE_LNK_X12;
915 lnk_wdth = PCIE_LNK_X16;
918 lnk_wdth = PCIE_LNK_X32;
921 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
926 dbg("Current link width = %d\n", lnk_wdth);
931 static struct hpc_ops pciehp_hpc_ops = {
932 .power_on_slot = hpc_power_on_slot,
933 .power_off_slot = hpc_power_off_slot,
934 .set_attention_status = hpc_set_attention_status,
935 .get_power_status = hpc_get_power_status,
936 .get_attention_status = hpc_get_attention_status,
937 .get_latch_status = hpc_get_latch_status,
938 .get_adapter_status = hpc_get_adapter_status,
939 .get_emi_status = hpc_get_emi_status,
940 .toggle_emi = hpc_toggle_emi,
942 .get_max_bus_speed = hpc_get_max_lnk_speed,
943 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
944 .get_max_lnk_width = hpc_get_max_lnk_width,
945 .get_cur_lnk_width = hpc_get_cur_lnk_width,
947 .query_power_fault = hpc_query_power_fault,
948 .green_led_on = hpc_set_green_led_on,
949 .green_led_off = hpc_set_green_led_off,
950 .green_led_blink = hpc_set_green_led_blink,
952 .release_ctlr = hpc_release_ctlr,
953 .check_lnk_status = hpc_check_lnk_status,
957 static int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
960 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
961 struct pci_dev *pdev = dev;
962 struct pci_bus *parent;
963 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
966 * Per PCI firmware specification, we should run the ACPI _OSC
967 * method to get control of hotplug hardware before using it.
968 * If an _OSC is missing, we look for an OSHP to do the same thing.
969 * To handle different BIOS behavior, we look for _OSC and OSHP
970 * within the scope of the hotplug controller and its parents, upto
971 * the host bridge under which this controller exists.
975 * This hotplug controller was not listed in the ACPI name
976 * space at all. Try to get acpi handle of parent pci bus.
978 if (!pdev || !pdev->bus->parent)
980 parent = pdev->bus->parent;
981 dbg("Could not find %s in acpi namespace, trying parent\n",
984 /* Parent must be a host bridge */
985 handle = acpi_get_pci_rootbridge_handle(
986 pci_domain_nr(parent),
989 handle = DEVICE_ACPI_HANDLE(
990 &(parent->self->dev));
995 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
996 dbg("Trying to get hotplug control for %s \n",
997 (char *)string.pointer);
998 status = pci_osc_control_set(handle,
999 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL |
1000 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1001 if (status == AE_NOT_FOUND)
1002 status = acpi_run_oshp(handle);
1003 if (ACPI_SUCCESS(status)) {
1004 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1005 pci_name(dev), (char *)string.pointer);
1006 kfree(string.pointer);
1009 if (acpi_root_bridge(handle))
1012 status = acpi_get_parent(chandle, &handle);
1013 if (ACPI_FAILURE(status))
1017 err("Cannot get control of hotplug hardware for pci %s\n",
1020 kfree(string.pointer);
1025 static int pcie_init_hardware_part1(struct controller *ctrl,
1026 struct pcie_device *dev)
1028 /* Mask Hot-plug Interrupt Enable */
1029 if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) {
1030 err("%s: Cannot mask hotplug interrupt enable\n", __func__);
1036 int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
1041 * We need to clear all events before enabling hotplug interrupt
1042 * notification mechanism in order for hotplug controler to
1043 * generate interrupts.
1045 if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) {
1046 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1050 cmd = PRSN_DETECT_ENABLE;
1051 if (ATTN_BUTTN(ctrl))
1052 cmd |= ATTN_BUTTN_ENABLE;
1053 if (POWER_CTRL(ctrl))
1054 cmd |= PWR_FAULT_DETECT_ENABLE;
1056 cmd |= MRL_DETECT_ENABLE;
1057 if (!pciehp_poll_mode)
1058 cmd |= HP_INTR_ENABLE;
1060 mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE |
1061 PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | HP_INTR_ENABLE;
1063 if (pcie_write_cmd(ctrl, cmd, mask)) {
1064 err("%s: Cannot enable software notification\n", __func__);
1069 dbg("Bypassing BIOS check for pciehp use on %s\n",
1070 pci_name(ctrl->pci_dev));
1071 else if (pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev))
1072 goto abort_disable_intr;
1076 /* We end up here for the many possible ways to fail this API. */
1078 if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE))
1079 err("%s : disabling interrupts failed\n", __func__);
1084 static inline void dbg_ctrl(struct controller *ctrl)
1088 struct pci_dev *pdev = ctrl->pci_dev;
1093 dbg("Hotplug Controller:\n");
1094 dbg(" Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq);
1095 dbg(" Vendor ID : 0x%04x\n", pdev->vendor);
1096 dbg(" Device ID : 0x%04x\n", pdev->device);
1097 dbg(" Subsystem ID : 0x%04x\n", pdev->subsystem_device);
1098 dbg(" Subsystem Vendor ID : 0x%04x\n", pdev->subsystem_vendor);
1099 dbg(" PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
1100 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1101 if (!pci_resource_len(pdev, i))
1103 dbg(" PCI resource [%d] : 0x%llx@0x%llx\n", i,
1104 (unsigned long long)pci_resource_len(pdev, i),
1105 (unsigned long long)pci_resource_start(pdev, i));
1107 dbg("Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
1108 dbg(" Physical Slot Number : %d\n", ctrl->first_slot);
1109 dbg(" Attention Button : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no");
1110 dbg(" Power Controller : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no");
1111 dbg(" MRL Sensor : %3s\n", MRL_SENS(ctrl) ? "yes" : "no");
1112 dbg(" Attention Indicator : %3s\n", ATTN_LED(ctrl) ? "yes" : "no");
1113 dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no");
1114 dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no");
1115 dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no");
1116 pciehp_readw(ctrl, SLOTSTATUS, ®16);
1117 dbg("Slot Status : 0x%04x\n", reg16);
1118 pciehp_readw(ctrl, SLOTSTATUS, ®16);
1119 dbg("Slot Control : 0x%04x\n", reg16);
1122 int pcie_init(struct controller *ctrl, struct pcie_device *dev)
1125 struct pci_dev *pdev = dev->port;
1127 ctrl->pci_dev = pdev;
1128 ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1129 if (!ctrl->cap_base) {
1130 err("%s: Cannot find PCI Express capability\n", __func__);
1133 if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) {
1134 err("%s: Cannot read SLOTCAP register\n", __func__);
1138 ctrl->slot_cap = slot_cap;
1139 ctrl->first_slot = slot_cap >> 19;
1140 ctrl->slot_device_offset = 0;
1141 ctrl->num_slots = 1;
1142 ctrl->hpc_ops = &pciehp_hpc_ops;
1143 mutex_init(&ctrl->crit_sect);
1144 mutex_init(&ctrl->ctrl_lock);
1145 init_waitqueue_head(&ctrl->queue);
1148 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1149 pdev->vendor, pdev->device,
1150 pdev->subsystem_vendor, pdev->subsystem_device);
1152 if (pcie_init_hardware_part1(ctrl, dev))
1155 if (pciehp_request_irq(ctrl))
1159 * If this is the first controller to be initialized,
1160 * initialize the pciehp work queue
1162 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1163 pciehp_wq = create_singlethread_workqueue("pciehpd");
1165 goto abort_free_irq;
1169 if (pcie_init_hardware_part2(ctrl, dev))
1170 goto abort_free_irq;
1175 pciehp_free_irq(ctrl);