2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
61 } __attribute__ ((packed));
63 /* offsets to the controller registers based on the above structure layout */
65 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
66 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
67 CAPREG = offsetof(struct ctrl_reg, cap_reg),
68 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
69 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
70 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
71 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
72 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
73 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
74 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
75 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
76 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
77 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
78 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
83 struct pci_dev *dev = ctrl->pci_dev;
84 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
89 struct pci_dev *dev = ctrl->pci_dev;
90 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
95 struct pci_dev *dev = ctrl->pci_dev;
96 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
101 struct pci_dev *dev = ctrl->pci_dev;
102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
105 /* Field definitions in PCI Express Capabilities Register */
106 #define CAP_VER 0x000F
107 #define DEV_PORT_TYPE 0x00F0
108 #define SLOT_IMPL 0x0100
109 #define MSG_NUM 0x3E00
111 /* Device or Port Type */
112 #define NAT_ENDPT 0x00
113 #define LEG_ENDPT 0x01
114 #define ROOT_PORT 0x04
115 #define UP_STREAM 0x05
116 #define DN_STREAM 0x06
117 #define PCIE_PCI_BRDG 0x07
118 #define PCI_PCIE_BRDG 0x10
120 /* Field definitions in Device Capabilities Register */
121 #define DATTN_BUTTN_PRSN 0x1000
122 #define DATTN_LED_PRSN 0x2000
123 #define DPWR_LED_PRSN 0x4000
125 /* Field definitions in Link Capabilities Register */
126 #define MAX_LNK_SPEED 0x000F
127 #define MAX_LNK_WIDTH 0x03F0
129 /* Link Width Encoding */
138 /*Field definitions of Link Status Register */
139 #define LNK_SPEED 0x000F
140 #define NEG_LINK_WD 0x03F0
141 #define LNK_TRN_ERR 0x0400
142 #define LNK_TRN 0x0800
143 #define SLOT_CLK_CONF 0x1000
145 /* Field definitions in Slot Capabilities Register */
146 #define ATTN_BUTTN_PRSN 0x00000001
147 #define PWR_CTRL_PRSN 0x00000002
148 #define MRL_SENS_PRSN 0x00000004
149 #define ATTN_LED_PRSN 0x00000008
150 #define PWR_LED_PRSN 0x00000010
151 #define HP_SUPR_RM_SUP 0x00000020
152 #define HP_CAP 0x00000040
153 #define SLOT_PWR_VALUE 0x000003F8
154 #define SLOT_PWR_LIMIT 0x00000C00
155 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
157 /* Field definitions in Slot Control Register */
158 #define ATTN_BUTTN_ENABLE 0x0001
159 #define PWR_FAULT_DETECT_ENABLE 0x0002
160 #define MRL_DETECT_ENABLE 0x0004
161 #define PRSN_DETECT_ENABLE 0x0008
162 #define CMD_CMPL_INTR_ENABLE 0x0010
163 #define HP_INTR_ENABLE 0x0020
164 #define ATTN_LED_CTRL 0x00C0
165 #define PWR_LED_CTRL 0x0300
166 #define PWR_CTRL 0x0400
167 #define EMI_CTRL 0x0800
169 /* Attention indicator and Power indicator states */
171 #define LED_BLINK 0x10
174 /* Power Control Command */
176 #define POWER_OFF 0x0400
178 /* EMI Status defines */
179 #define EMI_DISENGAGED 0
180 #define EMI_ENGAGED 1
182 /* Field definitions in Slot Status Register */
183 #define ATTN_BUTTN_PRESSED 0x0001
184 #define PWR_FAULT_DETECTED 0x0002
185 #define MRL_SENS_CHANGED 0x0004
186 #define PRSN_DETECT_CHANGED 0x0008
187 #define CMD_COMPLETED 0x0010
188 #define MRL_STATE 0x0020
189 #define PRSN_STATE 0x0040
190 #define EMI_STATE 0x0080
191 #define EMI_STATUS_BIT 7
193 static irqreturn_t pcie_isr(int irq, void *dev_id);
194 static void start_int_poll_timer(struct controller *ctrl, int sec);
196 /* This is the interrupt polling timeout function. */
197 static void int_poll_timeout(unsigned long data)
199 struct controller *ctrl = (struct controller *)data;
201 /* Poll for interrupt events. regs == NULL => polling */
204 init_timer(&ctrl->poll_timer);
205 if (!pciehp_poll_time)
206 pciehp_poll_time = 2; /* default polling interval is 2 sec */
208 start_int_poll_timer(ctrl, pciehp_poll_time);
211 /* This function starts the interrupt polling timer. */
212 static void start_int_poll_timer(struct controller *ctrl, int sec)
214 /* Clamp to sane value */
215 if ((sec <= 0) || (sec > 60))
218 ctrl->poll_timer.function = &int_poll_timeout;
219 ctrl->poll_timer.data = (unsigned long)ctrl;
220 ctrl->poll_timer.expires = jiffies + sec * HZ;
221 add_timer(&ctrl->poll_timer);
224 static inline int pciehp_request_irq(struct controller *ctrl)
226 int retval, irq = ctrl->pci_dev->irq;
228 /* Install interrupt polling timer. Start with 10 sec delay */
229 if (pciehp_poll_mode) {
230 init_timer(&ctrl->poll_timer);
231 start_int_poll_timer(ctrl, 10);
235 /* Installs the interrupt handler */
236 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
238 err("Cannot get irq %d for the hotplug controller\n", irq);
242 static inline void pciehp_free_irq(struct controller *ctrl)
244 if (pciehp_poll_mode)
245 del_timer_sync(&ctrl->poll_timer);
247 free_irq(ctrl->pci_dev->irq, ctrl);
250 static inline int pcie_poll_cmd(struct controller *ctrl)
255 if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) {
256 if (slot_status & CMD_COMPLETED) {
257 pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED);
261 while (timeout > 1000) {
264 if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) {
265 if (slot_status & CMD_COMPLETED) {
266 pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED);
271 return 0; /* timeout */
274 static inline void pcie_wait_cmd(struct controller *ctrl, int poll)
276 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
277 unsigned long timeout = msecs_to_jiffies(msecs);
281 rc = pcie_poll_cmd(ctrl);
283 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
285 dbg("Command not completed in 1000 msec\n");
289 * pcie_write_cmd - Issue controller command
290 * @ctrl: controller to which the command is issued
291 * @cmd: command value written to slot control register
292 * @mask: bitmask of slot control register to be modified
294 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
300 mutex_lock(&ctrl->ctrl_lock);
302 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
304 err("%s: Cannot read SLOTSTATUS register\n", __func__);
308 if (slot_status & CMD_COMPLETED) {
309 if (!ctrl->no_cmd_complete) {
311 * After 1 sec and CMD_COMPLETED still not set, just
312 * proceed forward to issue the next command according
313 * to spec. Just print out the error message.
315 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
317 } else if (!NO_CMD_CMPL(ctrl)) {
319 * This controller semms to notify of command completed
320 * event even though it supports none of power
321 * controller, attention led, power led and EMI.
323 dbg("%s: Unexpected CMD_COMPLETED. Need to wait for "
324 "command completed event.\n", __func__);
325 ctrl->no_cmd_complete = 0;
327 dbg("%s: Unexpected CMD_COMPLETED. Maybe the "
328 "controller is broken.\n", __func__);
332 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
334 err("%s: Cannot read SLOTCTRL register\n", __func__);
339 slot_ctrl |= (cmd & mask);
340 /* Don't enable command completed if caller is changing it. */
341 if (!(mask & CMD_CMPL_INTR_ENABLE))
342 slot_ctrl |= CMD_CMPL_INTR_ENABLE;
346 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
348 err("%s: Cannot write to SLOTCTRL register\n", __func__);
351 * Wait for command completion.
353 if (!retval && !ctrl->no_cmd_complete) {
356 * if hotplug interrupt is not enabled or command
357 * completed interrupt is not enabled, we need to poll
358 * command completed event.
360 if (!(slot_ctrl & HP_INTR_ENABLE) ||
361 !(slot_ctrl & CMD_CMPL_INTR_ENABLE))
363 pcie_wait_cmd(ctrl, poll);
366 mutex_unlock(&ctrl->ctrl_lock);
370 static int hpc_check_lnk_status(struct controller *ctrl)
375 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
377 err("%s: Cannot read LNKSTATUS register\n", __func__);
381 dbg("%s: lnk_status = %x\n", __func__, lnk_status);
382 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
383 !(lnk_status & NEG_LINK_WD)) {
384 err("%s : Link Training Error occurs \n", __func__);
392 static int hpc_get_attention_status(struct slot *slot, u8 *status)
394 struct controller *ctrl = slot->ctrl;
399 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
401 err("%s: Cannot read SLOTCTRL register\n", __func__);
405 dbg("%s: SLOTCTRL %x, value read %x\n",
406 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
408 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
410 switch (atten_led_state) {
412 *status = 0xFF; /* Reserved */
415 *status = 1; /* On */
418 *status = 2; /* Blink */
421 *status = 0; /* Off */
431 static int hpc_get_power_status(struct slot *slot, u8 *status)
433 struct controller *ctrl = slot->ctrl;
438 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
440 err("%s: Cannot read SLOTCTRL register\n", __func__);
443 dbg("%s: SLOTCTRL %x value read %x\n",
444 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
446 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
463 static int hpc_get_latch_status(struct slot *slot, u8 *status)
465 struct controller *ctrl = slot->ctrl;
469 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
471 err("%s: Cannot read SLOTSTATUS register\n", __func__);
475 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
480 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
482 struct controller *ctrl = slot->ctrl;
487 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
489 err("%s: Cannot read SLOTSTATUS register\n", __func__);
492 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
493 *status = (card_state == 1) ? 1 : 0;
498 static int hpc_query_power_fault(struct slot *slot)
500 struct controller *ctrl = slot->ctrl;
505 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
507 err("%s: Cannot check for power fault\n", __func__);
510 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
515 static int hpc_get_emi_status(struct slot *slot, u8 *status)
517 struct controller *ctrl = slot->ctrl;
521 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
523 err("%s : Cannot check EMI status\n", __func__);
526 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
531 static int hpc_toggle_emi(struct slot *slot)
539 rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
540 slot->last_emi_toggle = get_seconds();
545 static int hpc_set_attention_status(struct slot *slot, u8 value)
547 struct controller *ctrl = slot->ctrl;
552 cmd_mask = ATTN_LED_CTRL;
554 case 0 : /* turn off */
557 case 1: /* turn on */
560 case 2: /* turn blink */
566 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
567 dbg("%s: SLOTCTRL %x write cmd %x\n",
568 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
573 static void hpc_set_green_led_on(struct slot *slot)
575 struct controller *ctrl = slot->ctrl;
580 cmd_mask = PWR_LED_CTRL;
581 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
582 dbg("%s: SLOTCTRL %x write cmd %x\n",
583 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
586 static void hpc_set_green_led_off(struct slot *slot)
588 struct controller *ctrl = slot->ctrl;
593 cmd_mask = PWR_LED_CTRL;
594 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
595 dbg("%s: SLOTCTRL %x write cmd %x\n",
596 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
599 static void hpc_set_green_led_blink(struct slot *slot)
601 struct controller *ctrl = slot->ctrl;
606 cmd_mask = PWR_LED_CTRL;
607 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
608 dbg("%s: SLOTCTRL %x write cmd %x\n",
609 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
612 static void hpc_release_ctlr(struct controller *ctrl)
614 /* Mask Hot-plug Interrupt Enable */
615 if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE))
616 err("%s: Cannot mask hotplug interrupt enable\n", __func__);
618 /* Free interrupt handler or interrupt polling timer */
619 pciehp_free_irq(ctrl);
622 * If this is the last controller to be released, destroy the
625 if (atomic_dec_and_test(&pciehp_num_controllers))
626 destroy_workqueue(pciehp_wq);
629 static int hpc_power_on_slot(struct slot * slot)
631 struct controller *ctrl = slot->ctrl;
637 dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
639 /* Clear sticky power-fault bit from previous power failures */
640 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
642 err("%s: Cannot read SLOTSTATUS register\n", __func__);
645 slot_status &= PWR_FAULT_DETECTED;
647 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
649 err("%s: Cannot write to SLOTSTATUS register\n",
657 /* Enable detection that we turned off at slot power-off time */
658 if (!pciehp_poll_mode) {
659 slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
661 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
665 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
668 err("%s: Write %x command failed!\n", __func__, slot_cmd);
671 dbg("%s: SLOTCTRL %x write cmd %x\n",
672 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
677 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
679 struct pci_dev *dev = ctrl->pci_dev;
683 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
686 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®);
687 if (reg & PCI_ERR_COR_BAD_DLLP)
689 reg |= PCI_ERR_COR_BAD_DLLP;
690 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
694 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
696 struct pci_dev *dev = ctrl->pci_dev;
700 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
703 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®);
704 if (!(reg & PCI_ERR_COR_BAD_DLLP))
706 reg &= ~PCI_ERR_COR_BAD_DLLP;
707 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
710 static int hpc_power_off_slot(struct slot * slot)
712 struct controller *ctrl = slot->ctrl;
718 dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
721 * Set Bad DLLP Mask bit in Correctable Error Mask
722 * Register. This is the workaround against Bad DLLP error
723 * that sometimes happens during turning power off the slot
724 * which conforms to PCI Express 1.0a spec.
726 changed = pcie_mask_bad_dllp(ctrl);
728 slot_cmd = POWER_OFF;
731 * If we get MRL or presence detect interrupts now, the isr
732 * will notice the sticky power-fault bit too and issue power
733 * indicator change commands. This will lead to an endless loop
734 * of command completions, since the power-fault bit remains on
735 * till the slot is powered on again.
737 if (!pciehp_poll_mode) {
738 slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
740 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
744 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
746 err("%s: Write command failed!\n", __func__);
750 dbg("%s: SLOTCTRL %x write cmd %x\n",
751 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
754 pcie_unmask_bad_dllp(ctrl);
759 static irqreturn_t pcie_isr(int irq, void *dev_id)
761 struct controller *ctrl = (struct controller *)dev_id;
762 u16 detected, intr_loc;
766 * In order to guarantee that all interrupt events are
767 * serviced, we need to re-inspect Slot Status register after
768 * clearing what is presumed to be the last pending interrupt.
772 if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) {
773 err("%s: Cannot read SLOTSTATUS\n", __func__);
777 detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
778 MRL_SENS_CHANGED | PRSN_DETECT_CHANGED |
780 intr_loc |= detected;
783 if (detected && pciehp_writew(ctrl, SLOTSTATUS, detected)) {
784 err("%s: Cannot write to SLOTSTATUS\n", __func__);
789 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
791 /* Check Command Complete Interrupt Pending */
792 if (intr_loc & CMD_COMPLETED) {
795 wake_up(&ctrl->queue);
798 if (!(intr_loc & ~CMD_COMPLETED))
802 * Return without handling events if this handler routine is
803 * called before controller initialization is done. This may
804 * happen if hotplug event or another interrupt that shares
805 * the IRQ with pciehp arrives before slot initialization is
806 * done after interrupt handler is registered.
808 * FIXME - Need more structural fixes. We need to be ready to
809 * handle the event before installing interrupt handler.
811 p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
812 if (!p_slot || !p_slot->hpc_ops)
815 /* Check MRL Sensor Changed */
816 if (intr_loc & MRL_SENS_CHANGED)
817 pciehp_handle_switch_change(p_slot);
819 /* Check Attention Button Pressed */
820 if (intr_loc & ATTN_BUTTN_PRESSED)
821 pciehp_handle_attention_button(p_slot);
823 /* Check Presence Detect Changed */
824 if (intr_loc & PRSN_DETECT_CHANGED)
825 pciehp_handle_presence_change(p_slot);
827 /* Check Power Fault Detected */
828 if (intr_loc & PWR_FAULT_DETECTED)
829 pciehp_handle_power_fault(p_slot);
834 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
836 struct controller *ctrl = slot->ctrl;
837 enum pcie_link_speed lnk_speed;
841 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
843 err("%s: Cannot read LNKCAP register\n", __func__);
847 switch (lnk_cap & 0x000F) {
849 lnk_speed = PCIE_2PT5GB;
852 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
857 dbg("Max link speed = %d\n", lnk_speed);
862 static int hpc_get_max_lnk_width(struct slot *slot,
863 enum pcie_link_width *value)
865 struct controller *ctrl = slot->ctrl;
866 enum pcie_link_width lnk_wdth;
870 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
872 err("%s: Cannot read LNKCAP register\n", __func__);
876 switch ((lnk_cap & 0x03F0) >> 4){
878 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
881 lnk_wdth = PCIE_LNK_X1;
884 lnk_wdth = PCIE_LNK_X2;
887 lnk_wdth = PCIE_LNK_X4;
890 lnk_wdth = PCIE_LNK_X8;
893 lnk_wdth = PCIE_LNK_X12;
896 lnk_wdth = PCIE_LNK_X16;
899 lnk_wdth = PCIE_LNK_X32;
902 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
907 dbg("Max link width = %d\n", lnk_wdth);
912 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
914 struct controller *ctrl = slot->ctrl;
915 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
919 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
921 err("%s: Cannot read LNKSTATUS register\n", __func__);
925 switch (lnk_status & 0x0F) {
927 lnk_speed = PCIE_2PT5GB;
930 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
935 dbg("Current link speed = %d\n", lnk_speed);
940 static int hpc_get_cur_lnk_width(struct slot *slot,
941 enum pcie_link_width *value)
943 struct controller *ctrl = slot->ctrl;
944 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
948 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
950 err("%s: Cannot read LNKSTATUS register\n", __func__);
954 switch ((lnk_status & 0x03F0) >> 4){
956 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
959 lnk_wdth = PCIE_LNK_X1;
962 lnk_wdth = PCIE_LNK_X2;
965 lnk_wdth = PCIE_LNK_X4;
968 lnk_wdth = PCIE_LNK_X8;
971 lnk_wdth = PCIE_LNK_X12;
974 lnk_wdth = PCIE_LNK_X16;
977 lnk_wdth = PCIE_LNK_X32;
980 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
985 dbg("Current link width = %d\n", lnk_wdth);
990 static struct hpc_ops pciehp_hpc_ops = {
991 .power_on_slot = hpc_power_on_slot,
992 .power_off_slot = hpc_power_off_slot,
993 .set_attention_status = hpc_set_attention_status,
994 .get_power_status = hpc_get_power_status,
995 .get_attention_status = hpc_get_attention_status,
996 .get_latch_status = hpc_get_latch_status,
997 .get_adapter_status = hpc_get_adapter_status,
998 .get_emi_status = hpc_get_emi_status,
999 .toggle_emi = hpc_toggle_emi,
1001 .get_max_bus_speed = hpc_get_max_lnk_speed,
1002 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1003 .get_max_lnk_width = hpc_get_max_lnk_width,
1004 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1006 .query_power_fault = hpc_query_power_fault,
1007 .green_led_on = hpc_set_green_led_on,
1008 .green_led_off = hpc_set_green_led_off,
1009 .green_led_blink = hpc_set_green_led_blink,
1011 .release_ctlr = hpc_release_ctlr,
1012 .check_lnk_status = hpc_check_lnk_status,
1015 static int pcie_init_hardware_part1(struct controller *ctrl,
1016 struct pcie_device *dev)
1018 /* Clear all remaining event bits in Slot Status register */
1019 if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) {
1020 err("%s: Cannot write to SLOTSTATUS register\n", __func__);
1024 /* Mask Hot-plug Interrupt Enable */
1025 if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) {
1026 err("%s: Cannot mask hotplug interrupt enable\n", __func__);
1032 int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
1036 cmd = PRSN_DETECT_ENABLE;
1037 if (ATTN_BUTTN(ctrl))
1038 cmd |= ATTN_BUTTN_ENABLE;
1039 if (POWER_CTRL(ctrl))
1040 cmd |= PWR_FAULT_DETECT_ENABLE;
1042 cmd |= MRL_DETECT_ENABLE;
1043 if (!pciehp_poll_mode)
1044 cmd |= HP_INTR_ENABLE;
1046 mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE |
1047 PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | HP_INTR_ENABLE;
1049 if (pcie_write_cmd(ctrl, cmd, mask)) {
1050 err("%s: Cannot enable software notification\n", __func__);
1057 static inline void dbg_ctrl(struct controller *ctrl)
1061 struct pci_dev *pdev = ctrl->pci_dev;
1066 dbg("Hotplug Controller:\n");
1067 dbg(" Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq);
1068 dbg(" Vendor ID : 0x%04x\n", pdev->vendor);
1069 dbg(" Device ID : 0x%04x\n", pdev->device);
1070 dbg(" Subsystem ID : 0x%04x\n", pdev->subsystem_device);
1071 dbg(" Subsystem Vendor ID : 0x%04x\n", pdev->subsystem_vendor);
1072 dbg(" PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
1073 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1074 if (!pci_resource_len(pdev, i))
1076 dbg(" PCI resource [%d] : 0x%llx@0x%llx\n", i,
1077 (unsigned long long)pci_resource_len(pdev, i),
1078 (unsigned long long)pci_resource_start(pdev, i));
1080 dbg("Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
1081 dbg(" Physical Slot Number : %d\n", ctrl->first_slot);
1082 dbg(" Attention Button : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no");
1083 dbg(" Power Controller : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no");
1084 dbg(" MRL Sensor : %3s\n", MRL_SENS(ctrl) ? "yes" : "no");
1085 dbg(" Attention Indicator : %3s\n", ATTN_LED(ctrl) ? "yes" : "no");
1086 dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no");
1087 dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no");
1088 dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no");
1089 dbg(" Comamnd Completed : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes");
1090 pciehp_readw(ctrl, SLOTSTATUS, ®16);
1091 dbg("Slot Status : 0x%04x\n", reg16);
1092 pciehp_readw(ctrl, SLOTCTRL, ®16);
1093 dbg("Slot Control : 0x%04x\n", reg16);
1096 int pcie_init(struct controller *ctrl, struct pcie_device *dev)
1099 struct pci_dev *pdev = dev->port;
1101 ctrl->pci_dev = pdev;
1102 ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1103 if (!ctrl->cap_base) {
1104 err("%s: Cannot find PCI Express capability\n", __func__);
1107 if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) {
1108 err("%s: Cannot read SLOTCAP register\n", __func__);
1112 ctrl->slot_cap = slot_cap;
1113 ctrl->first_slot = slot_cap >> 19;
1114 ctrl->slot_device_offset = 0;
1115 ctrl->num_slots = 1;
1116 ctrl->hpc_ops = &pciehp_hpc_ops;
1117 mutex_init(&ctrl->crit_sect);
1118 mutex_init(&ctrl->ctrl_lock);
1119 init_waitqueue_head(&ctrl->queue);
1122 * Controller doesn't notify of command completion if the "No
1123 * Command Completed Support" bit is set in Slot Capability
1124 * register or the controller supports none of power
1125 * controller, attention led, power led and EMI.
1127 if (NO_CMD_CMPL(ctrl) ||
1128 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
1129 ctrl->no_cmd_complete = 1;
1131 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1132 pdev->vendor, pdev->device,
1133 pdev->subsystem_vendor, pdev->subsystem_device);
1135 if (pcie_init_hardware_part1(ctrl, dev))
1138 if (pciehp_request_irq(ctrl))
1142 * If this is the first controller to be initialized,
1143 * initialize the pciehp work queue
1145 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1146 pciehp_wq = create_singlethread_workqueue("pciehpd");
1148 goto abort_free_irq;
1152 if (pcie_init_hardware_part2(ctrl, dev))
1153 goto abort_free_irq;
1158 pciehp_free_irq(ctrl);