drivers/pci/dmar.c

   1 /*
   2  * Copyright (c) 2006, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15  * Place - Suite 330, Boston, MA 02111-1307 USA.
  16  *
  17  * Copyright (C) 2006-2008 Intel Corporation
  18  * Author: Ashok Raj <ashok.raj@intel.com>
  19  * Author: Shaohua Li <shaohua.li@intel.com>
  20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  21  *
  22  * This file implements early detection/parsing of Remapping Devices
  23  * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
  24  * tables.
  25  *
  26  * These routines are used by both DMA-remapping and Interrupt-remapping
  27  */
  28
  29 #include <linux/pci.h>
  30 #include <linux/dmar.h>
  31 #include <linux/iova.h>
  32 #include <linux/intel-iommu.h>
  33 #include <linux/timer.h>
  34
  35 #undef PREFIX
  36 #define PREFIX "DMAR:"
  37
  38 /* No locks are needed as DMA remapping hardware unit
  39  * list is constructed at boot time and hotplug of
  40  * these units are not supported by the architecture.
  41  */
  42 LIST_HEAD(dmar_drhd_units);
  43
  44 static struct acpi_table_header * __initdata dmar_tbl;
  45
  46 static void __init dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
  47 {
  48         /*
  49          * add INCLUDE_ALL at the tail, so scan the list will find it at
  50          * the very end.
  51          */
  52         if (drhd->include_all)
  53                 list_add_tail(&drhd->list, &dmar_drhd_units);
  54         else
  55                 list_add(&drhd->list, &dmar_drhd_units);
  56 }
  57
  58 static int __init dmar_parse_one_dev_scope(struct acpi_dmar_device_scope *scope,
  59                                            struct pci_dev **dev, u16 segment)
  60 {
  61         struct pci_bus *bus;
  62         struct pci_dev *pdev = NULL;
  63         struct acpi_dmar_pci_path *path;
  64         int count;
  65
  66         bus = pci_find_bus(segment, scope->bus);
  67         path = (struct acpi_dmar_pci_path *)(scope + 1);
  68         count = (scope->length - sizeof(struct acpi_dmar_device_scope))
  69                 / sizeof(struct acpi_dmar_pci_path);
  70
  71         while (count) {
  72                 if (pdev)
  73                         pci_dev_put(pdev);
  74                 /*
  75                  * Some BIOSes list non-exist devices in DMAR table, just
  76                  * ignore it
  77                  */
  78                 if (!bus) {
  79                         printk(KERN_WARNING
  80                         PREFIX "Device scope bus [%d] not found\n",
  81                         scope->bus);
  82                         break;
  83                 }
  84                 pdev = pci_get_slot(bus, PCI_DEVFN(path->dev, path->fn));
  85                 if (!pdev) {
  86                         printk(KERN_WARNING PREFIX
  87                         "Device scope device [%04x:%02x:%02x.%02x] not found\n",
  88                                 segment, bus->number, path->dev, path->fn);
  89                         break;
  90                 }
  91                 path ++;
  92                 count --;
  93                 bus = pdev->subordinate;
  94         }
  95         if (!pdev) {
  96                 printk(KERN_WARNING PREFIX
  97                 "Device scope device [%04x:%02x:%02x.%02x] not found\n",
  98                 segment, scope->bus, path->dev, path->fn);
  99                 *dev = NULL;
 100                 return 0;
 101         }
 102         if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && \
 103                         pdev->subordinate) || (scope->entry_type == \
 104                         ACPI_DMAR_SCOPE_TYPE_BRIDGE && !pdev->subordinate)) {
 105                 pci_dev_put(pdev);
 106                 printk(KERN_WARNING PREFIX
 107                         "Device scope type does not match for %s\n",
 108                          pci_name(pdev));
 109                 return -EINVAL;
 110         }
 111         *dev = pdev;
 112         return 0;
 113 }
 114
 115 static int __init dmar_parse_dev_scope(void *start, void *end, int *cnt,
 116                                        struct pci_dev ***devices, u16 segment)
 117 {
 118         struct acpi_dmar_device_scope *scope;
 119         void * tmp = start;
 120         int index;
 121         int ret;
 122
 123         *cnt = 0;
 124         while (start < end) {
 125                 scope = start;
 126                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
 127                     scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
 128                         (*cnt)++;
 129                 else
 130                         printk(KERN_WARNING PREFIX
 131                                 "Unsupported device scope\n");
 132                 start += scope->length;
 133         }
 134         if (*cnt == 0)
 135                 return 0;
 136
 137         *devices = kcalloc(*cnt, sizeof(struct pci_dev *), GFP_KERNEL);
 138         if (!*devices)
 139                 return -ENOMEM;
 140
 141         start = tmp;
 142         index = 0;
 143         while (start < end) {
 144                 scope = start;
 145                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
 146                     scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) {
 147                         ret = dmar_parse_one_dev_scope(scope,
 148                                 &(*devices)[index], segment);
 149                         if (ret) {
 150                                 kfree(*devices);
 151                                 return ret;
 152                         }
 153                         index ++;
 154                 }
 155                 start += scope->length;
 156         }
 157
 158         return 0;
 159 }
 160
 161 /**
 162  * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
 163  * structure which uniquely represent one DMA remapping hardware unit
 164  * present in the platform
 165  */
 166 static int __init
 167 dmar_parse_one_drhd(struct acpi_dmar_header *header)
 168 {
 169         struct acpi_dmar_hardware_unit *drhd;
 170         struct dmar_drhd_unit *dmaru;
 171         int ret = 0;
 172
 173         dmaru = kzalloc(sizeof(*dmaru), GFP_KERNEL);
 174         if (!dmaru)
 175                 return -ENOMEM;
 176
 177         dmaru->hdr = header;
 178         drhd = (struct acpi_dmar_hardware_unit *)header;
 179         dmaru->reg_base_addr = drhd->address;
 180         dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
 181
 182         ret = alloc_iommu(dmaru);
 183         if (ret) {
 184                 kfree(dmaru);
 185                 return ret;
 186         }
 187         dmar_register_drhd_unit(dmaru);
 188         return 0;
 189 }
 190
 191 static int __init
 192 dmar_parse_dev(struct dmar_drhd_unit *dmaru)
 193 {
 194         struct acpi_dmar_hardware_unit *drhd;
 195         static int include_all;
 196         int ret;
 197
 198         drhd = (struct acpi_dmar_hardware_unit *) dmaru->hdr;
 199
 200         if (!dmaru->include_all)
 201                 ret = dmar_parse_dev_scope((void *)(drhd + 1),
 202                                 ((void *)drhd) + drhd->header.length,
 203                                 &dmaru->devices_cnt, &dmaru->devices,
 204                                 drhd->segment);
 205         else {
 206                 /* Only allow one INCLUDE_ALL */
 207                 if (include_all) {
 208                         printk(KERN_WARNING PREFIX "Only one INCLUDE_ALL "
 209                                 "device scope is allowed\n");
 210                         ret = -EINVAL;
 211                 }
 212                 include_all = 1;
 213         }
 214
 215         if (ret || (dmaru->devices_cnt == 0 && !dmaru->include_all)) {
 216                 list_del(&dmaru->list);
 217                 kfree(dmaru);
 218         }
 219         return ret;
 220 }
 221
 222 #ifdef CONFIG_DMAR
 223 LIST_HEAD(dmar_rmrr_units);
 224
 225 static void __init dmar_register_rmrr_unit(struct dmar_rmrr_unit *rmrr)
 226 {
 227         list_add(&rmrr->list, &dmar_rmrr_units);
 228 }
 229
 230
 231 static int __init
 232 dmar_parse_one_rmrr(struct acpi_dmar_header *header)
 233 {
 234         struct acpi_dmar_reserved_memory *rmrr;
 235         struct dmar_rmrr_unit *rmrru;
 236
 237         rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
 238         if (!rmrru)
 239                 return -ENOMEM;
 240
 241         rmrru->hdr = header;
 242         rmrr = (struct acpi_dmar_reserved_memory *)header;
 243         rmrru->base_address = rmrr->base_address;
 244         rmrru->end_address = rmrr->end_address;
 245
 246         dmar_register_rmrr_unit(rmrru);
 247         return 0;
 248 }
 249
 250 static int __init
 251 rmrr_parse_dev(struct dmar_rmrr_unit *rmrru)
 252 {
 253         struct acpi_dmar_reserved_memory *rmrr;
 254         int ret;
 255
 256         rmrr = (struct acpi_dmar_reserved_memory *) rmrru->hdr;
 257         ret = dmar_parse_dev_scope((void *)(rmrr + 1),
 258                 ((void *)rmrr) + rmrr->header.length,
 259                 &rmrru->devices_cnt, &rmrru->devices, rmrr->segment);
 260
 261         if (ret || (rmrru->devices_cnt == 0)) {
 262                 list_del(&rmrru->list);
 263                 kfree(rmrru);
 264         }
 265         return ret;
 266 }
 267 #endif
 268
 269 static void __init
 270 dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
 271 {
 272         struct acpi_dmar_hardware_unit *drhd;
 273         struct acpi_dmar_reserved_memory *rmrr;
 274
 275         switch (header->type) {
 276         case ACPI_DMAR_TYPE_HARDWARE_UNIT:
 277                 drhd = (struct acpi_dmar_hardware_unit *)header;
 278                 printk (KERN_INFO PREFIX
 279                         "DRHD (flags: 0x%08x)base: 0x%016Lx\n",
 280                         drhd->flags, (unsigned long long)drhd->address);
 281                 break;
 282         case ACPI_DMAR_TYPE_RESERVED_MEMORY:
 283                 rmrr = (struct acpi_dmar_reserved_memory *)header;
 284
 285                 printk (KERN_INFO PREFIX
 286                         "RMRR base: 0x%016Lx end: 0x%016Lx\n",
 287                         (unsigned long long)rmrr->base_address,
 288                         (unsigned long long)rmrr->end_address);
 289                 break;
 290         }
 291 }
 292
 293
 294 /**
 295  * parse_dmar_table - parses the DMA reporting table
 296  */
 297 static int __init
 298 parse_dmar_table(void)
 299 {
 300         struct acpi_table_dmar *dmar;
 301         struct acpi_dmar_header *entry_header;
 302         int ret = 0;
 303
 304         dmar = (struct acpi_table_dmar *)dmar_tbl;
 305         if (!dmar)
 306                 return -ENODEV;
 307
 308         if (dmar->width < PAGE_SHIFT - 1) {
 309                 printk(KERN_WARNING PREFIX "Invalid DMAR haw\n");
 310                 return -EINVAL;
 311         }
 312
 313         printk (KERN_INFO PREFIX "Host address width %d\n",
 314                 dmar->width + 1);
 315
 316         entry_header = (struct acpi_dmar_header *)(dmar + 1);
 317         while (((unsigned long)entry_header) <
 318                         (((unsigned long)dmar) + dmar_tbl->length)) {
 319                 dmar_table_print_dmar_entry(entry_header);
 320
 321                 switch (entry_header->type) {
 322                 case ACPI_DMAR_TYPE_HARDWARE_UNIT:
 323                         ret = dmar_parse_one_drhd(entry_header);
 324                         break;
 325                 case ACPI_DMAR_TYPE_RESERVED_MEMORY:
 326 #ifdef CONFIG_DMAR
 327                         ret = dmar_parse_one_rmrr(entry_header);
 328 #endif
 329                         break;
 330                 default:
 331                         printk(KERN_WARNING PREFIX
 332                                 "Unknown DMAR structure type\n");
 333                         ret = 0; /* for forward compatibility */
 334                         break;
 335                 }
 336                 if (ret)
 337                         break;
 338
 339                 entry_header = ((void *)entry_header + entry_header->length);
 340         }
 341         return ret;
 342 }
 343
 344 int dmar_pci_device_match(struct pci_dev *devices[], int cnt,
 345                           struct pci_dev *dev)
 346 {
 347         int index;
 348
 349         while (dev) {
 350                 for (index = 0; index < cnt; index++)
 351                         if (dev == devices[index])
 352                                 return 1;
 353
 354                 /* Check our parent */
 355                 dev = dev->bus->self;
 356         }
 357
 358         return 0;
 359 }
 360
 361 struct dmar_drhd_unit *
 362 dmar_find_matched_drhd_unit(struct pci_dev *dev)
 363 {
 364         struct dmar_drhd_unit *drhd = NULL;
 365
 366         list_for_each_entry(drhd, &dmar_drhd_units, list) {
 367                 if (drhd->include_all || dmar_pci_device_match(drhd->devices,
 368                                                 drhd->devices_cnt, dev))
 369                         return drhd;
 370         }
 371
 372         return NULL;
 373 }
 374
 375 int __init dmar_dev_scope_init(void)
 376 {
 377         struct dmar_drhd_unit *drhd;
 378         int ret = -ENODEV;
 379
 380         for_each_drhd_unit(drhd) {
 381                 ret = dmar_parse_dev(drhd);
 382                 if (ret)
 383                         return ret;
 384         }
 385
 386 #ifdef CONFIG_DMAR
 387         {
 388                 struct dmar_rmrr_unit *rmrr;
 389                 for_each_rmrr_units(rmrr) {
 390                         ret = rmrr_parse_dev(rmrr);
 391                         if (ret)
 392                                 return ret;
 393                 }
 394         }
 395 #endif
 396
 397         return ret;
 398 }
 399
 400
 401 int __init dmar_table_init(void)
 402 {
 403         static int dmar_table_initialized;
 404         int ret;
 405
 406         if (dmar_table_initialized)
 407                 return 0;
 408
 409         dmar_table_initialized = 1;
 410
 411         ret = parse_dmar_table();
 412         if (ret) {
 413                 if (ret != -ENODEV)
 414                         printk(KERN_INFO PREFIX "parse DMAR table failure.\n");
 415                 return ret;
 416         }
 417
 418         if (list_empty(&dmar_drhd_units)) {
 419                 printk(KERN_INFO PREFIX "No DMAR devices found\n");
 420                 return -ENODEV;
 421         }
 422
 423 #ifdef CONFIG_DMAR
 424         if (list_empty(&dmar_rmrr_units))
 425                 printk(KERN_INFO PREFIX "No RMRR found\n");
 426 #endif
 427
 428 #ifdef CONFIG_INTR_REMAP
 429         parse_ioapics_under_ir();
 430 #endif
 431         return 0;
 432 }
 433
 434 /**
 435  * early_dmar_detect - checks to see if the platform supports DMAR devices
 436  */
 437 int __init early_dmar_detect(void)
 438 {
 439         acpi_status status = AE_OK;
 440
 441         /* if we could find DMAR table, then there are DMAR devices */
 442         status = acpi_get_table(ACPI_SIG_DMAR, 0,
 443                                 (struct acpi_table_header **)&dmar_tbl);
 444
 445         if (ACPI_SUCCESS(status) && !dmar_tbl) {
 446                 printk (KERN_WARNING PREFIX "Unable to map DMAR\n");
 447                 status = AE_NOT_FOUND;
 448         }
 449
 450         return (ACPI_SUCCESS(status) ? 1 : 0);
 451 }
 452
 453 void __init detect_intel_iommu(void)
 454 {
 455         int ret;
 456
 457         ret = early_dmar_detect();
 458
 459         {
 460 #ifdef CONFIG_INTR_REMAP
 461                 struct acpi_table_dmar *dmar;
 462                 /*
 463                  * for now we will disable dma-remapping when interrupt
 464                  * remapping is enabled.
 465                  * When support for queued invalidation for IOTLB invalidation
 466                  * is added, we will not need this any more.
 467                  */
 468                 dmar = (struct acpi_table_dmar *) dmar_tbl;
 469                 if (ret && cpu_has_x2apic && dmar->flags & 0x1)
 470                         printk(KERN_INFO
 471                                "Queued invalidation will be enabled to support "
 472                                "x2apic and Intr-remapping.\n");
 473 #endif
 474
 475 #ifdef CONFIG_DMAR
 476                 if (ret && !no_iommu && !iommu_detected && !swiotlb &&
 477                     !dmar_disabled)
 478                         iommu_detected = 1;
 479 #endif
 480         }
 481 }
 482
 483
 484 int alloc_iommu(struct dmar_drhd_unit *drhd)
 485 {
 486         struct intel_iommu *iommu;
 487         int map_size;
 488         u32 ver;
 489         static int iommu_allocated = 0;
 490
 491         iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
 492         if (!iommu)
 493                 return -ENOMEM;
 494
 495         iommu->seq_id = iommu_allocated++;
 496
 497         iommu->reg = ioremap(drhd->reg_base_addr, VTD_PAGE_SIZE);
 498         if (!iommu->reg) {
 499                 printk(KERN_ERR "IOMMU: can't map the region\n");
 500                 goto error;
 501         }
 502         iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
 503         iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
 504
 505         /* the registers might be more than one page */
 506         map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
 507                 cap_max_fault_reg_offset(iommu->cap));
 508         map_size = VTD_PAGE_ALIGN(map_size);
 509         if (map_size > VTD_PAGE_SIZE) {
 510                 iounmap(iommu->reg);
 511                 iommu->reg = ioremap(drhd->reg_base_addr, map_size);
 512                 if (!iommu->reg) {
 513                         printk(KERN_ERR "IOMMU: can't map the region\n");
 514                         goto error;
 515                 }
 516         }
 517
 518         ver = readl(iommu->reg + DMAR_VER_REG);
 519         pr_debug("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n",
 520                 (unsigned long long)drhd->reg_base_addr,
 521                 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
 522                 (unsigned long long)iommu->cap,
 523                 (unsigned long long)iommu->ecap);
 524
 525         spin_lock_init(&iommu->register_lock);
 526
 527         drhd->iommu = iommu;
 528         return 0;
 529 error:
 530         kfree(iommu);
 531         return -1;
 532 }
 533
 534 void free_iommu(struct intel_iommu *iommu)
 535 {
 536         if (!iommu)
 537                 return;
 538
 539 #ifdef CONFIG_DMAR
 540         free_dmar_iommu(iommu);
 541 #endif
 542
 543         if (iommu->reg)
 544                 iounmap(iommu->reg);
 545         kfree(iommu);
 546 }
 547
 548 /*
 549  * Reclaim all the submitted descriptors which have completed its work.
 550  */
 551 static inline void reclaim_free_desc(struct q_inval *qi)
 552 {
 553         while (qi->desc_status[qi->free_tail] == QI_DONE) {
 554                 qi->desc_status[qi->free_tail] = QI_FREE;
 555                 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
 556                 qi->free_cnt++;
 557         }
 558 }
 559
 560 /*
 561  * Submit the queued invalidation descriptor to the remapping
 562  * hardware unit and wait for its completion.
 563  */
 564 void qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
 565 {
 566         struct q_inval *qi = iommu->qi;
 567         struct qi_desc *hw, wait_desc;
 568         int wait_index, index;
 569         unsigned long flags;
 570
 571         if (!qi)
 572                 return;
 573
 574         hw = qi->desc;
 575
 576         spin_lock_irqsave(&qi->q_lock, flags);
 577         while (qi->free_cnt < 3) {
 578                 spin_unlock_irqrestore(&qi->q_lock, flags);
 579                 cpu_relax();
 580                 spin_lock_irqsave(&qi->q_lock, flags);
 581         }
 582
 583         index = qi->free_head;
 584         wait_index = (index + 1) % QI_LENGTH;
 585
 586         qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE;
 587
 588         hw[index] = *desc;
 589
 590         wait_desc.low = QI_IWD_STATUS_DATA(2) | QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
 591         wait_desc.high = virt_to_phys(&qi->desc_status[wait_index]);
 592
 593         hw[wait_index] = wait_desc;
 594
 595         __iommu_flush_cache(iommu, &hw[index], sizeof(struct qi_desc));
 596         __iommu_flush_cache(iommu, &hw[wait_index], sizeof(struct qi_desc));
 597
 598         qi->free_head = (qi->free_head + 2) % QI_LENGTH;
 599         qi->free_cnt -= 2;
 600
 601         spin_lock(&iommu->register_lock);
 602         /*
 603          * update the HW tail register indicating the presence of
 604          * new descriptors.
 605          */
 606         writel(qi->free_head << 4, iommu->reg + DMAR_IQT_REG);
 607         spin_unlock(&iommu->register_lock);
 608
 609         while (qi->desc_status[wait_index] != QI_DONE) {
 610                 /*
 611                  * We will leave the interrupts disabled, to prevent interrupt
 612                  * context to queue another cmd while a cmd is already submitted
 613                  * and waiting for completion on this cpu. This is to avoid
 614                  * a deadlock where the interrupt context can wait indefinitely
 615                  * for free slots in the queue.
 616                  */
 617                 spin_unlock(&qi->q_lock);
 618                 cpu_relax();
 619                 spin_lock(&qi->q_lock);
 620         }
 621
 622         qi->desc_status[index] = QI_DONE;
 623
 624         reclaim_free_desc(qi);
 625         spin_unlock_irqrestore(&qi->q_lock, flags);
 626 }
 627
 628 /*
 629  * Flush the global interrupt entry cache.
 630  */
 631 void qi_global_iec(struct intel_iommu *iommu)
 632 {
 633         struct qi_desc desc;
 634
 635         desc.low = QI_IEC_TYPE;
 636         desc.high = 0;
 637
 638         qi_submit_sync(&desc, iommu);
 639 }
 640
 641 int qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
 642                      u64 type, int non_present_entry_flush)
 643 {
 644
 645         struct qi_desc desc;
 646
 647         if (non_present_entry_flush) {
 648                 if (!cap_caching_mode(iommu->cap))
 649                         return 1;
 650                 else
 651                         did = 0;
 652         }
 653
 654         desc.low = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
 655                         | QI_CC_GRAN(type) | QI_CC_TYPE;
 656         desc.high = 0;
 657
 658         qi_submit_sync(&desc, iommu);
 659
 660         return 0;
 661
 662 }
 663
 664 int qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
 665                    unsigned int size_order, u64 type,
 666                    int non_present_entry_flush)
 667 {
 668         u8 dw = 0, dr = 0;
 669
 670         struct qi_desc desc;
 671         int ih = 0;
 672
 673         if (non_present_entry_flush) {
 674                 if (!cap_caching_mode(iommu->cap))
 675                         return 1;
 676                 else
 677                         did = 0;
 678         }
 679
 680         if (cap_write_drain(iommu->cap))
 681                 dw = 1;
 682
 683         if (cap_read_drain(iommu->cap))
 684                 dr = 1;
 685
 686         desc.low = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
 687                 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
 688         desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
 689                 | QI_IOTLB_AM(size_order);
 690
 691         qi_submit_sync(&desc, iommu);
 692
 693         return 0;
 694
 695 }
 696
 697 /*
 698  * Enable Queued Invalidation interface. This is a must to support
 699  * interrupt-remapping. Also used by DMA-remapping, which replaces
 700  * register based IOTLB invalidation.
 701  */
 702 int dmar_enable_qi(struct intel_iommu *iommu)
 703 {
 704         u32 cmd, sts;
 705         unsigned long flags;
 706         struct q_inval *qi;
 707
 708         if (!ecap_qis(iommu->ecap))
 709                 return -ENOENT;
 710
 711         /*
 712          * queued invalidation is already setup and enabled.
 713          */
 714         if (iommu->qi)
 715                 return 0;
 716
 717         iommu->qi = kmalloc(sizeof(*qi), GFP_KERNEL);
 718         if (!iommu->qi)
 719                 return -ENOMEM;
 720
 721         qi = iommu->qi;
 722
 723         qi->desc = (void *)(get_zeroed_page(GFP_KERNEL));
 724         if (!qi->desc) {
 725                 kfree(qi);
 726                 iommu->qi = 0;
 727                 return -ENOMEM;
 728         }
 729
 730         qi->desc_status = kmalloc(QI_LENGTH * sizeof(int), GFP_KERNEL);
 731         if (!qi->desc_status) {
 732                 free_page((unsigned long) qi->desc);
 733                 kfree(qi);
 734                 iommu->qi = 0;
 735                 return -ENOMEM;
 736         }
 737
 738         qi->free_head = qi->free_tail = 0;
 739         qi->free_cnt = QI_LENGTH;
 740
 741         spin_lock_init(&qi->q_lock);
 742
 743         spin_lock_irqsave(&iommu->register_lock, flags);
 744         /* write zero to the tail reg */
 745         writel(0, iommu->reg + DMAR_IQT_REG);
 746
 747         dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc));
 748
 749         cmd = iommu->gcmd | DMA_GCMD_QIE;
 750         iommu->gcmd |= DMA_GCMD_QIE;
 751         writel(cmd, iommu->reg + DMAR_GCMD_REG);
 752
 753         /* Make sure hardware complete it */
 754         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
 755         spin_unlock_irqrestore(&iommu->register_lock, flags);
 756
 757         return 0;
 758 }