1 /* Low-level parallel-port routines for 8255-based PC-style hardware.
3 * Authors: Phil Blundell <philb@gnu.org>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
19 /* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
28 * In addition, there are some optional registers:
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
45 #include <linux/module.h>
46 #include <linux/init.h>
47 #include <linux/sched.h>
48 #include <linux/delay.h>
49 #include <linux/errno.h>
50 #include <linux/interrupt.h>
51 #include <linux/ioport.h>
52 #include <linux/kernel.h>
53 #include <linux/slab.h>
54 #include <linux/dma-mapping.h>
55 #include <linux/pci.h>
56 #include <linux/pnp.h>
57 #include <linux/platform_device.h>
58 #include <linux/sysctl.h>
62 #include <asm/uaccess.h>
64 #include <linux/parport.h>
65 #include <linux/parport_pc.h>
66 #include <linux/via.h>
67 #include <asm/parport.h>
69 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
71 #ifdef CONFIG_ISA_DMA_API
84 #define ECR_MODE_MASK 0xe0
85 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v))
90 #define DPRINTK printk
92 #define DPRINTK(stuff...)
97 static struct superio_struct { /* For Super-IO chips autodetection */
101 } superios[NR_SUPERIOS] = { {0,},};
103 static int user_specified;
104 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
105 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
106 static int verbose_probing;
108 static int pci_registered_parport;
109 static int pnp_registered_parport;
111 /* frob_control, but for ECR */
112 static void frob_econtrol (struct parport *pb, unsigned char m,
115 unsigned char ectr = 0;
118 ectr = inb (ECONTROL (pb));
120 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
121 m, v, ectr, (ectr & ~m) ^ v);
123 outb ((ectr & ~m) ^ v, ECONTROL (pb));
126 static __inline__ void frob_set_mode (struct parport *p, int mode)
128 frob_econtrol (p, ECR_MODE_MASK, mode << 5);
131 #ifdef CONFIG_PARPORT_PC_FIFO
132 /* Safely change the mode bits in the ECR
135 -EBUSY: Could not drain FIFO in some finite amount of time,
138 static int change_mode(struct parport *p, int m)
140 const struct parport_pc_private *priv = p->physport->private_data;
144 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m);
147 printk (KERN_DEBUG "change_mode: but there's no ECR!\n");
151 /* Bits <7:5> contain the mode. */
152 oecr = inb (ECONTROL (p));
153 mode = (oecr >> 5) & 0x7;
154 if (mode == m) return 0;
156 if (mode >= 2 && !(priv->ctr & 0x20)) {
157 /* This mode resets the FIFO, so we may
158 * have to wait for it to drain first. */
159 unsigned long expire = jiffies + p->physport->cad->timeout;
162 case ECR_PPF: /* Parallel Port FIFO mode */
163 case ECR_ECP: /* ECP Parallel Port mode */
164 /* Busy wait for 200us */
165 for (counter = 0; counter < 40; counter++) {
166 if (inb (ECONTROL (p)) & 0x01)
168 if (signal_pending (current)) break;
173 while (!(inb (ECONTROL (p)) & 0x01)) {
174 if (time_after_eq (jiffies, expire))
175 /* The FIFO is stuck. */
177 schedule_timeout_interruptible(msecs_to_jiffies(10));
178 if (signal_pending (current))
184 if (mode >= 2 && m >= 2) {
185 /* We have to go through mode 001 */
187 oecr |= ECR_PS2 << 5;
198 #ifdef CONFIG_PARPORT_1284
199 /* Find FIFO lossage; FIFO is reset */
201 static int get_fifo_residue (struct parport *p)
205 const struct parport_pc_private *priv = p->physport->private_data;
207 /* Adjust for the contents of the FIFO. */
208 for (residue = priv->fifo_depth; ; residue--) {
209 if (inb (ECONTROL (p)) & 0x2)
216 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
219 /* Reset the FIFO. */
220 frob_set_mode (p, ECR_PS2);
222 /* Now change to config mode and clean up. FIXME */
223 frob_set_mode (p, ECR_CNF);
224 cnfga = inb (CONFIGA (p));
225 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
227 if (!(cnfga & (1<<2))) {
228 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
232 /* Don't care about partial PWords until support is added for
233 * PWord != 1 byte. */
235 /* Back to PS2 mode. */
236 frob_set_mode (p, ECR_PS2);
238 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p)));
242 #endif /* IEEE 1284 support */
243 #endif /* FIFO support */
246 * Clear TIMEOUT BIT in EPP MODE
248 * This is also used in SPP detection.
250 static int clear_epp_timeout(struct parport *pb)
254 if (!(parport_pc_read_status(pb) & 0x01))
257 /* To clear timeout some chips require double read */
258 parport_pc_read_status(pb);
259 r = parport_pc_read_status(pb);
260 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
261 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
262 r = parport_pc_read_status(pb);
270 * Most of these aren't static because they may be used by the
271 * parport_xxx_yyy macros. extern __inline__ versions of several
272 * of these are in parport_pc.h.
275 static void parport_pc_init_state(struct pardevice *dev, struct parport_state *s)
279 dev->port->irq != PARPORT_IRQ_NONE)
283 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
287 static void parport_pc_save_state(struct parport *p, struct parport_state *s)
289 const struct parport_pc_private *priv = p->physport->private_data;
290 s->u.pc.ctr = priv->ctr;
292 s->u.pc.ecr = inb (ECONTROL (p));
295 static void parport_pc_restore_state(struct parport *p, struct parport_state *s)
297 struct parport_pc_private *priv = p->physport->private_data;
298 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
299 outb (c, CONTROL (p));
302 ECR_WRITE (p, s->u.pc.ecr);
305 #ifdef CONFIG_PARPORT_1284
306 static size_t parport_pc_epp_read_data (struct parport *port, void *buf,
307 size_t length, int flags)
311 if (flags & PARPORT_W91284PIC) {
312 unsigned char status;
313 size_t left = length;
315 /* use knowledge about data lines..:
316 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
317 * pError is 1 if there are 16 bytes in the Warp's FIFO
319 status = inb (STATUS (port));
321 while (!(status & 0x08) && (got < length)) {
322 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) {
323 /* can grab 16 bytes from warp fifo */
324 if (!((long)buf & 0x03)) {
325 insl (EPPDATA (port), buf, 4);
327 insb (EPPDATA (port), buf, 16);
333 /* grab single byte from the warp fifo */
334 *((char *)buf) = inb (EPPDATA (port));
339 status = inb (STATUS (port));
341 /* EPP timeout should never occur... */
342 printk (KERN_DEBUG "%s: EPP timeout occurred while talking to "
343 "w91284pic (should not have done)\n", port->name);
344 clear_epp_timeout (port);
349 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
350 if (!(((long)buf | length) & 0x03)) {
351 insl (EPPDATA (port), buf, (length >> 2));
353 insb (EPPDATA (port), buf, length);
355 if (inb (STATUS (port)) & 0x01) {
356 clear_epp_timeout (port);
361 for (; got < length; got++) {
362 *((char*)buf) = inb (EPPDATA(port));
364 if (inb (STATUS (port)) & 0x01) {
366 clear_epp_timeout (port);
374 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf,
375 size_t length, int flags)
379 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
380 if (!(((long)buf | length) & 0x03)) {
381 outsl (EPPDATA (port), buf, (length >> 2));
383 outsb (EPPDATA (port), buf, length);
385 if (inb (STATUS (port)) & 0x01) {
386 clear_epp_timeout (port);
391 for (; written < length; written++) {
392 outb (*((char*)buf), EPPDATA(port));
394 if (inb (STATUS(port)) & 0x01) {
395 clear_epp_timeout (port);
403 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf,
404 size_t length, int flags)
408 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
409 insb (EPPADDR (port), buf, length);
410 if (inb (STATUS (port)) & 0x01) {
411 clear_epp_timeout (port);
416 for (; got < length; got++) {
417 *((char*)buf) = inb (EPPADDR (port));
419 if (inb (STATUS (port)) & 0x01) {
420 clear_epp_timeout (port);
428 static size_t parport_pc_epp_write_addr (struct parport *port,
429 const void *buf, size_t length,
434 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
435 outsb (EPPADDR (port), buf, length);
436 if (inb (STATUS (port)) & 0x01) {
437 clear_epp_timeout (port);
442 for (; written < length; written++) {
443 outb (*((char*)buf), EPPADDR (port));
445 if (inb (STATUS (port)) & 0x01) {
446 clear_epp_timeout (port);
454 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf,
455 size_t length, int flags)
459 frob_set_mode (port, ECR_EPP);
460 parport_pc_data_reverse (port);
461 parport_pc_write_control (port, 0x4);
462 got = parport_pc_epp_read_data (port, buf, length, flags);
463 frob_set_mode (port, ECR_PS2);
468 static size_t parport_pc_ecpepp_write_data (struct parport *port,
469 const void *buf, size_t length,
474 frob_set_mode (port, ECR_EPP);
475 parport_pc_write_control (port, 0x4);
476 parport_pc_data_forward (port);
477 written = parport_pc_epp_write_data (port, buf, length, flags);
478 frob_set_mode (port, ECR_PS2);
483 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf,
484 size_t length, int flags)
488 frob_set_mode (port, ECR_EPP);
489 parport_pc_data_reverse (port);
490 parport_pc_write_control (port, 0x4);
491 got = parport_pc_epp_read_addr (port, buf, length, flags);
492 frob_set_mode (port, ECR_PS2);
497 static size_t parport_pc_ecpepp_write_addr (struct parport *port,
498 const void *buf, size_t length,
503 frob_set_mode (port, ECR_EPP);
504 parport_pc_write_control (port, 0x4);
505 parport_pc_data_forward (port);
506 written = parport_pc_epp_write_addr (port, buf, length, flags);
507 frob_set_mode (port, ECR_PS2);
511 #endif /* IEEE 1284 support */
513 #ifdef CONFIG_PARPORT_PC_FIFO
514 static size_t parport_pc_fifo_write_block_pio (struct parport *port,
515 const void *buf, size_t length)
518 const unsigned char *bufp = buf;
519 size_t left = length;
520 unsigned long expire = jiffies + port->physport->cad->timeout;
521 const int fifo = FIFO (port);
522 int poll_for = 8; /* 80 usecs */
523 const struct parport_pc_private *priv = port->physport->private_data;
524 const int fifo_depth = priv->fifo_depth;
526 port = port->physport;
528 /* We don't want to be interrupted every character. */
529 parport_pc_disable_irq (port);
530 /* set nErrIntrEn and serviceIntr */
531 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
534 parport_pc_data_forward (port); /* Must be in PS2 mode */
538 unsigned char ecrval = inb (ECONTROL (port));
541 if (need_resched() && time_before (jiffies, expire))
542 /* Can't yield the port. */
545 /* Anyone else waiting for the port? */
546 if (port->waithead) {
547 printk (KERN_DEBUG "Somebody wants the port\n");
552 /* FIFO is full. Wait for interrupt. */
554 /* Clear serviceIntr */
555 ECR_WRITE (port, ecrval & ~(1<<2));
557 ret = parport_wait_event (port, HZ);
560 if (!time_before (jiffies, expire)) {
562 printk (KERN_DEBUG "FIFO write timed out\n");
565 ecrval = inb (ECONTROL (port));
566 if (!(ecrval & (1<<2))) {
567 if (need_resched() &&
568 time_before (jiffies, expire))
577 /* Can't fail now. */
578 expire = jiffies + port->cad->timeout;
581 if (signal_pending (current))
585 /* FIFO is empty. Blast it full. */
586 const int n = left < fifo_depth ? left : fifo_depth;
587 outsb (fifo, bufp, n);
591 /* Adjust the poll time. */
592 if (i < (poll_for - 2)) poll_for--;
594 } else if (i++ < poll_for) {
596 ecrval = inb (ECONTROL (port));
600 /* Half-full (call me an optimist) */
606 dump_parport_state ("leave fifo_write_block_pio", port);
607 return length - left;
611 static size_t parport_pc_fifo_write_block_dma (struct parport *port,
612 const void *buf, size_t length)
615 unsigned long dmaflag;
616 size_t left = length;
617 const struct parport_pc_private *priv = port->physport->private_data;
618 struct device *dev = port->physport->dev;
619 dma_addr_t dma_addr, dma_handle;
620 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
621 unsigned long start = (unsigned long) buf;
622 unsigned long end = (unsigned long) buf + length - 1;
624 dump_parport_state ("enter fifo_write_block_dma", port);
625 if (end < MAX_DMA_ADDRESS) {
626 /* If it would cross a 64k boundary, cap it at the end. */
627 if ((start ^ end) & ~0xffffUL)
628 maxlen = 0x10000 - (start & 0xffff);
630 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
633 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */
634 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
635 dma_addr = priv->dma_handle;
639 port = port->physport;
641 /* We don't want to be interrupted every character. */
642 parport_pc_disable_irq (port);
643 /* set nErrIntrEn and serviceIntr */
644 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
647 parport_pc_data_forward (port); /* Must be in PS2 mode */
650 unsigned long expire = jiffies + port->physport->cad->timeout;
657 if (!dma_handle) /* bounce buffer ! */
658 memcpy(priv->dma_buf, buf, count);
660 dmaflag = claim_dma_lock();
661 disable_dma(port->dma);
662 clear_dma_ff(port->dma);
663 set_dma_mode(port->dma, DMA_MODE_WRITE);
664 set_dma_addr(port->dma, dma_addr);
665 set_dma_count(port->dma, count);
668 frob_econtrol (port, 1<<3, 1<<3);
670 /* Clear serviceIntr */
671 frob_econtrol (port, 1<<2, 0);
673 enable_dma(port->dma);
674 release_dma_lock(dmaflag);
676 /* assume DMA will be successful */
679 if (dma_handle) dma_addr += count;
681 /* Wait for interrupt. */
683 ret = parport_wait_event (port, HZ);
686 if (!time_before (jiffies, expire)) {
688 printk (KERN_DEBUG "DMA write timed out\n");
691 /* Is serviceIntr set? */
692 if (!(inb (ECONTROL (port)) & (1<<2))) {
698 dmaflag = claim_dma_lock();
699 disable_dma(port->dma);
700 clear_dma_ff(port->dma);
701 count = get_dma_residue(port->dma);
702 release_dma_lock(dmaflag);
704 cond_resched(); /* Can't yield the port. */
706 /* Anyone else waiting for the port? */
707 if (port->waithead) {
708 printk (KERN_DEBUG "Somebody wants the port\n");
712 /* update for possible DMA residue ! */
715 if (dma_handle) dma_addr -= count;
718 /* Maybe got here through break, so adjust for DMA residue! */
719 dmaflag = claim_dma_lock();
720 disable_dma(port->dma);
721 clear_dma_ff(port->dma);
722 left += get_dma_residue(port->dma);
723 release_dma_lock(dmaflag);
725 /* Turn off DMA mode */
726 frob_econtrol (port, 1<<3, 0);
729 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
731 dump_parport_state ("leave fifo_write_block_dma", port);
732 return length - left;
736 static inline size_t parport_pc_fifo_write_block(struct parport *port,
737 const void *buf, size_t length)
740 if (port->dma != PARPORT_DMA_NONE)
741 return parport_pc_fifo_write_block_dma (port, buf, length);
743 return parport_pc_fifo_write_block_pio (port, buf, length);
746 /* Parallel Port FIFO mode (ECP chipsets) */
747 static size_t parport_pc_compat_write_block_pio (struct parport *port,
748 const void *buf, size_t length,
753 unsigned long expire;
754 const struct parport_pc_private *priv = port->physport->private_data;
756 /* Special case: a timeout of zero means we cannot call schedule().
757 * Also if O_NONBLOCK is set then use the default implementation. */
758 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
759 return parport_ieee1284_write_compat (port, buf,
762 /* Set up parallel port FIFO mode.*/
763 parport_pc_data_forward (port); /* Must be in PS2 mode */
764 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0);
765 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */
766 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name);
768 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
770 /* Write the data to the FIFO. */
771 written = parport_pc_fifo_write_block(port, buf, length);
774 /* For some hardware we don't want to touch the mode until
775 * the FIFO is empty, so allow 4 seconds for each position
778 expire = jiffies + (priv->fifo_depth * HZ * 4);
780 /* Wait for the FIFO to empty */
781 r = change_mode (port, ECR_PS2);
785 } while (time_before (jiffies, expire));
788 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
790 /* Prevent further data transfer. */
791 frob_set_mode (port, ECR_TST);
793 /* Adjust for the contents of the FIFO. */
794 for (written -= priv->fifo_depth; ; written++) {
795 if (inb (ECONTROL (port)) & 0x2) {
799 outb (0, FIFO (port));
802 /* Reset the FIFO and return to PS2 mode. */
803 frob_set_mode (port, ECR_PS2);
806 r = parport_wait_peripheral (port,
808 PARPORT_STATUS_BUSY);
811 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
814 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
820 #ifdef CONFIG_PARPORT_1284
821 static size_t parport_pc_ecp_write_block_pio (struct parport *port,
822 const void *buf, size_t length,
827 unsigned long expire;
828 const struct parport_pc_private *priv = port->physport->private_data;
830 /* Special case: a timeout of zero means we cannot call schedule().
831 * Also if O_NONBLOCK is set then use the default implementation. */
832 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
833 return parport_ieee1284_ecp_write_data (port, buf,
836 /* Switch to forward mode if necessary. */
837 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
838 /* Event 47: Set nInit high. */
839 parport_frob_control (port,
841 | PARPORT_CONTROL_AUTOFD,
843 | PARPORT_CONTROL_AUTOFD);
845 /* Event 49: PError goes high. */
846 r = parport_wait_peripheral (port,
847 PARPORT_STATUS_PAPEROUT,
848 PARPORT_STATUS_PAPEROUT);
850 printk (KERN_DEBUG "%s: PError timeout (%d) "
851 "in ecp_write_block_pio\n", port->name, r);
855 /* Set up ECP parallel port mode.*/
856 parport_pc_data_forward (port); /* Must be in PS2 mode */
857 parport_pc_frob_control (port,
858 PARPORT_CONTROL_STROBE |
859 PARPORT_CONTROL_AUTOFD,
861 r = change_mode (port, ECR_ECP); /* ECP FIFO */
862 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
863 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
865 /* Write the data to the FIFO. */
866 written = parport_pc_fifo_write_block(port, buf, length);
869 /* For some hardware we don't want to touch the mode until
870 * the FIFO is empty, so allow 4 seconds for each position
873 expire = jiffies + (priv->fifo_depth * (HZ * 4));
875 /* Wait for the FIFO to empty */
876 r = change_mode (port, ECR_PS2);
880 } while (time_before (jiffies, expire));
883 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
885 /* Prevent further data transfer. */
886 frob_set_mode (port, ECR_TST);
888 /* Adjust for the contents of the FIFO. */
889 for (written -= priv->fifo_depth; ; written++) {
890 if (inb (ECONTROL (port)) & 0x2) {
894 outb (0, FIFO (port));
897 /* Reset the FIFO and return to PS2 mode. */
898 frob_set_mode (port, ECR_PS2);
900 /* Host transfer recovery. */
901 parport_pc_data_reverse (port); /* Must be in PS2 mode */
903 parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
904 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
906 printk (KERN_DEBUG "%s: PE,1 timeout (%d) "
907 "in ecp_write_block_pio\n", port->name, r);
909 parport_frob_control (port,
910 PARPORT_CONTROL_INIT,
911 PARPORT_CONTROL_INIT);
912 r = parport_wait_peripheral (port,
913 PARPORT_STATUS_PAPEROUT,
914 PARPORT_STATUS_PAPEROUT);
916 printk (KERN_DEBUG "%s: PE,2 timeout (%d) "
917 "in ecp_write_block_pio\n", port->name, r);
920 r = parport_wait_peripheral (port,
922 PARPORT_STATUS_BUSY);
925 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
928 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
934 static size_t parport_pc_ecp_read_block_pio (struct parport *port,
935 void *buf, size_t length,
938 size_t left = length;
941 const int fifo = FIFO(port);
942 const struct parport_pc_private *priv = port->physport->private_data;
943 const int fifo_depth = priv->fifo_depth;
946 port = port->physport;
947 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
948 dump_parport_state ("enter fcn", port);
950 /* Special case: a timeout of zero means we cannot call schedule().
951 * Also if O_NONBLOCK is set then use the default implementation. */
952 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
953 return parport_ieee1284_ecp_read_data (port, buf,
956 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
957 /* If the peripheral is allowed to send RLE compressed
958 * data, it is possible for a byte to expand to 128
959 * bytes in the FIFO. */
962 fifofull = fifo_depth;
965 /* If the caller wants less than a full FIFO's worth of data,
966 * go through software emulation. Otherwise we may have to throw
968 if (length < fifofull)
969 return parport_ieee1284_ecp_read_data (port, buf,
972 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
973 /* change to reverse-idle phase (must be in forward-idle) */
975 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
976 parport_frob_control (port,
977 PARPORT_CONTROL_AUTOFD
978 | PARPORT_CONTROL_STROBE,
979 PARPORT_CONTROL_AUTOFD);
980 parport_pc_data_reverse (port); /* Must be in PS2 mode */
982 /* Event 39: Set nInit low to initiate bus reversal */
983 parport_frob_control (port,
984 PARPORT_CONTROL_INIT,
986 /* Event 40: Wait for nAckReverse (PError) to go low */
987 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
989 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) "
990 "in ecp_read_block_pio\n", port->name, r);
995 /* Set up ECP FIFO mode.*/
996 /* parport_pc_frob_control (port,
997 PARPORT_CONTROL_STROBE |
998 PARPORT_CONTROL_AUTOFD,
999 PARPORT_CONTROL_AUTOFD); */
1000 r = change_mode (port, ECR_ECP); /* ECP FIFO */
1001 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
1003 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
1005 /* the first byte must be collected manually */
1006 dump_parport_state ("pre 43", port);
1007 /* Event 43: Wait for nAck to go low */
1008 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0);
1010 /* timed out while reading -- no data */
1011 printk (KERN_DEBUG "PIO read timed out (initial byte)\n");
1015 *bufp++ = inb (DATA (port));
1017 dump_parport_state ("43-44", port);
1018 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1019 parport_pc_frob_control (port,
1020 PARPORT_CONTROL_AUTOFD,
1022 dump_parport_state ("pre 45", port);
1023 /* Event 45: Wait for nAck to go high */
1024 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */
1025 dump_parport_state ("post 45", port);
1028 /* timed out while waiting for peripheral to respond to ack */
1029 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
1031 /* keep hold of the byte we've got already */
1034 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1035 parport_pc_frob_control (port,
1036 PARPORT_CONTROL_AUTOFD,
1037 PARPORT_CONTROL_AUTOFD);
1040 dump_parport_state ("rev idle", port);
1041 /* Do the transfer. */
1042 while (left > fifofull) {
1044 unsigned long expire = jiffies + port->cad->timeout;
1045 unsigned char ecrval = inb (ECONTROL (port));
1047 if (need_resched() && time_before (jiffies, expire))
1048 /* Can't yield the port. */
1051 /* At this point, the FIFO may already be full. In
1052 * that case ECP is already holding back the
1053 * peripheral (assuming proper design) with a delayed
1054 * handshake. Work fast to avoid a peripheral
1057 if (ecrval & 0x01) {
1058 /* FIFO is empty. Wait for interrupt. */
1059 dump_parport_state ("FIFO empty", port);
1061 /* Anyone else waiting for the port? */
1062 if (port->waithead) {
1063 printk (KERN_DEBUG "Somebody wants the port\n");
1067 /* Clear serviceIntr */
1068 ECR_WRITE (port, ecrval & ~(1<<2));
1070 dump_parport_state ("waiting", port);
1071 ret = parport_wait_event (port, HZ);
1072 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret);
1076 if (!time_before (jiffies, expire)) {
1078 dump_parport_state ("timeout", port);
1079 printk (KERN_DEBUG "PIO read timed out\n");
1082 ecrval = inb (ECONTROL (port));
1083 if (!(ecrval & (1<<2))) {
1084 if (need_resched() &&
1085 time_before (jiffies, expire)) {
1091 /* Depending on how the FIFO threshold was
1092 * set, how long interrupt service took, and
1093 * how fast the peripheral is, we might be
1094 * lucky and have a just filled FIFO. */
1098 if (ecrval & 0x02) {
1100 dump_parport_state ("FIFO full", port);
1101 insb (fifo, bufp, fifo_depth);
1107 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n");
1109 /* FIFO not filled. We will cycle this loop for a while
1110 * and either the peripheral will fill it faster,
1111 * tripping a fast empty with insb, or we empty it. */
1112 *bufp++ = inb (fifo);
1116 /* scoop up anything left in the FIFO */
1117 while (left && !(inb (ECONTROL (port) & 0x01))) {
1118 *bufp++ = inb (fifo);
1122 port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
1123 dump_parport_state ("rev idle2", port);
1127 /* Go to forward idle mode to shut the peripheral up (event 47). */
1128 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
1130 /* event 49: PError goes high */
1131 r = parport_wait_peripheral (port,
1132 PARPORT_STATUS_PAPEROUT,
1133 PARPORT_STATUS_PAPEROUT);
1136 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1140 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1144 int lost = get_fifo_residue (port);
1146 /* Shouldn't happen with compliant peripherals. */
1147 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
1151 dump_parport_state ("fwd idle", port);
1152 return length - left;
1155 #endif /* IEEE 1284 support */
1156 #endif /* Allowed to use FIFO/DMA */
1160 * ******************************************
1161 * INITIALISATION AND MODULE STUFF BELOW HERE
1162 * ******************************************
1165 /* GCC is not inlining extern inline function later overwriten to non-inline,
1166 so we use outlined_ variants here. */
1167 static const struct parport_operations parport_pc_ops =
1169 .write_data = parport_pc_write_data,
1170 .read_data = parport_pc_read_data,
1172 .write_control = parport_pc_write_control,
1173 .read_control = parport_pc_read_control,
1174 .frob_control = parport_pc_frob_control,
1176 .read_status = parport_pc_read_status,
1178 .enable_irq = parport_pc_enable_irq,
1179 .disable_irq = parport_pc_disable_irq,
1181 .data_forward = parport_pc_data_forward,
1182 .data_reverse = parport_pc_data_reverse,
1184 .init_state = parport_pc_init_state,
1185 .save_state = parport_pc_save_state,
1186 .restore_state = parport_pc_restore_state,
1188 .epp_write_data = parport_ieee1284_epp_write_data,
1189 .epp_read_data = parport_ieee1284_epp_read_data,
1190 .epp_write_addr = parport_ieee1284_epp_write_addr,
1191 .epp_read_addr = parport_ieee1284_epp_read_addr,
1193 .ecp_write_data = parport_ieee1284_ecp_write_data,
1194 .ecp_read_data = parport_ieee1284_ecp_read_data,
1195 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1197 .compat_write_data = parport_ieee1284_write_compat,
1198 .nibble_read_data = parport_ieee1284_read_nibble,
1199 .byte_read_data = parport_ieee1284_read_byte,
1201 .owner = THIS_MODULE,
1204 #ifdef CONFIG_PARPORT_PC_SUPERIO
1205 /* Super-IO chipset detection, Winbond, SMSC */
1206 static void __devinit show_parconfig_smsc37c669(int io, int key)
1208 int cr1,cr4,cra,cr23,cr26,cr27,i=0;
1209 static const char *const modes[]={
1210 "SPP and Bidirectional (PS/2)",
1231 if (verbose_probing) {
1232 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1233 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1234 cr1,cr4,cra,cr23,cr26,cr27);
1236 /* The documentation calls DMA and IRQ-Lines by letters, so
1237 the board maker can/will wire them
1238 appropriately/randomly... G=reserved H=IDE-irq, */
1239 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, "
1240 "fifo threshold=%d\n", cr23*4,
1241 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-',
1242 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f);
1243 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1244 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no");
1245 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1246 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03],
1247 (cr4 & 0x40) ? "1.7" : "1.9");
1250 /* Heuristics ! BIOS setup for this mainboard device limits
1251 the choices to standard settings, i.e. io-address and IRQ
1252 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1253 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1254 if(cr23*4 >=0x100) { /* if active */
1255 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1258 printk(KERN_INFO "Super-IO: too many chips!\n");
1263 superios[i].io = 0x3bc;
1264 superios[i].irq = 7;
1267 superios[i].io = 0x378;
1268 superios[i].irq = 7;
1271 superios[i].io = 0x278;
1272 superios[i].irq = 5;
1275 if((d==1) || (d==3))
1278 superios[i].dma= PARPORT_DMA_NONE;
1284 static void __devinit show_parconfig_winbond(int io, int key)
1286 int cr30,cr60,cr61,cr70,cr74,crf0,i=0;
1287 static const char *const modes[] = {
1288 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1293 "EPP-1.7 and SPP", /* 5 */
1295 "ECP and EPP-1.7" };
1296 static char *const irqtypes[] = {
1297 "pulsed low, high-Z",
1300 /* The registers are called compatible-PnP because the
1301 register layout is modelled after ISA-PnP, the access
1302 method is just another ... */
1305 outb(0x07,io); /* Register 7: Select Logical Device */
1306 outb(0x01,io+1); /* LD1 is Parallel Port */
1321 if (verbose_probing) {
1322 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x "
1323 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0);
1324 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1325 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f );
1326 if ((cr74 & 0x07) > 3)
1327 printk("dma=none\n");
1329 printk("dma=%d\n",cr74 & 0x07);
1330 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1331 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1332 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]);
1335 if(cr30 & 0x01) { /* the settings can be interrogated later ... */
1336 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1339 printk(KERN_INFO "Super-IO: too many chips!\n");
1341 superios[i].io = (cr60<<8)|cr61;
1342 superios[i].irq = cr70&0x0f;
1343 superios[i].dma = (((cr74 & 0x07) > 3) ?
1344 PARPORT_DMA_NONE : (cr74 & 0x07));
1349 static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1351 const char *type = "unknown";
1354 if (devid == devrev)
1355 /* simple heuristics, we happened to read some
1356 non-winbond register */
1359 id=(devid<<8) | devrev;
1361 /* Values are from public data sheets pdf files, I can just
1362 confirm 83977TF is correct :-) */
1363 if (id == 0x9771) type="83977F/AF";
1364 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x";
1365 else if (id == 0x9774) type="83977ATF";
1366 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x";
1367 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x";
1368 else if ((id & ~0x0f) == 0x5210) type="83627";
1369 else if ((id & ~0x0f) == 0x6010) type="83697HF";
1370 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;}
1371 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;}
1372 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;}
1373 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;}
1376 if (verbose_probing)
1377 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1378 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1379 efer, key, devid, devrev, oldid, type);
1382 show_parconfig_winbond(efer,key);
1385 static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1387 const char *type = "unknown";
1388 void (*func)(int io, int key);
1391 if (devid == devrev)
1392 /* simple heuristics, we happened to read some
1393 non-smsc register */
1397 id=(devid<<8) | devrev;
1399 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;}
1400 else if (id==0x6582) type="37c665IR";
1401 else if (devid==0x65) type="37c665GT";
1402 else if (devid==0x66) type="37c666GT";
1404 if (verbose_probing)
1405 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1406 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1407 efer, key, devid, devrev, type);
1414 static void __devinit winbond_check(int io, int key)
1416 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1418 if (!request_region(io, 3, __func__))
1421 /* First probe without key */
1430 outb(key,io); /* Write Magic Sequence to EFER, extended
1431 funtion enable register */
1432 outb(0x20,io); /* Write EFIR, extended function index register */
1433 devid=inb(io+1); /* Read EFDR, extended function data register */
1438 outb(0xaa,io); /* Magic Seal */
1440 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1441 goto out; /* protection against false positives */
1443 decode_winbond(io,key,devid,devrev,oldid);
1445 release_region(io, 3);
1448 static void __devinit winbond_check2(int io,int key)
1450 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1452 if (!request_region(io, 3, __func__))
1455 /* First probe without the key */
1463 outb(key,io); /* Write Magic Byte to EFER, extended
1464 funtion enable register */
1465 outb(0x20,io+2); /* Write EFIR, extended function index register */
1466 devid=inb(io+2); /* Read EFDR, extended function data register */
1471 outb(0xaa,io); /* Magic Seal */
1473 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1474 goto out; /* protection against false positives */
1476 decode_winbond(io,key,devid,devrev,oldid);
1478 release_region(io, 3);
1481 static void __devinit smsc_check(int io, int key)
1483 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev;
1485 if (!request_region(io, 3, __func__))
1488 /* First probe without the key */
1499 outb(key,io); /* Write Magic Sequence to EFER, extended
1500 funtion enable register */
1501 outb(0x0d,io); /* Write EFIR, extended function index register */
1502 oldid=inb(io+1); /* Read EFDR, extended function data register */
1509 outb(0xaa,io); /* Magic Seal */
1511 if ((x_id == id) && (x_oldrev == oldrev) &&
1512 (x_oldid == oldid) && (x_rev == rev))
1513 goto out; /* protection against false positives */
1515 decode_smsc(io,key,oldid,oldrev);
1517 release_region(io, 3);
1521 static void __devinit detect_and_report_winbond (void)
1523 if (verbose_probing)
1524 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1525 winbond_check(0x3f0,0x87);
1526 winbond_check(0x370,0x87);
1527 winbond_check(0x2e ,0x87);
1528 winbond_check(0x4e ,0x87);
1529 winbond_check(0x3f0,0x86);
1530 winbond_check2(0x250,0x88);
1531 winbond_check2(0x250,0x89);
1534 static void __devinit detect_and_report_smsc (void)
1536 if (verbose_probing)
1537 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1538 smsc_check(0x3f0,0x55);
1539 smsc_check(0x370,0x55);
1540 smsc_check(0x3f0,0x44);
1541 smsc_check(0x370,0x44);
1544 static void __devinit detect_and_report_it87(void)
1548 if (verbose_probing)
1549 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1550 if (!request_region(0x2e, 1, __func__))
1557 dev = inb(0x2f) << 8;
1560 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1561 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1562 printk(KERN_INFO "IT%04X SuperIO detected.\n", dev);
1563 outb(0x07, 0x2E); /* Parallel Port */
1565 outb(0xF0, 0x2E); /* BOOT 0x80 off */
1569 outb(0x02, 0x2E); /* Lock */
1572 release_region(0x2e, 1);
1574 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1576 static int get_superio_dma (struct parport *p)
1579 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1582 return superios[i].dma;
1583 return PARPORT_DMA_NONE;
1586 static int get_superio_irq (struct parport *p)
1589 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1592 return superios[i].irq;
1593 return PARPORT_IRQ_NONE;
1597 /* --- Mode detection ------------------------------------- */
1600 * Checks for port existence, all ports support SPP MODE
1602 * 0 : No parallel port at this address
1603 * PARPORT_MODE_PCSPP : SPP port detected
1604 * (if the user specified an ioport himself,
1605 * this shall always be the case!)
1608 static int parport_SPP_supported(struct parport *pb)
1613 * first clear an eventually pending EPP timeout
1614 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1615 * that does not even respond to SPP cycles if an EPP
1616 * timeout is pending
1618 clear_epp_timeout(pb);
1620 /* Do a simple read-write test to make sure the port exists. */
1622 outb (w, CONTROL (pb));
1624 /* Is there a control register that we can read from? Some
1625 * ports don't allow reads, so read_control just returns a
1626 * software copy. Some ports _do_ allow reads, so bypass the
1627 * software copy here. In addition, some bits aren't
1629 r = inb (CONTROL (pb));
1630 if ((r & 0xf) == w) {
1632 outb (w, CONTROL (pb));
1633 r = inb (CONTROL (pb));
1634 outb (0xc, CONTROL (pb));
1636 return PARPORT_MODE_PCSPP;
1640 /* That didn't work, but the user thinks there's a
1642 printk (KERN_INFO "parport 0x%lx (WARNING): CTR: "
1643 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1645 /* Try the data register. The data lines aren't tri-stated at
1646 * this stage, so we expect back what we wrote. */
1648 parport_pc_write_data (pb, w);
1649 r = parport_pc_read_data (pb);
1652 parport_pc_write_data (pb, w);
1653 r = parport_pc_read_data (pb);
1655 return PARPORT_MODE_PCSPP;
1658 if (user_specified) {
1659 /* Didn't work, but the user is convinced this is the
1661 printk (KERN_INFO "parport 0x%lx (WARNING): DATA: "
1662 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1663 printk (KERN_INFO "parport 0x%lx: You gave this address, "
1664 "but there is probably no parallel port there!\n",
1668 /* It's possible that we can't read the control register or
1669 * the data register. In that case just believe the user. */
1671 return PARPORT_MODE_PCSPP;
1678 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1679 * on these cards actually accesses the CTR.
1681 * Modern cards don't do this but reading from ECR will return 0xff
1682 * regardless of what is written here if the card does NOT support
1685 * We first check to see if ECR is the same as CTR. If not, the low
1686 * two bits of ECR aren't writable, so we check by writing ECR and
1687 * reading it back to see if it's what we expect.
1689 static int parport_ECR_present(struct parport *pb)
1691 struct parport_pc_private *priv = pb->private_data;
1692 unsigned char r = 0xc;
1694 outb (r, CONTROL (pb));
1695 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) {
1696 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
1698 r = inb (CONTROL (pb));
1699 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2))
1700 goto no_reg; /* Sure that no ECR register exists */
1703 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1)
1706 ECR_WRITE (pb, 0x34);
1707 if (inb (ECONTROL (pb)) != 0x35)
1711 outb (0xc, CONTROL (pb));
1713 /* Go to mode 000 */
1714 frob_set_mode (pb, ECR_SPP);
1719 outb (0xc, CONTROL (pb));
1723 #ifdef CONFIG_PARPORT_1284
1724 /* Detect PS/2 support.
1726 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1727 * allows us to read data from the data lines. In theory we would get back
1728 * 0xff but any peripheral attached to the port may drag some or all of the
1729 * lines down to zero. So if we get back anything that isn't the contents
1730 * of the data register we deem PS/2 support to be present.
1732 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1733 * drivers, but an external peripheral with sufficiently beefy drivers of
1734 * its own can overpower them and assert its own levels onto the bus, from
1735 * where they can then be read back as normal. Ports with this property
1736 * and the right type of device attached are likely to fail the SPP test,
1737 * (as they will appear to have stuck bits) and so the fact that they might
1738 * be misdetected here is rather academic.
1741 static int parport_PS2_supported(struct parport *pb)
1745 clear_epp_timeout(pb);
1747 /* try to tri-state the buffer */
1748 parport_pc_data_reverse (pb);
1750 parport_pc_write_data(pb, 0x55);
1751 if (parport_pc_read_data(pb) != 0x55) ok++;
1753 parport_pc_write_data(pb, 0xaa);
1754 if (parport_pc_read_data(pb) != 0xaa) ok++;
1756 /* cancel input mode */
1757 parport_pc_data_forward (pb);
1760 pb->modes |= PARPORT_MODE_TRISTATE;
1762 struct parport_pc_private *priv = pb->private_data;
1763 priv->ctr_writable &= ~0x20;
1769 #ifdef CONFIG_PARPORT_PC_FIFO
1770 static int parport_ECP_supported(struct parport *pb)
1773 int config, configb;
1775 struct parport_pc_private *priv = pb->private_data;
1776 /* Translate ECP intrLine to ISA irq value */
1777 static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 };
1779 /* If there is no ECR, we have no hope of supporting ECP. */
1783 /* Find out FIFO depth */
1784 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1785 ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */
1786 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++)
1787 outb (0xaa, FIFO (pb));
1790 * Using LGS chipset it uses ECR register, but
1791 * it doesn't support ECP or FIFO MODE
1794 ECR_WRITE (pb, ECR_SPP << 5);
1798 priv->fifo_depth = i;
1799 if (verbose_probing)
1800 printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1802 /* Find out writeIntrThreshold */
1803 frob_econtrol (pb, 1<<2, 1<<2);
1804 frob_econtrol (pb, 1<<2, 0);
1805 for (i = 1; i <= priv->fifo_depth; i++) {
1808 if (inb (ECONTROL (pb)) & (1<<2))
1812 if (i <= priv->fifo_depth) {
1813 if (verbose_probing)
1814 printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1817 /* Number of bytes we know we can write if we get an
1821 priv->writeIntrThreshold = i;
1823 /* Find out readIntrThreshold */
1824 frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1825 parport_pc_data_reverse (pb); /* Must be in PS2 mode */
1826 frob_set_mode (pb, ECR_TST); /* Test FIFO */
1827 frob_econtrol (pb, 1<<2, 1<<2);
1828 frob_econtrol (pb, 1<<2, 0);
1829 for (i = 1; i <= priv->fifo_depth; i++) {
1830 outb (0xaa, FIFO (pb));
1831 if (inb (ECONTROL (pb)) & (1<<2))
1835 if (i <= priv->fifo_depth) {
1836 if (verbose_probing)
1837 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1840 /* Number of bytes we can read if we get an interrupt. */
1843 priv->readIntrThreshold = i;
1845 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1846 ECR_WRITE (pb, 0xf4); /* Configuration mode */
1847 config = inb (CONFIGA (pb));
1848 pword = (config >> 4) & 0x7;
1852 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1857 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1861 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n",
1867 priv->pword = pword;
1869 if (verbose_probing) {
1870 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword);
1872 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1873 config & 0x80 ? "Level" : "Pulses");
1875 configb = inb (CONFIGB (pb));
1876 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1877 pb->base, config, configb);
1878 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1879 if ((configb >>3) & 0x07)
1880 printk("%d",intrline[(configb >>3) & 0x07]);
1882 printk("<none or set by other means>");
1884 if( (configb & 0x03 ) == 0x00)
1885 printk("<none or set by other means>\n");
1887 printk("%d\n",configb & 0x07);
1890 /* Go back to mode 000 */
1891 frob_set_mode (pb, ECR_SPP);
1897 static int parport_ECPPS2_supported(struct parport *pb)
1899 const struct parport_pc_private *priv = pb->private_data;
1906 oecr = inb (ECONTROL (pb));
1907 ECR_WRITE (pb, ECR_PS2 << 5);
1908 result = parport_PS2_supported(pb);
1909 ECR_WRITE (pb, oecr);
1913 /* EPP mode detection */
1915 static int parport_EPP_supported(struct parport *pb)
1917 const struct parport_pc_private *priv = pb->private_data;
1921 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1922 * when EPP is possible and is set high when an EPP timeout
1923 * occurs (EPP uses the HALT line to stop the CPU while it does
1924 * the byte transfer, an EPP timeout occurs if the attached
1925 * device fails to respond after 10 micro seconds).
1927 * This bit is cleared by either reading it (National Semi)
1928 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1929 * This bit is always high in non EPP modes.
1932 /* If EPP timeout bit clear then EPP available */
1933 if (!clear_epp_timeout(pb)) {
1934 return 0; /* No way to clear timeout */
1937 /* Check for Intel bug. */
1940 for (i = 0x00; i < 0x80; i += 0x20) {
1942 if (clear_epp_timeout (pb)) {
1943 /* Phony EPP in ECP. */
1949 pb->modes |= PARPORT_MODE_EPP;
1951 /* Set up access functions to use EPP hardware. */
1952 pb->ops->epp_read_data = parport_pc_epp_read_data;
1953 pb->ops->epp_write_data = parport_pc_epp_write_data;
1954 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1955 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1960 static int parport_ECPEPP_supported(struct parport *pb)
1962 struct parport_pc_private *priv = pb->private_data;
1970 oecr = inb (ECONTROL (pb));
1971 /* Search for SMC style EPP+ECP mode */
1972 ECR_WRITE (pb, 0x80);
1973 outb (0x04, CONTROL (pb));
1974 result = parport_EPP_supported(pb);
1976 ECR_WRITE (pb, oecr);
1979 /* Set up access functions to use ECP+EPP hardware. */
1980 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1981 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1982 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1983 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1989 #else /* No IEEE 1284 support */
1991 /* Don't bother probing for modes we know we won't use. */
1992 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
1993 #ifdef CONFIG_PARPORT_PC_FIFO
1994 static int parport_ECP_supported(struct parport *pb) { return 0; }
1996 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; }
1997 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;}
1998 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;}
2000 #endif /* No IEEE 1284 support */
2002 /* --- IRQ detection -------------------------------------- */
2004 /* Only if supports ECP mode */
2005 static int programmable_irq_support(struct parport *pb)
2008 unsigned char oecr = inb (ECONTROL (pb));
2009 static const int lookup[8] = {
2010 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
2013 ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */
2015 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07;
2016 irq = lookup[intrLine];
2018 ECR_WRITE (pb, oecr);
2022 static int irq_probe_ECP(struct parport *pb)
2027 irqs = probe_irq_on();
2029 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
2030 ECR_WRITE (pb, (ECR_TST << 5) | 0x04);
2031 ECR_WRITE (pb, ECR_TST << 5);
2033 /* If Full FIFO sure that writeIntrThreshold is generated */
2034 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++)
2035 outb (0xaa, FIFO (pb));
2037 pb->irq = probe_irq_off(irqs);
2038 ECR_WRITE (pb, ECR_SPP << 5);
2041 pb->irq = PARPORT_IRQ_NONE;
2047 * This detection seems that only works in National Semiconductors
2048 * This doesn't work in SMC, LGS, and Winbond
2050 static int irq_probe_EPP(struct parport *pb)
2052 #ifndef ADVANCED_DETECT
2053 return PARPORT_IRQ_NONE;
2058 if (pb->modes & PARPORT_MODE_PCECR)
2059 oecr = inb (ECONTROL (pb));
2061 irqs = probe_irq_on();
2063 if (pb->modes & PARPORT_MODE_PCECR)
2064 frob_econtrol (pb, 0x10, 0x10);
2066 clear_epp_timeout(pb);
2067 parport_pc_frob_control (pb, 0x20, 0x20);
2068 parport_pc_frob_control (pb, 0x10, 0x10);
2069 clear_epp_timeout(pb);
2071 /* Device isn't expecting an EPP read
2072 * and generates an IRQ.
2074 parport_pc_read_epp(pb);
2077 pb->irq = probe_irq_off (irqs);
2078 if (pb->modes & PARPORT_MODE_PCECR)
2079 ECR_WRITE (pb, oecr);
2080 parport_pc_write_control(pb, 0xc);
2083 pb->irq = PARPORT_IRQ_NONE;
2086 #endif /* Advanced detection */
2089 static int irq_probe_SPP(struct parport *pb)
2091 /* Don't even try to do this. */
2092 return PARPORT_IRQ_NONE;
2095 /* We will attempt to share interrupt requests since other devices
2096 * such as sound cards and network cards seem to like using the
2099 * When ECP is available we can autoprobe for IRQs.
2100 * NOTE: If we can autoprobe it, we can register the IRQ.
2102 static int parport_irq_probe(struct parport *pb)
2104 struct parport_pc_private *priv = pb->private_data;
2107 pb->irq = programmable_irq_support(pb);
2109 if (pb->irq == PARPORT_IRQ_NONE)
2110 pb->irq = irq_probe_ECP(pb);
2113 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
2114 (pb->modes & PARPORT_MODE_EPP))
2115 pb->irq = irq_probe_EPP(pb);
2117 clear_epp_timeout(pb);
2119 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
2120 pb->irq = irq_probe_EPP(pb);
2122 clear_epp_timeout(pb);
2124 if (pb->irq == PARPORT_IRQ_NONE)
2125 pb->irq = irq_probe_SPP(pb);
2127 if (pb->irq == PARPORT_IRQ_NONE)
2128 pb->irq = get_superio_irq(pb);
2133 /* --- DMA detection -------------------------------------- */
2135 /* Only if chipset conforms to ECP ISA Interface Standard */
2136 static int programmable_dma_support (struct parport *p)
2138 unsigned char oecr = inb (ECONTROL (p));
2141 frob_set_mode (p, ECR_CNF);
2143 dma = inb (CONFIGB(p)) & 0x07;
2144 /* 000: Indicates jumpered 8-bit DMA if read-only.
2145 100: Indicates jumpered 16-bit DMA if read-only. */
2146 if ((dma & 0x03) == 0)
2147 dma = PARPORT_DMA_NONE;
2149 ECR_WRITE (p, oecr);
2153 static int parport_dma_probe (struct parport *p)
2155 const struct parport_pc_private *priv = p->private_data;
2157 p->dma = programmable_dma_support(p); /* ask ECP chipset first */
2158 if (p->dma == PARPORT_DMA_NONE) {
2159 /* ask known Super-IO chips proper, although these
2160 claim ECP compatible, some don't report their DMA
2161 conforming to ECP standards */
2162 p->dma = get_superio_dma(p);
2168 /* --- Initialisation code -------------------------------- */
2170 static LIST_HEAD(ports_list);
2171 static DEFINE_SPINLOCK(ports_lock);
2173 struct parport *parport_pc_probe_port (unsigned long int base,
2174 unsigned long int base_hi,
2178 struct parport_pc_private *priv;
2179 struct parport_operations *ops;
2181 int probedirq = PARPORT_IRQ_NONE;
2182 struct resource *base_res;
2183 struct resource *ECR_res = NULL;
2184 struct resource *EPP_res = NULL;
2185 struct platform_device *pdev = NULL;
2188 /* We need a physical device to attach to, but none was
2189 * provided. Create our own. */
2190 pdev = platform_device_register_simple("parport_pc",
2197 ops = kmalloc(sizeof (struct parport_operations), GFP_KERNEL);
2201 priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
2205 /* a misnomer, actually - it's allocate and reserve parport number */
2206 p = parport_register_port(base, irq, dma, ops);
2210 base_res = request_region(base, 3, p->name);
2214 memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations));
2216 priv->ctr_writable = ~0x10;
2218 priv->fifo_depth = 0;
2219 priv->dma_buf = NULL;
2220 priv->dma_handle = 0;
2221 INIT_LIST_HEAD(&priv->list);
2225 p->base_hi = base_hi;
2226 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2227 p->private_data = priv;
2230 ECR_res = request_region(base_hi, 3, p->name);
2232 parport_ECR_present(p);
2235 if (base != 0x3bc) {
2236 EPP_res = request_region(base+0x3, 5, p->name);
2238 if (!parport_EPP_supported(p))
2239 parport_ECPEPP_supported(p);
2241 if (!parport_SPP_supported (p))
2245 parport_ECPPS2_supported(p);
2247 parport_PS2_supported(p);
2249 p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
2251 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2252 if (p->base_hi && priv->ecr)
2253 printk(" (0x%lx)", p->base_hi);
2254 if (p->irq == PARPORT_IRQ_AUTO) {
2255 p->irq = PARPORT_IRQ_NONE;
2256 parport_irq_probe(p);
2257 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2258 p->irq = PARPORT_IRQ_NONE;
2259 parport_irq_probe(p);
2261 p->irq = PARPORT_IRQ_NONE;
2263 if (p->irq != PARPORT_IRQ_NONE) {
2264 printk(", irq %d", p->irq);
2265 priv->ctr_writable |= 0x10;
2267 if (p->dma == PARPORT_DMA_AUTO) {
2268 p->dma = PARPORT_DMA_NONE;
2269 parport_dma_probe(p);
2272 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2273 is mandatory (see above) */
2274 p->dma = PARPORT_DMA_NONE;
2276 #ifdef CONFIG_PARPORT_PC_FIFO
2277 if (parport_ECP_supported(p) &&
2278 p->dma != PARPORT_DMA_NOFIFO &&
2279 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2280 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2281 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2282 #ifdef CONFIG_PARPORT_1284
2283 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2284 /* currently broken, but working on it.. (FB) */
2285 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2286 #endif /* IEEE 1284 support */
2287 if (p->dma != PARPORT_DMA_NONE) {
2288 printk(", dma %d", p->dma);
2289 p->modes |= PARPORT_MODE_DMA;
2291 else printk(", using FIFO");
2294 /* We can't use the DMA channel after all. */
2295 p->dma = PARPORT_DMA_NONE;
2296 #endif /* Allowed to use FIFO/DMA */
2299 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}}
2303 printmode(TRISTATE);
2310 #ifndef CONFIG_PARPORT_1284
2312 #endif /* CONFIG_PARPORT_1284 */
2314 if (probedirq != PARPORT_IRQ_NONE)
2315 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2317 /* If No ECP release the ports grabbed above. */
2318 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2319 release_region(base_hi, 3);
2322 /* Likewise for EEP ports */
2323 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2324 release_region(base+3, 5);
2327 if (p->irq != PARPORT_IRQ_NONE) {
2328 if (request_irq (p->irq, parport_irq_handler,
2330 printk (KERN_WARNING "%s: irq %d in use, "
2331 "resorting to polled operation\n",
2333 p->irq = PARPORT_IRQ_NONE;
2334 p->dma = PARPORT_DMA_NONE;
2337 #ifdef CONFIG_PARPORT_PC_FIFO
2339 if (p->dma != PARPORT_DMA_NONE) {
2340 if (request_dma (p->dma, p->name)) {
2341 printk (KERN_WARNING "%s: dma %d in use, "
2342 "resorting to PIO operation\n",
2344 p->dma = PARPORT_DMA_NONE;
2347 dma_alloc_coherent(dev,
2351 if (! priv->dma_buf) {
2352 printk (KERN_WARNING "%s: "
2353 "cannot get buffer for DMA, "
2354 "resorting to PIO operation\n",
2357 p->dma = PARPORT_DMA_NONE;
2365 /* Done probing. Now put the port into a sensible start-up state. */
2368 * Put the ECP detected port in PS2 mode.
2369 * Do this also for ports that have ECR but don't do ECP.
2371 ECR_WRITE (p, 0x34);
2373 parport_pc_write_data(p, 0);
2374 parport_pc_data_forward (p);
2376 /* Now that we've told the sharing engine about the port, and
2377 found out its characteristics, let the high-level drivers
2379 spin_lock(&ports_lock);
2380 list_add(&priv->list, &ports_list);
2381 spin_unlock(&ports_lock);
2382 parport_announce_port (p);
2388 release_region(base_hi, 3);
2390 release_region(base+0x3, 5);
2391 release_region(base, 3);
2393 parport_put_port(p);
2400 platform_device_unregister(pdev);
2404 EXPORT_SYMBOL (parport_pc_probe_port);
2406 void parport_pc_unregister_port (struct parport *p)
2408 struct parport_pc_private *priv = p->private_data;
2409 struct parport_operations *ops = p->ops;
2411 parport_remove_port(p);
2412 spin_lock(&ports_lock);
2413 list_del_init(&priv->list);
2414 spin_unlock(&ports_lock);
2415 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2416 if (p->dma != PARPORT_DMA_NONE)
2419 if (p->irq != PARPORT_IRQ_NONE)
2420 free_irq(p->irq, p);
2421 release_region(p->base, 3);
2423 release_region(p->base + 3, p->size - 3);
2424 if (p->modes & PARPORT_MODE_ECP)
2425 release_region(p->base_hi, 3);
2426 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2428 dma_free_coherent(p->physport->dev, PAGE_SIZE,
2432 kfree (p->private_data);
2433 parport_put_port(p);
2434 kfree (ops); /* hope no-one cached it */
2437 EXPORT_SYMBOL (parport_pc_unregister_port);
2441 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
2442 static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq,
2444 const struct parport_pc_via_data *via)
2446 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2447 struct resource *base_res;
2449 u32 ite8872_lpt, ite8872_lpthi;
2450 u8 ite8872_irq, type;
2454 DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n");
2456 // make sure which one chip
2457 for(i = 0; i < 5; i++) {
2458 base_res = request_region(inta_addr[i], 32, "it887x");
2461 pci_write_config_dword (pdev, 0x60,
2462 0xe5000000 | inta_addr[i]);
2463 pci_write_config_dword (pdev, 0x78,
2464 0x00000000 | inta_addr[i]);
2465 test = inb (inta_addr[i]);
2466 if (test != 0xff) break;
2467 release_region(inta_addr[i], 0x8);
2471 printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2475 type = inb (inta_addr[i] + 0x18);
2480 printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2481 ite8872set = 0x64200000;
2484 printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2485 ite8872set = 0x64200000;
2488 printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2489 ite8872set = 0x64e00000;
2492 printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2495 DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n");
2498 printk (KERN_INFO "parport_pc: unknown ITE887x\n");
2499 printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2500 "output to Rich.Liu@ite.com.tw\n");
2504 pci_read_config_byte (pdev, 0x3c, &ite8872_irq);
2505 pci_read_config_dword (pdev, 0x1c, &ite8872_lpt);
2506 ite8872_lpt &= 0x0000ff00;
2507 pci_read_config_dword (pdev, 0x20, &ite8872_lpthi);
2508 ite8872_lpthi &= 0x0000ff00;
2509 pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2510 pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2511 pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2512 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function
2514 pci_write_config_dword (pdev, 0x9c,
2515 ite8872set | (ite8872_irq * 0x11111));
2517 DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2518 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2520 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2523 /* Let the user (or defaults) steer us away from interrupts */
2525 if (autoirq != PARPORT_IRQ_AUTO)
2526 irq = PARPORT_IRQ_NONE;
2529 * Release the resource so that parport_pc_probe_port can get it.
2531 release_resource(base_res);
2532 if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi,
2533 irq, PARPORT_DMA_NONE, &pdev->dev)) {
2535 "parport_pc: ITE 8872 parallel port: io=0x%X",
2537 if (irq != PARPORT_IRQ_NONE)
2538 printk (", irq=%d", irq);
2546 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2547 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2548 static int __devinitdata parport_init_mode = 0;
2550 /* Data for two known VIA chips */
2551 static struct parport_pc_via_data via_686a_data __devinitdata = {
2560 static struct parport_pc_via_data via_8231_data __devinitdata = {
2570 static int __devinit sio_via_probe (struct pci_dev *pdev, int autoirq,
2572 const struct parport_pc_via_data *via)
2574 u8 tmp, tmp2, siofunc;
2577 unsigned port1, port2;
2578 unsigned have_epp = 0;
2580 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2582 switch(parport_init_mode)
2585 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2586 siofunc = VIA_FUNCTION_PARPORT_SPP;
2589 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2590 siofunc = VIA_FUNCTION_PARPORT_SPP;
2591 ppcontrol = VIA_PARPORT_BIDIR;
2594 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2595 siofunc = VIA_FUNCTION_PARPORT_EPP;
2596 ppcontrol = VIA_PARPORT_BIDIR;
2600 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2601 siofunc = VIA_FUNCTION_PARPORT_ECP;
2602 ppcontrol = VIA_PARPORT_BIDIR;
2605 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2606 siofunc = VIA_FUNCTION_PARPORT_ECP;
2607 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2611 printk(KERN_DEBUG "parport_pc: probing current configuration\n");
2612 siofunc = VIA_FUNCTION_PROBE;
2616 * unlock super i/o configuration
2618 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2619 tmp |= via->via_pci_superio_config_data;
2620 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2622 /* Bits 1-0: Parallel Port Mode / Enable */
2623 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2624 tmp = inb (VIA_CONFIG_DATA);
2625 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2626 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2627 tmp2 = inb (VIA_CONFIG_DATA);
2628 if (siofunc == VIA_FUNCTION_PROBE)
2630 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2635 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2637 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2638 outb(tmp, VIA_CONFIG_DATA);
2639 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2641 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2642 outb(tmp2, VIA_CONFIG_DATA);
2645 /* Parallel Port I/O Base Address, bits 9-2 */
2646 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2647 port1 = inb(VIA_CONFIG_DATA) << 2;
2649 printk (KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",port1);
2650 if ((port1 == 0x3BC) && have_epp)
2652 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2653 outb((0x378 >> 2), VIA_CONFIG_DATA);
2654 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n");
2659 * lock super i/o configuration
2661 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2662 tmp &= ~via->via_pci_superio_config_data;
2663 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2665 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2666 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2670 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2671 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2672 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2674 if (siofunc == VIA_FUNCTION_PARPORT_ECP)
2676 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2677 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2678 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2681 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */
2682 dma = PARPORT_DMA_NONE;
2684 /* Let the user (or defaults) steer us away from interrupts and DMA */
2685 if (autoirq == PARPORT_IRQ_NONE) {
2686 irq = PARPORT_IRQ_NONE;
2687 dma = PARPORT_DMA_NONE;
2689 if (autodma == PARPORT_DMA_NONE)
2690 dma = PARPORT_DMA_NONE;
2693 case 0x3bc: port2 = 0x7bc; break;
2694 case 0x378: port2 = 0x778; break;
2695 case 0x278: port2 = 0x678; break;
2697 printk(KERN_INFO "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2702 /* filter bogus IRQs */
2708 irq = PARPORT_IRQ_NONE;
2711 default: /* do nothing */
2715 /* finally, do the probe with values obtained */
2716 if (parport_pc_probe_port (port1, port2, irq, dma, &pdev->dev)) {
2718 "parport_pc: VIA parallel port: io=0x%X", port1);
2719 if (irq != PARPORT_IRQ_NONE)
2720 printk (", irq=%d", irq);
2721 if (dma != PARPORT_DMA_NONE)
2722 printk (", dma=%d", dma);
2727 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2733 enum parport_pc_sio_types {
2734 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2735 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2740 /* each element directly indexed from enum list, above */
2741 static struct parport_pc_superio {
2742 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2743 const struct parport_pc_via_data *via);
2744 const struct parport_pc_via_data *via;
2745 } parport_pc_superio_info[] __devinitdata = {
2746 { sio_via_probe, &via_686a_data, },
2747 { sio_via_probe, &via_8231_data, },
2748 { sio_ite_8872_probe, NULL, },
2751 enum parport_pc_pci_cards {
2752 siig_1p_10x = last_sio,
2757 lava_parallel_dual_a,
2758 lava_parallel_dual_b,
2805 /* each element directly indexed from enum list, above
2806 * (but offset by last_sio) */
2807 static struct parport_pc_pci {
2809 struct { /* BAR (base address registers) numbers in the config
2812 int hi; /* -1 if not there, >6 for offset-method (max
2816 /* If set, this is called immediately after pci_enable_device.
2817 * If it returns non-zero, no probing will take place and the
2818 * ports will not be used. */
2819 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2821 /* If set, this is called after probing for ports. If 'failed'
2822 * is non-zero we couldn't use any of the ports. */
2823 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2825 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2826 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2827 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2828 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2829 /* lava_parallel */ { 1, { { 0, -1 }, } },
2830 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2831 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2832 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2833 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2834 /* timedia_4078a */ { 1, { { 2, -1 }, } },
2835 /* timedia_4079h */ { 1, { { 2, 3 }, } },
2836 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
2837 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2838 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2839 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2840 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2841 /* timedia_4078u */ { 1, { { 2, -1 }, } },
2842 /* timedia_4079a */ { 1, { { 2, 3 }, } },
2843 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
2844 /* timedia_4079r */ { 1, { { 2, 3 }, } },
2845 /* timedia_4079s */ { 1, { { 2, 3 }, } },
2846 /* timedia_4079d */ { 1, { { 2, 3 }, } },
2847 /* timedia_4079e */ { 1, { { 2, 3 }, } },
2848 /* timedia_4079f */ { 1, { { 2, 3 }, } },
2849 /* timedia_9079a */ { 1, { { 2, 3 }, } },
2850 /* timedia_9079b */ { 1, { { 2, 3 }, } },
2851 /* timedia_9079c */ { 1, { { 2, 3 }, } },
2852 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2853 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2854 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2855 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2856 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2857 /* SYBA uses fixed offsets in
2859 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2860 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2861 /* titan_010l */ { 1, { { 3, -1 }, } },
2862 /* titan_1284p1 */ { 1, { { 0, 1 }, } },
2863 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2864 /* avlab_1p */ { 1, { { 0, 1}, } },
2865 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2866 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2867 * and 840 locks up if you write 1 to bit 2! */
2868 /* oxsemi_952 */ { 1, { { 0, 1 }, } },
2869 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2870 /* oxsemi_840 */ { 1, { { 0, 1 }, } },
2871 /* aks_0100 */ { 1, { { 0, -1 }, } },
2872 /* mobility_pp */ { 1, { { 0, 1 }, } },
2873 /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */
2874 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
2875 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
2876 /* netmos_9805 */ { 1, { { 0, -1 }, } }, /* untested */
2877 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */
2878 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2881 static const struct pci_device_id parport_pc_pci_tbl[] = {
2882 /* Super-IO onboard chips */
2883 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2884 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2885 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2886 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2889 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2890 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2891 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2892 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2893 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2894 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2895 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2896 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2897 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2898 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2899 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2900 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2901 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2902 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2903 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2904 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2905 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2906 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 },
2907 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2908 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
2909 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
2910 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
2911 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
2912 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
2913 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
2914 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
2915 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
2916 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
2917 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
2918 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
2919 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
2920 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
2921 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
2922 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
2923 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
2924 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
2925 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
2926 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2927 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2928 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2929 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2930 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2931 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2932 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2933 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2934 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2935 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2936 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2937 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2938 { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 },
2939 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2940 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2941 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */
2942 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2943 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
2944 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
2945 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2946 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2947 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2948 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2949 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2950 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2951 /* NetMos communication controllers */
2952 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2953 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2954 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2955 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2956 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2957 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2958 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2959 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2960 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2961 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2962 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2963 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
2964 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
2965 { 0, } /* terminate list */
2967 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl);
2969 struct pci_parport_data {
2971 struct parport *ports[2];
2974 static int parport_pc_pci_probe (struct pci_dev *dev,
2975 const struct pci_device_id *id)
2977 int err, count, n, i = id->driver_data;
2978 struct pci_parport_data *data;
2981 /* This is an onboard Super-IO and has already been probed */
2984 /* This is a PCI card */
2987 if ((err = pci_enable_device (dev)) != 0)
2990 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2994 if (cards[i].preinit_hook &&
2995 cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
3000 for (n = 0; n < cards[i].numports; n++) {
3001 int lo = cards[i].addr[n].lo;
3002 int hi = cards[i].addr[n].hi;
3003 unsigned long io_lo, io_hi;
3004 io_lo = pci_resource_start (dev, lo);
3006 if ((hi >= 0) && (hi <= 6))
3007 io_hi = pci_resource_start (dev, hi);
3009 io_lo += hi; /* Reinterpret the meaning of
3010 "hi" as an offset (see SYBA
3012 /* TODO: test if sharing interrupts works */
3013 printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, "
3014 "I/O at %#lx(%#lx)\n",
3015 parport_pc_pci_tbl[i + last_sio].vendor,
3016 parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi);
3017 data->ports[count] =
3018 parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE,
3019 PARPORT_DMA_NONE, &dev->dev);
3020 if (data->ports[count])
3026 if (cards[i].postinit_hook)
3027 cards[i].postinit_hook (dev, count == 0);
3030 pci_set_drvdata(dev, data);
3039 static void __devexit parport_pc_pci_remove(struct pci_dev *dev)
3041 struct pci_parport_data *data = pci_get_drvdata(dev);
3044 pci_set_drvdata(dev, NULL);
3047 for (i = data->num - 1; i >= 0; i--)
3048 parport_pc_unregister_port(data->ports[i]);
3054 static struct pci_driver parport_pc_pci_driver = {
3055 .name = "parport_pc",
3056 .id_table = parport_pc_pci_tbl,
3057 .probe = parport_pc_pci_probe,
3058 .remove = __devexit_p(parport_pc_pci_remove),
3061 static int __init parport_pc_init_superio (int autoirq, int autodma)
3063 const struct pci_device_id *id;
3064 struct pci_dev *pdev = NULL;
3067 for_each_pci_dev(pdev) {
3068 id = pci_match_id(parport_pc_pci_tbl, pdev);
3069 if (id == NULL || id->driver_data >= last_sio)
3072 if (parport_pc_superio_info[id->driver_data].probe
3073 (pdev, autoirq, autodma,parport_pc_superio_info[id->driver_data].via)) {
3078 return ret; /* number of devices found */
3081 static struct pci_driver parport_pc_pci_driver;
3082 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;}
3083 #endif /* CONFIG_PCI */
3087 static const struct pnp_device_id parport_pc_pnp_tbl[] = {
3088 /* Standard LPT Printer Port */
3089 {.id = "PNP0400", .driver_data = 0},
3090 /* ECP Printer Port */
3091 {.id = "PNP0401", .driver_data = 0},
3095 MODULE_DEVICE_TABLE(pnp,parport_pc_pnp_tbl);
3097 static int parport_pc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id)
3099 struct parport *pdata;
3100 unsigned long io_lo, io_hi;
3103 if (pnp_port_valid(dev,0) &&
3104 !(pnp_port_flags(dev,0) & IORESOURCE_DISABLED)) {
3105 io_lo = pnp_port_start(dev,0);
3109 if (pnp_port_valid(dev,1) &&
3110 !(pnp_port_flags(dev,1) & IORESOURCE_DISABLED)) {
3111 io_hi = pnp_port_start(dev,1);
3115 if (pnp_irq_valid(dev,0) &&
3116 !(pnp_irq_flags(dev,0) & IORESOURCE_DISABLED)) {
3117 irq = pnp_irq(dev,0);
3119 irq = PARPORT_IRQ_NONE;
3121 if (pnp_dma_valid(dev,0) &&
3122 !(pnp_dma_flags(dev,0) & IORESOURCE_DISABLED)) {
3123 dma = pnp_dma(dev,0);
3125 dma = PARPORT_DMA_NONE;
3127 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
3128 if (!(pdata = parport_pc_probe_port (io_lo, io_hi, irq, dma, &dev->dev)))
3131 pnp_set_drvdata(dev,pdata);
3135 static void parport_pc_pnp_remove(struct pnp_dev *dev)
3137 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
3141 parport_pc_unregister_port(pdata);
3144 /* we only need the pnp layer to activate the device, at least for now */
3145 static struct pnp_driver parport_pc_pnp_driver = {
3146 .name = "parport_pc",
3147 .id_table = parport_pc_pnp_tbl,
3148 .probe = parport_pc_pnp_probe,
3149 .remove = parport_pc_pnp_remove,
3153 static struct pnp_driver parport_pc_pnp_driver;
3154 #endif /* CONFIG_PNP */
3156 static int __devinit parport_pc_platform_probe(struct platform_device *pdev)
3158 /* Always succeed, the actual probing is done in
3159 * parport_pc_probe_port(). */
3163 static struct platform_driver parport_pc_platform_driver = {
3165 .owner = THIS_MODULE,
3166 .name = "parport_pc",
3168 .probe = parport_pc_platform_probe,
3171 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3172 static int __devinit __attribute__((unused))
3173 parport_pc_find_isa_ports (int autoirq, int autodma)
3177 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL))
3179 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL))
3181 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL))
3187 /* This function is called by parport_pc_init if the user didn't
3188 * specify any ports to probe. Its job is to find some ports. Order
3189 * is important here -- we want ISA ports to be registered first,
3190 * followed by PCI cards (for least surprise), but before that we want
3191 * to do chipset-specific tests for some onboard ports that we know
3194 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3195 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3197 static void __init parport_pc_find_ports (int autoirq, int autodma)
3201 #ifdef CONFIG_PARPORT_PC_SUPERIO
3202 detect_and_report_it87();
3203 detect_and_report_winbond();
3204 detect_and_report_smsc();
3207 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3208 count += parport_pc_init_superio(autoirq, autodma);
3210 /* PnP ports, skip detection if SuperIO already found them */
3212 err = pnp_register_driver(&parport_pc_pnp_driver);
3214 pnp_registered_parport = 1;
3217 /* ISA ports and whatever (see asm/parport.h). */
3218 parport_pc_find_nonpci_ports(autoirq, autodma);
3220 err = pci_register_driver(&parport_pc_pci_driver);
3222 pci_registered_parport = 1;
3226 * Piles of crap below pretend to be a parser for module and kernel
3227 * parameters. Say "thank you" to whoever had come up with that
3228 * syntax and keep in mind that code below is a cleaned up version.
3231 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 };
3232 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] =
3233 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO };
3234 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE };
3235 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY };
3237 static int __init parport_parse_param(const char *s, int *val,
3238 int automatic, int none, int nofifo)
3242 if (!strncmp(s, "auto", 4))
3244 else if (!strncmp(s, "none", 4))
3246 else if (nofifo && !strncmp(s, "nofifo", 4))
3250 unsigned long r = simple_strtoul(s, &ep, 0);
3254 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3261 static int __init parport_parse_irq(const char *irqstr, int *val)
3263 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3264 PARPORT_IRQ_NONE, 0);
3267 static int __init parport_parse_dma(const char *dmastr, int *val)
3269 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3270 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3274 static int __init parport_init_mode_setup(char *str)
3276 printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3278 if (!strcmp (str, "spp"))
3279 parport_init_mode=1;
3280 if (!strcmp (str, "ps2"))
3281 parport_init_mode=2;
3282 if (!strcmp (str, "epp"))
3283 parport_init_mode=3;
3284 if (!strcmp (str, "ecp"))
3285 parport_init_mode=4;
3286 if (!strcmp (str, "ecpepp"))
3287 parport_init_mode=5;
3293 static const char *irq[PARPORT_PC_MAX_PORTS];
3294 static const char *dma[PARPORT_PC_MAX_PORTS];
3296 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3297 module_param_array(io, int, NULL, 0);
3298 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3299 module_param_array(io_hi, int, NULL, 0);
3300 MODULE_PARM_DESC(irq, "IRQ line");
3301 module_param_array(irq, charp, NULL, 0);
3302 MODULE_PARM_DESC(dma, "DMA channel");
3303 module_param_array(dma, charp, NULL, 0);
3304 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3305 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3306 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3307 module_param(verbose_probing, int, 0644);
3310 static char *init_mode;
3311 MODULE_PARM_DESC(init_mode, "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3312 module_param(init_mode, charp, 0);
3315 static int __init parse_parport_params(void)
3322 parport_init_mode_setup(init_mode);
3325 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3326 if (parport_parse_irq(irq[i], &val))
3329 if (parport_parse_dma(dma[i], &val))
3334 /* The user can make us use any IRQs or DMAs we find. */
3335 if (irq[0] && !parport_parse_irq(irq[0], &val))
3337 case PARPORT_IRQ_NONE:
3338 case PARPORT_IRQ_AUTO:
3342 printk (KERN_WARNING
3343 "parport_pc: irq specified "
3344 "without base address. Use 'io=' "
3345 "to specify one\n");
3348 if (dma[0] && !parport_parse_dma(dma[0], &val))
3350 case PARPORT_DMA_NONE:
3351 case PARPORT_DMA_AUTO:
3355 printk (KERN_WARNING
3356 "parport_pc: dma specified "
3357 "without base address. Use 'io=' "
3358 "to specify one\n");
3366 static int parport_setup_ptr __initdata = 0;
3369 * Acceptable parameters:
3373 * parport=0xBASE[,IRQ[,DMA]]
3375 * IRQ/DMA may be numeric or 'auto' or 'none'
3377 static int __init parport_setup (char *str)
3383 if (!str || !*str || (*str == '0' && !*(str+1))) {
3384 /* Disable parport if "parport=0" in cmdline */
3385 io[0] = PARPORT_DISABLE;
3389 if (!strncmp (str, "auto", 4)) {
3390 irqval[0] = PARPORT_IRQ_AUTO;
3391 dmaval[0] = PARPORT_DMA_AUTO;
3395 val = simple_strtoul (str, &endptr, 0);
3396 if (endptr == str) {
3397 printk (KERN_WARNING "parport=%s not understood\n", str);
3401 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3402 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3406 io[parport_setup_ptr] = val;
3407 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3408 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3410 sep = strchr(str, ',');
3412 if (parport_parse_irq(sep, &val))
3414 irqval[parport_setup_ptr] = val;
3415 sep = strchr(sep, ',');
3417 if (parport_parse_dma(sep, &val))
3419 dmaval[parport_setup_ptr] = val;
3422 parport_setup_ptr++;
3426 static int __init parse_parport_params(void)
3428 return io[0] == PARPORT_DISABLE;
3431 __setup ("parport=", parport_setup);
3434 * Acceptable parameters:
3436 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3439 __setup("parport_init_mode=",parport_init_mode_setup);
3443 /* "Parser" ends here */
3445 static int __init parport_pc_init(void)
3449 if (parse_parport_params())
3452 err = platform_driver_register(&parport_pc_platform_driver);
3458 /* Only probe the ports we were given. */
3460 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3463 if ((io_hi[i]) == PARPORT_IOHI_AUTO)
3464 io_hi[i] = 0x400 + io[i];
3465 parport_pc_probe_port(io[i], io_hi[i],
3466 irqval[i], dmaval[i], NULL);
3469 parport_pc_find_ports (irqval[0], dmaval[0]);
3474 static void __exit parport_pc_exit(void)
3476 if (pci_registered_parport)
3477 pci_unregister_driver (&parport_pc_pci_driver);
3478 if (pnp_registered_parport)
3479 pnp_unregister_driver (&parport_pc_pnp_driver);
3480 platform_driver_unregister(&parport_pc_platform_driver);
3482 while (!list_empty(&ports_list)) {
3483 struct parport_pc_private *priv;
3484 struct parport *port;
3485 priv = list_entry(ports_list.next,
3486 struct parport_pc_private, list);
3488 if (port->dev && port->dev->bus == &platform_bus_type)
3489 platform_device_unregister(
3490 to_platform_device(port->dev));
3491 parport_pc_unregister_port(port);
3495 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3496 MODULE_DESCRIPTION("PC-style parallel port driver");
3497 MODULE_LICENSE("GPL");
3498 module_init(parport_pc_init)
3499 module_exit(parport_pc_exit)