3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 /* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
28 #include "zd_ieee80211.h"
33 void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
43 void zd_chip_clear(struct zd_chip *chip)
45 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
48 mutex_destroy(&chip->mutex);
49 ZD_MEMCLEAR(chip, sizeof(*chip));
52 static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size)
54 return scnprintf(buffer, size, "%02x-%02x-%02x",
55 addr[0], addr[1], addr[2]);
58 /* Prints an identifier line, which will support debugging. */
59 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
63 i = scnprintf(buffer, size, "zd1211%s chip ",
64 chip->is_zd1211b ? "b" : "");
65 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
66 i += scnprintf(buffer+i, size-i, " ");
67 i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i);
68 i += scnprintf(buffer+i, size-i, " ");
69 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
70 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
71 chip->patch_cck_gain ? 'g' : '-',
72 chip->patch_cr157 ? '7' : '-',
73 chip->patch_6m_band_edge ? '6' : '-',
74 chip->new_phy_layout ? 'N' : '-',
75 chip->al2230s_bit ? 'S' : '-');
79 static void print_id(struct zd_chip *chip)
83 scnprint_id(chip, buffer, sizeof(buffer));
84 buffer[sizeof(buffer)-1] = 0;
85 dev_info(zd_chip_dev(chip), "%s\n", buffer);
88 static zd_addr_t inc_addr(zd_addr_t addr)
91 /* Control registers use byte addressing, but everything else uses word
93 if ((a & 0xf000) == CR_START)
100 /* Read a variable number of 32-bit values. Parameter count is not allowed to
101 * exceed USB_MAX_IOREAD32_COUNT.
103 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
108 zd_addr_t *a16 = (zd_addr_t *)NULL;
110 unsigned int count16;
112 if (count > USB_MAX_IOREAD32_COUNT)
115 /* Allocate a single memory block for values and addresses. */
117 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
120 dev_dbg_f(zd_chip_dev(chip),
121 "error ENOMEM in allocation of a16\n");
125 v16 = (u16 *)(a16 + count16);
127 for (i = 0; i < count; i++) {
129 /* We read the high word always first. */
130 a16[j] = inc_addr(addr[i]);
134 r = zd_ioread16v_locked(chip, v16, a16, count16);
136 dev_dbg_f(zd_chip_dev(chip),
137 "error: zd_ioread16v_locked. Error number %d\n", r);
141 for (i = 0; i < count; i++) {
143 values[i] = (v16[j] << 16) | v16[j+1];
151 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
155 struct zd_ioreq16 *ioreqs16;
156 unsigned int count16;
158 ZD_ASSERT(mutex_is_locked(&chip->mutex));
162 if (count > USB_MAX_IOWRITE32_COUNT)
165 /* Allocate a single memory block for values and addresses. */
167 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
170 dev_dbg_f(zd_chip_dev(chip),
171 "error %d in ioreqs16 allocation\n", r);
175 for (i = 0; i < count; i++) {
177 /* We write the high word always first. */
178 ioreqs16[j].value = ioreqs[i].value >> 16;
179 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
180 ioreqs16[j+1].value = ioreqs[i].value;
181 ioreqs16[j+1].addr = ioreqs[i].addr;
184 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
187 dev_dbg_f(zd_chip_dev(chip),
188 "error %d in zd_usb_write16v\n", r);
196 int zd_iowrite16a_locked(struct zd_chip *chip,
197 const struct zd_ioreq16 *ioreqs, unsigned int count)
200 unsigned int i, j, t, max;
202 ZD_ASSERT(mutex_is_locked(&chip->mutex));
203 for (i = 0; i < count; i += j + t) {
206 if (max > USB_MAX_IOWRITE16_COUNT)
207 max = USB_MAX_IOWRITE16_COUNT;
208 for (j = 0; j < max; j++) {
209 if (!ioreqs[i+j].addr) {
215 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
217 dev_dbg_f(zd_chip_dev(chip),
218 "error zd_usb_iowrite16v. Error number %d\n",
227 /* Writes a variable number of 32 bit registers. The functions will split
228 * that in several USB requests. A split can be forced by inserting an IO
229 * request with an zero address field.
231 int zd_iowrite32a_locked(struct zd_chip *chip,
232 const struct zd_ioreq32 *ioreqs, unsigned int count)
235 unsigned int i, j, t, max;
237 for (i = 0; i < count; i += j + t) {
240 if (max > USB_MAX_IOWRITE32_COUNT)
241 max = USB_MAX_IOWRITE32_COUNT;
242 for (j = 0; j < max; j++) {
243 if (!ioreqs[i+j].addr) {
249 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
251 dev_dbg_f(zd_chip_dev(chip),
252 "error _zd_iowrite32v_locked."
253 " Error number %d\n", r);
261 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
265 mutex_lock(&chip->mutex);
266 r = zd_ioread16_locked(chip, value, addr);
267 mutex_unlock(&chip->mutex);
271 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
275 mutex_lock(&chip->mutex);
276 r = zd_ioread32_locked(chip, value, addr);
277 mutex_unlock(&chip->mutex);
281 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
285 mutex_lock(&chip->mutex);
286 r = zd_iowrite16_locked(chip, value, addr);
287 mutex_unlock(&chip->mutex);
291 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
295 mutex_lock(&chip->mutex);
296 r = zd_iowrite32_locked(chip, value, addr);
297 mutex_unlock(&chip->mutex);
301 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
302 u32 *values, unsigned int count)
306 mutex_lock(&chip->mutex);
307 r = zd_ioread32v_locked(chip, values, addresses, count);
308 mutex_unlock(&chip->mutex);
312 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
317 mutex_lock(&chip->mutex);
318 r = zd_iowrite32a_locked(chip, ioreqs, count);
319 mutex_unlock(&chip->mutex);
323 static int read_pod(struct zd_chip *chip, u8 *rf_type)
328 ZD_ASSERT(mutex_is_locked(&chip->mutex));
329 r = zd_ioread32_locked(chip, &value, E2P_POD);
332 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
334 /* FIXME: AL2230 handling (Bit 7 in POD) */
335 *rf_type = value & 0x0f;
336 chip->pa_type = (value >> 16) & 0x0f;
337 chip->patch_cck_gain = (value >> 8) & 0x1;
338 chip->patch_cr157 = (value >> 13) & 0x1;
339 chip->patch_6m_band_edge = (value >> 21) & 0x1;
340 chip->new_phy_layout = (value >> 31) & 0x1;
341 chip->al2230s_bit = (value >> 7) & 0x1;
342 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
343 chip->supports_tx_led = 1;
344 if (value & (1 << 24)) { /* LED scenario */
345 if (value & (1 << 29))
346 chip->supports_tx_led = 0;
349 dev_dbg_f(zd_chip_dev(chip),
350 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
351 "patch 6M %d new PHY %d link LED%d tx led %d\n",
352 zd_rf_name(*rf_type), *rf_type,
353 chip->pa_type, chip->patch_cck_gain,
354 chip->patch_cr157, chip->patch_6m_band_edge,
355 chip->new_phy_layout,
356 chip->link_led == LED1 ? 1 : 2,
357 chip->supports_tx_led);
362 chip->patch_cck_gain = 0;
363 chip->patch_cr157 = 0;
364 chip->patch_6m_band_edge = 0;
365 chip->new_phy_layout = 0;
369 static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr,
370 const zd_addr_t *addr)
375 r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2);
377 dev_dbg_f(zd_chip_dev(chip),
378 "error: couldn't read e2p macs. Error number %d\n", r);
382 mac_addr[0] = parts[0];
383 mac_addr[1] = parts[0] >> 8;
384 mac_addr[2] = parts[0] >> 16;
385 mac_addr[3] = parts[0] >> 24;
386 mac_addr[4] = parts[1];
387 mac_addr[5] = parts[1] >> 8;
392 static int read_e2p_mac_addr(struct zd_chip *chip)
394 static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 };
396 ZD_ASSERT(mutex_is_locked(&chip->mutex));
397 return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr);
400 /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
401 * CR_MAC_ADDR_P2 must be overwritten
403 void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr)
405 mutex_lock(&chip->mutex);
406 memcpy(mac_addr, chip->e2p_mac, ETH_ALEN);
407 mutex_unlock(&chip->mutex);
410 static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
412 static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 };
413 return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr);
416 int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
420 dev_dbg_f(zd_chip_dev(chip), "\n");
421 mutex_lock(&chip->mutex);
422 r = read_mac_addr(chip, mac_addr);
423 mutex_unlock(&chip->mutex);
427 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
430 struct zd_ioreq32 reqs[2] = {
431 [0] = { .addr = CR_MAC_ADDR_P1 },
432 [1] = { .addr = CR_MAC_ADDR_P2 },
435 reqs[0].value = (mac_addr[3] << 24)
436 | (mac_addr[2] << 16)
439 reqs[1].value = (mac_addr[5] << 8)
442 dev_dbg_f(zd_chip_dev(chip),
443 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
445 mutex_lock(&chip->mutex);
446 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
450 read_mac_addr(chip, tmp);
453 mutex_unlock(&chip->mutex);
457 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
462 mutex_lock(&chip->mutex);
463 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
464 mutex_unlock(&chip->mutex);
468 *regdomain = value >> 16;
469 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
474 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
475 zd_addr_t e2p_addr, u32 guard)
481 ZD_ASSERT(mutex_is_locked(&chip->mutex));
483 r = zd_ioread32_locked(chip, &v,
484 (zd_addr_t)((u16)e2p_addr+i/2));
490 values[i++] = v >> 8;
491 values[i++] = v >> 16;
492 values[i++] = v >> 24;
495 for (;i < count; i++)
496 values[i] = v >> (8*(i%3));
501 static int read_pwr_cal_values(struct zd_chip *chip)
503 return read_values(chip, chip->pwr_cal_values,
504 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
508 static int read_pwr_int_values(struct zd_chip *chip)
510 return read_values(chip, chip->pwr_int_values,
511 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
515 static int read_ofdm_cal_values(struct zd_chip *chip)
519 static const zd_addr_t addresses[] = {
525 for (i = 0; i < 3; i++) {
526 r = read_values(chip, chip->ofdm_cal_values[i],
527 E2P_CHANNEL_COUNT, addresses[i], 0);
534 static int read_cal_int_tables(struct zd_chip *chip)
538 r = read_pwr_cal_values(chip);
541 r = read_pwr_int_values(chip);
544 r = read_ofdm_cal_values(chip);
550 /* phy means physical registers */
551 int zd_chip_lock_phy_regs(struct zd_chip *chip)
556 ZD_ASSERT(mutex_is_locked(&chip->mutex));
557 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
559 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
563 dev_dbg_f(zd_chip_dev(chip),
564 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS);
565 tmp &= ~UNLOCK_PHY_REGS;
567 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
569 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
573 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
578 ZD_ASSERT(mutex_is_locked(&chip->mutex));
579 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
581 dev_err(zd_chip_dev(chip),
582 "error ioread32(CR_REG1): %d\n", r);
586 dev_dbg_f(zd_chip_dev(chip),
587 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS);
588 tmp |= UNLOCK_PHY_REGS;
590 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
592 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
596 /* CR157 can be optionally patched by the EEPROM for original ZD1211 */
597 static int patch_cr157(struct zd_chip *chip)
602 if (!chip->patch_cr157)
605 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
609 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
610 return zd_iowrite32_locked(chip, value >> 8, CR157);
614 * 6M band edge can be optionally overwritten for certain RF's
615 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
616 * bit (for AL2230, AL2230S)
618 static int patch_6m_band_edge(struct zd_chip *chip, int channel)
620 struct zd_ioreq16 ioreqs[] = {
621 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
625 if (!chip->patch_6m_band_edge || !chip->rf.patch_6m_band_edge)
628 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
629 if (channel == 1 || channel == 11)
630 ioreqs[0].value = 0x12;
632 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
633 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
636 static int zd1211_hw_reset_phy(struct zd_chip *chip)
638 static const struct zd_ioreq16 ioreqs[] = {
639 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
640 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
641 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
642 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
643 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
644 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
645 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
646 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
647 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
648 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
649 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
650 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
651 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
652 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
653 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
654 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
655 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
656 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
657 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
658 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
659 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
660 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
661 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
662 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
663 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
664 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
665 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
666 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
667 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
668 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
669 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
670 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
671 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
673 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
674 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
675 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
676 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
677 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
678 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
679 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
680 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
681 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
682 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
683 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
684 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
685 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
686 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
687 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
688 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
689 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
690 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
691 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
692 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
693 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
694 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
695 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
696 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
697 { CR170, 0xba }, { CR171, 0xba },
698 /* Note: CR204 must lead the CR203 */
706 dev_dbg_f(zd_chip_dev(chip), "\n");
708 r = zd_chip_lock_phy_regs(chip);
712 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
716 r = patch_cr157(chip);
718 t = zd_chip_unlock_phy_regs(chip);
725 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
727 static const struct zd_ioreq16 ioreqs[] = {
728 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
729 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
731 /* power control { { CR11, 1 << 6 }, */
733 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
734 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
735 { CR18, 0x0a }, { CR19, 0x48 },
736 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
737 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
738 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
739 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
740 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
741 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
742 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
743 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
744 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
745 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
746 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
747 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
748 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
749 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
750 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
751 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
752 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
753 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
754 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
755 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
756 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
758 { CR95, 0x20 }, /* ZD1211B */
759 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
760 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
761 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
762 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
763 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
764 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
765 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
766 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
767 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
768 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
769 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
770 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
771 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
772 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
773 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
774 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
775 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
776 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
777 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
778 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
779 { CR170, 0xba }, { CR171, 0xba },
780 /* Note: CR204 must lead the CR203 */
788 dev_dbg_f(zd_chip_dev(chip), "\n");
790 r = zd_chip_lock_phy_regs(chip);
794 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
795 t = zd_chip_unlock_phy_regs(chip);
802 static int hw_reset_phy(struct zd_chip *chip)
804 return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) :
805 zd1211_hw_reset_phy(chip);
808 static int zd1211_hw_init_hmac(struct zd_chip *chip)
810 static const struct zd_ioreq32 ioreqs[] = {
811 { CR_ZD1211_RETRY_MAX, 0x2 },
812 { CR_RX_THRESHOLD, 0x000c0640 },
815 dev_dbg_f(zd_chip_dev(chip), "\n");
816 ZD_ASSERT(mutex_is_locked(&chip->mutex));
817 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
820 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
822 static const struct zd_ioreq32 ioreqs[] = {
823 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
824 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
825 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
826 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
827 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
828 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
829 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
830 { CR_ZD1211B_TXOP, 0x01800824 },
831 { CR_RX_THRESHOLD, 0x000c0eff, },
834 dev_dbg_f(zd_chip_dev(chip), "\n");
835 ZD_ASSERT(mutex_is_locked(&chip->mutex));
836 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
839 static int hw_init_hmac(struct zd_chip *chip)
842 static const struct zd_ioreq32 ioreqs[] = {
843 { CR_ACK_TIMEOUT_EXT, 0x20 },
844 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
845 { CR_SNIFFER_ON, 0 },
846 { CR_RX_FILTER, STA_RX_FILTER },
847 { CR_GROUP_HASH_P1, 0x00 },
848 { CR_GROUP_HASH_P2, 0x80000000 },
850 { CR_ADDA_PWR_DWN, 0x7f },
851 { CR_BCN_PLCP_CFG, 0x00f00401 },
852 { CR_PHY_DELAY, 0x00 },
853 { CR_ACK_TIMEOUT_EXT, 0x80 },
854 { CR_ADDA_PWR_DWN, 0x00 },
855 { CR_ACK_TIME_80211, 0x100 },
856 { CR_RX_PE_DELAY, 0x70 },
857 { CR_PS_CTRL, 0x10000000 },
858 { CR_RTS_CTS_RATE, 0x02030203 },
859 { CR_AFTER_PNP, 0x1 },
860 { CR_WEP_PROTECT, 0x114 },
861 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
864 ZD_ASSERT(mutex_is_locked(&chip->mutex));
865 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
869 return chip->is_zd1211b ?
870 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
879 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
882 static const zd_addr_t aw_pt_bi_addr[] =
883 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
886 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
887 ARRAY_SIZE(aw_pt_bi_addr));
889 memset(s, 0, sizeof(*s));
893 s->atim_wnd_period = values[0];
894 s->pre_tbtt = values[1];
895 s->beacon_interval = values[2];
896 dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n",
897 s->atim_wnd_period, s->pre_tbtt, s->beacon_interval);
901 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
903 struct zd_ioreq32 reqs[3];
905 if (s->beacon_interval <= 5)
906 s->beacon_interval = 5;
907 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
908 s->pre_tbtt = s->beacon_interval - 1;
909 if (s->atim_wnd_period >= s->pre_tbtt)
910 s->atim_wnd_period = s->pre_tbtt - 1;
912 reqs[0].addr = CR_ATIM_WND_PERIOD;
913 reqs[0].value = s->atim_wnd_period;
914 reqs[1].addr = CR_PRE_TBTT;
915 reqs[1].value = s->pre_tbtt;
916 reqs[2].addr = CR_BCN_INTERVAL;
917 reqs[2].value = s->beacon_interval;
919 dev_dbg_f(zd_chip_dev(chip),
920 "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt,
922 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
926 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
931 ZD_ASSERT(mutex_is_locked(&chip->mutex));
932 r = get_aw_pt_bi(chip, &s);
935 s.beacon_interval = interval;
936 return set_aw_pt_bi(chip, &s);
939 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
943 mutex_lock(&chip->mutex);
944 r = set_beacon_interval(chip, interval);
945 mutex_unlock(&chip->mutex);
949 static int hw_init(struct zd_chip *chip)
953 dev_dbg_f(zd_chip_dev(chip), "\n");
954 ZD_ASSERT(mutex_is_locked(&chip->mutex));
955 r = hw_reset_phy(chip);
959 r = hw_init_hmac(chip);
963 return set_beacon_interval(chip, 100);
966 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
968 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
972 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
973 const char *addr_string)
978 r = zd_ioread32_locked(chip, &value, addr);
980 dev_dbg_f(zd_chip_dev(chip),
981 "error reading %s. Error number %d\n", addr_string, r);
985 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
986 addr_string, (unsigned int)value);
990 static int test_init(struct zd_chip *chip)
994 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
997 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
1000 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
1003 static void dump_fw_registers(struct zd_chip *chip)
1005 const zd_addr_t addr[4] = {
1006 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
1007 fw_reg_addr(chip, FW_REG_USB_SPEED),
1008 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
1009 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1015 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
1018 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1023 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1024 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1025 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1026 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1030 static int print_fw_version(struct zd_chip *chip)
1035 r = zd_ioread16_locked(chip, &version,
1036 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
1040 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1044 static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
1047 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1048 /* This sets the mandatory rates, which only depend from the standard
1049 * that the device is supporting. Until further notice we should try
1050 * to support 802.11g also for full speed USB.
1054 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1057 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1058 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1063 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1066 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1067 u8 rts_rate, int preamble)
1069 int rts_mod = ZD_RX_CCK;
1072 /* Modulation bit */
1073 if (ZD_CS_TYPE(rts_rate) == ZD_CS_OFDM)
1074 rts_mod = ZD_RX_OFDM;
1076 dev_dbg_f(zd_chip_dev(chip), "rts_rate=%x preamble=%x\n",
1077 rts_rate, preamble);
1079 value |= rts_rate << RTSCTS_SH_RTS_RATE;
1080 value |= rts_mod << RTSCTS_SH_RTS_MOD_TYPE;
1081 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1082 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1084 /* We always send 11M self-CTS messages, like the vendor driver. */
1085 value |= ZD_CCK_RATE_11M << RTSCTS_SH_CTS_RATE;
1086 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1088 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1091 int zd_chip_enable_hwint(struct zd_chip *chip)
1095 mutex_lock(&chip->mutex);
1096 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1097 mutex_unlock(&chip->mutex);
1101 static int disable_hwint(struct zd_chip *chip)
1103 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1106 int zd_chip_disable_hwint(struct zd_chip *chip)
1110 mutex_lock(&chip->mutex);
1111 r = disable_hwint(chip);
1112 mutex_unlock(&chip->mutex);
1116 static int read_fw_regs_offset(struct zd_chip *chip)
1120 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1121 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1125 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1126 (u16)chip->fw_regs_base);
1132 int zd_chip_init_hw(struct zd_chip *chip, u8 device_type)
1137 dev_dbg_f(zd_chip_dev(chip), "\n");
1139 mutex_lock(&chip->mutex);
1140 chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0;
1143 r = test_init(chip);
1147 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1151 r = read_fw_regs_offset(chip);
1155 /* GPI is always disabled, also in the other driver.
1157 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1160 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1163 /* Currently we support IEEE 802.11g for full and high speed USB.
1164 * It might be discussed, whether we should suppport pure b mode for
1167 r = set_mandatory_rates(chip, IEEE80211G);
1170 /* Disabling interrupts is certainly a smart thing here.
1172 r = disable_hwint(chip);
1175 r = read_pod(chip, &rf_type);
1181 r = zd_rf_init_hw(&chip->rf, rf_type);
1185 r = print_fw_version(chip);
1190 dump_fw_registers(chip);
1191 r = test_init(chip);
1196 r = read_e2p_mac_addr(chip);
1200 r = read_cal_int_tables(chip);
1206 mutex_unlock(&chip->mutex);
1210 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1212 u8 value = chip->pwr_int_values[channel - 1];
1213 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n",
1215 return zd_iowrite16_locked(chip, value, CR31);
1218 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1220 u8 value = chip->pwr_cal_values[channel-1];
1221 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n",
1223 return zd_iowrite16_locked(chip, value, CR68);
1226 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1228 struct zd_ioreq16 ioreqs[3];
1230 ioreqs[0].addr = CR67;
1231 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1232 ioreqs[1].addr = CR66;
1233 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1234 ioreqs[2].addr = CR65;
1235 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1237 dev_dbg_f(zd_chip_dev(chip),
1238 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1239 channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value);
1240 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1243 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1248 r = update_pwr_int(chip, channel);
1251 if (chip->is_zd1211b) {
1252 static const struct zd_ioreq16 ioreqs[] = {
1258 r = update_ofdm_cal(chip, channel);
1261 r = update_pwr_cal(chip, channel);
1264 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1272 /* The CCK baseband gain can be optionally patched by the EEPROM */
1273 static int patch_cck_gain(struct zd_chip *chip)
1278 if (!chip->patch_cck_gain)
1281 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1282 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1285 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1286 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1289 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1293 mutex_lock(&chip->mutex);
1294 r = zd_chip_lock_phy_regs(chip);
1297 r = zd_rf_set_channel(&chip->rf, channel);
1300 r = update_channel_integration_and_calibration(chip, channel);
1303 r = patch_cck_gain(chip);
1306 r = patch_6m_band_edge(chip, channel);
1309 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1311 t = zd_chip_unlock_phy_regs(chip);
1315 mutex_unlock(&chip->mutex);
1319 u8 zd_chip_get_channel(struct zd_chip *chip)
1323 mutex_lock(&chip->mutex);
1324 channel = chip->rf.channel;
1325 mutex_unlock(&chip->mutex);
1329 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1331 const zd_addr_t a[] = {
1332 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1337 u16 v[ARRAY_SIZE(a)];
1338 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1339 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1344 mutex_lock(&chip->mutex);
1345 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1349 other_led = chip->link_led == LED1 ? LED2 : LED1;
1353 ioreqs[0].value = FW_LINK_OFF;
1354 ioreqs[1].value = v[1] & ~(LED1|LED2);
1357 ioreqs[0].value = FW_LINK_OFF;
1358 ioreqs[1].value = v[1] & ~other_led;
1359 if (get_seconds() % 3 == 0) {
1360 ioreqs[1].value &= ~chip->link_led;
1362 ioreqs[1].value |= chip->link_led;
1365 case LED_ASSOCIATED:
1366 ioreqs[0].value = FW_LINK_TX;
1367 ioreqs[1].value = v[1] & ~other_led;
1368 ioreqs[1].value |= chip->link_led;
1375 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1376 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1382 mutex_unlock(&chip->mutex);
1386 int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates)
1388 ZD_ASSERT((cr_rates & ~(CR_RATES_80211B | CR_RATES_80211G)) == 0);
1389 dev_dbg_f(zd_chip_dev(chip), "%x\n", cr_rates);
1391 return zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1394 static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
1396 static const u16 constants[] = {
1397 715, 655, 585, 540, 470, 410, 360, 315,
1398 270, 235, 205, 175, 150, 125, 105, 85,
1405 /* It seems that their quality parameter is somehow per signal
1406 * and is now transferred per bit.
1409 case ZD_OFDM_RATE_6M:
1410 case ZD_OFDM_RATE_12M:
1411 case ZD_OFDM_RATE_24M:
1414 case ZD_OFDM_RATE_9M:
1415 case ZD_OFDM_RATE_18M:
1416 case ZD_OFDM_RATE_36M:
1417 case ZD_OFDM_RATE_54M:
1421 case ZD_OFDM_RATE_48M:
1429 x = (10000 * status_quality)/size;
1430 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1431 if (x > constants[i])
1436 case ZD_OFDM_RATE_6M:
1437 case ZD_OFDM_RATE_9M:
1440 case ZD_OFDM_RATE_12M:
1441 case ZD_OFDM_RATE_18M:
1444 case ZD_OFDM_RATE_24M:
1445 case ZD_OFDM_RATE_36M:
1448 case ZD_OFDM_RATE_48M:
1449 case ZD_OFDM_RATE_54M:
1459 static int ofdm_qual_percent(u8 status_quality, u8 rate, unsigned int size)
1463 r = ofdm_qual_db(status_quality, rate, size);
1469 return r <= 100 ? r : 100;
1472 static unsigned int log10times100(unsigned int x)
1474 static const u8 log10[] = {
1476 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1477 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1478 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1479 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1480 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1481 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1482 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1483 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1484 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1485 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1486 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1487 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1488 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1489 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1490 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1491 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1492 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1493 223, 223, 223, 224, 224, 224, 224,
1496 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1500 MAX_CCK_EVM_DB = 45,
1503 static int cck_evm_db(u8 status_quality)
1505 return (20 * log10times100(status_quality)) / 100;
1508 static int cck_snr_db(u8 status_quality)
1510 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1515 static int cck_qual_percent(u8 status_quality)
1519 r = cck_snr_db(status_quality);
1521 return r <= 100 ? r : 100;
1524 u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1525 const struct rx_status *status)
1527 return (status->frame_status&ZD_RX_OFDM) ?
1528 ofdm_qual_percent(status->signal_quality_ofdm,
1529 zd_ofdm_plcp_header_rate(rx_frame),
1531 cck_qual_percent(status->signal_quality_cck);
1534 u8 zd_rx_strength_percent(u8 rssi)
1536 int r = (rssi*100) / 41;
1542 u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1544 static const u16 ofdm_rates[] = {
1545 [ZD_OFDM_RATE_6M] = 60,
1546 [ZD_OFDM_RATE_9M] = 90,
1547 [ZD_OFDM_RATE_12M] = 120,
1548 [ZD_OFDM_RATE_18M] = 180,
1549 [ZD_OFDM_RATE_24M] = 240,
1550 [ZD_OFDM_RATE_36M] = 360,
1551 [ZD_OFDM_RATE_48M] = 480,
1552 [ZD_OFDM_RATE_54M] = 540,
1555 if (status->frame_status & ZD_RX_OFDM) {
1556 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1557 rate = ofdm_rates[ofdm_rate & 0xf];
1559 u8 cck_rate = zd_cck_plcp_header_rate(rx_frame);
1561 case ZD_CCK_SIGNAL_1M:
1564 case ZD_CCK_SIGNAL_2M:
1567 case ZD_CCK_SIGNAL_5M5:
1570 case ZD_CCK_SIGNAL_11M:
1581 int zd_chip_switch_radio_on(struct zd_chip *chip)
1585 mutex_lock(&chip->mutex);
1586 r = zd_switch_radio_on(&chip->rf);
1587 mutex_unlock(&chip->mutex);
1591 int zd_chip_switch_radio_off(struct zd_chip *chip)
1595 mutex_lock(&chip->mutex);
1596 r = zd_switch_radio_off(&chip->rf);
1597 mutex_unlock(&chip->mutex);
1601 int zd_chip_enable_int(struct zd_chip *chip)
1605 mutex_lock(&chip->mutex);
1606 r = zd_usb_enable_int(&chip->usb);
1607 mutex_unlock(&chip->mutex);
1611 void zd_chip_disable_int(struct zd_chip *chip)
1613 mutex_lock(&chip->mutex);
1614 zd_usb_disable_int(&chip->usb);
1615 mutex_unlock(&chip->mutex);
1618 int zd_chip_enable_rx(struct zd_chip *chip)
1622 mutex_lock(&chip->mutex);
1623 r = zd_usb_enable_rx(&chip->usb);
1624 mutex_unlock(&chip->mutex);
1628 void zd_chip_disable_rx(struct zd_chip *chip)
1630 mutex_lock(&chip->mutex);
1631 zd_usb_disable_rx(&chip->usb);
1632 mutex_unlock(&chip->mutex);
1635 int zd_rfwritev_locked(struct zd_chip *chip,
1636 const u32* values, unsigned int count, u8 bits)
1641 for (i = 0; i < count; i++) {
1642 r = zd_rfwrite_locked(chip, values[i], bits);
1651 * We can optionally program the RF directly through CR regs, if supported by
1652 * the hardware. This is much faster than the older method.
1654 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1656 struct zd_ioreq16 ioreqs[] = {
1657 { CR244, (value >> 16) & 0xff },
1658 { CR243, (value >> 8) & 0xff },
1659 { CR242, value & 0xff },
1661 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1662 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1665 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1666 const u32 *values, unsigned int count)
1671 for (i = 0; i < count; i++) {
1672 r = zd_rfwrite_cr_locked(chip, values[i]);
1680 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1681 struct zd_mc_hash *hash)
1683 struct zd_ioreq32 ioreqs[] = {
1684 { CR_GROUP_HASH_P1, hash->low },
1685 { CR_GROUP_HASH_P2, hash->high },
1688 dev_dbg_f(zd_chip_dev(chip), "hash l 0x%08x h 0x%08x\n",
1689 ioreqs[0].value, ioreqs[1].value);
1690 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));