3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 /* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
28 #include "zd_ieee80211.h"
33 void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
43 void zd_chip_clear(struct zd_chip *chip)
45 mutex_lock(&chip->mutex);
46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
48 mutex_unlock(&chip->mutex);
49 mutex_destroy(&chip->mutex);
50 memset(chip, 0, sizeof(*chip));
53 static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size)
55 return scnprintf(buffer, size, "%02x-%02x-%02x",
56 addr[0], addr[1], addr[2]);
59 /* Prints an identifier line, which will support debugging. */
60 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
64 i = scnprintf(buffer, size, "zd1211%s chip ",
65 chip->is_zd1211b ? "b" : "");
66 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
67 i += scnprintf(buffer+i, size-i, " ");
68 i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i);
69 i += scnprintf(buffer+i, size-i, " ");
70 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
71 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c", chip->pa_type,
72 chip->patch_cck_gain ? 'g' : '-',
73 chip->patch_cr157 ? '7' : '-',
74 chip->patch_6m_band_edge ? '6' : '-');
78 static void print_id(struct zd_chip *chip)
82 scnprint_id(chip, buffer, sizeof(buffer));
83 buffer[sizeof(buffer)-1] = 0;
84 dev_info(zd_chip_dev(chip), "%s\n", buffer);
87 /* Read a variable number of 32-bit values. Parameter count is not allowed to
88 * exceed USB_MAX_IOREAD32_COUNT.
90 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
95 zd_addr_t *a16 = (zd_addr_t *)NULL;
99 if (count > USB_MAX_IOREAD32_COUNT)
102 /* Allocate a single memory block for values and addresses. */
104 a16 = (zd_addr_t *)kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
107 dev_dbg_f(zd_chip_dev(chip),
108 "error ENOMEM in allocation of a16\n");
112 v16 = (u16 *)(a16 + count16);
114 for (i = 0; i < count; i++) {
116 /* We read the high word always first. */
117 a16[j] = zd_inc_word(addr[i]);
121 r = zd_ioread16v_locked(chip, v16, a16, count16);
123 dev_dbg_f(zd_chip_dev(chip),
124 "error: zd_ioread16v_locked. Error number %d\n", r);
128 for (i = 0; i < count; i++) {
130 values[i] = (v16[j] << 16) | v16[j+1];
138 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
142 struct zd_ioreq16 *ioreqs16;
143 unsigned int count16;
145 ZD_ASSERT(mutex_is_locked(&chip->mutex));
149 if (count > USB_MAX_IOWRITE32_COUNT)
152 /* Allocate a single memory block for values and addresses. */
154 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_NOFS);
157 dev_dbg_f(zd_chip_dev(chip),
158 "error %d in ioreqs16 allocation\n", r);
162 for (i = 0; i < count; i++) {
164 /* We write the high word always first. */
165 ioreqs16[j].value = ioreqs[i].value >> 16;
166 ioreqs16[j].addr = zd_inc_word(ioreqs[i].addr);
167 ioreqs16[j+1].value = ioreqs[i].value;
168 ioreqs16[j+1].addr = ioreqs[i].addr;
171 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
174 dev_dbg_f(zd_chip_dev(chip),
175 "error %d in zd_usb_write16v\n", r);
183 int zd_iowrite16a_locked(struct zd_chip *chip,
184 const struct zd_ioreq16 *ioreqs, unsigned int count)
187 unsigned int i, j, t, max;
189 ZD_ASSERT(mutex_is_locked(&chip->mutex));
190 for (i = 0; i < count; i += j + t) {
193 if (max > USB_MAX_IOWRITE16_COUNT)
194 max = USB_MAX_IOWRITE16_COUNT;
195 for (j = 0; j < max; j++) {
196 if (!ioreqs[i+j].addr) {
202 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
204 dev_dbg_f(zd_chip_dev(chip),
205 "error zd_usb_iowrite16v. Error number %d\n",
214 /* Writes a variable number of 32 bit registers. The functions will split
215 * that in several USB requests. A split can be forced by inserting an IO
216 * request with an zero address field.
218 int zd_iowrite32a_locked(struct zd_chip *chip,
219 const struct zd_ioreq32 *ioreqs, unsigned int count)
222 unsigned int i, j, t, max;
224 for (i = 0; i < count; i += j + t) {
227 if (max > USB_MAX_IOWRITE32_COUNT)
228 max = USB_MAX_IOWRITE32_COUNT;
229 for (j = 0; j < max; j++) {
230 if (!ioreqs[i+j].addr) {
236 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
238 dev_dbg_f(zd_chip_dev(chip),
239 "error _zd_iowrite32v_locked."
240 " Error number %d\n", r);
248 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
252 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
253 mutex_lock(&chip->mutex);
254 r = zd_ioread16_locked(chip, value, addr);
255 mutex_unlock(&chip->mutex);
259 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
263 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
264 mutex_lock(&chip->mutex);
265 r = zd_ioread32_locked(chip, value, addr);
266 mutex_unlock(&chip->mutex);
270 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
274 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
275 mutex_lock(&chip->mutex);
276 r = zd_iowrite16_locked(chip, value, addr);
277 mutex_unlock(&chip->mutex);
281 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
285 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
286 mutex_lock(&chip->mutex);
287 r = zd_iowrite32_locked(chip, value, addr);
288 mutex_unlock(&chip->mutex);
292 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
293 u32 *values, unsigned int count)
297 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
298 mutex_lock(&chip->mutex);
299 r = zd_ioread32v_locked(chip, values, addresses, count);
300 mutex_unlock(&chip->mutex);
304 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
309 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
310 mutex_lock(&chip->mutex);
311 r = zd_iowrite32a_locked(chip, ioreqs, count);
312 mutex_unlock(&chip->mutex);
316 static int read_pod(struct zd_chip *chip, u8 *rf_type)
321 ZD_ASSERT(mutex_is_locked(&chip->mutex));
322 r = zd_ioread32_locked(chip, &value, E2P_POD);
325 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
327 /* FIXME: AL2230 handling (Bit 7 in POD) */
328 *rf_type = value & 0x0f;
329 chip->pa_type = (value >> 16) & 0x0f;
330 chip->patch_cck_gain = (value >> 8) & 0x1;
331 chip->patch_cr157 = (value >> 13) & 0x1;
332 chip->patch_6m_band_edge = (value >> 21) & 0x1;
334 dev_dbg_f(zd_chip_dev(chip),
335 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
337 zd_rf_name(*rf_type), *rf_type,
338 chip->pa_type, chip->patch_cck_gain,
339 chip->patch_cr157, chip->patch_6m_band_edge);
344 chip->patch_cck_gain = 0;
345 chip->patch_cr157 = 0;
346 chip->patch_6m_band_edge = 0;
350 static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr,
351 const zd_addr_t *addr)
356 r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2);
358 dev_dbg_f(zd_chip_dev(chip),
359 "error: couldn't read e2p macs. Error number %d\n", r);
363 mac_addr[0] = parts[0];
364 mac_addr[1] = parts[0] >> 8;
365 mac_addr[2] = parts[0] >> 16;
366 mac_addr[3] = parts[0] >> 24;
367 mac_addr[4] = parts[1];
368 mac_addr[5] = parts[1] >> 8;
373 static int read_e2p_mac_addr(struct zd_chip *chip)
375 static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 };
377 ZD_ASSERT(mutex_is_locked(&chip->mutex));
378 return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr);
381 /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
382 * CR_MAC_ADDR_P2 must be overwritten
384 void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr)
386 mutex_lock(&chip->mutex);
387 memcpy(mac_addr, chip->e2p_mac, ETH_ALEN);
388 mutex_unlock(&chip->mutex);
391 static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
393 static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 };
394 return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr);
397 int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
401 dev_dbg_f(zd_chip_dev(chip), "\n");
402 mutex_lock(&chip->mutex);
403 r = read_mac_addr(chip, mac_addr);
404 mutex_unlock(&chip->mutex);
408 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
411 struct zd_ioreq32 reqs[2] = {
412 [0] = { .addr = CR_MAC_ADDR_P1 },
413 [1] = { .addr = CR_MAC_ADDR_P2 },
416 reqs[0].value = (mac_addr[3] << 24)
417 | (mac_addr[2] << 16)
420 reqs[1].value = (mac_addr[5] << 8)
423 dev_dbg_f(zd_chip_dev(chip),
424 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
426 mutex_lock(&chip->mutex);
427 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
431 read_mac_addr(chip, tmp);
434 mutex_unlock(&chip->mutex);
438 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
443 mutex_lock(&chip->mutex);
444 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
445 mutex_unlock(&chip->mutex);
449 *regdomain = value >> 16;
450 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
455 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
456 zd_addr_t e2p_addr, u32 guard)
462 ZD_ASSERT(mutex_is_locked(&chip->mutex));
464 r = zd_ioread32_locked(chip, &v, e2p_addr+i/2);
470 values[i++] = v >> 8;
471 values[i++] = v >> 16;
472 values[i++] = v >> 24;
475 for (;i < count; i++)
476 values[i] = v >> (8*(i%3));
481 static int read_pwr_cal_values(struct zd_chip *chip)
483 return read_values(chip, chip->pwr_cal_values,
484 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
488 static int read_pwr_int_values(struct zd_chip *chip)
490 return read_values(chip, chip->pwr_int_values,
491 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
495 static int read_ofdm_cal_values(struct zd_chip *chip)
499 static const zd_addr_t addresses[] = {
505 for (i = 0; i < 3; i++) {
506 r = read_values(chip, chip->ofdm_cal_values[i],
507 E2P_CHANNEL_COUNT, addresses[i], 0);
514 static int read_cal_int_tables(struct zd_chip *chip)
518 r = read_pwr_cal_values(chip);
521 r = read_pwr_int_values(chip);
524 r = read_ofdm_cal_values(chip);
530 /* phy means physical registers */
531 int zd_chip_lock_phy_regs(struct zd_chip *chip)
536 ZD_ASSERT(mutex_is_locked(&chip->mutex));
537 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
539 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
543 dev_dbg_f(zd_chip_dev(chip),
544 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS);
545 tmp &= ~UNLOCK_PHY_REGS;
547 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
549 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
553 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
558 ZD_ASSERT(mutex_is_locked(&chip->mutex));
559 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
561 dev_err(zd_chip_dev(chip),
562 "error ioread32(CR_REG1): %d\n", r);
566 dev_dbg_f(zd_chip_dev(chip),
567 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS);
568 tmp |= UNLOCK_PHY_REGS;
570 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
572 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
576 /* CR157 can be optionally patched by the EEPROM */
577 static int patch_cr157(struct zd_chip *chip)
582 if (!chip->patch_cr157)
585 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
589 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
590 return zd_iowrite32_locked(chip, value >> 8, CR157);
594 * 6M band edge can be optionally overwritten for certain RF's
595 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
596 * bit (for AL2230, AL2230S)
598 static int patch_6m_band_edge(struct zd_chip *chip, int channel)
600 struct zd_ioreq16 ioreqs[] = {
601 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
605 if (!chip->patch_6m_band_edge || !chip->rf.patch_6m_band_edge)
608 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
609 if (channel == 1 || channel == 11)
610 ioreqs[0].value = 0x12;
612 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
613 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
616 static int zd1211_hw_reset_phy(struct zd_chip *chip)
618 static const struct zd_ioreq16 ioreqs[] = {
619 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
620 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
621 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
622 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
623 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
624 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
625 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
626 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
627 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
628 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
629 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
630 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
631 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
632 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
633 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
634 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
635 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
636 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
637 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
638 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
639 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
640 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
641 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
642 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
643 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
644 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
645 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
646 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
647 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
648 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
649 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
650 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
651 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
653 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
654 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
655 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
656 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
657 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
658 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
659 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
660 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
661 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
662 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
663 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
664 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
665 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
666 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
667 { CR123, 0x27 }, { CR125, 0xaa }, { CR127, 0x03 },
668 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
669 { CR131, 0x0C }, { CR136, 0xdf }, { CR137, 0x40 },
670 { CR138, 0xa0 }, { CR139, 0xb0 }, { CR140, 0x99 },
671 { CR141, 0x82 }, { CR142, 0x54 }, { CR143, 0x1c },
672 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x4c },
673 { CR149, 0x50 }, { CR150, 0x0e }, { CR151, 0x18 },
674 { CR160, 0xfe }, { CR161, 0xee }, { CR162, 0xaa },
675 { CR163, 0xfa }, { CR164, 0xfa }, { CR165, 0xea },
676 { CR166, 0xbe }, { CR167, 0xbe }, { CR168, 0x6a },
677 { CR169, 0xba }, { CR170, 0xba }, { CR171, 0xba },
678 /* Note: CR204 must lead the CR203 */
686 dev_dbg_f(zd_chip_dev(chip), "\n");
688 r = zd_chip_lock_phy_regs(chip);
692 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
696 r = patch_cr157(chip);
698 t = zd_chip_unlock_phy_regs(chip);
705 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
707 static const struct zd_ioreq16 ioreqs[] = {
708 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
709 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
711 /* power control { { CR11, 1 << 6 }, */
713 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
714 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
715 { CR18, 0x0a }, { CR19, 0x48 },
716 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
717 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
718 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
719 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
720 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
721 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
722 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
723 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
724 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
725 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
726 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
727 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
728 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
729 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
730 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
731 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
732 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
733 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
734 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
735 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
736 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
738 { CR95, 0x20 }, /* ZD1211B */
739 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
740 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
741 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
742 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
743 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
744 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
745 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
746 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
747 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
748 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
749 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
750 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
751 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
752 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
753 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
754 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
755 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
756 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
757 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
758 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
759 { CR170, 0xba }, { CR171, 0xba },
760 /* Note: CR204 must lead the CR203 */
768 dev_dbg_f(zd_chip_dev(chip), "\n");
770 r = zd_chip_lock_phy_regs(chip);
774 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
778 r = patch_cr157(chip);
780 t = zd_chip_unlock_phy_regs(chip);
787 static int hw_reset_phy(struct zd_chip *chip)
789 return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) :
790 zd1211_hw_reset_phy(chip);
793 static int zd1211_hw_init_hmac(struct zd_chip *chip)
795 static const struct zd_ioreq32 ioreqs[] = {
796 { CR_ACK_TIMEOUT_EXT, 0x20 },
797 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
798 { CR_ZD1211_RETRY_MAX, 0x2 },
799 { CR_SNIFFER_ON, 0 },
800 { CR_RX_FILTER, STA_RX_FILTER },
801 { CR_GROUP_HASH_P1, 0x00 },
802 { CR_GROUP_HASH_P2, 0x80000000 },
804 { CR_ADDA_PWR_DWN, 0x7f },
805 { CR_BCN_PLCP_CFG, 0x00f00401 },
806 { CR_PHY_DELAY, 0x00 },
807 { CR_ACK_TIMEOUT_EXT, 0x80 },
808 { CR_ADDA_PWR_DWN, 0x00 },
809 { CR_ACK_TIME_80211, 0x100 },
810 { CR_RX_PE_DELAY, 0x70 },
811 { CR_PS_CTRL, 0x10000000 },
812 { CR_RTS_CTS_RATE, 0x02030203 },
813 { CR_RX_THRESHOLD, 0x000c0640 },
814 { CR_AFTER_PNP, 0x1 },
815 { CR_WEP_PROTECT, 0x114 },
820 dev_dbg_f(zd_chip_dev(chip), "\n");
821 ZD_ASSERT(mutex_is_locked(&chip->mutex));
822 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
825 dev_err(zd_chip_dev(chip),
826 "error in zd_iowrite32a_locked. Error number %d\n", r);
832 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
834 static const struct zd_ioreq32 ioreqs[] = {
835 { CR_ACK_TIMEOUT_EXT, 0x20 },
836 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
837 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
838 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
839 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
840 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
841 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
842 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
843 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
844 { CR_ZD1211B_TXOP, 0x01800824 },
845 { CR_SNIFFER_ON, 0 },
846 { CR_RX_FILTER, STA_RX_FILTER },
847 { CR_GROUP_HASH_P1, 0x00 },
848 { CR_GROUP_HASH_P2, 0x80000000 },
850 { CR_ADDA_PWR_DWN, 0x7f },
851 { CR_BCN_PLCP_CFG, 0x00f00401 },
852 { CR_PHY_DELAY, 0x00 },
853 { CR_ACK_TIMEOUT_EXT, 0x80 },
854 { CR_ADDA_PWR_DWN, 0x00 },
855 { CR_ACK_TIME_80211, 0x100 },
856 { CR_RX_PE_DELAY, 0x70 },
857 { CR_PS_CTRL, 0x10000000 },
858 { CR_RTS_CTS_RATE, 0x02030203 },
859 { CR_RX_THRESHOLD, 0x000c0640 },
860 { CR_AFTER_PNP, 0x1 },
861 { CR_WEP_PROTECT, 0x114 },
866 dev_dbg_f(zd_chip_dev(chip), "\n");
867 ZD_ASSERT(mutex_is_locked(&chip->mutex));
868 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
870 dev_dbg_f(zd_chip_dev(chip),
871 "error in zd_iowrite32a_locked. Error number %d\n", r);
876 static int hw_init_hmac(struct zd_chip *chip)
878 return chip->is_zd1211b ?
879 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
888 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
891 static const zd_addr_t aw_pt_bi_addr[] =
892 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
895 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
896 ARRAY_SIZE(aw_pt_bi_addr));
898 memset(s, 0, sizeof(*s));
902 s->atim_wnd_period = values[0];
903 s->pre_tbtt = values[1];
904 s->beacon_interval = values[2];
905 dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n",
906 s->atim_wnd_period, s->pre_tbtt, s->beacon_interval);
910 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
912 struct zd_ioreq32 reqs[3];
914 if (s->beacon_interval <= 5)
915 s->beacon_interval = 5;
916 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
917 s->pre_tbtt = s->beacon_interval - 1;
918 if (s->atim_wnd_period >= s->pre_tbtt)
919 s->atim_wnd_period = s->pre_tbtt - 1;
921 reqs[0].addr = CR_ATIM_WND_PERIOD;
922 reqs[0].value = s->atim_wnd_period;
923 reqs[1].addr = CR_PRE_TBTT;
924 reqs[1].value = s->pre_tbtt;
925 reqs[2].addr = CR_BCN_INTERVAL;
926 reqs[2].value = s->beacon_interval;
928 dev_dbg_f(zd_chip_dev(chip),
929 "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt,
931 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
935 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
940 ZD_ASSERT(mutex_is_locked(&chip->mutex));
941 r = get_aw_pt_bi(chip, &s);
944 s.beacon_interval = interval;
945 return set_aw_pt_bi(chip, &s);
948 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
952 mutex_lock(&chip->mutex);
953 r = set_beacon_interval(chip, interval);
954 mutex_unlock(&chip->mutex);
958 static int hw_init(struct zd_chip *chip)
962 dev_dbg_f(zd_chip_dev(chip), "\n");
963 ZD_ASSERT(mutex_is_locked(&chip->mutex));
964 r = hw_reset_phy(chip);
968 r = hw_init_hmac(chip);
972 /* Although the vendor driver defaults to a different value during
973 * init, it overwrites the IFS value with the following every time
974 * the channel changes. We should aim to be more intelligent... */
975 r = zd_iowrite32_locked(chip, IFS_VALUE_DEFAULT, CR_IFS_VALUE);
979 return set_beacon_interval(chip, 100);
983 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
984 const char *addr_string)
989 r = zd_ioread32_locked(chip, &value, addr);
991 dev_dbg_f(zd_chip_dev(chip),
992 "error reading %s. Error number %d\n", addr_string, r);
996 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
997 addr_string, (unsigned int)value);
1001 static int test_init(struct zd_chip *chip)
1005 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
1008 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
1011 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
1014 static void dump_fw_registers(struct zd_chip *chip)
1016 static const zd_addr_t addr[4] = {
1017 FW_FIRMWARE_VER, FW_USB_SPEED, FW_FIX_TX_RATE,
1024 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
1027 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1032 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1033 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1034 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1035 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1039 static int print_fw_version(struct zd_chip *chip)
1044 r = zd_ioread16_locked(chip, &version, FW_FIRMWARE_VER);
1048 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1052 static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
1055 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1056 /* This sets the mandatory rates, which only depend from the standard
1057 * that the device is supporting. Until further notice we should try
1058 * to support 802.11g also for full speed USB.
1062 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1065 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1066 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1071 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1074 int zd_chip_enable_hwint(struct zd_chip *chip)
1078 mutex_lock(&chip->mutex);
1079 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1080 mutex_unlock(&chip->mutex);
1084 static int disable_hwint(struct zd_chip *chip)
1086 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1089 int zd_chip_disable_hwint(struct zd_chip *chip)
1093 mutex_lock(&chip->mutex);
1094 r = disable_hwint(chip);
1095 mutex_unlock(&chip->mutex);
1099 int zd_chip_init_hw(struct zd_chip *chip, u8 device_type)
1104 dev_dbg_f(zd_chip_dev(chip), "\n");
1106 mutex_lock(&chip->mutex);
1107 chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0;
1110 r = test_init(chip);
1114 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1118 r = zd_usb_init_hw(&chip->usb);
1122 /* GPI is always disabled, also in the other driver.
1124 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1127 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1130 /* Currently we support IEEE 802.11g for full and high speed USB.
1131 * It might be discussed, whether we should suppport pure b mode for
1134 r = set_mandatory_rates(chip, IEEE80211G);
1137 /* Disabling interrupts is certainly a smart thing here.
1139 r = disable_hwint(chip);
1142 r = read_pod(chip, &rf_type);
1148 r = zd_rf_init_hw(&chip->rf, rf_type);
1152 r = print_fw_version(chip);
1157 dump_fw_registers(chip);
1158 r = test_init(chip);
1163 r = read_e2p_mac_addr(chip);
1167 r = read_cal_int_tables(chip);
1173 mutex_unlock(&chip->mutex);
1177 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1179 u8 value = chip->pwr_int_values[channel - 1];
1180 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n",
1182 return zd_iowrite32_locked(chip, value, CR31);
1185 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1187 u8 value = chip->pwr_cal_values[channel-1];
1188 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n",
1190 return zd_iowrite32_locked(chip, value, CR68);
1193 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1195 struct zd_ioreq32 ioreqs[3];
1197 ioreqs[0].addr = CR67;
1198 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1199 ioreqs[1].addr = CR66;
1200 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1201 ioreqs[2].addr = CR65;
1202 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1204 dev_dbg_f(zd_chip_dev(chip),
1205 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1206 channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value);
1207 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1210 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1215 r = update_pwr_int(chip, channel);
1218 if (chip->is_zd1211b) {
1219 static const struct zd_ioreq32 ioreqs[] = {
1225 r = update_ofdm_cal(chip, channel);
1228 r = update_pwr_cal(chip, channel);
1231 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1239 /* The CCK baseband gain can be optionally patched by the EEPROM */
1240 static int patch_cck_gain(struct zd_chip *chip)
1245 if (!chip->patch_cck_gain)
1248 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1249 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1252 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1253 return zd_iowrite32_locked(chip, value & 0xff, CR47);
1256 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1260 mutex_lock(&chip->mutex);
1261 r = zd_chip_lock_phy_regs(chip);
1264 r = zd_rf_set_channel(&chip->rf, channel);
1267 r = update_channel_integration_and_calibration(chip, channel);
1270 r = patch_cck_gain(chip);
1273 r = patch_6m_band_edge(chip, channel);
1276 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1278 t = zd_chip_unlock_phy_regs(chip);
1282 mutex_unlock(&chip->mutex);
1286 u8 zd_chip_get_channel(struct zd_chip *chip)
1290 mutex_lock(&chip->mutex);
1291 channel = chip->rf.channel;
1292 mutex_unlock(&chip->mutex);
1296 static u16 led_mask(int led)
1308 static int read_led_reg(struct zd_chip *chip, u16 *status)
1310 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1311 return zd_ioread16_locked(chip, status, CR_LED);
1314 static int write_led_reg(struct zd_chip *chip, u16 status)
1316 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1317 return zd_iowrite16_locked(chip, status, CR_LED);
1320 int zd_chip_led_status(struct zd_chip *chip, int led, enum led_status status)
1323 u16 mask = led_mask(led);
1328 mutex_lock(&chip->mutex);
1329 r = read_led_reg(chip, ®);
1334 return (reg & mask) ? LED_ON : LED_OFF;
1341 ret = (reg&mask) ? LED_ON : LED_OFF;
1350 r = write_led_reg(chip, reg);
1356 mutex_unlock(&chip->mutex);
1360 int zd_chip_led_flip(struct zd_chip *chip, int led,
1361 const unsigned int *phases_msecs, unsigned int count)
1364 enum led_status status;
1366 r = zd_chip_led_status(chip, led, LED_STATUS);
1370 for (i = 0; i < count; i++) {
1371 r = zd_chip_led_status(chip, led, LED_FLIP);
1374 msleep(phases_msecs[i]);
1378 zd_chip_led_status(chip, led, status);
1382 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1386 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1389 mutex_lock(&chip->mutex);
1390 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1391 mutex_unlock(&chip->mutex);
1395 static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
1397 static const u16 constants[] = {
1398 715, 655, 585, 540, 470, 410, 360, 315,
1399 270, 235, 205, 175, 150, 125, 105, 85,
1406 /* It seems that their quality parameter is somehow per signal
1407 * and is now transferred per bit.
1410 case ZD_OFDM_RATE_6M:
1411 case ZD_OFDM_RATE_12M:
1412 case ZD_OFDM_RATE_24M:
1415 case ZD_OFDM_RATE_9M:
1416 case ZD_OFDM_RATE_18M:
1417 case ZD_OFDM_RATE_36M:
1418 case ZD_OFDM_RATE_54M:
1422 case ZD_OFDM_RATE_48M:
1430 x = (10000 * status_quality)/size;
1431 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1432 if (x > constants[i])
1439 static unsigned int log10times100(unsigned int x)
1441 static const u8 log10[] = {
1443 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1444 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1445 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1446 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1447 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1448 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1449 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1450 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1451 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1452 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1453 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1454 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1455 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1456 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1457 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1458 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1459 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1460 223, 223, 223, 224, 224, 224, 224,
1463 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1467 MAX_CCK_EVM_DB = 45,
1470 static int cck_evm_db(u8 status_quality)
1472 return (20 * log10times100(status_quality)) / 100;
1475 static int cck_snr_db(u8 status_quality)
1477 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1482 static int rx_qual_db(const void *rx_frame, unsigned int size,
1483 const struct rx_status *status)
1485 return (status->frame_status&ZD_RX_OFDM) ?
1486 ofdm_qual_db(status->signal_quality_ofdm,
1487 zd_ofdm_plcp_header_rate(rx_frame),
1489 cck_snr_db(status->signal_quality_cck);
1492 u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1493 const struct rx_status *status)
1495 int r = rx_qual_db(rx_frame, size, status);
1504 u8 zd_rx_strength_percent(u8 rssi)
1506 int r = (rssi*100) / 30;
1512 u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1514 static const u16 ofdm_rates[] = {
1515 [ZD_OFDM_RATE_6M] = 60,
1516 [ZD_OFDM_RATE_9M] = 90,
1517 [ZD_OFDM_RATE_12M] = 120,
1518 [ZD_OFDM_RATE_18M] = 180,
1519 [ZD_OFDM_RATE_24M] = 240,
1520 [ZD_OFDM_RATE_36M] = 360,
1521 [ZD_OFDM_RATE_48M] = 480,
1522 [ZD_OFDM_RATE_54M] = 540,
1525 if (status->frame_status & ZD_RX_OFDM) {
1526 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1527 rate = ofdm_rates[ofdm_rate & 0xf];
1529 u8 cck_rate = zd_cck_plcp_header_rate(rx_frame);
1531 case ZD_CCK_SIGNAL_1M:
1534 case ZD_CCK_SIGNAL_2M:
1537 case ZD_CCK_SIGNAL_5M5:
1540 case ZD_CCK_SIGNAL_11M:
1551 int zd_chip_switch_radio_on(struct zd_chip *chip)
1555 mutex_lock(&chip->mutex);
1556 r = zd_switch_radio_on(&chip->rf);
1557 mutex_unlock(&chip->mutex);
1561 int zd_chip_switch_radio_off(struct zd_chip *chip)
1565 mutex_lock(&chip->mutex);
1566 r = zd_switch_radio_off(&chip->rf);
1567 mutex_unlock(&chip->mutex);
1571 int zd_chip_enable_int(struct zd_chip *chip)
1575 mutex_lock(&chip->mutex);
1576 r = zd_usb_enable_int(&chip->usb);
1577 mutex_unlock(&chip->mutex);
1581 void zd_chip_disable_int(struct zd_chip *chip)
1583 mutex_lock(&chip->mutex);
1584 zd_usb_disable_int(&chip->usb);
1585 mutex_unlock(&chip->mutex);
1588 int zd_chip_enable_rx(struct zd_chip *chip)
1592 mutex_lock(&chip->mutex);
1593 r = zd_usb_enable_rx(&chip->usb);
1594 mutex_unlock(&chip->mutex);
1598 void zd_chip_disable_rx(struct zd_chip *chip)
1600 mutex_lock(&chip->mutex);
1601 zd_usb_disable_rx(&chip->usb);
1602 mutex_unlock(&chip->mutex);
1605 int zd_rfwritev_locked(struct zd_chip *chip,
1606 const u32* values, unsigned int count, u8 bits)
1611 for (i = 0; i < count; i++) {
1612 r = zd_rfwrite_locked(chip, values[i], bits);