3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
55 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
56 MODULE_AUTHOR("Martin Langer");
57 MODULE_AUTHOR("Stefano Brivio");
58 MODULE_AUTHOR("Michael Buesch");
59 MODULE_LICENSE("GPL");
61 extern char *nvram_get(char *name);
63 #if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
64 static int modparam_pio;
65 module_param_named(pio, modparam_pio, int, 0444);
66 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
67 #elif defined(CONFIG_B43_DMA)
68 # define modparam_pio 0
69 #elif defined(CONFIG_B43_PIO)
70 # define modparam_pio 1
73 static int modparam_bad_frames_preempt;
74 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
75 MODULE_PARM_DESC(bad_frames_preempt,
76 "enable(1) / disable(0) Bad Frames Preemption");
78 static char modparam_fwpostfix[16];
79 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
80 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
82 static int modparam_hwpctl;
83 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
84 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
86 static int modparam_nohwcrypt;
87 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
88 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
90 static const struct ssb_device_id b43_ssb_tbl[] = {
91 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
92 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
99 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
101 /* Channel and ratetables are shared for all devices.
102 * They can't be const, because ieee80211 puts some precalculated
103 * data in there. This data is the same for all devices, so we don't
104 * get concurrency issues */
105 #define RATETAB_ENT(_rateid, _flags) \
107 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 static struct ieee80211_rate __b43_ratetable[] = {
113 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
114 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
115 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
116 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
117 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
118 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
119 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
120 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
121 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
122 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
123 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
124 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
127 #define b43_a_ratetable (__b43_ratetable + 4)
128 #define b43_a_ratetable_size 8
129 #define b43_b_ratetable (__b43_ratetable + 0)
130 #define b43_b_ratetable_size 4
131 #define b43_g_ratetable (__b43_ratetable + 0)
132 #define b43_g_ratetable_size 12
134 #define CHANTAB_ENT(_chanid, _freq) \
139 .flag = IEEE80211_CHAN_W_SCAN | \
140 IEEE80211_CHAN_W_ACTIVE_SCAN | \
141 IEEE80211_CHAN_W_IBSS, \
142 .power_level = 0xFF, \
143 .antenna_max = 0xFF, \
145 static struct ieee80211_channel b43_bg_chantable[] = {
146 CHANTAB_ENT(1, 2412),
147 CHANTAB_ENT(2, 2417),
148 CHANTAB_ENT(3, 2422),
149 CHANTAB_ENT(4, 2427),
150 CHANTAB_ENT(5, 2432),
151 CHANTAB_ENT(6, 2437),
152 CHANTAB_ENT(7, 2442),
153 CHANTAB_ENT(8, 2447),
154 CHANTAB_ENT(9, 2452),
155 CHANTAB_ENT(10, 2457),
156 CHANTAB_ENT(11, 2462),
157 CHANTAB_ENT(12, 2467),
158 CHANTAB_ENT(13, 2472),
159 CHANTAB_ENT(14, 2484),
162 #define b43_bg_chantable_size ARRAY_SIZE(b43_bg_chantable)
163 static struct ieee80211_channel b43_a_chantable[] = {
164 CHANTAB_ENT(36, 5180),
165 CHANTAB_ENT(40, 5200),
166 CHANTAB_ENT(44, 5220),
167 CHANTAB_ENT(48, 5240),
168 CHANTAB_ENT(52, 5260),
169 CHANTAB_ENT(56, 5280),
170 CHANTAB_ENT(60, 5300),
171 CHANTAB_ENT(64, 5320),
172 CHANTAB_ENT(149, 5745),
173 CHANTAB_ENT(153, 5765),
174 CHANTAB_ENT(157, 5785),
175 CHANTAB_ENT(161, 5805),
176 CHANTAB_ENT(165, 5825),
179 #define b43_a_chantable_size ARRAY_SIZE(b43_a_chantable)
181 static void b43_wireless_core_exit(struct b43_wldev *dev);
182 static int b43_wireless_core_init(struct b43_wldev *dev);
183 static void b43_wireless_core_stop(struct b43_wldev *dev);
184 static int b43_wireless_core_start(struct b43_wldev *dev);
186 static int b43_ratelimit(struct b43_wl *wl)
188 if (!wl || !wl->current_dev)
190 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
192 /* We are up and running.
193 * Ratelimit the messages to avoid DoS over the net. */
194 return net_ratelimit();
197 void b43info(struct b43_wl *wl, const char *fmt, ...)
201 if (!b43_ratelimit(wl))
204 printk(KERN_INFO "b43-%s: ",
205 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
210 void b43err(struct b43_wl *wl, const char *fmt, ...)
214 if (!b43_ratelimit(wl))
217 printk(KERN_ERR "b43-%s ERROR: ",
218 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
223 void b43warn(struct b43_wl *wl, const char *fmt, ...)
227 if (!b43_ratelimit(wl))
230 printk(KERN_WARNING "b43-%s warning: ",
231 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
237 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
242 printk(KERN_DEBUG "b43-%s debug: ",
243 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
249 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
253 B43_WARN_ON(offset % 4 != 0);
255 macctl = b43_read32(dev, B43_MMIO_MACCTL);
256 if (macctl & B43_MACCTL_BE)
259 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
261 b43_write32(dev, B43_MMIO_RAM_DATA, val);
265 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
269 /* "offset" is the WORD offset. */
274 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
277 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
281 if (routing == B43_SHM_SHARED) {
282 B43_WARN_ON(offset & 0x0001);
283 if (offset & 0x0003) {
284 /* Unaligned access */
285 b43_shm_control_word(dev, routing, offset >> 2);
286 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
288 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
289 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
295 b43_shm_control_word(dev, routing, offset);
296 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
301 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
305 if (routing == B43_SHM_SHARED) {
306 B43_WARN_ON(offset & 0x0001);
307 if (offset & 0x0003) {
308 /* Unaligned access */
309 b43_shm_control_word(dev, routing, offset >> 2);
310 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
316 b43_shm_control_word(dev, routing, offset);
317 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
322 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
324 if (routing == B43_SHM_SHARED) {
325 B43_WARN_ON(offset & 0x0001);
326 if (offset & 0x0003) {
327 /* Unaligned access */
328 b43_shm_control_word(dev, routing, offset >> 2);
330 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
331 (value >> 16) & 0xffff);
333 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
335 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
340 b43_shm_control_word(dev, routing, offset);
342 b43_write32(dev, B43_MMIO_SHM_DATA, value);
345 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
347 if (routing == B43_SHM_SHARED) {
348 B43_WARN_ON(offset & 0x0001);
349 if (offset & 0x0003) {
350 /* Unaligned access */
351 b43_shm_control_word(dev, routing, offset >> 2);
353 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
358 b43_shm_control_word(dev, routing, offset);
360 b43_write16(dev, B43_MMIO_SHM_DATA, value);
364 u32 b43_hf_read(struct b43_wldev * dev)
368 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
370 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
375 /* Write HostFlags */
376 void b43_hf_write(struct b43_wldev *dev, u32 value)
378 b43_shm_write16(dev, B43_SHM_SHARED,
379 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
380 b43_shm_write16(dev, B43_SHM_SHARED,
381 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
384 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
386 /* We need to be careful. As we read the TSF from multiple
387 * registers, we should take care of register overflows.
388 * In theory, the whole tsf read process should be atomic.
389 * We try to be atomic here, by restaring the read process,
390 * if any of the high registers changed (overflew).
392 if (dev->dev->id.revision >= 3) {
393 u32 low, high, high2;
396 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
397 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
398 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
399 } while (unlikely(high != high2));
407 u16 test1, test2, test3;
410 v3 = b43_read16(dev, B43_MMIO_TSF_3);
411 v2 = b43_read16(dev, B43_MMIO_TSF_2);
412 v1 = b43_read16(dev, B43_MMIO_TSF_1);
413 v0 = b43_read16(dev, B43_MMIO_TSF_0);
415 test3 = b43_read16(dev, B43_MMIO_TSF_3);
416 test2 = b43_read16(dev, B43_MMIO_TSF_2);
417 test1 = b43_read16(dev, B43_MMIO_TSF_1);
418 } while (v3 != test3 || v2 != test2 || v1 != test1);
432 static void b43_time_lock(struct b43_wldev *dev)
436 macctl = b43_read32(dev, B43_MMIO_MACCTL);
437 macctl |= B43_MACCTL_TBTTHOLD;
438 b43_write32(dev, B43_MMIO_MACCTL, macctl);
439 /* Commit the write */
440 b43_read32(dev, B43_MMIO_MACCTL);
443 static void b43_time_unlock(struct b43_wldev *dev)
447 macctl = b43_read32(dev, B43_MMIO_MACCTL);
448 macctl &= ~B43_MACCTL_TBTTHOLD;
449 b43_write32(dev, B43_MMIO_MACCTL, macctl);
450 /* Commit the write */
451 b43_read32(dev, B43_MMIO_MACCTL);
454 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
456 /* Be careful with the in-progress timer.
457 * First zero out the low register, so we have a full
458 * register-overflow duration to complete the operation.
460 if (dev->dev->id.revision >= 3) {
461 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
462 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
464 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
466 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
468 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
470 u16 v0 = (tsf & 0x000000000000FFFFULL);
471 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
472 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
473 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
475 b43_write16(dev, B43_MMIO_TSF_0, 0);
477 b43_write16(dev, B43_MMIO_TSF_3, v3);
479 b43_write16(dev, B43_MMIO_TSF_2, v2);
481 b43_write16(dev, B43_MMIO_TSF_1, v1);
483 b43_write16(dev, B43_MMIO_TSF_0, v0);
487 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
490 b43_tsf_write_locked(dev, tsf);
491 b43_time_unlock(dev);
495 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
497 static const u8 zero_addr[ETH_ALEN] = { 0 };
504 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
508 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
511 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
514 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
517 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
521 u8 mac_bssid[ETH_ALEN * 2];
525 bssid = dev->wl->bssid;
526 mac = dev->wl->mac_addr;
528 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
530 memcpy(mac_bssid, mac, ETH_ALEN);
531 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
533 /* Write our MAC address and BSSID to template ram */
534 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
535 tmp = (u32) (mac_bssid[i + 0]);
536 tmp |= (u32) (mac_bssid[i + 1]) << 8;
537 tmp |= (u32) (mac_bssid[i + 2]) << 16;
538 tmp |= (u32) (mac_bssid[i + 3]) << 24;
539 b43_ram_write(dev, 0x20 + i, tmp);
543 static void b43_upload_card_macaddress(struct b43_wldev *dev)
545 b43_write_mac_bssid_templates(dev);
546 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
549 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
551 /* slot_time is in usec. */
552 if (dev->phy.type != B43_PHYTYPE_G)
554 b43_write16(dev, 0x684, 510 + slot_time);
555 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
558 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
560 b43_set_slot_time(dev, 9);
564 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
566 b43_set_slot_time(dev, 20);
570 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
571 * Returns the _previously_ enabled IRQ mask.
573 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
577 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
578 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
583 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
584 * Returns the _previously_ enabled IRQ mask.
586 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
590 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
591 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
596 /* Synchronize IRQ top- and bottom-half.
597 * IRQs must be masked before calling this.
598 * This must not be called with the irq_lock held.
600 static void b43_synchronize_irq(struct b43_wldev *dev)
602 synchronize_irq(dev->dev->irq);
603 tasklet_kill(&dev->isr_tasklet);
606 /* DummyTransmission function, as documented on
607 * http://bcm-specs.sipsolutions.net/DummyTransmission
609 void b43_dummy_transmission(struct b43_wldev *dev)
611 struct b43_phy *phy = &dev->phy;
612 unsigned int i, max_loop;
625 buffer[0] = 0x000201CC;
630 buffer[0] = 0x000B846E;
637 for (i = 0; i < 5; i++)
638 b43_ram_write(dev, i * 4, buffer[i]);
641 b43_read32(dev, B43_MMIO_MACCTL);
643 b43_write16(dev, 0x0568, 0x0000);
644 b43_write16(dev, 0x07C0, 0x0000);
645 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
646 b43_write16(dev, 0x050C, value);
647 b43_write16(dev, 0x0508, 0x0000);
648 b43_write16(dev, 0x050A, 0x0000);
649 b43_write16(dev, 0x054C, 0x0000);
650 b43_write16(dev, 0x056A, 0x0014);
651 b43_write16(dev, 0x0568, 0x0826);
652 b43_write16(dev, 0x0500, 0x0000);
653 b43_write16(dev, 0x0502, 0x0030);
655 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
656 b43_radio_write16(dev, 0x0051, 0x0017);
657 for (i = 0x00; i < max_loop; i++) {
658 value = b43_read16(dev, 0x050E);
663 for (i = 0x00; i < 0x0A; i++) {
664 value = b43_read16(dev, 0x050E);
669 for (i = 0x00; i < 0x0A; i++) {
670 value = b43_read16(dev, 0x0690);
671 if (!(value & 0x0100))
675 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
676 b43_radio_write16(dev, 0x0051, 0x0037);
679 static void key_write(struct b43_wldev *dev,
680 u8 index, u8 algorithm, const u8 * key)
687 /* Key index/algo block */
688 kidx = b43_kidx_to_fw(dev, index);
689 value = ((kidx << 4) | algorithm);
690 b43_shm_write16(dev, B43_SHM_SHARED,
691 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
693 /* Write the key to the Key Table Pointer offset */
694 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
695 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
697 value |= (u16) (key[i + 1]) << 8;
698 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
702 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
704 u32 addrtmp[2] = { 0, 0, };
705 u8 per_sta_keys_start = 8;
707 if (b43_new_kidx_api(dev))
708 per_sta_keys_start = 4;
710 B43_WARN_ON(index < per_sta_keys_start);
711 /* We have two default TX keys and possibly two default RX keys.
712 * Physical mac 0 is mapped to physical key 4 or 8, depending
713 * on the firmware version.
714 * So we must adjust the index here.
716 index -= per_sta_keys_start;
719 addrtmp[0] = addr[0];
720 addrtmp[0] |= ((u32) (addr[1]) << 8);
721 addrtmp[0] |= ((u32) (addr[2]) << 16);
722 addrtmp[0] |= ((u32) (addr[3]) << 24);
723 addrtmp[1] = addr[4];
724 addrtmp[1] |= ((u32) (addr[5]) << 8);
727 if (dev->dev->id.revision >= 5) {
728 /* Receive match transmitter address mechanism */
729 b43_shm_write32(dev, B43_SHM_RCMTA,
730 (index * 2) + 0, addrtmp[0]);
731 b43_shm_write16(dev, B43_SHM_RCMTA,
732 (index * 2) + 1, addrtmp[1]);
734 /* RXE (Receive Engine) and
735 * PSM (Programmable State Machine) mechanism
738 /* TODO write to RCM 16, 19, 22 and 25 */
740 b43_shm_write32(dev, B43_SHM_SHARED,
741 B43_SHM_SH_PSM + (index * 6) + 0,
743 b43_shm_write16(dev, B43_SHM_SHARED,
744 B43_SHM_SH_PSM + (index * 6) + 4,
750 static void do_key_write(struct b43_wldev *dev,
751 u8 index, u8 algorithm,
752 const u8 * key, size_t key_len, const u8 * mac_addr)
754 u8 buf[B43_SEC_KEYSIZE] = { 0, };
755 u8 per_sta_keys_start = 8;
757 if (b43_new_kidx_api(dev))
758 per_sta_keys_start = 4;
760 B43_WARN_ON(index >= dev->max_nr_keys);
761 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
763 if (index >= per_sta_keys_start)
764 keymac_write(dev, index, NULL); /* First zero out mac. */
766 memcpy(buf, key, key_len);
767 key_write(dev, index, algorithm, buf);
768 if (index >= per_sta_keys_start)
769 keymac_write(dev, index, mac_addr);
771 dev->key[index].algorithm = algorithm;
774 static int b43_key_write(struct b43_wldev *dev,
775 int index, u8 algorithm,
776 const u8 * key, size_t key_len,
778 struct ieee80211_key_conf *keyconf)
783 if (key_len > B43_SEC_KEYSIZE)
785 for (i = 0; i < dev->max_nr_keys; i++) {
786 /* Check that we don't already have this key. */
787 B43_WARN_ON(dev->key[i].keyconf == keyconf);
790 /* Either pairwise key or address is 00:00:00:00:00:00
791 * for transmit-only keys. Search the index. */
792 if (b43_new_kidx_api(dev))
796 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
797 if (!dev->key[i].keyconf) {
804 b43err(dev->wl, "Out of hardware key memory\n");
808 B43_WARN_ON(index > 3);
810 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
811 if ((index <= 3) && !b43_new_kidx_api(dev)) {
813 B43_WARN_ON(mac_addr);
814 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
816 keyconf->hw_key_idx = index;
817 dev->key[index].keyconf = keyconf;
822 static int b43_key_clear(struct b43_wldev *dev, int index)
824 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
826 do_key_write(dev, index, B43_SEC_ALGO_NONE,
827 NULL, B43_SEC_KEYSIZE, NULL);
828 if ((index <= 3) && !b43_new_kidx_api(dev)) {
829 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
830 NULL, B43_SEC_KEYSIZE, NULL);
832 dev->key[index].keyconf = NULL;
837 static void b43_clear_keys(struct b43_wldev *dev)
841 for (i = 0; i < dev->max_nr_keys; i++)
842 b43_key_clear(dev, i);
845 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
853 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
854 (ps_flags & B43_PS_DISABLED));
855 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
857 if (ps_flags & B43_PS_ENABLED) {
859 } else if (ps_flags & B43_PS_DISABLED) {
862 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
863 // and thus is not an AP and we are associated, set bit 25
865 if (ps_flags & B43_PS_AWAKE) {
867 } else if (ps_flags & B43_PS_ASLEEP) {
870 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
871 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
872 // successful, set bit26
875 /* FIXME: For now we force awake-on and hwps-off */
879 macctl = b43_read32(dev, B43_MMIO_MACCTL);
881 macctl |= B43_MACCTL_HWPS;
883 macctl &= ~B43_MACCTL_HWPS;
885 macctl |= B43_MACCTL_AWAKE;
887 macctl &= ~B43_MACCTL_AWAKE;
888 b43_write32(dev, B43_MMIO_MACCTL, macctl);
890 b43_read32(dev, B43_MMIO_MACCTL);
891 if (awake && dev->dev->id.revision >= 5) {
892 /* Wait for the microcode to wake up. */
893 for (i = 0; i < 100; i++) {
894 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
895 B43_SHM_SH_UCODESTAT);
896 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
903 /* Turn the Analog ON/OFF */
904 static void b43_switch_analog(struct b43_wldev *dev, int on)
906 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
909 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
914 flags |= B43_TMSLOW_PHYCLKEN;
915 flags |= B43_TMSLOW_PHYRESET;
916 ssb_device_enable(dev->dev, flags);
917 msleep(2); /* Wait for the PLL to turn on. */
919 /* Now take the PHY out of Reset again */
920 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
921 tmslow |= SSB_TMSLOW_FGC;
922 tmslow &= ~B43_TMSLOW_PHYRESET;
923 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
924 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
926 tmslow &= ~SSB_TMSLOW_FGC;
927 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
928 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
932 b43_switch_analog(dev, 1);
934 macctl = b43_read32(dev, B43_MMIO_MACCTL);
935 macctl &= ~B43_MACCTL_GMODE;
936 if (flags & B43_TMSLOW_GMODE)
937 macctl |= B43_MACCTL_GMODE;
938 macctl |= B43_MACCTL_IHR_ENABLED;
939 b43_write32(dev, B43_MMIO_MACCTL, macctl);
942 static void handle_irq_transmit_status(struct b43_wldev *dev)
946 struct b43_txstatus stat;
949 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
950 if (!(v0 & 0x00000001))
952 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
954 stat.cookie = (v0 >> 16);
955 stat.seq = (v1 & 0x0000FFFF);
956 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
957 tmp = (v0 & 0x0000FFFF);
958 stat.frame_count = ((tmp & 0xF000) >> 12);
959 stat.rts_count = ((tmp & 0x0F00) >> 8);
960 stat.supp_reason = ((tmp & 0x001C) >> 2);
961 stat.pm_indicated = !!(tmp & 0x0080);
962 stat.intermediate = !!(tmp & 0x0040);
963 stat.for_ampdu = !!(tmp & 0x0020);
964 stat.acked = !!(tmp & 0x0002);
966 b43_handle_txstatus(dev, &stat);
970 static void drain_txstatus_queue(struct b43_wldev *dev)
974 if (dev->dev->id.revision < 5)
976 /* Read all entries from the microcode TXstatus FIFO
977 * and throw them away.
980 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
981 if (!(dummy & 0x00000001))
983 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
987 static u32 b43_jssi_read(struct b43_wldev *dev)
991 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
993 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
998 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1000 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1001 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1004 static void b43_generate_noise_sample(struct b43_wldev *dev)
1006 b43_jssi_write(dev, 0x7F7F7F7F);
1007 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1008 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1010 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1013 static void b43_calculate_link_quality(struct b43_wldev *dev)
1015 /* Top half of Link Quality calculation. */
1017 if (dev->noisecalc.calculation_running)
1019 dev->noisecalc.channel_at_start = dev->phy.channel;
1020 dev->noisecalc.calculation_running = 1;
1021 dev->noisecalc.nr_samples = 0;
1023 b43_generate_noise_sample(dev);
1026 static void handle_irq_noise(struct b43_wldev *dev)
1028 struct b43_phy *phy = &dev->phy;
1034 /* Bottom half of Link Quality calculation. */
1036 B43_WARN_ON(!dev->noisecalc.calculation_running);
1037 if (dev->noisecalc.channel_at_start != phy->channel)
1038 goto drop_calculation;
1039 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1040 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1041 noise[2] == 0x7F || noise[3] == 0x7F)
1044 /* Get the noise samples. */
1045 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1046 i = dev->noisecalc.nr_samples;
1047 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1048 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1049 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1050 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1051 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1052 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1053 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1054 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1055 dev->noisecalc.nr_samples++;
1056 if (dev->noisecalc.nr_samples == 8) {
1057 /* Calculate the Link Quality by the noise samples. */
1059 for (i = 0; i < 8; i++) {
1060 for (j = 0; j < 4; j++)
1061 average += dev->noisecalc.samples[i][j];
1067 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1068 tmp = (tmp / 128) & 0x1F;
1078 dev->stats.link_noise = average;
1080 dev->noisecalc.calculation_running = 0;
1084 b43_generate_noise_sample(dev);
1087 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1089 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1092 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1093 b43_power_saving_ctl_bits(dev, 0);
1095 dev->reg124_set_0x4 = 0;
1096 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1097 dev->reg124_set_0x4 = 1;
1100 static void handle_irq_atim_end(struct b43_wldev *dev)
1102 if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
1104 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1105 b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1109 static void handle_irq_pmq(struct b43_wldev *dev)
1116 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1117 if (!(tmp & 0x00000008))
1120 /* 16bit write is odd, but correct. */
1121 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1124 static void b43_write_template_common(struct b43_wldev *dev,
1125 const u8 * data, u16 size,
1127 u16 shm_size_offset, u8 rate)
1130 struct b43_plcp_hdr4 plcp;
1133 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1134 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1135 ram_offset += sizeof(u32);
1136 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1137 * So leave the first two bytes of the next write blank.
1139 tmp = (u32) (data[0]) << 16;
1140 tmp |= (u32) (data[1]) << 24;
1141 b43_ram_write(dev, ram_offset, tmp);
1142 ram_offset += sizeof(u32);
1143 for (i = 2; i < size; i += sizeof(u32)) {
1144 tmp = (u32) (data[i + 0]);
1146 tmp |= (u32) (data[i + 1]) << 8;
1148 tmp |= (u32) (data[i + 2]) << 16;
1150 tmp |= (u32) (data[i + 3]) << 24;
1151 b43_ram_write(dev, ram_offset + i - 2, tmp);
1153 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1154 size + sizeof(struct b43_plcp_hdr6));
1157 static void b43_write_beacon_template(struct b43_wldev *dev,
1159 u16 shm_size_offset, u8 rate)
1164 B43_WARN_ON(!dev->cached_beacon);
1165 len = min((size_t) dev->cached_beacon->len,
1166 0x200 - sizeof(struct b43_plcp_hdr6));
1167 data = (const u8 *)(dev->cached_beacon->data);
1168 b43_write_template_common(dev, data,
1169 len, ram_offset, shm_size_offset, rate);
1172 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1173 u16 shm_offset, u16 size, u8 rate)
1175 struct b43_plcp_hdr4 plcp;
1180 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1181 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1182 dev->wl->if_id, size,
1183 B43_RATE_TO_BASE100KBPS(rate));
1184 /* Write PLCP in two parts and timing for packet transfer */
1185 tmp = le32_to_cpu(plcp.data);
1186 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1187 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1188 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1191 /* Instead of using custom probe response template, this function
1192 * just patches custom beacon template by:
1193 * 1) Changing packet type
1194 * 2) Patching duration field
1197 static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1198 u16 * dest_size, u8 rate)
1202 u16 src_size, elem_size, src_pos, dest_pos;
1204 struct ieee80211_hdr *hdr;
1206 B43_WARN_ON(!dev->cached_beacon);
1207 src_size = dev->cached_beacon->len;
1208 src_data = (const u8 *)dev->cached_beacon->data;
1210 if (unlikely(src_size < 0x24)) {
1211 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1215 dest_data = kmalloc(src_size, GFP_ATOMIC);
1216 if (unlikely(!dest_data))
1219 /* 0x24 is offset of first variable-len Information-Element
1222 memcpy(dest_data, src_data, 0x24);
1223 src_pos = dest_pos = 0x24;
1224 for (; src_pos < src_size - 2; src_pos += elem_size) {
1225 elem_size = src_data[src_pos + 1] + 2;
1226 if (src_data[src_pos] != 0x05) { /* TIM */
1227 memcpy(dest_data + dest_pos, src_data + src_pos,
1229 dest_pos += elem_size;
1232 *dest_size = dest_pos;
1233 hdr = (struct ieee80211_hdr *)dest_data;
1235 /* Set the frame control. */
1236 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1237 IEEE80211_STYPE_PROBE_RESP);
1238 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1239 dev->wl->if_id, *dest_size,
1240 B43_RATE_TO_BASE100KBPS(rate));
1241 hdr->duration_id = dur;
1246 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1248 u16 shm_size_offset, u8 rate)
1250 u8 *probe_resp_data;
1253 B43_WARN_ON(!dev->cached_beacon);
1254 size = dev->cached_beacon->len;
1255 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1256 if (unlikely(!probe_resp_data))
1259 /* Looks like PLCP headers plus packet timings are stored for
1260 * all possible basic rates
1262 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1263 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1264 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1265 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1267 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1268 b43_write_template_common(dev, probe_resp_data,
1269 size, ram_offset, shm_size_offset, rate);
1270 kfree(probe_resp_data);
1273 static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1274 struct sk_buff *beacon)
1276 if (dev->cached_beacon)
1277 kfree_skb(dev->cached_beacon);
1278 dev->cached_beacon = beacon;
1283 static void b43_update_templates(struct b43_wldev *dev)
1287 B43_WARN_ON(!dev->cached_beacon);
1289 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1290 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1291 b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1293 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1295 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1298 static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1302 err = b43_refresh_cached_beacon(dev, beacon);
1305 b43_update_templates(dev);
1308 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1313 len = min((u16) ssid_len, (u16) 0x100);
1314 for (i = 0; i < len; i += sizeof(u32)) {
1315 tmp = (u32) (ssid[i + 0]);
1317 tmp |= (u32) (ssid[i + 1]) << 8;
1319 tmp |= (u32) (ssid[i + 2]) << 16;
1321 tmp |= (u32) (ssid[i + 3]) << 24;
1322 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1324 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1327 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1330 if (dev->dev->id.revision >= 3) {
1331 b43_write32(dev, 0x188, (beacon_int << 16));
1333 b43_write16(dev, 0x606, (beacon_int >> 6));
1334 b43_write16(dev, 0x610, beacon_int);
1336 b43_time_unlock(dev);
1339 static void handle_irq_beacon(struct b43_wldev *dev)
1343 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1346 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1347 status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1349 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1350 /* ACK beacon IRQ. */
1351 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1352 dev->irq_savedstate |= B43_IRQ_BEACON;
1353 if (dev->cached_beacon)
1354 kfree_skb(dev->cached_beacon);
1355 dev->cached_beacon = NULL;
1358 if (!(status & 0x1)) {
1359 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1361 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1363 if (!(status & 0x2)) {
1364 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1366 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1370 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1375 /* Interrupt handler bottom-half */
1376 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1379 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1380 u32 merged_dma_reason = 0;
1382 unsigned long flags;
1384 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1386 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1388 reason = dev->irq_reason;
1389 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1390 dma_reason[i] = dev->dma_reason[i];
1391 merged_dma_reason |= dma_reason[i];
1394 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1395 b43err(dev->wl, "MAC transmission error\n");
1397 if (unlikely(reason & B43_IRQ_PHY_TXERR))
1398 b43err(dev->wl, "PHY transmission error\n");
1400 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1401 B43_DMAIRQ_NONFATALMASK))) {
1402 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1403 b43err(dev->wl, "Fatal DMA error: "
1404 "0x%08X, 0x%08X, 0x%08X, "
1405 "0x%08X, 0x%08X, 0x%08X\n",
1406 dma_reason[0], dma_reason[1],
1407 dma_reason[2], dma_reason[3],
1408 dma_reason[4], dma_reason[5]);
1409 b43_controller_restart(dev, "DMA error");
1411 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1414 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1415 b43err(dev->wl, "DMA error: "
1416 "0x%08X, 0x%08X, 0x%08X, "
1417 "0x%08X, 0x%08X, 0x%08X\n",
1418 dma_reason[0], dma_reason[1],
1419 dma_reason[2], dma_reason[3],
1420 dma_reason[4], dma_reason[5]);
1424 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1425 handle_irq_ucode_debug(dev);
1426 if (reason & B43_IRQ_TBTT_INDI)
1427 handle_irq_tbtt_indication(dev);
1428 if (reason & B43_IRQ_ATIM_END)
1429 handle_irq_atim_end(dev);
1430 if (reason & B43_IRQ_BEACON)
1431 handle_irq_beacon(dev);
1432 if (reason & B43_IRQ_PMQ)
1433 handle_irq_pmq(dev);
1434 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1436 if (reason & B43_IRQ_NOISESAMPLE_OK)
1437 handle_irq_noise(dev);
1439 /* Check the DMA reason registers for received data. */
1440 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1441 if (b43_using_pio(dev))
1442 b43_pio_rx(dev->pio.queue0);
1444 b43_dma_rx(dev->dma.rx_ring0);
1446 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1447 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1448 if (dma_reason[3] & B43_DMAIRQ_RX_DONE) {
1449 if (b43_using_pio(dev))
1450 b43_pio_rx(dev->pio.queue3);
1452 b43_dma_rx(dev->dma.rx_ring3);
1454 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1455 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1457 if (reason & B43_IRQ_TX_OK)
1458 handle_irq_transmit_status(dev);
1460 b43_interrupt_enable(dev, dev->irq_savedstate);
1462 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1465 static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx)
1469 rxctl = b43_read16(dev, base + B43_PIO_RXCTL);
1470 if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE)
1471 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE;
1473 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE;
1476 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1478 if (b43_using_pio(dev) &&
1479 (dev->dev->id.revision < 3) &&
1480 (!(reason & B43_IRQ_PIO_WORKAROUND))) {
1481 /* Apply a PIO specific workaround to the dma_reasons */
1482 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0);
1483 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1);
1484 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2);
1485 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3);
1488 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1490 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1491 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1492 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1493 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1494 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1495 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1498 /* Interrupt handler top-half */
1499 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1501 irqreturn_t ret = IRQ_NONE;
1502 struct b43_wldev *dev = dev_id;
1508 spin_lock(&dev->wl->irq_lock);
1510 if (b43_status(dev) < B43_STAT_STARTED)
1512 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1513 if (reason == 0xffffffff) /* shared IRQ */
1516 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1520 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1522 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1524 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1526 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1528 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1530 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1533 b43_interrupt_ack(dev, reason);
1534 /* disable all IRQs. They are enabled again in the bottom half. */
1535 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1536 /* save the reason code and call our bottom half. */
1537 dev->irq_reason = reason;
1538 tasklet_schedule(&dev->isr_tasklet);
1541 spin_unlock(&dev->wl->irq_lock);
1546 static void b43_release_firmware(struct b43_wldev *dev)
1548 release_firmware(dev->fw.ucode);
1549 dev->fw.ucode = NULL;
1550 release_firmware(dev->fw.pcm);
1552 release_firmware(dev->fw.initvals);
1553 dev->fw.initvals = NULL;
1554 release_firmware(dev->fw.initvals_band);
1555 dev->fw.initvals_band = NULL;
1558 static void b43_print_fw_helptext(struct b43_wl *wl)
1560 b43err(wl, "You must go to "
1561 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1562 "and download the correct firmware (version 4).\n");
1565 static int do_request_fw(struct b43_wldev *dev,
1567 const struct firmware **fw)
1569 char path[sizeof(modparam_fwpostfix) + 32];
1570 struct b43_fw_header *hdr;
1577 snprintf(path, ARRAY_SIZE(path),
1579 modparam_fwpostfix, name);
1580 err = request_firmware(fw, path, dev->dev->dev);
1582 b43err(dev->wl, "Firmware file \"%s\" not found "
1583 "or load failed.\n", path);
1586 if ((*fw)->size < sizeof(struct b43_fw_header))
1588 hdr = (struct b43_fw_header *)((*fw)->data);
1589 switch (hdr->type) {
1590 case B43_FW_TYPE_UCODE:
1591 case B43_FW_TYPE_PCM:
1592 size = be32_to_cpu(hdr->size);
1593 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1596 case B43_FW_TYPE_IV:
1607 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1611 static int b43_request_firmware(struct b43_wldev *dev)
1613 struct b43_firmware *fw = &dev->fw;
1614 const u8 rev = dev->dev->id.revision;
1615 const char *filename;
1619 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1621 if ((rev >= 5) && (rev <= 10))
1622 filename = "ucode5";
1623 else if ((rev >= 11) && (rev <= 12))
1624 filename = "ucode11";
1626 filename = "ucode13";
1629 err = do_request_fw(dev, filename, &fw->ucode);
1634 if ((rev >= 5) && (rev <= 10))
1640 err = do_request_fw(dev, filename, &fw->pcm);
1644 if (!fw->initvals) {
1645 switch (dev->phy.type) {
1647 if ((rev >= 5) && (rev <= 10)) {
1648 if (tmshigh & B43_TMSHIGH_GPHY)
1649 filename = "a0g1initvals5";
1651 filename = "a0g0initvals5";
1653 goto err_no_initvals;
1656 if ((rev >= 5) && (rev <= 10))
1657 filename = "b0g0initvals5";
1659 filename = "lp0initvals13";
1661 goto err_no_initvals;
1664 goto err_no_initvals;
1666 err = do_request_fw(dev, filename, &fw->initvals);
1670 if (!fw->initvals_band) {
1671 switch (dev->phy.type) {
1673 if ((rev >= 5) && (rev <= 10)) {
1674 if (tmshigh & B43_TMSHIGH_GPHY)
1675 filename = "a0g1bsinitvals5";
1677 filename = "a0g0bsinitvals5";
1678 } else if (rev >= 11)
1681 goto err_no_initvals;
1684 if ((rev >= 5) && (rev <= 10))
1685 filename = "b0g0bsinitvals5";
1689 goto err_no_initvals;
1692 goto err_no_initvals;
1694 err = do_request_fw(dev, filename, &fw->initvals_band);
1702 b43_print_fw_helptext(dev->wl);
1707 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1712 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1717 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1718 "core rev %u\n", dev->phy.type, rev);
1722 b43_release_firmware(dev);
1726 static int b43_upload_microcode(struct b43_wldev *dev)
1728 const size_t hdr_len = sizeof(struct b43_fw_header);
1730 unsigned int i, len;
1731 u16 fwrev, fwpatch, fwdate, fwtime;
1735 /* Upload Microcode. */
1736 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1737 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1738 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1739 for (i = 0; i < len; i++) {
1740 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1745 /* Upload PCM data. */
1746 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1747 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1748 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1749 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1750 /* No need for autoinc bit in SHM_HW */
1751 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1752 for (i = 0; i < len; i++) {
1753 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1758 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1759 b43_write32(dev, B43_MMIO_MACCTL,
1760 B43_MACCTL_PSM_RUN |
1761 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1763 /* Wait for the microcode to load and respond */
1766 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1767 if (tmp == B43_IRQ_MAC_SUSPENDED)
1771 b43err(dev->wl, "Microcode not responding\n");
1772 b43_print_fw_helptext(dev->wl);
1778 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1780 /* Get and check the revisions. */
1781 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1782 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1783 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1784 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1786 if (fwrev <= 0x128) {
1787 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1788 "binary drivers older than version 4.x is unsupported. "
1789 "You must upgrade your firmware files.\n");
1790 b43_print_fw_helptext(dev->wl);
1791 b43_write32(dev, B43_MMIO_MACCTL, 0);
1795 b43dbg(dev->wl, "Loading firmware version %u.%u "
1796 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1798 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1799 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1801 dev->fw.rev = fwrev;
1802 dev->fw.patch = fwpatch;
1808 static int b43_write_initvals(struct b43_wldev *dev,
1809 const struct b43_iv *ivals,
1813 const struct b43_iv *iv;
1818 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1820 for (i = 0; i < count; i++) {
1821 if (array_size < sizeof(iv->offset_size))
1823 array_size -= sizeof(iv->offset_size);
1824 offset = be16_to_cpu(iv->offset_size);
1825 bit32 = !!(offset & B43_IV_32BIT);
1826 offset &= B43_IV_OFFSET_MASK;
1827 if (offset >= 0x1000)
1832 if (array_size < sizeof(iv->data.d32))
1834 array_size -= sizeof(iv->data.d32);
1836 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1837 b43_write32(dev, offset, value);
1839 iv = (const struct b43_iv *)((const uint8_t *)iv +
1845 if (array_size < sizeof(iv->data.d16))
1847 array_size -= sizeof(iv->data.d16);
1849 value = be16_to_cpu(iv->data.d16);
1850 b43_write16(dev, offset, value);
1852 iv = (const struct b43_iv *)((const uint8_t *)iv +
1863 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1864 b43_print_fw_helptext(dev->wl);
1869 static int b43_upload_initvals(struct b43_wldev *dev)
1871 const size_t hdr_len = sizeof(struct b43_fw_header);
1872 const struct b43_fw_header *hdr;
1873 struct b43_firmware *fw = &dev->fw;
1874 const struct b43_iv *ivals;
1878 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1879 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1880 count = be32_to_cpu(hdr->size);
1881 err = b43_write_initvals(dev, ivals, count,
1882 fw->initvals->size - hdr_len);
1885 if (fw->initvals_band) {
1886 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1887 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1888 count = be32_to_cpu(hdr->size);
1889 err = b43_write_initvals(dev, ivals, count,
1890 fw->initvals_band->size - hdr_len);
1899 /* Initialize the GPIOs
1900 * http://bcm-specs.sipsolutions.net/GPIO
1902 static int b43_gpio_init(struct b43_wldev *dev)
1904 struct ssb_bus *bus = dev->dev->bus;
1905 struct ssb_device *gpiodev, *pcidev = NULL;
1908 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1909 & ~B43_MACCTL_GPOUTSMSK);
1911 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1916 if (dev->dev->bus->chip_id == 0x4301) {
1920 if (0 /* FIXME: conditional unknown */ ) {
1921 b43_write16(dev, B43_MMIO_GPIO_MASK,
1922 b43_read16(dev, B43_MMIO_GPIO_MASK)
1927 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL) {
1928 b43_write16(dev, B43_MMIO_GPIO_MASK,
1929 b43_read16(dev, B43_MMIO_GPIO_MASK)
1934 if (dev->dev->id.revision >= 2)
1935 mask |= 0x0010; /* FIXME: This is redundant. */
1937 #ifdef CONFIG_SSB_DRIVER_PCICORE
1938 pcidev = bus->pcicore.dev;
1940 gpiodev = bus->chipco.dev ? : pcidev;
1943 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1944 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1950 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1951 static void b43_gpio_cleanup(struct b43_wldev *dev)
1953 struct ssb_bus *bus = dev->dev->bus;
1954 struct ssb_device *gpiodev, *pcidev = NULL;
1956 #ifdef CONFIG_SSB_DRIVER_PCICORE
1957 pcidev = bus->pcicore.dev;
1959 gpiodev = bus->chipco.dev ? : pcidev;
1962 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1965 /* http://bcm-specs.sipsolutions.net/EnableMac */
1966 void b43_mac_enable(struct b43_wldev *dev)
1968 dev->mac_suspended--;
1969 B43_WARN_ON(dev->mac_suspended < 0);
1970 B43_WARN_ON(irqs_disabled());
1971 if (dev->mac_suspended == 0) {
1972 b43_write32(dev, B43_MMIO_MACCTL,
1973 b43_read32(dev, B43_MMIO_MACCTL)
1974 | B43_MACCTL_ENABLED);
1975 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1976 B43_IRQ_MAC_SUSPENDED);
1978 b43_read32(dev, B43_MMIO_MACCTL);
1979 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1980 b43_power_saving_ctl_bits(dev, 0);
1982 /* Re-enable IRQs. */
1983 spin_lock_irq(&dev->wl->irq_lock);
1984 b43_interrupt_enable(dev, dev->irq_savedstate);
1985 spin_unlock_irq(&dev->wl->irq_lock);
1989 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1990 void b43_mac_suspend(struct b43_wldev *dev)
1996 B43_WARN_ON(irqs_disabled());
1997 B43_WARN_ON(dev->mac_suspended < 0);
1999 if (dev->mac_suspended == 0) {
2000 /* Mask IRQs before suspending MAC. Otherwise
2001 * the MAC stays busy and won't suspend. */
2002 spin_lock_irq(&dev->wl->irq_lock);
2003 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2004 spin_unlock_irq(&dev->wl->irq_lock);
2005 b43_synchronize_irq(dev);
2006 dev->irq_savedstate = tmp;
2008 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2009 b43_write32(dev, B43_MMIO_MACCTL,
2010 b43_read32(dev, B43_MMIO_MACCTL)
2011 & ~B43_MACCTL_ENABLED);
2012 /* force pci to flush the write */
2013 b43_read32(dev, B43_MMIO_MACCTL);
2014 for (i = 40; i; i--) {
2015 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2016 if (tmp & B43_IRQ_MAC_SUSPENDED)
2020 b43err(dev->wl, "MAC suspend failed\n");
2023 dev->mac_suspended++;
2026 static void b43_adjust_opmode(struct b43_wldev *dev)
2028 struct b43_wl *wl = dev->wl;
2032 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2033 /* Reset status to STA infrastructure mode. */
2034 ctl &= ~B43_MACCTL_AP;
2035 ctl &= ~B43_MACCTL_KEEP_CTL;
2036 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2037 ctl &= ~B43_MACCTL_KEEP_BAD;
2038 ctl &= ~B43_MACCTL_PROMISC;
2039 ctl &= ~B43_MACCTL_BEACPROMISC;
2040 ctl |= B43_MACCTL_INFRA;
2042 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2043 ctl |= B43_MACCTL_AP;
2044 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2045 ctl &= ~B43_MACCTL_INFRA;
2047 if (wl->filter_flags & FIF_CONTROL)
2048 ctl |= B43_MACCTL_KEEP_CTL;
2049 if (wl->filter_flags & FIF_FCSFAIL)
2050 ctl |= B43_MACCTL_KEEP_BAD;
2051 if (wl->filter_flags & FIF_PLCPFAIL)
2052 ctl |= B43_MACCTL_KEEP_BADPLCP;
2053 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2054 ctl |= B43_MACCTL_PROMISC;
2055 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2056 ctl |= B43_MACCTL_BEACPROMISC;
2058 /* Workaround: On old hardware the HW-MAC-address-filter
2059 * doesn't work properly, so always run promisc in filter
2060 * it in software. */
2061 if (dev->dev->id.revision <= 4)
2062 ctl |= B43_MACCTL_PROMISC;
2064 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2067 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2068 if (dev->dev->bus->chip_id == 0x4306 &&
2069 dev->dev->bus->chip_rev == 3)
2074 b43_write16(dev, 0x612, cfp_pretbtt);
2077 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2083 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2086 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2088 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2089 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2092 static void b43_rate_memory_init(struct b43_wldev *dev)
2094 switch (dev->phy.type) {
2097 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2098 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2099 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2100 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2101 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2102 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2103 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2104 if (dev->phy.type == B43_PHYTYPE_A)
2108 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2109 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2110 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2111 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2118 /* Set the TX-Antenna for management frames sent by firmware. */
2119 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2126 ant |= B43_TX4_PHY_ANT0;
2129 ant |= B43_TX4_PHY_ANT1;
2131 case B43_ANTENNA_AUTO:
2132 ant |= B43_TX4_PHY_ANTLAST;
2138 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2141 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2142 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2143 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2145 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2146 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2147 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2148 /* For Probe Resposes */
2149 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2150 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2151 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2154 /* This is the opposite of b43_chip_init() */
2155 static void b43_chip_exit(struct b43_wldev *dev)
2157 b43_radio_turn_off(dev, 1);
2158 b43_gpio_cleanup(dev);
2159 /* firmware is released later */
2162 /* Initialize the chip
2163 * http://bcm-specs.sipsolutions.net/ChipInit
2165 static int b43_chip_init(struct b43_wldev *dev)
2167 struct b43_phy *phy = &dev->phy;
2172 b43_write32(dev, B43_MMIO_MACCTL,
2173 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2175 err = b43_request_firmware(dev);
2178 err = b43_upload_microcode(dev);
2180 goto out; /* firmware is released later */
2182 err = b43_gpio_init(dev);
2184 goto out; /* firmware is released later */
2186 err = b43_upload_initvals(dev);
2188 goto err_gpio_clean;
2189 b43_radio_turn_on(dev);
2191 b43_write16(dev, 0x03E6, 0x0000);
2192 err = b43_phy_init(dev);
2196 /* Select initial Interference Mitigation. */
2197 tmp = phy->interfmode;
2198 phy->interfmode = B43_INTERFMODE_NONE;
2199 b43_radio_set_interference_mitigation(dev, tmp);
2201 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2202 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2204 if (phy->type == B43_PHYTYPE_B) {
2205 value16 = b43_read16(dev, 0x005E);
2207 b43_write16(dev, 0x005E, value16);
2209 b43_write32(dev, 0x0100, 0x01000000);
2210 if (dev->dev->id.revision < 5)
2211 b43_write32(dev, 0x010C, 0x01000000);
2213 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2214 & ~B43_MACCTL_INFRA);
2215 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2216 | B43_MACCTL_INFRA);
2218 if (b43_using_pio(dev)) {
2219 b43_write32(dev, 0x0210, 0x00000100);
2220 b43_write32(dev, 0x0230, 0x00000100);
2221 b43_write32(dev, 0x0250, 0x00000100);
2222 b43_write32(dev, 0x0270, 0x00000100);
2223 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000);
2226 /* Probe Response Timeout value */
2227 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2228 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2230 /* Initially set the wireless operation mode. */
2231 b43_adjust_opmode(dev);
2233 if (dev->dev->id.revision < 3) {
2234 b43_write16(dev, 0x060E, 0x0000);
2235 b43_write16(dev, 0x0610, 0x8000);
2236 b43_write16(dev, 0x0604, 0x0000);
2237 b43_write16(dev, 0x0606, 0x0200);
2239 b43_write32(dev, 0x0188, 0x80000000);
2240 b43_write32(dev, 0x018C, 0x02000000);
2242 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2243 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2244 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2245 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2246 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2247 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2248 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2250 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2251 value32 |= 0x00100000;
2252 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2254 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2255 dev->dev->bus->chipco.fast_pwrup_delay);
2258 b43dbg(dev->wl, "Chip initialized\n");
2263 b43_radio_turn_off(dev, 1);
2265 b43_gpio_cleanup(dev);
2269 static void b43_periodic_every120sec(struct b43_wldev *dev)
2271 struct b43_phy *phy = &dev->phy;
2273 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2276 b43_mac_suspend(dev);
2277 b43_lo_g_measure(dev);
2278 b43_mac_enable(dev);
2279 if (b43_has_hardware_pctl(phy))
2280 b43_lo_g_ctl_mark_all_unused(dev);
2283 static void b43_periodic_every60sec(struct b43_wldev *dev)
2285 struct b43_phy *phy = &dev->phy;
2287 if (!b43_has_hardware_pctl(phy))
2288 b43_lo_g_ctl_mark_all_unused(dev);
2289 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
2290 b43_mac_suspend(dev);
2291 b43_calc_nrssi_slope(dev);
2292 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2293 u8 old_chan = phy->channel;
2295 /* VCO Calibration */
2297 b43_radio_selectchannel(dev, 1, 0);
2299 b43_radio_selectchannel(dev, 13, 0);
2300 b43_radio_selectchannel(dev, old_chan, 0);
2302 b43_mac_enable(dev);
2306 static void b43_periodic_every30sec(struct b43_wldev *dev)
2308 /* Update device statistics. */
2309 b43_calculate_link_quality(dev);
2312 static void b43_periodic_every15sec(struct b43_wldev *dev)
2314 struct b43_phy *phy = &dev->phy;
2316 if (phy->type == B43_PHYTYPE_G) {
2317 //TODO: update_aci_moving_average
2318 if (phy->aci_enable && phy->aci_wlan_automatic) {
2319 b43_mac_suspend(dev);
2320 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2321 if (0 /*TODO: bunch of conditions */ ) {
2322 b43_radio_set_interference_mitigation
2323 (dev, B43_INTERFMODE_MANUALWLAN);
2325 } else if (1 /*TODO*/) {
2327 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2328 b43_radio_set_interference_mitigation(dev,
2329 B43_INTERFMODE_NONE);
2333 b43_mac_enable(dev);
2334 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2336 //TODO: implement rev1 workaround
2339 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2340 //TODO for APHY (temperature?)
2343 static void do_periodic_work(struct b43_wldev *dev)
2347 state = dev->periodic_state;
2349 b43_periodic_every120sec(dev);
2351 b43_periodic_every60sec(dev);
2353 b43_periodic_every30sec(dev);
2354 b43_periodic_every15sec(dev);
2357 /* Periodic work locking policy:
2358 * The whole periodic work handler is protected by
2359 * wl->mutex. If another lock is needed somewhere in the
2360 * pwork callchain, it's aquired in-place, where it's needed.
2362 static void b43_periodic_work_handler(struct work_struct *work)
2364 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2365 periodic_work.work);
2366 struct b43_wl *wl = dev->wl;
2367 unsigned long delay;
2369 mutex_lock(&wl->mutex);
2371 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2373 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2376 do_periodic_work(dev);
2378 dev->periodic_state++;
2380 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2381 delay = msecs_to_jiffies(50);
2383 delay = round_jiffies_relative(HZ * 15);
2384 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2386 mutex_unlock(&wl->mutex);
2389 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2391 struct delayed_work *work = &dev->periodic_work;
2393 dev->periodic_state = 0;
2394 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2395 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2398 /* Validate access to the chip (SHM) */
2399 static int b43_validate_chipaccess(struct b43_wldev *dev)
2404 shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2405 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2406 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2408 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2409 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2411 b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup);
2413 value = b43_read32(dev, B43_MMIO_MACCTL);
2414 if ((value | B43_MACCTL_GMODE) !=
2415 (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2418 value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2424 b43err(dev->wl, "Failed to validate the chipaccess\n");
2428 static void b43_security_init(struct b43_wldev *dev)
2430 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2431 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2432 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2433 /* KTP is a word address, but we address SHM bytewise.
2434 * So multiply by two.
2437 if (dev->dev->id.revision >= 5) {
2438 /* Number of RCMTA address slots */
2439 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2441 b43_clear_keys(dev);
2444 static int b43_rng_read(struct hwrng *rng, u32 * data)
2446 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2447 unsigned long flags;
2449 /* Don't take wl->mutex here, as it could deadlock with
2450 * hwrng internal locking. It's not needed to take
2451 * wl->mutex here, anyway. */
2453 spin_lock_irqsave(&wl->irq_lock, flags);
2454 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2455 spin_unlock_irqrestore(&wl->irq_lock, flags);
2457 return (sizeof(u16));
2460 static void b43_rng_exit(struct b43_wl *wl)
2462 if (wl->rng_initialized)
2463 hwrng_unregister(&wl->rng);
2466 static int b43_rng_init(struct b43_wl *wl)
2470 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2471 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2472 wl->rng.name = wl->rng_name;
2473 wl->rng.data_read = b43_rng_read;
2474 wl->rng.priv = (unsigned long)wl;
2475 wl->rng_initialized = 1;
2476 err = hwrng_register(&wl->rng);
2478 wl->rng_initialized = 0;
2479 b43err(wl, "Failed to register the random "
2480 "number generator (%d)\n", err);
2486 static int b43_op_tx(struct ieee80211_hw *hw,
2487 struct sk_buff *skb,
2488 struct ieee80211_tx_control *ctl)
2490 struct b43_wl *wl = hw_to_b43_wl(hw);
2491 struct b43_wldev *dev = wl->current_dev;
2493 unsigned long flags;
2497 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2499 /* DMA-TX is done without a global lock. */
2500 if (b43_using_pio(dev)) {
2501 spin_lock_irqsave(&wl->irq_lock, flags);
2502 err = b43_pio_tx(dev, skb, ctl);
2503 spin_unlock_irqrestore(&wl->irq_lock, flags);
2505 err = b43_dma_tx(dev, skb, ctl);
2508 return NETDEV_TX_BUSY;
2509 return NETDEV_TX_OK;
2512 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2514 const struct ieee80211_tx_queue_params *params)
2519 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2520 struct ieee80211_tx_queue_stats *stats)
2522 struct b43_wl *wl = hw_to_b43_wl(hw);
2523 struct b43_wldev *dev = wl->current_dev;
2524 unsigned long flags;
2529 spin_lock_irqsave(&wl->irq_lock, flags);
2530 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2531 if (b43_using_pio(dev))
2532 b43_pio_get_tx_stats(dev, stats);
2534 b43_dma_get_tx_stats(dev, stats);
2537 spin_unlock_irqrestore(&wl->irq_lock, flags);
2542 static int b43_op_get_stats(struct ieee80211_hw *hw,
2543 struct ieee80211_low_level_stats *stats)
2545 struct b43_wl *wl = hw_to_b43_wl(hw);
2546 unsigned long flags;
2548 spin_lock_irqsave(&wl->irq_lock, flags);
2549 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2550 spin_unlock_irqrestore(&wl->irq_lock, flags);
2555 static const char *phymode_to_string(unsigned int phymode)
2570 static int find_wldev_for_phymode(struct b43_wl *wl,
2571 unsigned int phymode,
2572 struct b43_wldev **dev, bool * gmode)
2574 struct b43_wldev *d;
2576 list_for_each_entry(d, &wl->devlist, list) {
2577 if (d->phy.possible_phymodes & phymode) {
2578 /* Ok, this device supports the PHY-mode.
2579 * Now figure out how the gmode bit has to be
2580 * set to support it. */
2581 if (phymode == B43_PHYMODE_A)
2594 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2596 struct ssb_device *sdev = dev->dev;
2599 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2600 tmslow &= ~B43_TMSLOW_GMODE;
2601 tmslow |= B43_TMSLOW_PHYRESET;
2602 tmslow |= SSB_TMSLOW_FGC;
2603 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2606 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2607 tmslow &= ~SSB_TMSLOW_FGC;
2608 tmslow |= B43_TMSLOW_PHYRESET;
2609 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2613 /* Expects wl->mutex locked */
2614 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2616 struct b43_wldev *up_dev;
2617 struct b43_wldev *down_dev;
2622 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2624 b43err(wl, "Could not find a device for %s-PHY mode\n",
2625 phymode_to_string(new_mode));
2628 if ((up_dev == wl->current_dev) &&
2629 (!!wl->current_dev->phy.gmode == !!gmode)) {
2630 /* This device is already running. */
2633 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2634 phymode_to_string(new_mode));
2635 down_dev = wl->current_dev;
2637 prev_status = b43_status(down_dev);
2638 /* Shutdown the currently running core. */
2639 if (prev_status >= B43_STAT_STARTED)
2640 b43_wireless_core_stop(down_dev);
2641 if (prev_status >= B43_STAT_INITIALIZED)
2642 b43_wireless_core_exit(down_dev);
2644 if (down_dev != up_dev) {
2645 /* We switch to a different core, so we put PHY into
2646 * RESET on the old core. */
2647 b43_put_phy_into_reset(down_dev);
2650 /* Now start the new core. */
2651 up_dev->phy.gmode = gmode;
2652 if (prev_status >= B43_STAT_INITIALIZED) {
2653 err = b43_wireless_core_init(up_dev);
2655 b43err(wl, "Fatal: Could not initialize device for "
2656 "newly selected %s-PHY mode\n",
2657 phymode_to_string(new_mode));
2661 if (prev_status >= B43_STAT_STARTED) {
2662 err = b43_wireless_core_start(up_dev);
2664 b43err(wl, "Fatal: Coult not start device for "
2665 "newly selected %s-PHY mode\n",
2666 phymode_to_string(new_mode));
2667 b43_wireless_core_exit(up_dev);
2671 B43_WARN_ON(b43_status(up_dev) != prev_status);
2673 wl->current_dev = up_dev;
2677 /* Whoops, failed to init the new core. No core is operating now. */
2678 wl->current_dev = NULL;
2682 static int b43_antenna_from_ieee80211(u8 antenna)
2685 case 0: /* default/diversity */
2686 return B43_ANTENNA_DEFAULT;
2687 case 1: /* Antenna 0 */
2688 return B43_ANTENNA0;
2689 case 2: /* Antenna 1 */
2690 return B43_ANTENNA1;
2692 return B43_ANTENNA_DEFAULT;
2696 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2698 struct b43_wl *wl = hw_to_b43_wl(hw);
2699 struct b43_wldev *dev;
2700 struct b43_phy *phy;
2701 unsigned long flags;
2702 unsigned int new_phymode = 0xFFFF;
2708 antenna_tx = b43_antenna_from_ieee80211(conf->antenna_sel_tx);
2709 antenna_rx = b43_antenna_from_ieee80211(conf->antenna_sel_rx);
2711 mutex_lock(&wl->mutex);
2713 /* Switch the PHY mode (if necessary). */
2714 switch (conf->phymode) {
2715 case MODE_IEEE80211A:
2716 new_phymode = B43_PHYMODE_A;
2718 case MODE_IEEE80211B:
2719 new_phymode = B43_PHYMODE_B;
2721 case MODE_IEEE80211G:
2722 new_phymode = B43_PHYMODE_G;
2727 err = b43_switch_phymode(wl, new_phymode);
2729 goto out_unlock_mutex;
2730 dev = wl->current_dev;
2733 /* Disable IRQs while reconfiguring the device.
2734 * This makes it possible to drop the spinlock throughout
2735 * the reconfiguration process. */
2736 spin_lock_irqsave(&wl->irq_lock, flags);
2737 if (b43_status(dev) < B43_STAT_STARTED) {
2738 spin_unlock_irqrestore(&wl->irq_lock, flags);
2739 goto out_unlock_mutex;
2741 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2742 spin_unlock_irqrestore(&wl->irq_lock, flags);
2743 b43_synchronize_irq(dev);
2745 /* Switch to the requested channel.
2746 * The firmware takes care of races with the TX handler. */
2747 if (conf->channel_val != phy->channel)
2748 b43_radio_selectchannel(dev, conf->channel_val, 0);
2750 /* Enable/Disable ShortSlot timing. */
2751 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2753 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2754 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2755 b43_short_slot_timing_enable(dev);
2757 b43_short_slot_timing_disable(dev);
2760 /* Adjust the desired TX power level. */
2761 if (conf->power_level != 0) {
2762 if (conf->power_level != phy->power_level) {
2763 phy->power_level = conf->power_level;
2764 b43_phy_xmitpower(dev);
2768 /* Antennas for RX and management frame TX. */
2769 b43_mgmtframe_txantenna(dev, antenna_tx);
2770 b43_set_rx_antenna(dev, antenna_rx);
2772 /* Update templates for AP mode. */
2773 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2774 b43_set_beacon_int(dev, conf->beacon_int);
2776 if (!!conf->radio_enabled != phy->radio_on) {
2777 if (conf->radio_enabled) {
2778 b43_radio_turn_on(dev);
2779 b43info(dev->wl, "Radio turned on by software\n");
2780 if (!dev->radio_hw_enable) {
2781 b43info(dev->wl, "The hardware RF-kill button "
2782 "still turns the radio physically off. "
2783 "Press the button to turn it on.\n");
2786 b43_radio_turn_off(dev, 0);
2787 b43info(dev->wl, "Radio turned off by software\n");
2791 spin_lock_irqsave(&wl->irq_lock, flags);
2792 b43_interrupt_enable(dev, savedirqs);
2794 spin_unlock_irqrestore(&wl->irq_lock, flags);
2796 mutex_unlock(&wl->mutex);
2801 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2802 const u8 *local_addr, const u8 *addr,
2803 struct ieee80211_key_conf *key)
2805 struct b43_wl *wl = hw_to_b43_wl(hw);
2806 struct b43_wldev *dev;
2807 unsigned long flags;
2811 DECLARE_MAC_BUF(mac);
2813 if (modparam_nohwcrypt)
2814 return -ENOSPC; /* User disabled HW-crypto */
2816 mutex_lock(&wl->mutex);
2817 spin_lock_irqsave(&wl->irq_lock, flags);
2819 dev = wl->current_dev;
2821 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2827 if (key->keylen == 5)
2828 algorithm = B43_SEC_ALGO_WEP40;
2830 algorithm = B43_SEC_ALGO_WEP104;
2833 algorithm = B43_SEC_ALGO_TKIP;
2836 algorithm = B43_SEC_ALGO_AES;
2842 index = (u8) (key->keyidx);
2848 if (algorithm == B43_SEC_ALGO_TKIP) {
2849 /* FIXME: No TKIP hardware encryption for now. */
2854 if (is_broadcast_ether_addr(addr)) {
2855 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2856 err = b43_key_write(dev, index, algorithm,
2857 key->key, key->keylen, NULL, key);
2860 * either pairwise key or address is 00:00:00:00:00:00
2861 * for transmit-only keys
2863 err = b43_key_write(dev, -1, algorithm,
2864 key->key, key->keylen, addr, key);
2869 if (algorithm == B43_SEC_ALGO_WEP40 ||
2870 algorithm == B43_SEC_ALGO_WEP104) {
2871 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2874 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2876 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2879 err = b43_key_clear(dev, key->hw_key_idx);
2888 spin_unlock_irqrestore(&wl->irq_lock, flags);
2889 mutex_unlock(&wl->mutex);
2891 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2893 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2894 print_mac(mac, addr));
2899 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2900 unsigned int changed, unsigned int *fflags,
2901 int mc_count, struct dev_addr_list *mc_list)
2903 struct b43_wl *wl = hw_to_b43_wl(hw);
2904 struct b43_wldev *dev = wl->current_dev;
2905 unsigned long flags;
2912 spin_lock_irqsave(&wl->irq_lock, flags);
2913 *fflags &= FIF_PROMISC_IN_BSS |
2919 FIF_BCN_PRBRESP_PROMISC;
2921 changed &= FIF_PROMISC_IN_BSS |
2927 FIF_BCN_PRBRESP_PROMISC;
2929 wl->filter_flags = *fflags;
2931 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2932 b43_adjust_opmode(dev);
2933 spin_unlock_irqrestore(&wl->irq_lock, flags);
2936 static int b43_op_config_interface(struct ieee80211_hw *hw,
2938 struct ieee80211_if_conf *conf)
2940 struct b43_wl *wl = hw_to_b43_wl(hw);
2941 struct b43_wldev *dev = wl->current_dev;
2942 unsigned long flags;
2946 mutex_lock(&wl->mutex);
2947 spin_lock_irqsave(&wl->irq_lock, flags);
2948 B43_WARN_ON(wl->if_id != if_id);
2950 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2952 memset(wl->bssid, 0, ETH_ALEN);
2953 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2954 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2955 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2956 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2958 b43_refresh_templates(dev, conf->beacon);
2960 b43_write_mac_bssid_templates(dev);
2962 spin_unlock_irqrestore(&wl->irq_lock, flags);
2963 mutex_unlock(&wl->mutex);
2968 /* Locking: wl->mutex */
2969 static void b43_wireless_core_stop(struct b43_wldev *dev)
2971 struct b43_wl *wl = dev->wl;
2972 unsigned long flags;
2974 if (b43_status(dev) < B43_STAT_STARTED)
2977 /* Disable and sync interrupts. We must do this before than
2978 * setting the status to INITIALIZED, as the interrupt handler
2979 * won't care about IRQs then. */
2980 spin_lock_irqsave(&wl->irq_lock, flags);
2981 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
2982 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
2983 spin_unlock_irqrestore(&wl->irq_lock, flags);
2984 b43_synchronize_irq(dev);
2986 b43_set_status(dev, B43_STAT_INITIALIZED);
2988 mutex_unlock(&wl->mutex);
2989 /* Must unlock as it would otherwise deadlock. No races here.
2990 * Cancel the possibly running self-rearming periodic work. */
2991 cancel_delayed_work_sync(&dev->periodic_work);
2992 mutex_lock(&wl->mutex);
2994 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
2996 b43_mac_suspend(dev);
2997 free_irq(dev->dev->irq, dev);
2998 b43dbg(wl, "Wireless interface stopped\n");
3001 /* Locking: wl->mutex */
3002 static int b43_wireless_core_start(struct b43_wldev *dev)
3006 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3008 drain_txstatus_queue(dev);
3009 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3010 IRQF_SHARED, KBUILD_MODNAME, dev);
3012 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3016 /* We are ready to run. */
3017 b43_set_status(dev, B43_STAT_STARTED);
3019 /* Start data flow (TX/RX). */
3020 b43_mac_enable(dev);
3021 b43_interrupt_enable(dev, dev->irq_savedstate);
3022 ieee80211_start_queues(dev->wl->hw);
3024 /* Start maintainance work */
3025 b43_periodic_tasks_setup(dev);
3027 b43dbg(dev->wl, "Wireless interface started\n");
3032 /* Get PHY and RADIO versioning numbers */
3033 static int b43_phy_versioning(struct b43_wldev *dev)
3035 struct b43_phy *phy = &dev->phy;
3043 int unsupported = 0;
3045 /* Get PHY versioning */
3046 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3047 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3048 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3049 phy_rev = (tmp & B43_PHYVER_VERSION);
3056 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3068 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3069 "(Analog %u, Type %u, Revision %u)\n",
3070 analog_type, phy_type, phy_rev);
3073 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3074 analog_type, phy_type, phy_rev);
3076 /* Get RADIO versioning */
3077 if (dev->dev->bus->chip_id == 0x4317) {
3078 if (dev->dev->bus->chip_rev == 0)
3080 else if (dev->dev->bus->chip_rev == 1)
3085 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3086 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3088 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3089 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3091 radio_manuf = (tmp & 0x00000FFF);
3092 radio_ver = (tmp & 0x0FFFF000) >> 12;
3093 radio_rev = (tmp & 0xF0000000) >> 28;
3096 if (radio_ver != 0x2060)
3100 if (radio_manuf != 0x17F)
3104 if ((radio_ver & 0xFFF0) != 0x2050)
3108 if (radio_ver != 0x2050)
3115 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3116 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3117 radio_manuf, radio_ver, radio_rev);
3120 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3121 radio_manuf, radio_ver, radio_rev);
3123 phy->radio_manuf = radio_manuf;
3124 phy->radio_ver = radio_ver;
3125 phy->radio_rev = radio_rev;
3127 phy->analog = analog_type;
3128 phy->type = phy_type;
3134 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3135 struct b43_phy *phy)
3137 struct b43_txpower_lo_control *lo;
3140 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3141 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3146 phy->aci_enable = 0;
3147 phy->aci_wlan_automatic = 0;
3148 phy->aci_hw_rssi = 0;
3150 phy->radio_off_context.valid = 0;
3152 lo = phy->lo_control;
3154 memset(lo, 0, sizeof(*(phy->lo_control)));
3158 phy->max_lb_gain = 0;
3159 phy->trsw_rx_gain = 0;
3160 phy->txpwr_offset = 0;
3163 phy->nrssislope = 0;
3164 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3165 phy->nrssi[i] = -1000;
3166 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3167 phy->nrssi_lt[i] = i;
3169 phy->lofcal = 0xFFFF;
3170 phy->initval = 0xFFFF;
3172 spin_lock_init(&phy->lock);
3173 phy->interfmode = B43_INTERFMODE_NONE;
3174 phy->channel = 0xFF;
3176 phy->hardware_power_control = !!modparam_hwpctl;
3179 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3182 dev->reg124_set_0x4 = 0;
3183 /* Assume the radio is enabled. If it's not enabled, the state will
3184 * immediately get fixed on the first periodic work run. */
3185 dev->radio_hw_enable = 1;
3188 memset(&dev->stats, 0, sizeof(dev->stats));
3190 setup_struct_phy_for_init(dev, &dev->phy);
3192 /* IRQ related flags */
3193 dev->irq_reason = 0;
3194 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3195 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3197 dev->mac_suspended = 1;
3199 /* Noise calculation context */
3200 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3203 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3205 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3208 if (!(sprom->r1.boardflags_lo & B43_BFL_BTCOEXIST))
3210 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3213 hf = b43_hf_read(dev);
3214 if (sprom->r1.boardflags_lo & B43_BFL_BTCMOD)
3215 hf |= B43_HF_BTCOEXALT;
3217 hf |= B43_HF_BTCOEX;
3218 b43_hf_write(dev, hf);
3222 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3226 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3228 #ifdef CONFIG_SSB_DRIVER_PCICORE
3229 struct ssb_bus *bus = dev->dev->bus;
3232 if (bus->pcicore.dev &&
3233 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3234 bus->pcicore.dev->id.revision <= 5) {
3235 /* IMCFGLO timeouts workaround. */
3236 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3237 tmp &= ~SSB_IMCFGLO_REQTO;
3238 tmp &= ~SSB_IMCFGLO_SERTO;
3239 switch (bus->bustype) {
3240 case SSB_BUSTYPE_PCI:
3241 case SSB_BUSTYPE_PCMCIA:
3244 case SSB_BUSTYPE_SSB:
3248 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3250 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3253 /* Write the short and long frame retry limit values. */
3254 static void b43_set_retry_limits(struct b43_wldev *dev,
3255 unsigned int short_retry,
3256 unsigned int long_retry)
3258 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3259 * the chip-internal counter. */
3260 short_retry = min(short_retry, (unsigned int)0xF);
3261 long_retry = min(long_retry, (unsigned int)0xF);
3263 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3265 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3269 /* Shutdown a wireless core */
3270 /* Locking: wl->mutex */
3271 static void b43_wireless_core_exit(struct b43_wldev *dev)
3273 struct b43_phy *phy = &dev->phy;
3275 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3276 if (b43_status(dev) != B43_STAT_INITIALIZED)
3278 b43_set_status(dev, B43_STAT_UNINIT);
3281 b43_rng_exit(dev->wl);
3285 b43_radio_turn_off(dev, 1);
3286 b43_switch_analog(dev, 0);
3287 if (phy->dyn_tssi_tbl)
3288 kfree(phy->tssi2dbm);
3289 kfree(phy->lo_control);
3290 phy->lo_control = NULL;
3291 ssb_device_disable(dev->dev, 0);
3292 ssb_bus_may_powerdown(dev->dev->bus);
3295 /* Initialize a wireless core */
3296 static int b43_wireless_core_init(struct b43_wldev *dev)
3298 struct b43_wl *wl = dev->wl;
3299 struct ssb_bus *bus = dev->dev->bus;
3300 struct ssb_sprom *sprom = &bus->sprom;
3301 struct b43_phy *phy = &dev->phy;
3305 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3307 err = ssb_bus_powerup(bus, 0);
3310 if (!ssb_device_is_enabled(dev->dev)) {
3311 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3312 b43_wireless_core_reset(dev, tmp);
3315 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3317 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3318 if (!phy->lo_control) {
3323 setup_struct_wldev_for_init(dev);
3325 err = b43_phy_init_tssi2dbm_table(dev);
3327 goto err_kfree_lo_control;
3329 /* Enable IRQ routing to this device. */
3330 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3332 b43_imcfglo_timeouts_workaround(dev);
3333 b43_bluetooth_coext_disable(dev);
3334 b43_phy_early_init(dev);
3335 err = b43_chip_init(dev);
3337 goto err_kfree_tssitbl;
3338 b43_shm_write16(dev, B43_SHM_SHARED,
3339 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3340 hf = b43_hf_read(dev);
3341 if (phy->type == B43_PHYTYPE_G) {
3345 if (sprom->r1.boardflags_lo & B43_BFL_PACTRL)
3346 hf |= B43_HF_OFDMPABOOST;
3347 } else if (phy->type == B43_PHYTYPE_B) {
3349 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3352 b43_hf_write(dev, hf);
3354 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3355 B43_DEFAULT_LONG_RETRY_LIMIT);
3356 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3357 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3359 /* Disable sending probe responses from firmware.
3360 * Setting the MaxTime to one usec will always trigger
3361 * a timeout, so we never send any probe resp.
3362 * A timeout of zero is infinite. */
3363 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3365 b43_rate_memory_init(dev);
3367 /* Minimum Contention Window */
3368 if (phy->type == B43_PHYTYPE_B) {
3369 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3371 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3373 /* Maximum Contention Window */
3374 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3377 if (b43_using_pio(dev)) {
3378 err = b43_pio_init(dev);
3380 err = b43_dma_init(dev);
3384 } while (err == -EAGAIN);
3390 b43_write16(dev, 0x0612, 0x0050);
3391 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3392 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3395 b43_bluetooth_coext_enable(dev);
3397 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3398 memset(wl->bssid, 0, ETH_ALEN);
3399 memset(wl->mac_addr, 0, ETH_ALEN);
3400 b43_upload_card_macaddress(dev);
3401 b43_security_init(dev);
3404 b43_set_status(dev, B43_STAT_INITIALIZED);
3413 if (phy->dyn_tssi_tbl)
3414 kfree(phy->tssi2dbm);
3415 err_kfree_lo_control:
3416 kfree(phy->lo_control);
3417 phy->lo_control = NULL;
3419 ssb_bus_may_powerdown(bus);
3420 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3424 static int b43_op_add_interface(struct ieee80211_hw *hw,
3425 struct ieee80211_if_init_conf *conf)
3427 struct b43_wl *wl = hw_to_b43_wl(hw);
3428 struct b43_wldev *dev;
3429 unsigned long flags;
3430 int err = -EOPNOTSUPP;
3432 /* TODO: allow WDS/AP devices to coexist */
3434 if (conf->type != IEEE80211_IF_TYPE_AP &&
3435 conf->type != IEEE80211_IF_TYPE_STA &&
3436 conf->type != IEEE80211_IF_TYPE_WDS &&
3437 conf->type != IEEE80211_IF_TYPE_IBSS)
3440 mutex_lock(&wl->mutex);
3442 goto out_mutex_unlock;
3444 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3446 dev = wl->current_dev;
3448 wl->if_id = conf->if_id;
3449 wl->if_type = conf->type;
3450 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3452 spin_lock_irqsave(&wl->irq_lock, flags);
3453 b43_adjust_opmode(dev);
3454 b43_upload_card_macaddress(dev);
3455 spin_unlock_irqrestore(&wl->irq_lock, flags);
3459 mutex_unlock(&wl->mutex);
3464 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3465 struct ieee80211_if_init_conf *conf)
3467 struct b43_wl *wl = hw_to_b43_wl(hw);
3468 struct b43_wldev *dev = wl->current_dev;
3469 unsigned long flags;
3471 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3473 mutex_lock(&wl->mutex);
3475 B43_WARN_ON(!wl->operating);
3476 B43_WARN_ON(wl->if_id != conf->if_id);
3480 spin_lock_irqsave(&wl->irq_lock, flags);
3481 b43_adjust_opmode(dev);
3482 memset(wl->mac_addr, 0, ETH_ALEN);
3483 b43_upload_card_macaddress(dev);
3484 spin_unlock_irqrestore(&wl->irq_lock, flags);
3486 mutex_unlock(&wl->mutex);
3489 static int b43_op_start(struct ieee80211_hw *hw)
3491 struct b43_wl *wl = hw_to_b43_wl(hw);
3492 struct b43_wldev *dev = wl->current_dev;
3496 /* First register RFkill.
3497 * LEDs that are registered later depend on it. */
3498 b43_rfkill_init(dev);
3500 mutex_lock(&wl->mutex);
3502 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3503 err = b43_wireless_core_init(dev);
3505 goto out_mutex_unlock;
3509 if (b43_status(dev) < B43_STAT_STARTED) {
3510 err = b43_wireless_core_start(dev);
3513 b43_wireless_core_exit(dev);
3514 goto out_mutex_unlock;
3519 mutex_unlock(&wl->mutex);
3524 static void b43_op_stop(struct ieee80211_hw *hw)
3526 struct b43_wl *wl = hw_to_b43_wl(hw);
3527 struct b43_wldev *dev = wl->current_dev;
3529 b43_rfkill_exit(dev);
3531 mutex_lock(&wl->mutex);
3532 if (b43_status(dev) >= B43_STAT_STARTED)
3533 b43_wireless_core_stop(dev);
3534 b43_wireless_core_exit(dev);
3535 mutex_unlock(&wl->mutex);
3538 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3539 u32 short_retry_limit, u32 long_retry_limit)
3541 struct b43_wl *wl = hw_to_b43_wl(hw);
3542 struct b43_wldev *dev;
3545 mutex_lock(&wl->mutex);
3546 dev = wl->current_dev;
3547 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3551 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3553 mutex_unlock(&wl->mutex);
3558 static const struct ieee80211_ops b43_hw_ops = {
3560 .conf_tx = b43_op_conf_tx,
3561 .add_interface = b43_op_add_interface,
3562 .remove_interface = b43_op_remove_interface,
3563 .config = b43_op_config,
3564 .config_interface = b43_op_config_interface,
3565 .configure_filter = b43_op_configure_filter,
3566 .set_key = b43_op_set_key,
3567 .get_stats = b43_op_get_stats,
3568 .get_tx_stats = b43_op_get_tx_stats,
3569 .start = b43_op_start,
3570 .stop = b43_op_stop,
3571 .set_retry_limit = b43_op_set_retry_limit,
3574 /* Hard-reset the chip. Do not call this directly.
3575 * Use b43_controller_restart()
3577 static void b43_chip_reset(struct work_struct *work)
3579 struct b43_wldev *dev =
3580 container_of(work, struct b43_wldev, restart_work);
3581 struct b43_wl *wl = dev->wl;
3585 mutex_lock(&wl->mutex);
3587 prev_status = b43_status(dev);
3588 /* Bring the device down... */
3589 if (prev_status >= B43_STAT_STARTED)
3590 b43_wireless_core_stop(dev);
3591 if (prev_status >= B43_STAT_INITIALIZED)
3592 b43_wireless_core_exit(dev);
3594 /* ...and up again. */
3595 if (prev_status >= B43_STAT_INITIALIZED) {
3596 err = b43_wireless_core_init(dev);
3600 if (prev_status >= B43_STAT_STARTED) {
3601 err = b43_wireless_core_start(dev);
3603 b43_wireless_core_exit(dev);
3608 mutex_unlock(&wl->mutex);
3610 b43err(wl, "Controller restart FAILED\n");
3612 b43info(wl, "Controller restarted\n");
3615 static int b43_setup_modes(struct b43_wldev *dev,
3616 int have_aphy, int have_bphy, int have_gphy)
3618 struct ieee80211_hw *hw = dev->wl->hw;
3619 struct ieee80211_hw_mode *mode;
3620 struct b43_phy *phy = &dev->phy;
3624 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3627 phy->possible_phymodes = 0;
3630 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3631 mode = &phy->hwmodes[cnt];
3633 mode->mode = MODE_IEEE80211A;
3634 mode->num_channels = b43_a_chantable_size;
3635 mode->channels = b43_a_chantable;
3636 mode->num_rates = b43_a_ratetable_size;
3637 mode->rates = b43_a_ratetable;
3638 err = ieee80211_register_hwmode(hw, mode);
3642 phy->possible_phymodes |= B43_PHYMODE_A;
3647 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3648 mode = &phy->hwmodes[cnt];
3650 mode->mode = MODE_IEEE80211B;
3651 mode->num_channels = b43_bg_chantable_size;
3652 mode->channels = b43_bg_chantable;
3653 mode->num_rates = b43_b_ratetable_size;
3654 mode->rates = b43_b_ratetable;
3655 err = ieee80211_register_hwmode(hw, mode);
3659 phy->possible_phymodes |= B43_PHYMODE_B;
3664 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3665 mode = &phy->hwmodes[cnt];
3667 mode->mode = MODE_IEEE80211G;
3668 mode->num_channels = b43_bg_chantable_size;
3669 mode->channels = b43_bg_chantable;
3670 mode->num_rates = b43_g_ratetable_size;
3671 mode->rates = b43_g_ratetable;
3672 err = ieee80211_register_hwmode(hw, mode);
3676 phy->possible_phymodes |= B43_PHYMODE_G;
3686 static void b43_wireless_core_detach(struct b43_wldev *dev)
3688 /* We release firmware that late to not be required to re-request
3689 * is all the time when we reinit the core. */
3690 b43_release_firmware(dev);
3693 static int b43_wireless_core_attach(struct b43_wldev *dev)
3695 struct b43_wl *wl = dev->wl;
3696 struct ssb_bus *bus = dev->dev->bus;
3697 struct pci_dev *pdev = bus->host_pci;
3699 int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3702 /* Do NOT do any device initialization here.
3703 * Do it in wireless_core_init() instead.
3704 * This function is for gathering basic information about the HW, only.
3705 * Also some structs may be set up here. But most likely you want to have
3706 * that in core_init(), too.
3709 err = ssb_bus_powerup(bus, 0);
3711 b43err(wl, "Bus powerup failed\n");
3714 /* Get the PHY type. */
3715 if (dev->dev->id.revision >= 5) {
3718 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3719 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3720 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3721 if (!have_aphy && !have_gphy)
3723 } else if (dev->dev->id.revision == 4) {
3729 dev->phy.gmode = (have_gphy || have_bphy);
3730 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3731 b43_wireless_core_reset(dev, tmp);
3733 err = b43_phy_versioning(dev);
3736 /* Check if this device supports multiband. */
3738 (pdev->device != 0x4312 &&
3739 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3740 /* No multiband support. */
3744 switch (dev->phy.type) {
3758 dev->phy.gmode = (have_gphy || have_bphy);
3759 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3760 b43_wireless_core_reset(dev, tmp);
3762 err = b43_validate_chipaccess(dev);
3765 err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3769 /* Now set some default "current_dev" */
3770 if (!wl->current_dev)
3771 wl->current_dev = dev;
3772 INIT_WORK(&dev->restart_work, b43_chip_reset);
3774 b43_radio_turn_off(dev, 1);
3775 b43_switch_analog(dev, 0);
3776 ssb_device_disable(dev->dev, 0);
3777 ssb_bus_may_powerdown(bus);
3783 ssb_bus_may_powerdown(bus);
3787 static void b43_one_core_detach(struct ssb_device *dev)
3789 struct b43_wldev *wldev;
3792 wldev = ssb_get_drvdata(dev);
3794 cancel_work_sync(&wldev->restart_work);
3795 b43_debugfs_remove_device(wldev);
3796 b43_wireless_core_detach(wldev);
3797 list_del(&wldev->list);
3799 ssb_set_drvdata(dev, NULL);
3803 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3805 struct b43_wldev *wldev;
3806 struct pci_dev *pdev;
3809 if (!list_empty(&wl->devlist)) {
3810 /* We are not the first core on this chip. */
3811 pdev = dev->bus->host_pci;
3812 /* Only special chips support more than one wireless
3813 * core, although some of the other chips have more than
3814 * one wireless core as well. Check for this and
3818 ((pdev->device != 0x4321) &&
3819 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3820 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3825 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3831 b43_set_status(wldev, B43_STAT_UNINIT);
3832 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3833 tasklet_init(&wldev->isr_tasklet,
3834 (void (*)(unsigned long))b43_interrupt_tasklet,
3835 (unsigned long)wldev);
3837 wldev->__using_pio = 1;
3838 INIT_LIST_HEAD(&wldev->list);
3840 err = b43_wireless_core_attach(wldev);
3842 goto err_kfree_wldev;
3844 list_add(&wldev->list, &wl->devlist);
3846 ssb_set_drvdata(dev, wldev);
3847 b43_debugfs_add_device(wldev);
3857 static void b43_sprom_fixup(struct ssb_bus *bus)
3859 /* boardflags workarounds */
3860 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3861 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3862 bus->sprom.r1.boardflags_lo |= B43_BFL_BTCOEXIST;
3863 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3864 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3865 bus->sprom.r1.boardflags_lo |= B43_BFL_PACTRL;
3867 /* Handle case when gain is not set in sprom */
3868 if (bus->sprom.r1.antenna_gain_a == 0xFF)
3869 bus->sprom.r1.antenna_gain_a = 2;
3870 if (bus->sprom.r1.antenna_gain_bg == 0xFF)
3871 bus->sprom.r1.antenna_gain_bg = 2;
3873 /* Convert Antennagain values to Q5.2 */
3874 bus->sprom.r1.antenna_gain_a <<= 2;
3875 bus->sprom.r1.antenna_gain_bg <<= 2;
3878 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3880 struct ieee80211_hw *hw = wl->hw;
3882 ssb_set_devtypedata(dev, NULL);
3883 ieee80211_free_hw(hw);
3886 static int b43_wireless_init(struct ssb_device *dev)
3888 struct ssb_sprom *sprom = &dev->bus->sprom;
3889 struct ieee80211_hw *hw;
3893 b43_sprom_fixup(dev->bus);
3895 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3897 b43err(NULL, "Could not allocate ieee80211 device\n");
3902 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
3903 hw->max_signal = 100;
3904 hw->max_rssi = -110;
3905 hw->max_noise = -110;
3906 hw->queues = 1; /* FIXME: hardware has more queues */
3907 SET_IEEE80211_DEV(hw, dev->dev);
3908 if (is_valid_ether_addr(sprom->r1.et1mac))
3909 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac);
3911 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac);
3913 /* Get and initialize struct b43_wl */
3914 wl = hw_to_b43_wl(hw);
3915 memset(wl, 0, sizeof(*wl));
3917 spin_lock_init(&wl->irq_lock);
3918 spin_lock_init(&wl->leds_lock);
3919 mutex_init(&wl->mutex);
3920 INIT_LIST_HEAD(&wl->devlist);
3922 ssb_set_devtypedata(dev, wl);
3923 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3929 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3935 wl = ssb_get_devtypedata(dev);
3937 /* Probing the first core. Must setup common struct b43_wl */
3939 err = b43_wireless_init(dev);
3942 wl = ssb_get_devtypedata(dev);
3945 err = b43_one_core_attach(dev, wl);
3947 goto err_wireless_exit;
3950 err = ieee80211_register_hw(wl->hw);
3952 goto err_one_core_detach;
3958 err_one_core_detach:
3959 b43_one_core_detach(dev);
3962 b43_wireless_exit(dev, wl);
3966 static void b43_remove(struct ssb_device *dev)
3968 struct b43_wl *wl = ssb_get_devtypedata(dev);
3969 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3972 if (wl->current_dev == wldev)
3973 ieee80211_unregister_hw(wl->hw);
3975 b43_one_core_detach(dev);
3977 if (list_empty(&wl->devlist)) {
3978 /* Last core on the chip unregistered.
3979 * We can destroy common struct b43_wl.
3981 b43_wireless_exit(dev, wl);
3985 /* Perform a hardware reset. This can be called from any context. */
3986 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
3988 /* Must avoid requeueing, if we are in shutdown. */
3989 if (b43_status(dev) < B43_STAT_INITIALIZED)
3991 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
3992 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3997 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
3999 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4000 struct b43_wl *wl = wldev->wl;
4002 b43dbg(wl, "Suspending...\n");
4004 mutex_lock(&wl->mutex);
4005 wldev->suspend_init_status = b43_status(wldev);
4006 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4007 b43_wireless_core_stop(wldev);
4008 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4009 b43_wireless_core_exit(wldev);
4010 mutex_unlock(&wl->mutex);
4012 b43dbg(wl, "Device suspended.\n");
4017 static int b43_resume(struct ssb_device *dev)
4019 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4020 struct b43_wl *wl = wldev->wl;
4023 b43dbg(wl, "Resuming...\n");
4025 mutex_lock(&wl->mutex);
4026 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4027 err = b43_wireless_core_init(wldev);
4029 b43err(wl, "Resume failed at core init\n");
4033 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4034 err = b43_wireless_core_start(wldev);
4036 b43_wireless_core_exit(wldev);
4037 b43err(wl, "Resume failed at core start\n");
4041 mutex_unlock(&wl->mutex);
4043 b43dbg(wl, "Device resumed.\n");
4048 #else /* CONFIG_PM */
4049 # define b43_suspend NULL
4050 # define b43_resume NULL
4051 #endif /* CONFIG_PM */
4053 static struct ssb_driver b43_ssb_driver = {
4054 .name = KBUILD_MODNAME,
4055 .id_table = b43_ssb_tbl,
4057 .remove = b43_remove,
4058 .suspend = b43_suspend,
4059 .resume = b43_resume,
4062 static int __init b43_init(void)
4067 err = b43_pcmcia_init();
4070 err = ssb_driver_register(&b43_ssb_driver);
4072 goto err_pcmcia_exit;
4083 static void __exit b43_exit(void)
4085 ssb_driver_unregister(&b43_ssb_driver);
4090 module_init(b43_init)
4091 module_exit(b43_exit)