drivers/net/wireless/b43/dma.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   DMA ringbuffer and descriptor allocation/management
   6
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8
   9   Some code in this file is derived from the b44.c driver
  10   Copyright (C) 2002 David S. Miller
  11   Copyright (C) Pekka Pietikainen
  12
  13   This program is free software; you can redistribute it and/or modify
  14   it under the terms of the GNU General Public License as published by
  15   the Free Software Foundation; either version 2 of the License, or
  16   (at your option) any later version.
  17
  18   This program is distributed in the hope that it will be useful,
  19   but WITHOUT ANY WARRANTY; without even the implied warranty of
  20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21   GNU General Public License for more details.
  22
  23   You should have received a copy of the GNU General Public License
  24   along with this program; see the file COPYING.  If not, write to
  25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  26   Boston, MA 02110-1301, USA.
  27
  28 */
  29
  30 #include "b43.h"
  31 #include "dma.h"
  32 #include "main.h"
  33 #include "debugfs.h"
  34 #include "xmit.h"
  35
  36 #include <linux/dma-mapping.h>
  37 #include <linux/pci.h>
  38 #include <linux/delay.h>
  39 #include <linux/skbuff.h>
  40 #include <linux/etherdevice.h>
  41
  42
  43 /* 32bit DMA ops. */
  44 static
  45 struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
  46                                           int slot,
  47                                           struct b43_dmadesc_meta **meta)
  48 {
  49         struct b43_dmadesc32 *desc;
  50
  51         *meta = &(ring->meta[slot]);
  52         desc = ring->descbase;
  53         desc = &(desc[slot]);
  54
  55         return (struct b43_dmadesc_generic *)desc;
  56 }
  57
  58 static void op32_fill_descriptor(struct b43_dmaring *ring,
  59                                  struct b43_dmadesc_generic *desc,
  60                                  dma_addr_t dmaaddr, u16 bufsize,
  61                                  int start, int end, int irq)
  62 {
  63         struct b43_dmadesc32 *descbase = ring->descbase;
  64         int slot;
  65         u32 ctl;
  66         u32 addr;
  67         u32 addrext;
  68
  69         slot = (int)(&(desc->dma32) - descbase);
  70         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
  71
  72         addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
  73         addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
  74             >> SSB_DMA_TRANSLATION_SHIFT;
  75         addr |= ssb_dma_translation(ring->dev->dev);
  76         ctl = (bufsize - ring->frameoffset)
  77             & B43_DMA32_DCTL_BYTECNT;
  78         if (slot == ring->nr_slots - 1)
  79                 ctl |= B43_DMA32_DCTL_DTABLEEND;
  80         if (start)
  81                 ctl |= B43_DMA32_DCTL_FRAMESTART;
  82         if (end)
  83                 ctl |= B43_DMA32_DCTL_FRAMEEND;
  84         if (irq)
  85                 ctl |= B43_DMA32_DCTL_IRQ;
  86         ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
  87             & B43_DMA32_DCTL_ADDREXT_MASK;
  88
  89         desc->dma32.control = cpu_to_le32(ctl);
  90         desc->dma32.address = cpu_to_le32(addr);
  91 }
  92
  93 static void op32_poke_tx(struct b43_dmaring *ring, int slot)
  94 {
  95         b43_dma_write(ring, B43_DMA32_TXINDEX,
  96                       (u32) (slot * sizeof(struct b43_dmadesc32)));
  97 }
  98
  99 static void op32_tx_suspend(struct b43_dmaring *ring)
 100 {
 101         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 102                       | B43_DMA32_TXSUSPEND);
 103 }
 104
 105 static void op32_tx_resume(struct b43_dmaring *ring)
 106 {
 107         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 108                       & ~B43_DMA32_TXSUSPEND);
 109 }
 110
 111 static int op32_get_current_rxslot(struct b43_dmaring *ring)
 112 {
 113         u32 val;
 114
 115         val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
 116         val &= B43_DMA32_RXDPTR;
 117
 118         return (val / sizeof(struct b43_dmadesc32));
 119 }
 120
 121 static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
 122 {
 123         b43_dma_write(ring, B43_DMA32_RXINDEX,
 124                       (u32) (slot * sizeof(struct b43_dmadesc32)));
 125 }
 126
 127 static const struct b43_dma_ops dma32_ops = {
 128         .idx2desc = op32_idx2desc,
 129         .fill_descriptor = op32_fill_descriptor,
 130         .poke_tx = op32_poke_tx,
 131         .tx_suspend = op32_tx_suspend,
 132         .tx_resume = op32_tx_resume,
 133         .get_current_rxslot = op32_get_current_rxslot,
 134         .set_current_rxslot = op32_set_current_rxslot,
 135 };
 136
 137 /* 64bit DMA ops. */
 138 static
 139 struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
 140                                           int slot,
 141                                           struct b43_dmadesc_meta **meta)
 142 {
 143         struct b43_dmadesc64 *desc;
 144
 145         *meta = &(ring->meta[slot]);
 146         desc = ring->descbase;
 147         desc = &(desc[slot]);
 148
 149         return (struct b43_dmadesc_generic *)desc;
 150 }
 151
 152 static void op64_fill_descriptor(struct b43_dmaring *ring,
 153                                  struct b43_dmadesc_generic *desc,
 154                                  dma_addr_t dmaaddr, u16 bufsize,
 155                                  int start, int end, int irq)
 156 {
 157         struct b43_dmadesc64 *descbase = ring->descbase;
 158         int slot;
 159         u32 ctl0 = 0, ctl1 = 0;
 160         u32 addrlo, addrhi;
 161         u32 addrext;
 162
 163         slot = (int)(&(desc->dma64) - descbase);
 164         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
 165
 166         addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
 167         addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
 168         addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
 169             >> SSB_DMA_TRANSLATION_SHIFT;
 170         addrhi |= (ssb_dma_translation(ring->dev->dev) << 1);
 171         if (slot == ring->nr_slots - 1)
 172                 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
 173         if (start)
 174                 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
 175         if (end)
 176                 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
 177         if (irq)
 178                 ctl0 |= B43_DMA64_DCTL0_IRQ;
 179         ctl1 |= (bufsize - ring->frameoffset)
 180             & B43_DMA64_DCTL1_BYTECNT;
 181         ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
 182             & B43_DMA64_DCTL1_ADDREXT_MASK;
 183
 184         desc->dma64.control0 = cpu_to_le32(ctl0);
 185         desc->dma64.control1 = cpu_to_le32(ctl1);
 186         desc->dma64.address_low = cpu_to_le32(addrlo);
 187         desc->dma64.address_high = cpu_to_le32(addrhi);
 188 }
 189
 190 static void op64_poke_tx(struct b43_dmaring *ring, int slot)
 191 {
 192         b43_dma_write(ring, B43_DMA64_TXINDEX,
 193                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 194 }
 195
 196 static void op64_tx_suspend(struct b43_dmaring *ring)
 197 {
 198         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 199                       | B43_DMA64_TXSUSPEND);
 200 }
 201
 202 static void op64_tx_resume(struct b43_dmaring *ring)
 203 {
 204         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 205                       & ~B43_DMA64_TXSUSPEND);
 206 }
 207
 208 static int op64_get_current_rxslot(struct b43_dmaring *ring)
 209 {
 210         u32 val;
 211
 212         val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
 213         val &= B43_DMA64_RXSTATDPTR;
 214
 215         return (val / sizeof(struct b43_dmadesc64));
 216 }
 217
 218 static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
 219 {
 220         b43_dma_write(ring, B43_DMA64_RXINDEX,
 221                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 222 }
 223
 224 static const struct b43_dma_ops dma64_ops = {
 225         .idx2desc = op64_idx2desc,
 226         .fill_descriptor = op64_fill_descriptor,
 227         .poke_tx = op64_poke_tx,
 228         .tx_suspend = op64_tx_suspend,
 229         .tx_resume = op64_tx_resume,
 230         .get_current_rxslot = op64_get_current_rxslot,
 231         .set_current_rxslot = op64_set_current_rxslot,
 232 };
 233
 234 static inline int free_slots(struct b43_dmaring *ring)
 235 {
 236         return (ring->nr_slots - ring->used_slots);
 237 }
 238
 239 static inline int next_slot(struct b43_dmaring *ring, int slot)
 240 {
 241         B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
 242         if (slot == ring->nr_slots - 1)
 243                 return 0;
 244         return slot + 1;
 245 }
 246
 247 static inline int prev_slot(struct b43_dmaring *ring, int slot)
 248 {
 249         B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
 250         if (slot == 0)
 251                 return ring->nr_slots - 1;
 252         return slot - 1;
 253 }
 254
 255 #ifdef CONFIG_B43_DEBUG
 256 static void update_max_used_slots(struct b43_dmaring *ring,
 257                                   int current_used_slots)
 258 {
 259         if (current_used_slots <= ring->max_used_slots)
 260                 return;
 261         ring->max_used_slots = current_used_slots;
 262         if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
 263                 b43dbg(ring->dev->wl,
 264                        "max_used_slots increased to %d on %s ring %d\n",
 265                        ring->max_used_slots,
 266                        ring->tx ? "TX" : "RX", ring->index);
 267         }
 268 }
 269 #else
 270 static inline
 271     void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
 272 {
 273 }
 274 #endif /* DEBUG */
 275
 276 /* Request a slot for usage. */
 277 static inline int request_slot(struct b43_dmaring *ring)
 278 {
 279         int slot;
 280
 281         B43_WARN_ON(!ring->tx);
 282         B43_WARN_ON(ring->stopped);
 283         B43_WARN_ON(free_slots(ring) == 0);
 284
 285         slot = next_slot(ring, ring->current_slot);
 286         ring->current_slot = slot;
 287         ring->used_slots++;
 288
 289         update_max_used_slots(ring, ring->used_slots);
 290
 291         return slot;
 292 }
 293
 294 /* Mac80211-queue to b43-ring mapping */
 295 static struct b43_dmaring *priority_to_txring(struct b43_wldev *dev,
 296                                               int queue_priority)
 297 {
 298         struct b43_dmaring *ring;
 299
 300 /*FIXME: For now we always run on TX-ring-1 */
 301         return dev->dma.tx_ring1;
 302
 303         /* 0 = highest priority */
 304         switch (queue_priority) {
 305         default:
 306                 B43_WARN_ON(1);
 307                 /* fallthrough */
 308         case 0:
 309                 ring = dev->dma.tx_ring3;
 310                 break;
 311         case 1:
 312                 ring = dev->dma.tx_ring2;
 313                 break;
 314         case 2:
 315                 ring = dev->dma.tx_ring1;
 316                 break;
 317         case 3:
 318                 ring = dev->dma.tx_ring0;
 319                 break;
 320         }
 321
 322         return ring;
 323 }
 324
 325 /* b43-ring to mac80211-queue mapping */
 326 static inline int txring_to_priority(struct b43_dmaring *ring)
 327 {
 328         static const u8 idx_to_prio[] = { 3, 2, 1, 0, };
 329         unsigned int index;
 330
 331 /*FIXME: have only one queue, for now */
 332         return 0;
 333
 334         index = ring->index;
 335         if (B43_WARN_ON(index >= ARRAY_SIZE(idx_to_prio)))
 336                 index = 0;
 337         return idx_to_prio[index];
 338 }
 339
 340 u16 b43_dmacontroller_base(int dma64bit, int controller_idx)
 341 {
 342         static const u16 map64[] = {
 343                 B43_MMIO_DMA64_BASE0,
 344                 B43_MMIO_DMA64_BASE1,
 345                 B43_MMIO_DMA64_BASE2,
 346                 B43_MMIO_DMA64_BASE3,
 347                 B43_MMIO_DMA64_BASE4,
 348                 B43_MMIO_DMA64_BASE5,
 349         };
 350         static const u16 map32[] = {
 351                 B43_MMIO_DMA32_BASE0,
 352                 B43_MMIO_DMA32_BASE1,
 353                 B43_MMIO_DMA32_BASE2,
 354                 B43_MMIO_DMA32_BASE3,
 355                 B43_MMIO_DMA32_BASE4,
 356                 B43_MMIO_DMA32_BASE5,
 357         };
 358
 359         if (dma64bit) {
 360                 B43_WARN_ON(!(controller_idx >= 0 &&
 361                               controller_idx < ARRAY_SIZE(map64)));
 362                 return map64[controller_idx];
 363         }
 364         B43_WARN_ON(!(controller_idx >= 0 &&
 365                       controller_idx < ARRAY_SIZE(map32)));
 366         return map32[controller_idx];
 367 }
 368
 369 static inline
 370     dma_addr_t map_descbuffer(struct b43_dmaring *ring,
 371                               unsigned char *buf, size_t len, int tx)
 372 {
 373         dma_addr_t dmaaddr;
 374
 375         if (tx) {
 376                 dmaaddr = dma_map_single(ring->dev->dev->dev,
 377                                          buf, len, DMA_TO_DEVICE);
 378         } else {
 379                 dmaaddr = dma_map_single(ring->dev->dev->dev,
 380                                          buf, len, DMA_FROM_DEVICE);
 381         }
 382
 383         return dmaaddr;
 384 }
 385
 386 static inline
 387     void unmap_descbuffer(struct b43_dmaring *ring,
 388                           dma_addr_t addr, size_t len, int tx)
 389 {
 390         if (tx) {
 391                 dma_unmap_single(ring->dev->dev->dev, addr, len, DMA_TO_DEVICE);
 392         } else {
 393                 dma_unmap_single(ring->dev->dev->dev,
 394                                  addr, len, DMA_FROM_DEVICE);
 395         }
 396 }
 397
 398 static inline
 399     void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
 400                                  dma_addr_t addr, size_t len)
 401 {
 402         B43_WARN_ON(ring->tx);
 403         dma_sync_single_for_cpu(ring->dev->dev->dev,
 404                                 addr, len, DMA_FROM_DEVICE);
 405 }
 406
 407 static inline
 408     void sync_descbuffer_for_device(struct b43_dmaring *ring,
 409                                     dma_addr_t addr, size_t len)
 410 {
 411         B43_WARN_ON(ring->tx);
 412         dma_sync_single_for_device(ring->dev->dev->dev,
 413                                    addr, len, DMA_FROM_DEVICE);
 414 }
 415
 416 static inline
 417     void free_descriptor_buffer(struct b43_dmaring *ring,
 418                                 struct b43_dmadesc_meta *meta)
 419 {
 420         if (meta->skb) {
 421                 dev_kfree_skb_any(meta->skb);
 422                 meta->skb = NULL;
 423         }
 424 }
 425
 426 static int alloc_ringmemory(struct b43_dmaring *ring)
 427 {
 428         struct device *dev = ring->dev->dev->dev;
 429         gfp_t flags = GFP_KERNEL;
 430
 431         /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
 432          * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
 433          * has shown that 4K is sufficient for the latter as long as the buffer
 434          * does not cross an 8K boundary.
 435          *
 436          * For unknown reasons - possibly a hardware error - the BCM4311 rev
 437          * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
 438          * which accounts for the GFP_DMA flag below.
 439          */
 440         if (ring->dma64)
 441                 flags |= GFP_DMA;
 442         ring->descbase = dma_alloc_coherent(dev, B43_DMA_RINGMEMSIZE,
 443                                             &(ring->dmabase), flags);
 444         if (!ring->descbase) {
 445                 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
 446                 return -ENOMEM;
 447         }
 448         memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
 449
 450         return 0;
 451 }
 452
 453 static void free_ringmemory(struct b43_dmaring *ring)
 454 {
 455         struct device *dev = ring->dev->dev->dev;
 456
 457         dma_free_coherent(dev, B43_DMA_RINGMEMSIZE,
 458                           ring->descbase, ring->dmabase);
 459 }
 460
 461 /* Reset the RX DMA channel */
 462 int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
 463 {
 464         int i;
 465         u32 value;
 466         u16 offset;
 467
 468         might_sleep();
 469
 470         offset = dma64 ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
 471         b43_write32(dev, mmio_base + offset, 0);
 472         for (i = 0; i < 10; i++) {
 473                 offset = dma64 ? B43_DMA64_RXSTATUS : B43_DMA32_RXSTATUS;
 474                 value = b43_read32(dev, mmio_base + offset);
 475                 if (dma64) {
 476                         value &= B43_DMA64_RXSTAT;
 477                         if (value == B43_DMA64_RXSTAT_DISABLED) {
 478                                 i = -1;
 479                                 break;
 480                         }
 481                 } else {
 482                         value &= B43_DMA32_RXSTATE;
 483                         if (value == B43_DMA32_RXSTAT_DISABLED) {
 484                                 i = -1;
 485                                 break;
 486                         }
 487                 }
 488                 msleep(1);
 489         }
 490         if (i != -1) {
 491                 b43err(dev->wl, "DMA RX reset timed out\n");
 492                 return -ENODEV;
 493         }
 494
 495         return 0;
 496 }
 497
 498 /* Reset the TX DMA channel */
 499 int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
 500 {
 501         int i;
 502         u32 value;
 503         u16 offset;
 504
 505         might_sleep();
 506
 507         for (i = 0; i < 10; i++) {
 508                 offset = dma64 ? B43_DMA64_TXSTATUS : B43_DMA32_TXSTATUS;
 509                 value = b43_read32(dev, mmio_base + offset);
 510                 if (dma64) {
 511                         value &= B43_DMA64_TXSTAT;
 512                         if (value == B43_DMA64_TXSTAT_DISABLED ||
 513                             value == B43_DMA64_TXSTAT_IDLEWAIT ||
 514                             value == B43_DMA64_TXSTAT_STOPPED)
 515                                 break;
 516                 } else {
 517                         value &= B43_DMA32_TXSTATE;
 518                         if (value == B43_DMA32_TXSTAT_DISABLED ||
 519                             value == B43_DMA32_TXSTAT_IDLEWAIT ||
 520                             value == B43_DMA32_TXSTAT_STOPPED)
 521                                 break;
 522                 }
 523                 msleep(1);
 524         }
 525         offset = dma64 ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
 526         b43_write32(dev, mmio_base + offset, 0);
 527         for (i = 0; i < 10; i++) {
 528                 offset = dma64 ? B43_DMA64_TXSTATUS : B43_DMA32_TXSTATUS;
 529                 value = b43_read32(dev, mmio_base + offset);
 530                 if (dma64) {
 531                         value &= B43_DMA64_TXSTAT;
 532                         if (value == B43_DMA64_TXSTAT_DISABLED) {
 533                                 i = -1;
 534                                 break;
 535                         }
 536                 } else {
 537                         value &= B43_DMA32_TXSTATE;
 538                         if (value == B43_DMA32_TXSTAT_DISABLED) {
 539                                 i = -1;
 540                                 break;
 541                         }
 542                 }
 543                 msleep(1);
 544         }
 545         if (i != -1) {
 546                 b43err(dev->wl, "DMA TX reset timed out\n");
 547                 return -ENODEV;
 548         }
 549         /* ensure the reset is completed. */
 550         msleep(1);
 551
 552         return 0;
 553 }
 554
 555 static int setup_rx_descbuffer(struct b43_dmaring *ring,
 556                                struct b43_dmadesc_generic *desc,
 557                                struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
 558 {
 559         struct b43_rxhdr_fw4 *rxhdr;
 560         struct b43_hwtxstatus *txstat;
 561         dma_addr_t dmaaddr;
 562         struct sk_buff *skb;
 563
 564         B43_WARN_ON(ring->tx);
 565
 566         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 567         if (unlikely(!skb))
 568                 return -ENOMEM;
 569         dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
 570         if (dma_mapping_error(dmaaddr)) {
 571                 /* ugh. try to realloc in zone_dma */
 572                 gfp_flags |= GFP_DMA;
 573
 574                 dev_kfree_skb_any(skb);
 575
 576                 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 577                 if (unlikely(!skb))
 578                         return -ENOMEM;
 579                 dmaaddr = map_descbuffer(ring, skb->data,
 580                                          ring->rx_buffersize, 0);
 581         }
 582
 583         if (dma_mapping_error(dmaaddr)) {
 584                 dev_kfree_skb_any(skb);
 585                 return -EIO;
 586         }
 587
 588         meta->skb = skb;
 589         meta->dmaaddr = dmaaddr;
 590         ring->ops->fill_descriptor(ring, desc, dmaaddr,
 591                                    ring->rx_buffersize, 0, 0, 0);
 592
 593         rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
 594         rxhdr->frame_len = 0;
 595         txstat = (struct b43_hwtxstatus *)(skb->data);
 596         txstat->cookie = 0;
 597
 598         return 0;
 599 }
 600
 601 /* Allocate the initial descbuffers.
 602  * This is used for an RX ring only.
 603  */
 604 static int alloc_initial_descbuffers(struct b43_dmaring *ring)
 605 {
 606         int i, err = -ENOMEM;
 607         struct b43_dmadesc_generic *desc;
 608         struct b43_dmadesc_meta *meta;
 609
 610         for (i = 0; i < ring->nr_slots; i++) {
 611                 desc = ring->ops->idx2desc(ring, i, &meta);
 612
 613                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
 614                 if (err) {
 615                         b43err(ring->dev->wl,
 616                                "Failed to allocate initial descbuffers\n");
 617                         goto err_unwind;
 618                 }
 619         }
 620         mb();
 621         ring->used_slots = ring->nr_slots;
 622         err = 0;
 623       out:
 624         return err;
 625
 626       err_unwind:
 627         for (i--; i >= 0; i--) {
 628                 desc = ring->ops->idx2desc(ring, i, &meta);
 629
 630                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
 631                 dev_kfree_skb(meta->skb);
 632         }
 633         goto out;
 634 }
 635
 636 /* Do initial setup of the DMA controller.
 637  * Reset the controller, write the ring busaddress
 638  * and switch the "enable" bit on.
 639  */
 640 static int dmacontroller_setup(struct b43_dmaring *ring)
 641 {
 642         int err = 0;
 643         u32 value;
 644         u32 addrext;
 645         u32 trans = ssb_dma_translation(ring->dev->dev);
 646
 647         if (ring->tx) {
 648                 if (ring->dma64) {
 649                         u64 ringbase = (u64) (ring->dmabase);
 650
 651                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
 652                             >> SSB_DMA_TRANSLATION_SHIFT;
 653                         value = B43_DMA64_TXENABLE;
 654                         value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
 655                             & B43_DMA64_TXADDREXT_MASK;
 656                         b43_dma_write(ring, B43_DMA64_TXCTL, value);
 657                         b43_dma_write(ring, B43_DMA64_TXRINGLO,
 658                                       (ringbase & 0xFFFFFFFF));
 659                         b43_dma_write(ring, B43_DMA64_TXRINGHI,
 660                                       ((ringbase >> 32) &
 661                                        ~SSB_DMA_TRANSLATION_MASK)
 662                                       | (trans << 1));
 663                 } else {
 664                         u32 ringbase = (u32) (ring->dmabase);
 665
 666                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
 667                             >> SSB_DMA_TRANSLATION_SHIFT;
 668                         value = B43_DMA32_TXENABLE;
 669                         value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
 670                             & B43_DMA32_TXADDREXT_MASK;
 671                         b43_dma_write(ring, B43_DMA32_TXCTL, value);
 672                         b43_dma_write(ring, B43_DMA32_TXRING,
 673                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
 674                                       | trans);
 675                 }
 676         } else {
 677                 err = alloc_initial_descbuffers(ring);
 678                 if (err)
 679                         goto out;
 680                 if (ring->dma64) {
 681                         u64 ringbase = (u64) (ring->dmabase);
 682
 683                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
 684                             >> SSB_DMA_TRANSLATION_SHIFT;
 685                         value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
 686                         value |= B43_DMA64_RXENABLE;
 687                         value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
 688                             & B43_DMA64_RXADDREXT_MASK;
 689                         b43_dma_write(ring, B43_DMA64_RXCTL, value);
 690                         b43_dma_write(ring, B43_DMA64_RXRINGLO,
 691                                       (ringbase & 0xFFFFFFFF));
 692                         b43_dma_write(ring, B43_DMA64_RXRINGHI,
 693                                       ((ringbase >> 32) &
 694                                        ~SSB_DMA_TRANSLATION_MASK)
 695                                       | (trans << 1));
 696                         b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
 697                                       sizeof(struct b43_dmadesc64));
 698                 } else {
 699                         u32 ringbase = (u32) (ring->dmabase);
 700
 701                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
 702                             >> SSB_DMA_TRANSLATION_SHIFT;
 703                         value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
 704                         value |= B43_DMA32_RXENABLE;
 705                         value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
 706                             & B43_DMA32_RXADDREXT_MASK;
 707                         b43_dma_write(ring, B43_DMA32_RXCTL, value);
 708                         b43_dma_write(ring, B43_DMA32_RXRING,
 709                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
 710                                       | trans);
 711                         b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
 712                                       sizeof(struct b43_dmadesc32));
 713                 }
 714         }
 715
 716 out:
 717         return err;
 718 }
 719
 720 /* Shutdown the DMA controller. */
 721 static void dmacontroller_cleanup(struct b43_dmaring *ring)
 722 {
 723         if (ring->tx) {
 724                 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
 725                                            ring->dma64);
 726                 if (ring->dma64) {
 727                         b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
 728                         b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
 729                 } else
 730                         b43_dma_write(ring, B43_DMA32_TXRING, 0);
 731         } else {
 732                 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
 733                                            ring->dma64);
 734                 if (ring->dma64) {
 735                         b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
 736                         b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
 737                 } else
 738                         b43_dma_write(ring, B43_DMA32_RXRING, 0);
 739         }
 740 }
 741
 742 static void free_all_descbuffers(struct b43_dmaring *ring)
 743 {
 744         struct b43_dmadesc_generic *desc;
 745         struct b43_dmadesc_meta *meta;
 746         int i;
 747
 748         if (!ring->used_slots)
 749                 return;
 750         for (i = 0; i < ring->nr_slots; i++) {
 751                 desc = ring->ops->idx2desc(ring, i, &meta);
 752
 753                 if (!meta->skb) {
 754                         B43_WARN_ON(!ring->tx);
 755                         continue;
 756                 }
 757                 if (ring->tx) {
 758                         unmap_descbuffer(ring, meta->dmaaddr,
 759                                          meta->skb->len, 1);
 760                 } else {
 761                         unmap_descbuffer(ring, meta->dmaaddr,
 762                                          ring->rx_buffersize, 0);
 763                 }
 764                 free_descriptor_buffer(ring, meta);
 765         }
 766 }
 767
 768 static u64 supported_dma_mask(struct b43_wldev *dev)
 769 {
 770         u32 tmp;
 771         u16 mmio_base;
 772
 773         tmp = b43_read32(dev, SSB_TMSHIGH);
 774         if (tmp & SSB_TMSHIGH_DMA64)
 775                 return DMA_64BIT_MASK;
 776         mmio_base = b43_dmacontroller_base(0, 0);
 777         b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
 778         tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
 779         if (tmp & B43_DMA32_TXADDREXT_MASK)
 780                 return DMA_32BIT_MASK;
 781
 782         return DMA_30BIT_MASK;
 783 }
 784
 785 /* Main initialization function. */
 786 static
 787 struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
 788                                       int controller_index,
 789                                       int for_tx, int dma64)
 790 {
 791         struct b43_dmaring *ring;
 792         int err;
 793         int nr_slots;
 794         dma_addr_t dma_test;
 795
 796         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 797         if (!ring)
 798                 goto out;
 799
 800         nr_slots = B43_RXRING_SLOTS;
 801         if (for_tx)
 802                 nr_slots = B43_TXRING_SLOTS;
 803
 804         ring->meta = kcalloc(nr_slots, sizeof(struct b43_dmadesc_meta),
 805                              GFP_KERNEL);
 806         if (!ring->meta)
 807                 goto err_kfree_ring;
 808         if (for_tx) {
 809                 ring->txhdr_cache = kcalloc(nr_slots,
 810                                             b43_txhdr_size(dev),
 811                                             GFP_KERNEL);
 812                 if (!ring->txhdr_cache)
 813                         goto err_kfree_meta;
 814
 815                 /* test for ability to dma to txhdr_cache */
 816                 dma_test = dma_map_single(dev->dev->dev,
 817                                           ring->txhdr_cache,
 818                                           b43_txhdr_size(dev),
 819                                           DMA_TO_DEVICE);
 820
 821                 if (dma_mapping_error(dma_test)) {
 822                         /* ugh realloc */
 823                         kfree(ring->txhdr_cache);
 824                         ring->txhdr_cache = kcalloc(nr_slots,
 825                                                     b43_txhdr_size(dev),
 826                                                     GFP_KERNEL | GFP_DMA);
 827                         if (!ring->txhdr_cache)
 828                                 goto err_kfree_meta;
 829
 830                         dma_test = dma_map_single(dev->dev->dev,
 831                                                   ring->txhdr_cache,
 832                                                   b43_txhdr_size(dev),
 833                                                   DMA_TO_DEVICE);
 834
 835                         if (dma_mapping_error(dma_test))
 836                                 goto err_kfree_txhdr_cache;
 837                 }
 838
 839                 dma_unmap_single(dev->dev->dev,
 840                                  dma_test, b43_txhdr_size(dev),
 841                                  DMA_TO_DEVICE);
 842         }
 843
 844         ring->dev = dev;
 845         ring->nr_slots = nr_slots;
 846         ring->mmio_base = b43_dmacontroller_base(dma64, controller_index);
 847         ring->index = controller_index;
 848         ring->dma64 = !!dma64;
 849         if (dma64)
 850                 ring->ops = &dma64_ops;
 851         else
 852                 ring->ops = &dma32_ops;
 853         if (for_tx) {
 854                 ring->tx = 1;
 855                 ring->current_slot = -1;
 856         } else {
 857                 if (ring->index == 0) {
 858                         ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
 859                         ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
 860                 } else if (ring->index == 3) {
 861                         ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE;
 862                         ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET;
 863                 } else
 864                         B43_WARN_ON(1);
 865         }
 866         spin_lock_init(&ring->lock);
 867 #ifdef CONFIG_B43_DEBUG
 868         ring->last_injected_overflow = jiffies;
 869 #endif
 870
 871         err = alloc_ringmemory(ring);
 872         if (err)
 873                 goto err_kfree_txhdr_cache;
 874         err = dmacontroller_setup(ring);
 875         if (err)
 876                 goto err_free_ringmemory;
 877
 878       out:
 879         return ring;
 880
 881       err_free_ringmemory:
 882         free_ringmemory(ring);
 883       err_kfree_txhdr_cache:
 884         kfree(ring->txhdr_cache);
 885       err_kfree_meta:
 886         kfree(ring->meta);
 887       err_kfree_ring:
 888         kfree(ring);
 889         ring = NULL;
 890         goto out;
 891 }
 892
 893 /* Main cleanup function. */
 894 static void b43_destroy_dmaring(struct b43_dmaring *ring)
 895 {
 896         if (!ring)
 897                 return;
 898
 899         b43dbg(ring->dev->wl, "DMA-%s 0x%04X (%s) max used slots: %d/%d\n",
 900                (ring->dma64) ? "64" : "32",
 901                ring->mmio_base,
 902                (ring->tx) ? "TX" : "RX", ring->max_used_slots, ring->nr_slots);
 903         /* Device IRQs are disabled prior entering this function,
 904          * so no need to take care of concurrency with rx handler stuff.
 905          */
 906         dmacontroller_cleanup(ring);
 907         free_all_descbuffers(ring);
 908         free_ringmemory(ring);
 909
 910         kfree(ring->txhdr_cache);
 911         kfree(ring->meta);
 912         kfree(ring);
 913 }
 914
 915 void b43_dma_free(struct b43_wldev *dev)
 916 {
 917         struct b43_dma *dma = &dev->dma;
 918
 919         b43_destroy_dmaring(dma->rx_ring3);
 920         dma->rx_ring3 = NULL;
 921         b43_destroy_dmaring(dma->rx_ring0);
 922         dma->rx_ring0 = NULL;
 923
 924         b43_destroy_dmaring(dma->tx_ring5);
 925         dma->tx_ring5 = NULL;
 926         b43_destroy_dmaring(dma->tx_ring4);
 927         dma->tx_ring4 = NULL;
 928         b43_destroy_dmaring(dma->tx_ring3);
 929         dma->tx_ring3 = NULL;
 930         b43_destroy_dmaring(dma->tx_ring2);
 931         dma->tx_ring2 = NULL;
 932         b43_destroy_dmaring(dma->tx_ring1);
 933         dma->tx_ring1 = NULL;
 934         b43_destroy_dmaring(dma->tx_ring0);
 935         dma->tx_ring0 = NULL;
 936 }
 937
 938 int b43_dma_init(struct b43_wldev *dev)
 939 {
 940         struct b43_dma *dma = &dev->dma;
 941         struct b43_dmaring *ring;
 942         int err;
 943         u64 dmamask;
 944         int dma64 = 0;
 945
 946         dmamask = supported_dma_mask(dev);
 947         if (dmamask == DMA_64BIT_MASK)
 948                 dma64 = 1;
 949
 950         err = ssb_dma_set_mask(dev->dev, dmamask);
 951         if (err) {
 952                 b43err(dev->wl, "The machine/kernel does not support "
 953                        "the required DMA mask (0x%08X%08X)\n",
 954                        (unsigned int)((dmamask & 0xFFFFFFFF00000000ULL) >> 32),
 955                        (unsigned int)(dmamask & 0x00000000FFFFFFFFULL));
 956                 return -EOPNOTSUPP;
 957         }
 958
 959         err = -ENOMEM;
 960         /* setup TX DMA channels. */
 961         ring = b43_setup_dmaring(dev, 0, 1, dma64);
 962         if (!ring)
 963                 goto out;
 964         dma->tx_ring0 = ring;
 965
 966         ring = b43_setup_dmaring(dev, 1, 1, dma64);
 967         if (!ring)
 968                 goto err_destroy_tx0;
 969         dma->tx_ring1 = ring;
 970
 971         ring = b43_setup_dmaring(dev, 2, 1, dma64);
 972         if (!ring)
 973                 goto err_destroy_tx1;
 974         dma->tx_ring2 = ring;
 975
 976         ring = b43_setup_dmaring(dev, 3, 1, dma64);
 977         if (!ring)
 978                 goto err_destroy_tx2;
 979         dma->tx_ring3 = ring;
 980
 981         ring = b43_setup_dmaring(dev, 4, 1, dma64);
 982         if (!ring)
 983                 goto err_destroy_tx3;
 984         dma->tx_ring4 = ring;
 985
 986         ring = b43_setup_dmaring(dev, 5, 1, dma64);
 987         if (!ring)
 988                 goto err_destroy_tx4;
 989         dma->tx_ring5 = ring;
 990
 991         /* setup RX DMA channels. */
 992         ring = b43_setup_dmaring(dev, 0, 0, dma64);
 993         if (!ring)
 994                 goto err_destroy_tx5;
 995         dma->rx_ring0 = ring;
 996
 997         if (dev->dev->id.revision < 5) {
 998                 ring = b43_setup_dmaring(dev, 3, 0, dma64);
 999                 if (!ring)
1000                         goto err_destroy_rx0;
1001                 dma->rx_ring3 = ring;
1002         }
1003
1004         b43dbg(dev->wl, "%d-bit DMA initialized\n",
1005                (dmamask == DMA_64BIT_MASK) ? 64 :
1006                (dmamask == DMA_32BIT_MASK) ? 32 : 30);
1007         err = 0;
1008       out:
1009         return err;
1010
1011       err_destroy_rx0:
1012         b43_destroy_dmaring(dma->rx_ring0);
1013         dma->rx_ring0 = NULL;
1014       err_destroy_tx5:
1015         b43_destroy_dmaring(dma->tx_ring5);
1016         dma->tx_ring5 = NULL;
1017       err_destroy_tx4:
1018         b43_destroy_dmaring(dma->tx_ring4);
1019         dma->tx_ring4 = NULL;
1020       err_destroy_tx3:
1021         b43_destroy_dmaring(dma->tx_ring3);
1022         dma->tx_ring3 = NULL;
1023       err_destroy_tx2:
1024         b43_destroy_dmaring(dma->tx_ring2);
1025         dma->tx_ring2 = NULL;
1026       err_destroy_tx1:
1027         b43_destroy_dmaring(dma->tx_ring1);
1028         dma->tx_ring1 = NULL;
1029       err_destroy_tx0:
1030         b43_destroy_dmaring(dma->tx_ring0);
1031         dma->tx_ring0 = NULL;
1032         goto out;
1033 }
1034
1035 /* Generate a cookie for the TX header. */
1036 static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1037 {
1038         u16 cookie = 0x1000;
1039
1040         /* Use the upper 4 bits of the cookie as
1041          * DMA controller ID and store the slot number
1042          * in the lower 12 bits.
1043          * Note that the cookie must never be 0, as this
1044          * is a special value used in RX path.
1045          * It can also not be 0xFFFF because that is special
1046          * for multicast frames.
1047          */
1048         switch (ring->index) {
1049         case 0:
1050                 cookie = 0x1000;
1051                 break;
1052         case 1:
1053                 cookie = 0x2000;
1054                 break;
1055         case 2:
1056                 cookie = 0x3000;
1057                 break;
1058         case 3:
1059                 cookie = 0x4000;
1060                 break;
1061         case 4:
1062                 cookie = 0x5000;
1063                 break;
1064         case 5:
1065                 cookie = 0x6000;
1066                 break;
1067         default:
1068                 B43_WARN_ON(1);
1069         }
1070         B43_WARN_ON(slot & ~0x0FFF);
1071         cookie |= (u16) slot;
1072
1073         return cookie;
1074 }
1075
1076 /* Inspect a cookie and find out to which controller/slot it belongs. */
1077 static
1078 struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1079 {
1080         struct b43_dma *dma = &dev->dma;
1081         struct b43_dmaring *ring = NULL;
1082
1083         switch (cookie & 0xF000) {
1084         case 0x1000:
1085                 ring = dma->tx_ring0;
1086                 break;
1087         case 0x2000:
1088                 ring = dma->tx_ring1;
1089                 break;
1090         case 0x3000:
1091                 ring = dma->tx_ring2;
1092                 break;
1093         case 0x4000:
1094                 ring = dma->tx_ring3;
1095                 break;
1096         case 0x5000:
1097                 ring = dma->tx_ring4;
1098                 break;
1099         case 0x6000:
1100                 ring = dma->tx_ring5;
1101                 break;
1102         default:
1103                 B43_WARN_ON(1);
1104         }
1105         *slot = (cookie & 0x0FFF);
1106         B43_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1107
1108         return ring;
1109 }
1110
1111 static int dma_tx_fragment(struct b43_dmaring *ring,
1112                            struct sk_buff *skb,
1113                            struct ieee80211_tx_control *ctl)
1114 {
1115         const struct b43_dma_ops *ops = ring->ops;
1116         u8 *header;
1117         int slot, old_top_slot, old_used_slots;
1118         int err;
1119         struct b43_dmadesc_generic *desc;
1120         struct b43_dmadesc_meta *meta;
1121         struct b43_dmadesc_meta *meta_hdr;
1122         struct sk_buff *bounce_skb;
1123         u16 cookie;
1124         size_t hdrsize = b43_txhdr_size(ring->dev);
1125
1126 #define SLOTS_PER_PACKET  2
1127         B43_WARN_ON(skb_shinfo(skb)->nr_frags);
1128
1129         old_top_slot = ring->current_slot;
1130         old_used_slots = ring->used_slots;
1131
1132         /* Get a slot for the header. */
1133         slot = request_slot(ring);
1134         desc = ops->idx2desc(ring, slot, &meta_hdr);
1135         memset(meta_hdr, 0, sizeof(*meta_hdr));
1136
1137         header = &(ring->txhdr_cache[slot * hdrsize]);
1138         cookie = generate_cookie(ring, slot);
1139         err = b43_generate_txhdr(ring->dev, header,
1140                                  skb->data, skb->len, ctl, cookie);
1141         if (unlikely(err)) {
1142                 ring->current_slot = old_top_slot;
1143                 ring->used_slots = old_used_slots;
1144                 return err;
1145         }
1146
1147         meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1148                                            hdrsize, 1);
1149         if (dma_mapping_error(meta_hdr->dmaaddr)) {
1150                 ring->current_slot = old_top_slot;
1151                 ring->used_slots = old_used_slots;
1152                 return -EIO;
1153         }
1154         ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1155                              hdrsize, 1, 0, 0);
1156
1157         /* Get a slot for the payload. */
1158         slot = request_slot(ring);
1159         desc = ops->idx2desc(ring, slot, &meta);
1160         memset(meta, 0, sizeof(*meta));
1161
1162         memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
1163         meta->skb = skb;
1164         meta->is_last_fragment = 1;
1165
1166         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1167         /* create a bounce buffer in zone_dma on mapping failure. */
1168         if (dma_mapping_error(meta->dmaaddr)) {
1169                 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1170                 if (!bounce_skb) {
1171                         ring->current_slot = old_top_slot;
1172                         ring->used_slots = old_used_slots;
1173                         err = -ENOMEM;
1174                         goto out_unmap_hdr;
1175                 }
1176
1177                 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1178                 dev_kfree_skb_any(skb);
1179                 skb = bounce_skb;
1180                 meta->skb = skb;
1181                 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1182                 if (dma_mapping_error(meta->dmaaddr)) {
1183                         ring->current_slot = old_top_slot;
1184                         ring->used_slots = old_used_slots;
1185                         err = -EIO;
1186                         goto out_free_bounce;
1187                 }
1188         }
1189
1190         ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1191
1192         if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) {
1193                 /* Tell the firmware about the cookie of the last
1194                  * mcast frame, so it can clear the more-data bit in it. */
1195                 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1196                                 B43_SHM_SH_MCASTCOOKIE, cookie);
1197         }
1198         /* Now transfer the whole frame. */
1199         wmb();
1200         ops->poke_tx(ring, next_slot(ring, slot));
1201         return 0;
1202
1203 out_free_bounce:
1204         dev_kfree_skb_any(skb);
1205 out_unmap_hdr:
1206         unmap_descbuffer(ring, meta_hdr->dmaaddr,
1207                          hdrsize, 1);
1208         return err;
1209 }
1210
1211 static inline int should_inject_overflow(struct b43_dmaring *ring)
1212 {
1213 #ifdef CONFIG_B43_DEBUG
1214         if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1215                 /* Check if we should inject another ringbuffer overflow
1216                  * to test handling of this situation in the stack. */
1217                 unsigned long next_overflow;
1218
1219                 next_overflow = ring->last_injected_overflow + HZ;
1220                 if (time_after(jiffies, next_overflow)) {
1221                         ring->last_injected_overflow = jiffies;
1222                         b43dbg(ring->dev->wl,
1223                                "Injecting TX ring overflow on "
1224                                "DMA controller %d\n", ring->index);
1225                         return 1;
1226                 }
1227         }
1228 #endif /* CONFIG_B43_DEBUG */
1229         return 0;
1230 }
1231
1232 int b43_dma_tx(struct b43_wldev *dev,
1233                struct sk_buff *skb, struct ieee80211_tx_control *ctl)
1234 {
1235         struct b43_dmaring *ring;
1236         struct ieee80211_hdr *hdr;
1237         int err = 0;
1238         unsigned long flags;
1239
1240         if (unlikely(skb->len < 2 + 2 + 6)) {
1241                 /* Too short, this can't be a valid frame. */
1242                 return -EINVAL;
1243         }
1244
1245         hdr = (struct ieee80211_hdr *)skb->data;
1246         if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) {
1247                 /* The multicast ring will be sent after the DTIM */
1248                 ring = dev->dma.tx_ring4;
1249                 /* Set the more-data bit. Ucode will clear it on
1250                  * the last frame for us. */
1251                 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1252         } else {
1253                 /* Decide by priority where to put this frame. */
1254                 ring = priority_to_txring(dev, ctl->queue);
1255         }
1256
1257         spin_lock_irqsave(&ring->lock, flags);
1258         B43_WARN_ON(!ring->tx);
1259         if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
1260                 b43warn(dev->wl, "DMA queue overflow\n");
1261                 err = -ENOSPC;
1262                 goto out_unlock;
1263         }
1264         /* Check if the queue was stopped in mac80211,
1265          * but we got called nevertheless.
1266          * That would be a mac80211 bug. */
1267         B43_WARN_ON(ring->stopped);
1268
1269         err = dma_tx_fragment(ring, skb, ctl);
1270         if (unlikely(err == -ENOKEY)) {
1271                 /* Drop this packet, as we don't have the encryption key
1272                  * anymore and must not transmit it unencrypted. */
1273                 dev_kfree_skb_any(skb);
1274                 err = 0;
1275                 goto out_unlock;
1276         }
1277         if (unlikely(err)) {
1278                 b43err(dev->wl, "DMA tx mapping failure\n");
1279                 goto out_unlock;
1280         }
1281         ring->nr_tx_packets++;
1282         if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1283             should_inject_overflow(ring)) {
1284                 /* This TX ring is full. */
1285                 ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring));
1286                 ring->stopped = 1;
1287                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1288                         b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1289                 }
1290         }
1291 out_unlock:
1292         spin_unlock_irqrestore(&ring->lock, flags);
1293
1294         return err;
1295 }
1296
1297 void b43_dma_handle_txstatus(struct b43_wldev *dev,
1298                              const struct b43_txstatus *status)
1299 {
1300         const struct b43_dma_ops *ops;
1301         struct b43_dmaring *ring;
1302         struct b43_dmadesc_generic *desc;
1303         struct b43_dmadesc_meta *meta;
1304         int slot;
1305
1306         ring = parse_cookie(dev, status->cookie, &slot);
1307         if (unlikely(!ring))
1308                 return;
1309         B43_WARN_ON(!irqs_disabled());
1310         spin_lock(&ring->lock);
1311
1312         B43_WARN_ON(!ring->tx);
1313         ops = ring->ops;
1314         while (1) {
1315                 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1316                 desc = ops->idx2desc(ring, slot, &meta);
1317
1318                 if (meta->skb)
1319                         unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len,
1320                                          1);
1321                 else
1322                         unmap_descbuffer(ring, meta->dmaaddr,
1323                                          b43_txhdr_size(dev), 1);
1324
1325                 if (meta->is_last_fragment) {
1326                         B43_WARN_ON(!meta->skb);
1327                         /* Call back to inform the ieee80211 subsystem about the
1328                          * status of the transmission.
1329                          * Some fields of txstat are already filled in dma_tx().
1330                          */
1331                         if (status->acked) {
1332                                 meta->txstat.flags |= IEEE80211_TX_STATUS_ACK;
1333                         } else {
1334                                 if (!(meta->txstat.control.flags
1335                                       & IEEE80211_TXCTL_NO_ACK))
1336                                         meta->txstat.excessive_retries = 1;
1337                         }
1338                         if (status->frame_count == 0) {
1339                                 /* The frame was not transmitted at all. */
1340                                 meta->txstat.retry_count = 0;
1341                         } else
1342                                 meta->txstat.retry_count = status->frame_count - 1;
1343                         ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb,
1344                                                     &(meta->txstat));
1345                         /* skb is freed by ieee80211_tx_status_irqsafe() */
1346                         meta->skb = NULL;
1347                 } else {
1348                         /* No need to call free_descriptor_buffer here, as
1349                          * this is only the txhdr, which is not allocated.
1350                          */
1351                         B43_WARN_ON(meta->skb);
1352                 }
1353
1354                 /* Everything unmapped and free'd. So it's not used anymore. */
1355                 ring->used_slots--;
1356
1357                 if (meta->is_last_fragment)
1358                         break;
1359                 slot = next_slot(ring, slot);
1360         }
1361         dev->stats.last_tx = jiffies;
1362         if (ring->stopped) {
1363                 B43_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1364                 ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring));
1365                 ring->stopped = 0;
1366                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1367                         b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1368                 }
1369         }
1370
1371         spin_unlock(&ring->lock);
1372 }
1373
1374 void b43_dma_get_tx_stats(struct b43_wldev *dev,
1375                           struct ieee80211_tx_queue_stats *stats)
1376 {
1377         const int nr_queues = dev->wl->hw->queues;
1378         struct b43_dmaring *ring;
1379         struct ieee80211_tx_queue_stats_data *data;
1380         unsigned long flags;
1381         int i;
1382
1383         for (i = 0; i < nr_queues; i++) {
1384                 data = &(stats->data[i]);
1385                 ring = priority_to_txring(dev, i);
1386
1387                 spin_lock_irqsave(&ring->lock, flags);
1388                 data->len = ring->used_slots / SLOTS_PER_PACKET;
1389                 data->limit = ring->nr_slots / SLOTS_PER_PACKET;
1390                 data->count = ring->nr_tx_packets;
1391                 spin_unlock_irqrestore(&ring->lock, flags);
1392         }
1393 }
1394
1395 static void dma_rx(struct b43_dmaring *ring, int *slot)
1396 {
1397         const struct b43_dma_ops *ops = ring->ops;
1398         struct b43_dmadesc_generic *desc;
1399         struct b43_dmadesc_meta *meta;
1400         struct b43_rxhdr_fw4 *rxhdr;
1401         struct sk_buff *skb;
1402         u16 len;
1403         int err;
1404         dma_addr_t dmaaddr;
1405
1406         desc = ops->idx2desc(ring, *slot, &meta);
1407
1408         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1409         skb = meta->skb;
1410
1411         if (ring->index == 3) {
1412                 /* We received an xmit status. */
1413                 struct b43_hwtxstatus *hw = (struct b43_hwtxstatus *)skb->data;
1414                 int i = 0;
1415
1416                 while (hw->cookie == 0) {
1417                         if (i > 100)
1418                                 break;
1419                         i++;
1420                         udelay(2);
1421                         barrier();
1422                 }
1423                 b43_handle_hwtxstatus(ring->dev, hw);
1424                 /* recycle the descriptor buffer. */
1425                 sync_descbuffer_for_device(ring, meta->dmaaddr,
1426                                            ring->rx_buffersize);
1427
1428                 return;
1429         }
1430         rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1431         len = le16_to_cpu(rxhdr->frame_len);
1432         if (len == 0) {
1433                 int i = 0;
1434
1435                 do {
1436                         udelay(2);
1437                         barrier();
1438                         len = le16_to_cpu(rxhdr->frame_len);
1439                 } while (len == 0 && i++ < 5);
1440                 if (unlikely(len == 0)) {
1441                         /* recycle the descriptor buffer. */
1442                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1443                                                    ring->rx_buffersize);
1444                         goto drop;
1445                 }
1446         }
1447         if (unlikely(len > ring->rx_buffersize)) {
1448                 /* The data did not fit into one descriptor buffer
1449                  * and is split over multiple buffers.
1450                  * This should never happen, as we try to allocate buffers
1451                  * big enough. So simply ignore this packet.
1452                  */
1453                 int cnt = 0;
1454                 s32 tmp = len;
1455
1456                 while (1) {
1457                         desc = ops->idx2desc(ring, *slot, &meta);
1458                         /* recycle the descriptor buffer. */
1459                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1460                                                    ring->rx_buffersize);
1461                         *slot = next_slot(ring, *slot);
1462                         cnt++;
1463                         tmp -= ring->rx_buffersize;
1464                         if (tmp <= 0)
1465                                 break;
1466                 }
1467                 b43err(ring->dev->wl, "DMA RX buffer too small "
1468                        "(len: %u, buffer: %u, nr-dropped: %d)\n",
1469                        len, ring->rx_buffersize, cnt);
1470                 goto drop;
1471         }
1472
1473         dmaaddr = meta->dmaaddr;
1474         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1475         if (unlikely(err)) {
1476                 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1477                 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1478                 goto drop;
1479         }
1480
1481         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1482         skb_put(skb, len + ring->frameoffset);
1483         skb_pull(skb, ring->frameoffset);
1484
1485         b43_rx(ring->dev, skb, rxhdr);
1486       drop:
1487         return;
1488 }
1489
1490 void b43_dma_rx(struct b43_dmaring *ring)
1491 {
1492         const struct b43_dma_ops *ops = ring->ops;
1493         int slot, current_slot;
1494         int used_slots = 0;
1495
1496         B43_WARN_ON(ring->tx);
1497         current_slot = ops->get_current_rxslot(ring);
1498         B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1499
1500         slot = ring->current_slot;
1501         for (; slot != current_slot; slot = next_slot(ring, slot)) {
1502                 dma_rx(ring, &slot);
1503                 update_max_used_slots(ring, ++used_slots);
1504         }
1505         ops->set_current_rxslot(ring, slot);
1506         ring->current_slot = slot;
1507 }
1508
1509 static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1510 {
1511         unsigned long flags;
1512
1513         spin_lock_irqsave(&ring->lock, flags);
1514         B43_WARN_ON(!ring->tx);
1515         ring->ops->tx_suspend(ring);
1516         spin_unlock_irqrestore(&ring->lock, flags);
1517 }
1518
1519 static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1520 {
1521         unsigned long flags;
1522
1523         spin_lock_irqsave(&ring->lock, flags);
1524         B43_WARN_ON(!ring->tx);
1525         ring->ops->tx_resume(ring);
1526         spin_unlock_irqrestore(&ring->lock, flags);
1527 }
1528
1529 void b43_dma_tx_suspend(struct b43_wldev *dev)
1530 {
1531         b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1532         b43_dma_tx_suspend_ring(dev->dma.tx_ring0);
1533         b43_dma_tx_suspend_ring(dev->dma.tx_ring1);
1534         b43_dma_tx_suspend_ring(dev->dma.tx_ring2);
1535         b43_dma_tx_suspend_ring(dev->dma.tx_ring3);
1536         b43_dma_tx_suspend_ring(dev->dma.tx_ring4);
1537         b43_dma_tx_suspend_ring(dev->dma.tx_ring5);
1538 }
1539
1540 void b43_dma_tx_resume(struct b43_wldev *dev)
1541 {
1542         b43_dma_tx_resume_ring(dev->dma.tx_ring5);
1543         b43_dma_tx_resume_ring(dev->dma.tx_ring4);
1544         b43_dma_tx_resume_ring(dev->dma.tx_ring3);
1545         b43_dma_tx_resume_ring(dev->dma.tx_ring2);
1546         b43_dma_tx_resume_ring(dev->dma.tx_ring1);
1547         b43_dma_tx_resume_ring(dev->dma.tx_ring0);
1548         b43_power_saving_ctl_bits(dev, 0);
1549 }