2 * Copyright (c) 2008, Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 /* Implementation of the main "ATH" layer. */
22 static int ath_outdoor; /* enable outdoor use */
24 static const u8 ath_bcast_mac[ETH_ALEN] =
25 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
27 static u32 ath_chainmask_sel_up_rssi_thres =
28 ATH_CHAINMASK_SEL_UP_RSSI_THRES;
29 static u32 ath_chainmask_sel_down_rssi_thres =
30 ATH_CHAINMASK_SEL_DOWN_RSSI_THRES;
31 static u32 ath_chainmask_sel_period =
32 ATH_CHAINMASK_SEL_TIMEOUT;
34 /* return bus cachesize in 4B word units */
36 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
40 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
44 * This check was put in to avoid "unplesant" consequences if
45 * the bootrom has not fully initialized all PCI devices.
46 * Sometimes the cache line size register is not set
50 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
54 * Set current operating mode
56 * This function initializes and fills the rate table in the ATH object based
57 * on the operating mode. The blink rates are also set up here, although
58 * they have been superceeded by the ath_led module.
61 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
63 const struct ath9k_rate_table *rt;
66 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
67 rt = ath9k_hw_getratetable(sc->sc_ah, mode);
70 for (i = 0; i < rt->rateCount; i++)
71 sc->sc_rixmap[rt->info[i].rateCode] = (u8) i;
73 memzero(sc->sc_hwmap, sizeof(sc->sc_hwmap));
74 for (i = 0; i < 256; i++) {
75 u8 ix = rt->rateCodeToIndex[i];
80 sc->sc_hwmap[i].ieeerate =
81 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
82 sc->sc_hwmap[i].rateKbps = rt->info[ix].rateKbps;
84 if (rt->info[ix].shortPreamble ||
85 rt->info[ix].phy == PHY_OFDM) {
86 /* XXX: Handle this */
89 /* NB: this uses the last entry if the rate isn't found */
90 /* XXX beware of overlow */
93 sc->sc_curmode = mode;
95 * All protection frames are transmited at 2Mb/s for
96 * 11g, otherwise at 1Mb/s.
97 * XXX select protection rate index from rate table.
99 sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
103 * Set up rate table (legacy rates)
105 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
107 struct ath_hal *ah = sc->sc_ah;
108 const struct ath9k_rate_table *rt = NULL;
109 struct ieee80211_supported_band *sband;
110 struct ieee80211_rate *rate;
114 case IEEE80211_BAND_2GHZ:
115 rt = ath9k_hw_getratetable(ah, ATH9K_MODE_11G);
117 case IEEE80211_BAND_5GHZ:
118 rt = ath9k_hw_getratetable(ah, ATH9K_MODE_11A);
127 sband = &sc->sbands[band];
128 rate = sc->rates[band];
130 if (rt->rateCount > ATH_RATE_MAX)
131 maxrates = ATH_RATE_MAX;
133 maxrates = rt->rateCount;
135 for (i = 0; i < maxrates; i++) {
136 rate[i].bitrate = rt->info[i].rateKbps / 100;
137 rate[i].hw_value = rt->info[i].rateCode;
139 DPRINTF(sc, ATH_DBG_CONFIG,
140 "%s: Rate: %2dMbps, ratecode: %2d\n",
142 rate[i].bitrate / 10,
148 * Set up channel list
150 static int ath_setup_channels(struct ath_softc *sc)
152 struct ath_hal *ah = sc->sc_ah;
153 int nchan, i, a = 0, b = 0;
154 u8 regclassids[ATH_REGCLASSIDS_MAX];
156 struct ieee80211_supported_band *band_2ghz;
157 struct ieee80211_supported_band *band_5ghz;
158 struct ieee80211_channel *chan_2ghz;
159 struct ieee80211_channel *chan_5ghz;
160 struct ath9k_channel *c;
162 /* Fill in ah->ah_channels */
163 if (!ath9k_regd_init_channels(ah,
172 u32 rd = ah->ah_currentRD;
174 DPRINTF(sc, ATH_DBG_FATAL,
175 "%s: unable to collect channel list; "
176 "regdomain likely %u country code %u\n",
177 __func__, rd, CTRY_DEFAULT);
181 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
182 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
183 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
184 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
186 for (i = 0; i < nchan; i++) {
187 c = &ah->ah_channels[i];
188 if (IS_CHAN_2GHZ(c)) {
189 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
190 chan_2ghz[a].center_freq = c->channel;
191 chan_2ghz[a].max_power = c->maxTxPower;
193 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
194 chan_2ghz[a].flags |=
195 IEEE80211_CHAN_NO_IBSS;
196 if (c->channelFlags & CHANNEL_PASSIVE)
197 chan_2ghz[a].flags |=
198 IEEE80211_CHAN_PASSIVE_SCAN;
200 band_2ghz->n_channels = ++a;
202 DPRINTF(sc, ATH_DBG_CONFIG,
203 "%s: 2MHz channel: %d, "
204 "channelFlags: 0x%x\n",
208 } else if (IS_CHAN_5GHZ(c)) {
209 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
210 chan_5ghz[b].center_freq = c->channel;
211 chan_5ghz[b].max_power = c->maxTxPower;
213 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
214 chan_5ghz[b].flags |=
215 IEEE80211_CHAN_NO_IBSS;
216 if (c->channelFlags & CHANNEL_PASSIVE)
217 chan_5ghz[b].flags |=
218 IEEE80211_CHAN_PASSIVE_SCAN;
220 band_5ghz->n_channels = ++b;
222 DPRINTF(sc, ATH_DBG_CONFIG,
223 "%s: 5MHz channel: %d, "
224 "channelFlags: 0x%x\n",
235 * Determine mode from channel flags
237 * This routine will provide the enumerated WIRELESSS_MODE value based
238 * on the settings of the channel flags. If ho valid set of flags
239 * exist, the lowest mode (11b) is selected.
242 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
244 if (chan->chanmode == CHANNEL_A)
245 return ATH9K_MODE_11A;
246 else if (chan->chanmode == CHANNEL_G)
247 return ATH9K_MODE_11G;
248 else if (chan->chanmode == CHANNEL_B)
249 return ATH9K_MODE_11B;
250 else if (chan->chanmode == CHANNEL_A_HT20)
251 return ATH9K_MODE_11NA_HT20;
252 else if (chan->chanmode == CHANNEL_G_HT20)
253 return ATH9K_MODE_11NG_HT20;
254 else if (chan->chanmode == CHANNEL_A_HT40PLUS)
255 return ATH9K_MODE_11NA_HT40PLUS;
256 else if (chan->chanmode == CHANNEL_A_HT40MINUS)
257 return ATH9K_MODE_11NA_HT40MINUS;
258 else if (chan->chanmode == CHANNEL_G_HT40PLUS)
259 return ATH9K_MODE_11NG_HT40PLUS;
260 else if (chan->chanmode == CHANNEL_G_HT40MINUS)
261 return ATH9K_MODE_11NG_HT40MINUS;
263 /* NB: should not get here */
264 return ATH9K_MODE_11B;
268 * Stop the device, grabbing the top-level lock to protect
269 * against concurrent entry through ath_init (which can happen
270 * if another thread does a system call and the thread doing the
271 * stop is preempted).
274 static int ath_stop(struct ath_softc *sc)
276 struct ath_hal *ah = sc->sc_ah;
278 DPRINTF(sc, ATH_DBG_CONFIG, "%s: invalid %u\n",
279 __func__, sc->sc_invalid);
282 * Shutdown the hardware and driver:
283 * stop output from above
284 * reset 802.11 state machine
285 * (sends station deassoc/deauth frames)
288 * clear transmit machinery
289 * clear receive machinery
291 * reclaim beacon resources
293 * Note that some of this work is not possible if the
294 * hardware is gone (invalid).
297 ath_draintxq(sc, false);
298 if (!sc->sc_invalid) {
300 ath9k_hw_phy_disable(ah);
302 sc->sc_rxlink = NULL;
310 * This function is called when starting a channel scan. It will perform
311 * power save wakeup processing, set the filter for the scan, and get the
312 * chip ready to send broadcast packets out during the scan.
315 void ath_scan_start(struct ath_softc *sc)
317 struct ath_hal *ah = sc->sc_ah;
319 u32 now = (u32) jiffies_to_msecs(get_timestamp());
322 rfilt = ath_calcrxfilter(sc);
323 ath9k_hw_setrxfilter(ah, rfilt);
324 ath9k_hw_write_associd(ah, ath_bcast_mac, 0);
326 /* Restore previous power management state. */
328 DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0\n",
329 now / 1000, now % 1000, __func__, rfilt);
335 * This routine is called by the upper layer when the scan is completed. This
336 * will set the filters back to normal operating mode, set the BSSID to the
337 * correct value, and restore the power save state.
340 void ath_scan_end(struct ath_softc *sc)
342 struct ath_hal *ah = sc->sc_ah;
344 u32 now = (u32) jiffies_to_msecs(get_timestamp());
347 /* Request for a full reset due to rx packet filter changes */
348 sc->sc_full_reset = 1;
349 rfilt = ath_calcrxfilter(sc);
350 ath9k_hw_setrxfilter(ah, rfilt);
351 ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
353 DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0x%x\n",
354 now / 1000, now % 1000, __func__, rfilt, sc->sc_curaid);
358 * Set the current channel
360 * Set/change channels. If the channel is really being changed, it's done
361 * by reseting the chip. To accomplish this we must first cleanup any pending
362 * DMA, then restart stuff after a la ath_init.
364 int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
366 struct ath_hal *ah = sc->sc_ah;
367 bool fastcc = true, stopped;
368 enum ath9k_ht_macmode ht_macmode;
370 if (sc->sc_invalid) /* if the device is invalid or removed */
373 DPRINTF(sc, ATH_DBG_CONFIG,
374 "%s: %u (%u MHz) -> %u (%u MHz), cflags:%x\n",
376 ath9k_hw_mhz2ieee(ah, sc->sc_curchan.channel,
377 sc->sc_curchan.channelFlags),
378 sc->sc_curchan.channel,
379 ath9k_hw_mhz2ieee(ah, hchan->channel, hchan->channelFlags),
380 hchan->channel, hchan->channelFlags);
382 ht_macmode = ath_cwm_macmode(sc);
384 if (hchan->channel != sc->sc_curchan.channel ||
385 hchan->channelFlags != sc->sc_curchan.channelFlags ||
386 sc->sc_update_chainmask || sc->sc_full_reset) {
389 * This is only performed if the channel settings have
392 * To switch channels clear any pending DMA operations;
393 * wait long enough for the RX fifo to drain, reset the
394 * hardware at the new frequency, and then re-enable
395 * the relevant bits of the h/w.
397 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
398 ath_draintxq(sc, false); /* clear pending tx frames */
399 stopped = ath_stoprecv(sc); /* turn off frame recv */
401 /* XXX: do not flush receive queue here. We don't want
402 * to flush data frames already in queue because of
403 * changing channel. */
405 if (!stopped || sc->sc_full_reset)
408 spin_lock_bh(&sc->sc_resetlock);
409 if (!ath9k_hw_reset(ah, sc->sc_opmode, hchan,
410 ht_macmode, sc->sc_tx_chainmask,
412 sc->sc_ht_extprotspacing,
414 DPRINTF(sc, ATH_DBG_FATAL,
415 "%s: unable to reset channel %u (%uMhz) "
416 "flags 0x%x hal status %u\n", __func__,
417 ath9k_hw_mhz2ieee(ah, hchan->channel,
418 hchan->channelFlags),
419 hchan->channel, hchan->channelFlags, status);
420 spin_unlock_bh(&sc->sc_resetlock);
423 spin_unlock_bh(&sc->sc_resetlock);
425 sc->sc_curchan = *hchan;
426 sc->sc_update_chainmask = 0;
427 sc->sc_full_reset = 0;
429 /* Re-enable rx framework */
430 if (ath_startrecv(sc) != 0) {
431 DPRINTF(sc, ATH_DBG_FATAL,
432 "%s: unable to restart recv logic\n", __func__);
436 * Change channels and update the h/w rate map
437 * if we're switching; e.g. 11a to 11b/g.
439 ath_setcurmode(sc, ath_chan2mode(hchan));
441 ath_update_txpow(sc); /* update tx power state */
443 * Re-enable interrupts.
445 ath9k_hw_set_interrupts(ah, sc->sc_imask);
450 /**********************/
451 /* Chainmask Handling */
452 /**********************/
454 static void ath_chainmask_sel_timertimeout(unsigned long data)
456 struct ath_chainmask_sel *cm = (struct ath_chainmask_sel *)data;
457 cm->switch_allowed = 1;
460 /* Start chainmask select timer */
461 static void ath_chainmask_sel_timerstart(struct ath_chainmask_sel *cm)
463 cm->switch_allowed = 0;
464 mod_timer(&cm->timer, ath_chainmask_sel_period);
467 /* Stop chainmask select timer */
468 static void ath_chainmask_sel_timerstop(struct ath_chainmask_sel *cm)
470 cm->switch_allowed = 0;
471 del_timer_sync(&cm->timer);
474 static void ath_chainmask_sel_init(struct ath_softc *sc, struct ath_node *an)
476 struct ath_chainmask_sel *cm = &an->an_chainmask_sel;
478 memzero(cm, sizeof(struct ath_chainmask_sel));
480 cm->cur_tx_mask = sc->sc_tx_chainmask;
481 cm->cur_rx_mask = sc->sc_rx_chainmask;
482 cm->tx_avgrssi = ATH_RSSI_DUMMY_MARKER;
483 setup_timer(&cm->timer,
484 ath_chainmask_sel_timertimeout, (unsigned long) cm);
487 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
489 struct ath_chainmask_sel *cm = &an->an_chainmask_sel;
492 * Disable auto-swtiching in one of the following if conditions.
493 * sc_chainmask_auto_sel is used for internal global auto-switching
494 * enabled/disabled setting
496 if (sc->sc_ah->ah_caps.tx_chainmask != ATH_CHAINMASK_SEL_3X3) {
497 cm->cur_tx_mask = sc->sc_tx_chainmask;
498 return cm->cur_tx_mask;
501 if (cm->tx_avgrssi == ATH_RSSI_DUMMY_MARKER)
502 return cm->cur_tx_mask;
504 if (cm->switch_allowed) {
505 /* Switch down from tx 3 to tx 2. */
506 if (cm->cur_tx_mask == ATH_CHAINMASK_SEL_3X3 &&
507 ATH_RSSI_OUT(cm->tx_avgrssi) >=
508 ath_chainmask_sel_down_rssi_thres) {
509 cm->cur_tx_mask = sc->sc_tx_chainmask;
511 /* Don't let another switch happen until
512 * this timer expires */
513 ath_chainmask_sel_timerstart(cm);
515 /* Switch up from tx 2 to 3. */
516 else if (cm->cur_tx_mask == sc->sc_tx_chainmask &&
517 ATH_RSSI_OUT(cm->tx_avgrssi) <=
518 ath_chainmask_sel_up_rssi_thres) {
519 cm->cur_tx_mask = ATH_CHAINMASK_SEL_3X3;
521 /* Don't let another switch happen
522 * until this timer expires */
523 ath_chainmask_sel_timerstart(cm);
527 return cm->cur_tx_mask;
531 * Update tx/rx chainmask. For legacy association,
532 * hard code chainmask to 1x1, for 11n association, use
533 * the chainmask configuration.
536 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
538 sc->sc_update_chainmask = 1;
540 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
541 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
543 sc->sc_tx_chainmask = 1;
544 sc->sc_rx_chainmask = 1;
547 DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n",
548 __func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask);
558 * This routine brings the VAP out of the down state into a "listen" state
559 * where it waits for association requests. This is used in AP and AdHoc
563 int ath_vap_listen(struct ath_softc *sc, int if_id)
565 struct ath_hal *ah = sc->sc_ah;
568 DECLARE_MAC_BUF(mac);
570 avp = sc->sc_vaps[if_id];
572 DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
577 #ifdef CONFIG_SLOW_ANT_DIV
578 ath_slow_ant_div_stop(&sc->sc_antdiv);
581 /* update ratectrl about the new state */
582 ath_rate_newstate(sc, avp);
584 rfilt = ath_calcrxfilter(sc);
585 ath9k_hw_setrxfilter(ah, rfilt);
587 if (sc->sc_opmode == ATH9K_M_STA || sc->sc_opmode == ATH9K_M_IBSS) {
588 memcpy(sc->sc_curbssid, ath_bcast_mac, ETH_ALEN);
589 ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
593 DPRINTF(sc, ATH_DBG_CONFIG,
594 "%s: RX filter 0x%x bssid %s aid 0x%x\n",
595 __func__, rfilt, print_mac(mac,
596 sc->sc_curbssid), sc->sc_curaid);
600 * Disable BMISS interrupt when we're not associated
602 ath9k_hw_set_interrupts(ah,
603 sc->sc_imask & ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
604 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
605 /* need to reconfigure the beacons when it moves to RUN */
611 int ath_vap_attach(struct ath_softc *sc,
613 struct ieee80211_vif *if_data,
614 enum ath9k_opmode opmode)
618 if (if_id >= ATH_BCBUF || sc->sc_vaps[if_id] != NULL) {
619 DPRINTF(sc, ATH_DBG_FATAL,
620 "%s: Invalid interface id = %u\n", __func__, if_id);
627 case ATH9K_M_MONITOR:
630 /* XXX not right, beacon buffer is allocated on RUN trans */
631 if (list_empty(&sc->sc_bbuf))
639 avp = kmalloc(sizeof(struct ath_vap), GFP_KERNEL);
643 memzero(avp, sizeof(struct ath_vap));
644 avp->av_if_data = if_data;
645 /* Set the VAP opmode */
646 avp->av_opmode = opmode;
648 INIT_LIST_HEAD(&avp->av_mcastq.axq_q);
649 INIT_LIST_HEAD(&avp->av_mcastq.axq_acq);
650 spin_lock_init(&avp->av_mcastq.axq_lock);
652 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
654 sc->sc_vaps[if_id] = avp;
656 /* Set the device opmode */
657 sc->sc_opmode = opmode;
659 /* default VAP configuration */
660 avp->av_config.av_fixed_rateset = IEEE80211_FIXED_RATE_NONE;
661 avp->av_config.av_fixed_retryset = 0x03030303;
666 int ath_vap_detach(struct ath_softc *sc, int if_id)
668 struct ath_hal *ah = sc->sc_ah;
671 avp = sc->sc_vaps[if_id];
673 DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
679 * Quiesce the hardware while we remove the vap. In
680 * particular we need to reclaim all references to the
681 * vap state by any frames pending on the tx queues.
683 * XXX can we do this w/o affecting other vap's?
685 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
686 ath_draintxq(sc, false); /* stop xmit side */
687 ath_stoprecv(sc); /* stop recv side */
688 ath_flushrecv(sc); /* flush recv queue */
690 /* Reclaim any pending mcast bufs on the vap. */
691 ath_tx_draintxq(sc, &avp->av_mcastq, false);
694 sc->sc_vaps[if_id] = NULL;
700 int ath_vap_config(struct ath_softc *sc,
701 int if_id, struct ath_vap_config *if_config)
705 if (if_id >= ATH_BCBUF) {
706 DPRINTF(sc, ATH_DBG_FATAL,
707 "%s: Invalid interface id = %u\n", __func__, if_id);
711 avp = sc->sc_vaps[if_id];
715 memcpy(&avp->av_config, if_config, sizeof(avp->av_config));
724 int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
726 struct ath_hal *ah = sc->sc_ah;
729 enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
731 DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
734 * Stop anything previously setup. This is safe
735 * whether this is the first time through or not.
739 /* Initialize chanmask selection */
740 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
741 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
743 /* Reset SERDES registers */
744 ath9k_hw_configpcipowersave(ah, 0);
747 * The basic interface to setting the hardware in a good
748 * state is ``reset''. On return the hardware is known to
749 * be powered up and with interrupts disabled. This must
750 * be followed by initialization of the appropriate bits
751 * and then setup of the interrupt mask.
753 sc->sc_curchan = *initial_chan;
755 spin_lock_bh(&sc->sc_resetlock);
756 if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan, ht_macmode,
757 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
758 sc->sc_ht_extprotspacing, false, &status)) {
759 DPRINTF(sc, ATH_DBG_FATAL,
760 "%s: unable to reset hardware; hal status %u "
761 "(freq %u flags 0x%x)\n", __func__, status,
762 sc->sc_curchan.channel, sc->sc_curchan.channelFlags);
764 spin_unlock_bh(&sc->sc_resetlock);
767 spin_unlock_bh(&sc->sc_resetlock);
769 * This is needed only to setup initial state
770 * but it's best done after a reset.
772 ath_update_txpow(sc);
775 * Setup the hardware after reset:
776 * The receive engine is set going.
777 * Frame transmit is handled entirely
778 * in the frame output path; there's nothing to do
779 * here except setup the interrupt mask.
781 if (ath_startrecv(sc) != 0) {
782 DPRINTF(sc, ATH_DBG_FATAL,
783 "%s: unable to start recv logic\n", __func__);
787 /* Setup our intr mask. */
788 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
789 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
790 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
792 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
793 sc->sc_imask |= ATH9K_INT_GTT;
795 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
796 sc->sc_imask |= ATH9K_INT_CST;
798 /* Note: We disable MIB interrupts for now as we don't yet
799 * handle processing ANI, otherwise you will get an interrupt
800 * storm after about 7 hours of usage making the system unusable
801 * with huge latency. Once we do have ANI processing included
802 * we can re-enable this interrupt. */
805 * Enable MIB interrupts when there are hardware phy counters.
806 * Note we only do this (at the moment) for station mode.
808 if (ath9k_hw_phycounters(ah) &&
809 ((sc->sc_opmode == ATH9K_M_STA) || (sc->sc_opmode == ATH9K_M_IBSS)))
810 sc->sc_imask |= ATH9K_INT_MIB;
813 * Some hardware processes the TIM IE and fires an
814 * interrupt when the TIM bit is set. For hardware
815 * that does, if not overridden by configuration,
816 * enable the TIM interrupt when operating as station.
818 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
819 (sc->sc_opmode == ATH9K_M_STA) &&
820 !sc->sc_config.swBeaconProcess)
821 sc->sc_imask |= ATH9K_INT_TIM;
823 * Don't enable interrupts here as we've not yet built our
824 * vap and node data structures, which will be needed as soon
825 * as we start receiving.
827 ath_setcurmode(sc, ath_chan2mode(initial_chan));
829 /* XXX: we must make sure h/w is ready and clear invalid flag
830 * before turning on interrupt. */
837 * Reset the hardware w/o losing operational state. This is
838 * basically a more efficient way of doing ath_stop, ath_init,
839 * followed by state transitions to the current 802.11
840 * operational state. Used to recover from errors rx overrun
841 * and to reset the hardware when rf gain settings must be reset.
844 static int ath_reset_start(struct ath_softc *sc, u32 flag)
846 struct ath_hal *ah = sc->sc_ah;
848 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
849 ath_draintxq(sc, flag & RESET_RETRY_TXQ); /* stop xmit side */
850 ath_stoprecv(sc); /* stop recv side */
851 ath_flushrecv(sc); /* flush recv queue */
856 static int ath_reset_end(struct ath_softc *sc, u32 flag)
858 struct ath_hal *ah = sc->sc_ah;
860 if (ath_startrecv(sc) != 0) /* restart recv */
861 DPRINTF(sc, ATH_DBG_FATAL,
862 "%s: unable to start recv logic\n", __func__);
865 * We may be doing a reset in response to a request
866 * that changes the channel so update any state that
867 * might change as a result.
869 ath_setcurmode(sc, ath_chan2mode(&sc->sc_curchan));
871 ath_update_txpow(sc); /* update tx power state */
874 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
875 ath9k_hw_set_interrupts(ah, sc->sc_imask);
877 /* Restart the txq */
878 if (flag & RESET_RETRY_TXQ) {
880 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
881 if (ATH_TXQ_SETUP(sc, i)) {
882 spin_lock_bh(&sc->sc_txq[i].axq_lock);
883 ath_txq_schedule(sc, &sc->sc_txq[i]);
884 spin_unlock_bh(&sc->sc_txq[i].axq_lock);
891 int ath_reset(struct ath_softc *sc)
893 struct ath_hal *ah = sc->sc_ah;
896 enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
898 /* NB: indicate channel change so we do a full reset */
899 spin_lock_bh(&sc->sc_resetlock);
900 if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan,
902 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
903 sc->sc_ht_extprotspacing, false, &status)) {
904 DPRINTF(sc, ATH_DBG_FATAL,
905 "%s: unable to reset hardware; hal status %u\n",
909 spin_unlock_bh(&sc->sc_resetlock);
914 int ath_suspend(struct ath_softc *sc)
916 struct ath_hal *ah = sc->sc_ah;
918 /* No I/O if device has been surprise removed */
922 /* Shut off the interrupt before setting sc->sc_invalid to '1' */
923 ath9k_hw_set_interrupts(ah, 0);
925 /* XXX: we must make sure h/w will not generate any interrupt
926 * before setting the invalid flag. */
929 /* disable HAL and put h/w to sleep */
930 ath9k_hw_disable(sc->sc_ah);
932 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
937 /* Interrupt handler. Most of the actual processing is deferred.
938 * It's the caller's responsibility to ensure the chip is awake. */
940 irqreturn_t ath_isr(int irq, void *dev)
942 struct ath_softc *sc = dev;
943 struct ath_hal *ah = sc->sc_ah;
944 enum ath9k_int status;
948 if (sc->sc_invalid) {
950 * The hardware is not ready/present, don't
951 * touch anything. Note this can happen early
952 * on if the IRQ is shared.
956 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
961 * Figure out the reason(s) for the interrupt. Note
962 * that the hal returns a pseudo-ISR that may include
963 * bits we haven't explicitly enabled so we mask the
964 * value to insure we only process bits we requested.
966 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
968 status &= sc->sc_imask; /* discard unasked-for bits */
971 * If there are no status bits set, then this interrupt was not
972 * for me (should have been caught above).
978 sc->sc_intrstatus = status;
980 if (status & ATH9K_INT_FATAL) {
981 /* need a chip reset */
983 } else if (status & ATH9K_INT_RXORN) {
984 /* need a chip reset */
987 if (status & ATH9K_INT_SWBA) {
988 /* schedule a tasklet for beacon handling */
989 tasklet_schedule(&sc->bcon_tasklet);
991 if (status & ATH9K_INT_RXEOL) {
993 * NB: the hardware should re-read the link when
994 * RXE bit is written, but it doesn't work
995 * at least on older hardware revs.
1000 if (status & ATH9K_INT_TXURN)
1001 /* bump tx trigger level */
1002 ath9k_hw_updatetxtriglevel(ah, true);
1003 /* XXX: optimize this */
1004 if (status & ATH9K_INT_RX)
1006 if (status & ATH9K_INT_TX)
1008 if (status & ATH9K_INT_BMISS)
1010 /* carrier sense timeout */
1011 if (status & ATH9K_INT_CST)
1013 if (status & ATH9K_INT_MIB) {
1015 * Disable interrupts until we service the MIB
1016 * interrupt; otherwise it will continue to
1019 ath9k_hw_set_interrupts(ah, 0);
1021 * Let the hal handle the event. We assume
1022 * it will clear whatever condition caused
1025 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
1026 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1028 if (status & ATH9K_INT_TIM_TIMER) {
1029 if (!(ah->ah_caps.hw_caps &
1030 ATH9K_HW_CAP_AUTOSLEEP)) {
1031 /* Clear RxAbort bit so that we can
1033 ath9k_hw_setrxabort(ah, 0);
1041 /* turn off every interrupt except SWBA */
1042 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
1043 tasklet_schedule(&sc->intr_tq);
1049 /* Deferred interrupt processing */
1051 static void ath9k_tasklet(unsigned long data)
1053 struct ath_softc *sc = (struct ath_softc *)data;
1054 u32 status = sc->sc_intrstatus;
1056 if (status & ATH9K_INT_FATAL) {
1057 /* need a chip reset */
1058 ath_internal_reset(sc);
1063 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
1064 /* XXX: fill me in */
1066 if (status & ATH9K_INT_RXORN) {
1068 if (status & ATH9K_INT_RXEOL) {
1071 spin_lock_bh(&sc->sc_rxflushlock);
1072 ath_rx_tasklet(sc, 0);
1073 spin_unlock_bh(&sc->sc_rxflushlock);
1075 /* XXX: optimize this */
1076 if (status & ATH9K_INT_TX)
1078 /* XXX: fill me in */
1080 if (status & ATH9K_INT_BMISS) {
1082 if (status & (ATH9K_INT_TIM | ATH9K_INT_DTIMSYNC)) {
1083 if (status & ATH9K_INT_TIM) {
1085 if (status & ATH9K_INT_DTIMSYNC) {
1091 /* re-enable hardware interrupt */
1092 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1095 int ath_init(u16 devid, struct ath_softc *sc)
1097 struct ath_hal *ah = NULL;
1103 /* XXX: hardware will not be ready until ath_open() being called */
1106 sc->sc_debug = DBG_DEFAULT;
1107 DPRINTF(sc, ATH_DBG_CONFIG, "%s: devid 0x%x\n", __func__, devid);
1109 /* Initialize tasklet */
1110 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1111 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1115 * Cache line size is used to size and align various
1116 * structures used to communicate with the hardware.
1118 bus_read_cachesize(sc, &csz);
1119 /* XXX assert csz is non-zero */
1120 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1122 spin_lock_init(&sc->sc_resetlock);
1124 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1126 DPRINTF(sc, ATH_DBG_FATAL,
1127 "%s: unable to attach hardware; HAL status %u\n",
1134 /* Get the chipset-specific aggr limit. */
1135 sc->sc_rtsaggrlimit = ah->ah_caps.rts_aggr_limit;
1137 /* Get the hardware key cache size. */
1138 sc->sc_keymax = ah->ah_caps.keycache_size;
1139 if (sc->sc_keymax > ATH_KEYMAX) {
1140 DPRINTF(sc, ATH_DBG_KEYCACHE,
1141 "%s: Warning, using only %u entries in %u key cache\n",
1142 __func__, ATH_KEYMAX, sc->sc_keymax);
1143 sc->sc_keymax = ATH_KEYMAX;
1147 * Reset the key cache since some parts do not
1148 * reset the contents on initial power up.
1150 for (i = 0; i < sc->sc_keymax; i++)
1151 ath9k_hw_keyreset(ah, (u16) i);
1153 * Mark key cache slots associated with global keys
1154 * as in use. If we knew TKIP was not to be used we
1155 * could leave the +32, +64, and +32+64 slots free.
1156 * XXX only for splitmic.
1158 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1159 set_bit(i, sc->sc_keymap);
1160 set_bit(i + 32, sc->sc_keymap);
1161 set_bit(i + 64, sc->sc_keymap);
1162 set_bit(i + 32 + 64, sc->sc_keymap);
1165 * Collect the channel list using the default country
1166 * code and including outdoor channels. The 802.11 layer
1167 * is resposible for filtering this list based on settings
1168 * like the phy mode.
1170 rd = ah->ah_currentRD;
1172 error = ath_setup_channels(sc);
1176 /* default to STA mode */
1177 sc->sc_opmode = ATH9K_M_MONITOR;
1179 /* Setup rate tables */
1181 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1182 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1184 /* NB: setup here so ath_rate_update is happy */
1185 ath_setcurmode(sc, ATH9K_MODE_11A);
1188 * Allocate hardware transmit queues: one queue for
1189 * beacon frames and one data queue for each QoS
1190 * priority. Note that the hal handles reseting
1191 * these queues at the needed time.
1193 sc->sc_bhalq = ath_beaconq_setup(ah);
1194 if (sc->sc_bhalq == -1) {
1195 DPRINTF(sc, ATH_DBG_FATAL,
1196 "%s: unable to setup a beacon xmit queue\n", __func__);
1200 sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1201 if (sc->sc_cabq == NULL) {
1202 DPRINTF(sc, ATH_DBG_FATAL,
1203 "%s: unable to setup CAB xmit queue\n", __func__);
1208 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1209 ath_cabq_update(sc);
1211 for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
1212 sc->sc_haltype2q[i] = -1;
1214 /* Setup data queues */
1215 /* NB: ensure BK queue is the lowest priority h/w queue */
1216 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1217 DPRINTF(sc, ATH_DBG_FATAL,
1218 "%s: unable to setup xmit queue for BK traffic\n",
1224 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1225 DPRINTF(sc, ATH_DBG_FATAL,
1226 "%s: unable to setup xmit queue for BE traffic\n",
1231 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1232 DPRINTF(sc, ATH_DBG_FATAL,
1233 "%s: unable to setup xmit queue for VI traffic\n",
1238 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1239 DPRINTF(sc, ATH_DBG_FATAL,
1240 "%s: unable to setup xmit queue for VO traffic\n",
1246 sc->sc_rc = ath_rate_attach(ah);
1247 if (sc->sc_rc == NULL) {
1252 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1253 ATH9K_CIPHER_TKIP, NULL)) {
1255 * Whether we should enable h/w TKIP MIC.
1256 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1257 * report WMM capable, so it's always safe to turn on
1258 * TKIP MIC in this case.
1260 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1265 * Check whether the separate key cache entries
1266 * are required to handle both tx+rx MIC keys.
1267 * With split mic keys the number of stations is limited
1268 * to 27 otherwise 59.
1270 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1271 ATH9K_CIPHER_TKIP, NULL)
1272 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1273 ATH9K_CIPHER_MIC, NULL)
1274 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1276 sc->sc_splitmic = 1;
1278 /* turn on mcast key search if possible */
1279 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1280 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1283 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1284 sc->sc_config.txpowlimit_override = 0;
1286 /* 11n Capabilities */
1287 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1292 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1293 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1295 /* Configuration for rx chain detection */
1296 sc->sc_rxchaindetect_ref = 0;
1297 sc->sc_rxchaindetect_thresh5GHz = 35;
1298 sc->sc_rxchaindetect_thresh2GHz = 35;
1299 sc->sc_rxchaindetect_delta5GHz = 30;
1300 sc->sc_rxchaindetect_delta2GHz = 30;
1302 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1303 sc->sc_defant = ath9k_hw_getdefantenna(ah);
1305 ath9k_hw_getmac(ah, sc->sc_myaddr);
1306 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1307 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1308 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1309 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1311 sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1313 /* initialize beacon slots */
1314 for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
1315 sc->sc_bslot[i] = ATH_IF_ID_ANY;
1317 /* save MISC configurations */
1318 sc->sc_config.swBeaconProcess = 1;
1320 #ifdef CONFIG_SLOW_ANT_DIV
1321 /* range is 40 - 255, we use something in the middle */
1322 ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
1327 /* cleanup tx queues */
1328 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1329 if (ATH_TXQ_SETUP(sc, i))
1330 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1333 ath9k_hw_detach(ah);
1337 void ath_deinit(struct ath_softc *sc)
1339 struct ath_hal *ah = sc->sc_ah;
1342 DPRINTF(sc, ATH_DBG_CONFIG, "%s\n", __func__);
1344 tasklet_kill(&sc->intr_tq);
1345 tasklet_kill(&sc->bcon_tasklet);
1347 if (!sc->sc_invalid)
1348 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1349 ath_rate_detach(sc->sc_rc);
1350 /* cleanup tx queues */
1351 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1352 if (ATH_TXQ_SETUP(sc, i))
1353 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1354 ath9k_hw_detach(ah);
1357 /*******************/
1358 /* Node Management */
1359 /*******************/
1361 struct ath_node *ath_node_attach(struct ath_softc *sc, u8 *addr, int if_id)
1363 struct ath_vap *avp;
1364 struct ath_node *an;
1365 DECLARE_MAC_BUF(mac);
1367 avp = sc->sc_vaps[if_id];
1368 ASSERT(avp != NULL);
1370 /* mac80211 sta_notify callback is from an IRQ context, so no sleep */
1371 an = kmalloc(sizeof(struct ath_node), GFP_ATOMIC);
1374 memzero(an, sizeof(*an));
1377 memcpy(an->an_addr, addr, ETH_ALEN);
1378 atomic_set(&an->an_refcnt, 1);
1380 /* set up per-node tx/rx state */
1381 ath_tx_node_init(sc, an);
1382 ath_rx_node_init(sc, an);
1384 ath_chainmask_sel_init(sc, an);
1385 ath_chainmask_sel_timerstart(&an->an_chainmask_sel);
1386 list_add(&an->list, &sc->node_list);
1391 void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
1393 unsigned long flags;
1395 DECLARE_MAC_BUF(mac);
1397 ath_chainmask_sel_timerstop(&an->an_chainmask_sel);
1398 an->an_flags |= ATH_NODE_CLEAN;
1399 ath_tx_node_cleanup(sc, an, bh_flag);
1400 ath_rx_node_cleanup(sc, an);
1402 ath_tx_node_free(sc, an);
1403 ath_rx_node_free(sc, an);
1405 spin_lock_irqsave(&sc->node_lock, flags);
1407 list_del(&an->list);
1409 spin_unlock_irqrestore(&sc->node_lock, flags);
1414 /* Finds a node and increases the refcnt if found */
1416 struct ath_node *ath_node_get(struct ath_softc *sc, u8 *addr)
1418 struct ath_node *an = NULL, *an_found = NULL;
1420 if (list_empty(&sc->node_list)) /* FIXME */
1422 list_for_each_entry(an, &sc->node_list, list) {
1423 if (!compare_ether_addr(an->an_addr, addr)) {
1424 atomic_inc(&an->an_refcnt);
1433 /* Decrements the refcnt and if it drops to zero, detach the node */
1435 void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
1437 if (atomic_dec_and_test(&an->an_refcnt))
1438 ath_node_detach(sc, an, bh_flag);
1441 /* Finds a node, doesn't increment refcnt. Caller must hold sc->node_lock */
1442 struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr)
1444 struct ath_node *an = NULL, *an_found = NULL;
1446 if (list_empty(&sc->node_list))
1449 list_for_each_entry(an, &sc->node_list, list)
1450 if (!compare_ether_addr(an->an_addr, addr)) {
1461 * Setup driver-specific state for a newly associated node. This routine
1462 * really only applies if compression or XR are enabled, there is no code
1463 * covering any other cases.
1466 void ath_newassoc(struct ath_softc *sc,
1467 struct ath_node *an, int isnew, int isuapsd)
1471 /* if station reassociates, tear down the aggregation state. */
1473 for (tidno = 0; tidno < WME_NUM_TID; tidno++) {
1475 ath_tx_aggr_teardown(sc, an, tidno);
1477 ath_rx_aggr_teardown(sc, an, tidno);
1487 void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
1489 ath9k_hw_keyreset(sc->sc_ah, keyix);
1491 clear_bit(keyix, sc->sc_keymap);
1494 int ath_keyset(struct ath_softc *sc,
1496 struct ath9k_keyval *hk,
1497 const u8 mac[ETH_ALEN])
1501 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
1502 keyix, hk, mac, false);
1504 return status != false;
1507 /***********************/
1508 /* TX Power/Regulatory */
1509 /***********************/
1512 * Set Transmit power in HAL
1514 * This routine makes the actual HAL calls to set the new transmit power
1518 void ath_update_txpow(struct ath_softc *sc)
1520 struct ath_hal *ah = sc->sc_ah;
1523 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
1524 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
1525 /* read back in case value is clamped */
1526 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
1527 sc->sc_curtxpow = txpow;
1531 /* Return the current country and domain information */
1532 void ath_get_currentCountry(struct ath_softc *sc,
1533 struct ath9k_country_entry *ctry)
1535 ath9k_regd_get_current_country(sc->sc_ah, ctry);
1537 /* If HAL not specific yet, since it is band dependent,
1538 * use the one we passed in. */
1539 if (ctry->countryCode == CTRY_DEFAULT) {
1542 } else if (ctry->iso[0] && ctry->iso[1]) {
1543 if (!ctry->iso[2]) {
1552 /**************************/
1553 /* Slow Antenna Diversity */
1554 /**************************/
1556 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
1557 struct ath_softc *sc,
1562 /* antdivf_rssitrig can range from 40 - 0xff */
1563 trig = (rssitrig > 0xff) ? 0xff : rssitrig;
1564 trig = (rssitrig < 40) ? 40 : rssitrig;
1566 antdiv->antdiv_sc = sc;
1567 antdiv->antdivf_rssitrig = trig;
1570 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
1574 antdiv->antdiv_num_antcfg =
1575 num_antcfg < ATH_ANT_DIV_MAX_CFG ?
1576 num_antcfg : ATH_ANT_DIV_MAX_CFG;
1577 antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
1578 antdiv->antdiv_curcfg = 0;
1579 antdiv->antdiv_bestcfg = 0;
1580 antdiv->antdiv_laststatetsf = 0;
1582 memcpy(antdiv->antdiv_bssid, bssid, sizeof(antdiv->antdiv_bssid));
1584 antdiv->antdiv_start = 1;
1587 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv)
1589 antdiv->antdiv_start = 0;
1592 static int32_t ath_find_max_val(int32_t *val,
1593 u8 num_val, u8 *max_index)
1595 u32 MaxVal = *val++;
1599 while (++cur_index < num_val) {
1600 if (*val > MaxVal) {
1602 *max_index = cur_index;
1611 void ath_slow_ant_div(struct ath_antdiv *antdiv,
1612 struct ieee80211_hdr *hdr,
1613 struct ath_rx_status *rx_stats)
1615 struct ath_softc *sc = antdiv->antdiv_sc;
1616 struct ath_hal *ah = sc->sc_ah;
1618 u8 bestcfg, curcfg = antdiv->antdiv_curcfg;
1619 __le16 fc = hdr->frame_control;
1621 if (antdiv->antdiv_start && ieee80211_is_beacon(fc)
1622 && !compare_ether_addr(hdr->addr3, antdiv->antdiv_bssid)) {
1623 antdiv->antdiv_lastbrssi[curcfg] = rx_stats->rs_rssi;
1624 antdiv->antdiv_lastbtsf[curcfg] = ath9k_hw_gettsf64(sc->sc_ah);
1625 curtsf = antdiv->antdiv_lastbtsf[curcfg];
1630 switch (antdiv->antdiv_state) {
1631 case ATH_ANT_DIV_IDLE:
1632 if ((antdiv->antdiv_lastbrssi[curcfg] <
1633 antdiv->antdivf_rssitrig)
1634 && ((curtsf - antdiv->antdiv_laststatetsf) >
1635 ATH_ANT_DIV_MIN_IDLE_US)) {
1638 if (curcfg == antdiv->antdiv_num_antcfg)
1641 if (!ath9k_hw_select_antconfig(ah, curcfg)) {
1642 antdiv->antdiv_bestcfg = antdiv->antdiv_curcfg;
1643 antdiv->antdiv_curcfg = curcfg;
1644 antdiv->antdiv_laststatetsf = curtsf;
1645 antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
1650 case ATH_ANT_DIV_SCAN:
1651 if ((curtsf - antdiv->antdiv_laststatetsf) <
1652 ATH_ANT_DIV_MIN_SCAN_US)
1656 if (curcfg == antdiv->antdiv_num_antcfg)
1659 if (curcfg == antdiv->antdiv_bestcfg) {
1660 ath_find_max_val(antdiv->antdiv_lastbrssi,
1661 antdiv->antdiv_num_antcfg, &bestcfg);
1662 if (!ath9k_hw_select_antconfig(ah, bestcfg)) {
1663 antdiv->antdiv_bestcfg = bestcfg;
1664 antdiv->antdiv_curcfg = bestcfg;
1665 antdiv->antdiv_laststatetsf = curtsf;
1666 antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
1669 if (!ath9k_hw_select_antconfig(ah, curcfg)) {
1670 antdiv->antdiv_curcfg = curcfg;
1671 antdiv->antdiv_laststatetsf = curtsf;
1672 antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
1680 /***********************/
1681 /* Descriptor Handling */
1682 /***********************/
1685 * Set up DMA descriptors
1687 * This function will allocate both the DMA descriptor structure, and the
1688 * buffers it contains. These are used to contain the descriptors used
1692 int ath_descdma_setup(struct ath_softc *sc,
1693 struct ath_descdma *dd,
1694 struct list_head *head,
1699 #define DS2PHYS(_dd, _ds) \
1700 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1701 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1702 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1704 struct ath_desc *ds;
1706 int i, bsize, error;
1708 DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
1709 __func__, name, nbuf, ndesc);
1711 /* ath_desc must be a multiple of DWORDs */
1712 if ((sizeof(struct ath_desc) % 4) != 0) {
1713 DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n",
1715 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1721 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1724 * Need additional DMA memory because we can't use
1725 * descriptors that cross the 4K page boundary. Assume
1726 * one skipped descriptor per 4K page.
1728 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1730 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1733 while (ndesc_skipped) {
1734 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1735 dd->dd_desc_len += dma_len;
1737 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1741 /* allocate descriptors */
1742 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1744 &dd->dd_desc_paddr);
1745 if (dd->dd_desc == NULL) {
1750 DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
1751 __func__, dd->dd_name, ds, (u32) dd->dd_desc_len,
1752 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1754 /* allocate buffers */
1755 bsize = sizeof(struct ath_buf) * nbuf;
1756 bf = kmalloc(bsize, GFP_KERNEL);
1764 INIT_LIST_HEAD(head);
1765 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1767 bf->bf_daddr = DS2PHYS(dd, ds);
1769 if (!(sc->sc_ah->ah_caps.hw_caps &
1770 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1772 * Skip descriptor addresses which can cause 4KB
1773 * boundary crossing (addr + length) with a 32 dword
1776 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1777 ASSERT((caddr_t) bf->bf_desc <
1778 ((caddr_t) dd->dd_desc +
1783 bf->bf_daddr = DS2PHYS(dd, ds);
1786 list_add_tail(&bf->list, head);
1790 pci_free_consistent(sc->pdev,
1791 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1793 memzero(dd, sizeof(*dd));
1795 #undef ATH_DESC_4KB_BOUND_CHECK
1796 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1801 * Cleanup DMA descriptors
1803 * This function will free the DMA block that was allocated for the descriptor
1804 * pool. Since this was allocated as one "chunk", it is freed in the same
1808 void ath_descdma_cleanup(struct ath_softc *sc,
1809 struct ath_descdma *dd,
1810 struct list_head *head)
1812 /* Free memory associated with descriptors */
1813 pci_free_consistent(sc->pdev,
1814 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1816 INIT_LIST_HEAD(head);
1817 kfree(dd->dd_bufptr);
1818 memzero(dd, sizeof(*dd));
1825 void ath_internal_reset(struct ath_softc *sc)
1827 ath_reset_start(sc, 0);
1829 ath_reset_end(sc, 0);
1832 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1838 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
1841 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
1844 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1847 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
1850 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1857 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1862 case ATH9K_WME_AC_VO:
1865 case ATH9K_WME_AC_VI:
1868 case ATH9K_WME_AC_BE:
1871 case ATH9K_WME_AC_BK:
1884 * Expand time stamp to TSF
1886 * Extend 15-bit time stamp from rx descriptor to
1887 * a full 64-bit TSF using the current h/w TSF.
1890 u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
1894 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1895 if ((tsf & 0x7fff) < rstamp)
1897 return (tsf & ~0x7fff) | rstamp;
1901 * Set Default Antenna
1903 * Call into the HAL to set the default antenna to use. Not really valid for
1907 void ath_setdefantenna(void *context, u32 antenna)
1909 struct ath_softc *sc = (struct ath_softc *)context;
1910 struct ath_hal *ah = sc->sc_ah;
1912 /* XXX block beacon interrupts */
1913 ath9k_hw_setantenna(ah, antenna);
1914 sc->sc_defant = antenna;
1915 sc->sc_rxotherant = 0;
1921 * This will wake up the chip if required, and set the slot time for the
1922 * frame (maximum transmit time). Slot time is assumed to be already set
1923 * in the ATH object member sc_slottime
1926 void ath_setslottime(struct ath_softc *sc)
1928 ath9k_hw_setslottime(sc->sc_ah, sc->sc_slottime);
1929 sc->sc_updateslot = OK;