drivers/net/wireless/ath5k/base.c

   1 /*-
   2  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2004-2005 Atheros Communications, Inc.
   4  * Copyright (c) 2006 Devicescape Software, Inc.
   5  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
   6  * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
   7  *
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  18  *    redistribution must be conditioned upon including a substantially
  19  *    similar Disclaimer requirement for further binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  32  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  33  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  34  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  35  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  36  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  37  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  38  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  39  * THE POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  */
  42
  43 #include <linux/module.h>
  44 #include <linux/delay.h>
  45 #include <linux/hardirq.h>
  46 #include <linux/if.h>
  47 #include <linux/io.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/cache.h>
  50 #include <linux/pci.h>
  51 #include <linux/ethtool.h>
  52 #include <linux/uaccess.h>
  53
  54 #include <net/ieee80211_radiotap.h>
  55
  56 #include <asm/unaligned.h>
  57
  58 #include "base.h"
  59 #include "reg.h"
  60 #include "debug.h"
  61
  62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
  63
  64
  65 /******************\
  66 * Internal defines *
  67 \******************/
  68
  69 /* Module info */
  70 MODULE_AUTHOR("Jiri Slaby");
  71 MODULE_AUTHOR("Nick Kossifidis");
  72 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
  73 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
  74 MODULE_LICENSE("Dual BSD/GPL");
  75 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
  76
  77
  78 /* Known PCI ids */
  79 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
  80         { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
  81         { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
  82         { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
  83         { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
  84         { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
  85         { PCI_VDEVICE(3COM_2,  0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
  86         { PCI_VDEVICE(3COM,    0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
  87         { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
  88         { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  89         { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  90         { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  91         { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  92         { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  93         { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  94         { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
  95         { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
  96         { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
  97         { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
  98         { 0 }
  99 };
 100 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
 101
 102 /* Known SREVs */
 103 static struct ath5k_srev_name srev_names[] = {
 104         { "5210",       AR5K_VERSION_MAC,       AR5K_SREV_AR5210 },
 105         { "5311",       AR5K_VERSION_MAC,       AR5K_SREV_AR5311 },
 106         { "5311A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311A },
 107         { "5311B",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311B },
 108         { "5211",       AR5K_VERSION_MAC,       AR5K_SREV_AR5211 },
 109         { "5212",       AR5K_VERSION_MAC,       AR5K_SREV_AR5212 },
 110         { "5213",       AR5K_VERSION_MAC,       AR5K_SREV_AR5213 },
 111         { "5213A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5213A },
 112         { "2413",       AR5K_VERSION_MAC,       AR5K_SREV_AR2413 },
 113         { "2414",       AR5K_VERSION_MAC,       AR5K_SREV_AR2414 },
 114         { "5424",       AR5K_VERSION_MAC,       AR5K_SREV_AR5424 },
 115         { "5413",       AR5K_VERSION_MAC,       AR5K_SREV_AR5413 },
 116         { "5414",       AR5K_VERSION_MAC,       AR5K_SREV_AR5414 },
 117         { "2415",       AR5K_VERSION_MAC,       AR5K_SREV_AR2415 },
 118         { "5416",       AR5K_VERSION_MAC,       AR5K_SREV_AR5416 },
 119         { "5418",       AR5K_VERSION_MAC,       AR5K_SREV_AR5418 },
 120         { "2425",       AR5K_VERSION_MAC,       AR5K_SREV_AR2425 },
 121         { "2417",       AR5K_VERSION_MAC,       AR5K_SREV_AR2417 },
 122         { "xxxxx",      AR5K_VERSION_MAC,       AR5K_SREV_UNKNOWN },
 123         { "5110",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5110 },
 124         { "5111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111 },
 125         { "5111A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111A },
 126         { "2111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2111 },
 127         { "5112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112 },
 128         { "5112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112A },
 129         { "5112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112B },
 130         { "2112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112 },
 131         { "2112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112A },
 132         { "2112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112B },
 133         { "2413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2413 },
 134         { "5413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5413 },
 135         { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
 136         { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
 137         { "5424",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5424 },
 138         { "5133",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5133 },
 139         { "xxxxx",      AR5K_VERSION_RAD,       AR5K_SREV_UNKNOWN },
 140 };
 141
 142 static struct ieee80211_rate ath5k_rates[] = {
 143         { .bitrate = 10,
 144           .hw_value = ATH5K_RATE_CODE_1M, },
 145         { .bitrate = 20,
 146           .hw_value = ATH5K_RATE_CODE_2M,
 147           .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
 148           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 149         { .bitrate = 55,
 150           .hw_value = ATH5K_RATE_CODE_5_5M,
 151           .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
 152           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 153         { .bitrate = 110,
 154           .hw_value = ATH5K_RATE_CODE_11M,
 155           .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
 156           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 157         { .bitrate = 60,
 158           .hw_value = ATH5K_RATE_CODE_6M,
 159           .flags = 0 },
 160         { .bitrate = 90,
 161           .hw_value = ATH5K_RATE_CODE_9M,
 162           .flags = 0 },
 163         { .bitrate = 120,
 164           .hw_value = ATH5K_RATE_CODE_12M,
 165           .flags = 0 },
 166         { .bitrate = 180,
 167           .hw_value = ATH5K_RATE_CODE_18M,
 168           .flags = 0 },
 169         { .bitrate = 240,
 170           .hw_value = ATH5K_RATE_CODE_24M,
 171           .flags = 0 },
 172         { .bitrate = 360,
 173           .hw_value = ATH5K_RATE_CODE_36M,
 174           .flags = 0 },
 175         { .bitrate = 480,
 176           .hw_value = ATH5K_RATE_CODE_48M,
 177           .flags = 0 },
 178         { .bitrate = 540,
 179           .hw_value = ATH5K_RATE_CODE_54M,
 180           .flags = 0 },
 181         /* XR missing */
 182 };
 183
 184 /*
 185  * Prototypes - PCI stack related functions
 186  */
 187 static int __devinit    ath5k_pci_probe(struct pci_dev *pdev,
 188                                 const struct pci_device_id *id);
 189 static void __devexit   ath5k_pci_remove(struct pci_dev *pdev);
 190 #ifdef CONFIG_PM
 191 static int              ath5k_pci_suspend(struct pci_dev *pdev,
 192                                         pm_message_t state);
 193 static int              ath5k_pci_resume(struct pci_dev *pdev);
 194 #else
 195 #define ath5k_pci_suspend NULL
 196 #define ath5k_pci_resume NULL
 197 #endif /* CONFIG_PM */
 198
 199 static struct pci_driver ath5k_pci_driver = {
 200         .name           = "ath5k_pci",
 201         .id_table       = ath5k_pci_id_table,
 202         .probe          = ath5k_pci_probe,
 203         .remove         = __devexit_p(ath5k_pci_remove),
 204         .suspend        = ath5k_pci_suspend,
 205         .resume         = ath5k_pci_resume,
 206 };
 207
 208
 209
 210 /*
 211  * Prototypes - MAC 802.11 stack related functions
 212  */
 213 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
 214 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
 215 static int ath5k_reset_wake(struct ath5k_softc *sc);
 216 static int ath5k_start(struct ieee80211_hw *hw);
 217 static void ath5k_stop(struct ieee80211_hw *hw);
 218 static int ath5k_add_interface(struct ieee80211_hw *hw,
 219                 struct ieee80211_if_init_conf *conf);
 220 static void ath5k_remove_interface(struct ieee80211_hw *hw,
 221                 struct ieee80211_if_init_conf *conf);
 222 static int ath5k_config(struct ieee80211_hw *hw,
 223                 struct ieee80211_conf *conf);
 224 static int ath5k_config_interface(struct ieee80211_hw *hw,
 225                 struct ieee80211_vif *vif,
 226                 struct ieee80211_if_conf *conf);
 227 static void ath5k_configure_filter(struct ieee80211_hw *hw,
 228                 unsigned int changed_flags,
 229                 unsigned int *new_flags,
 230                 int mc_count, struct dev_mc_list *mclist);
 231 static int ath5k_set_key(struct ieee80211_hw *hw,
 232                 enum set_key_cmd cmd,
 233                 const u8 *local_addr, const u8 *addr,
 234                 struct ieee80211_key_conf *key);
 235 static int ath5k_get_stats(struct ieee80211_hw *hw,
 236                 struct ieee80211_low_level_stats *stats);
 237 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
 238                 struct ieee80211_tx_queue_stats *stats);
 239 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
 240 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
 241 static int ath5k_beacon_update(struct ieee80211_hw *hw,
 242                 struct sk_buff *skb);
 243
 244 static struct ieee80211_ops ath5k_hw_ops = {
 245         .tx             = ath5k_tx,
 246         .start          = ath5k_start,
 247         .stop           = ath5k_stop,
 248         .add_interface  = ath5k_add_interface,
 249         .remove_interface = ath5k_remove_interface,
 250         .config         = ath5k_config,
 251         .config_interface = ath5k_config_interface,
 252         .configure_filter = ath5k_configure_filter,
 253         .set_key        = ath5k_set_key,
 254         .get_stats      = ath5k_get_stats,
 255         .conf_tx        = NULL,
 256         .get_tx_stats   = ath5k_get_tx_stats,
 257         .get_tsf        = ath5k_get_tsf,
 258         .reset_tsf      = ath5k_reset_tsf,
 259 };
 260
 261 /*
 262  * Prototypes - Internal functions
 263  */
 264 /* Attach detach */
 265 static int      ath5k_attach(struct pci_dev *pdev,
 266                         struct ieee80211_hw *hw);
 267 static void     ath5k_detach(struct pci_dev *pdev,
 268                         struct ieee80211_hw *hw);
 269 /* Channel/mode setup */
 270 static inline short ath5k_ieee2mhz(short chan);
 271 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
 272                                 struct ieee80211_channel *channels,
 273                                 unsigned int mode,
 274                                 unsigned int max);
 275 static int      ath5k_setup_bands(struct ieee80211_hw *hw);
 276 static int      ath5k_chan_set(struct ath5k_softc *sc,
 277                                 struct ieee80211_channel *chan);
 278 static void     ath5k_setcurmode(struct ath5k_softc *sc,
 279                                 unsigned int mode);
 280 static void     ath5k_mode_setup(struct ath5k_softc *sc);
 281
 282 /* Descriptor setup */
 283 static int      ath5k_desc_alloc(struct ath5k_softc *sc,
 284                                 struct pci_dev *pdev);
 285 static void     ath5k_desc_free(struct ath5k_softc *sc,
 286                                 struct pci_dev *pdev);
 287 /* Buffers setup */
 288 static int      ath5k_rxbuf_setup(struct ath5k_softc *sc,
 289                                 struct ath5k_buf *bf);
 290 static int      ath5k_txbuf_setup(struct ath5k_softc *sc,
 291                                 struct ath5k_buf *bf);
 292 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
 293                                 struct ath5k_buf *bf)
 294 {
 295         BUG_ON(!bf);
 296         if (!bf->skb)
 297                 return;
 298         pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
 299                         PCI_DMA_TODEVICE);
 300         dev_kfree_skb_any(bf->skb);
 301         bf->skb = NULL;
 302 }
 303
 304 /* Queues setup */
 305 static struct   ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
 306                                 int qtype, int subtype);
 307 static int      ath5k_beaconq_setup(struct ath5k_hw *ah);
 308 static int      ath5k_beaconq_config(struct ath5k_softc *sc);
 309 static void     ath5k_txq_drainq(struct ath5k_softc *sc,
 310                                 struct ath5k_txq *txq);
 311 static void     ath5k_txq_cleanup(struct ath5k_softc *sc);
 312 static void     ath5k_txq_release(struct ath5k_softc *sc);
 313 /* Rx handling */
 314 static int      ath5k_rx_start(struct ath5k_softc *sc);
 315 static void     ath5k_rx_stop(struct ath5k_softc *sc);
 316 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
 317                                         struct ath5k_desc *ds,
 318                                         struct sk_buff *skb,
 319                                         struct ath5k_rx_status *rs);
 320 static void     ath5k_tasklet_rx(unsigned long data);
 321 /* Tx handling */
 322 static void     ath5k_tx_processq(struct ath5k_softc *sc,
 323                                 struct ath5k_txq *txq);
 324 static void     ath5k_tasklet_tx(unsigned long data);
 325 /* Beacon handling */
 326 static int      ath5k_beacon_setup(struct ath5k_softc *sc,
 327                                         struct ath5k_buf *bf);
 328 static void     ath5k_beacon_send(struct ath5k_softc *sc);
 329 static void     ath5k_beacon_config(struct ath5k_softc *sc);
 330 static void     ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
 331
 332 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
 333 {
 334         u64 tsf = ath5k_hw_get_tsf64(ah);
 335
 336         if ((tsf & 0x7fff) < rstamp)
 337                 tsf -= 0x8000;
 338
 339         return (tsf & ~0x7fff) | rstamp;
 340 }
 341
 342 /* Interrupt handling */
 343 static int      ath5k_init(struct ath5k_softc *sc);
 344 static int      ath5k_stop_locked(struct ath5k_softc *sc);
 345 static int      ath5k_stop_hw(struct ath5k_softc *sc);
 346 static irqreturn_t ath5k_intr(int irq, void *dev_id);
 347 static void     ath5k_tasklet_reset(unsigned long data);
 348
 349 static void     ath5k_calibrate(unsigned long data);
 350 /* LED functions */
 351 static int      ath5k_init_leds(struct ath5k_softc *sc);
 352 static void     ath5k_led_enable(struct ath5k_softc *sc);
 353 static void     ath5k_led_off(struct ath5k_softc *sc);
 354 static void     ath5k_unregister_leds(struct ath5k_softc *sc);
 355
 356 /*
 357  * Module init/exit functions
 358  */
 359 static int __init
 360 init_ath5k_pci(void)
 361 {
 362         int ret;
 363
 364         ath5k_debug_init();
 365
 366         ret = pci_register_driver(&ath5k_pci_driver);
 367         if (ret) {
 368                 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
 369                 return ret;
 370         }
 371
 372         return 0;
 373 }
 374
 375 static void __exit
 376 exit_ath5k_pci(void)
 377 {
 378         pci_unregister_driver(&ath5k_pci_driver);
 379
 380         ath5k_debug_finish();
 381 }
 382
 383 module_init(init_ath5k_pci);
 384 module_exit(exit_ath5k_pci);
 385
 386
 387 /********************\
 388 * PCI Initialization *
 389 \********************/
 390
 391 static const char *
 392 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
 393 {
 394         const char *name = "xxxxx";
 395         unsigned int i;
 396
 397         for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
 398                 if (srev_names[i].sr_type != type)
 399                         continue;
 400
 401                 if ((val & 0xf0) == srev_names[i].sr_val)
 402                         name = srev_names[i].sr_name;
 403
 404                 if ((val & 0xff) == srev_names[i].sr_val) {
 405                         name = srev_names[i].sr_name;
 406                         break;
 407                 }
 408         }
 409
 410         return name;
 411 }
 412
 413 static int __devinit
 414 ath5k_pci_probe(struct pci_dev *pdev,
 415                 const struct pci_device_id *id)
 416 {
 417         void __iomem *mem;
 418         struct ath5k_softc *sc;
 419         struct ieee80211_hw *hw;
 420         int ret;
 421         u8 csz;
 422
 423         ret = pci_enable_device(pdev);
 424         if (ret) {
 425                 dev_err(&pdev->dev, "can't enable device\n");
 426                 goto err;
 427         }
 428
 429         /* XXX 32-bit addressing only */
 430         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 431         if (ret) {
 432                 dev_err(&pdev->dev, "32-bit DMA not available\n");
 433                 goto err_dis;
 434         }
 435
 436         /*
 437          * Cache line size is used to size and align various
 438          * structures used to communicate with the hardware.
 439          */
 440         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 441         if (csz == 0) {
 442                 /*
 443                  * Linux 2.4.18 (at least) writes the cache line size
 444                  * register as a 16-bit wide register which is wrong.
 445                  * We must have this setup properly for rx buffer
 446                  * DMA to work so force a reasonable value here if it
 447                  * comes up zero.
 448                  */
 449                 csz = L1_CACHE_BYTES / sizeof(u32);
 450                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 451         }
 452         /*
 453          * The default setting of latency timer yields poor results,
 454          * set it to the value used by other systems.  It may be worth
 455          * tweaking this setting more.
 456          */
 457         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 458
 459         /* Enable bus mastering */
 460         pci_set_master(pdev);
 461
 462         /*
 463          * Disable the RETRY_TIMEOUT register (0x41) to keep
 464          * PCI Tx retries from interfering with C3 CPU state.
 465          */
 466         pci_write_config_byte(pdev, 0x41, 0);
 467
 468         ret = pci_request_region(pdev, 0, "ath5k");
 469         if (ret) {
 470                 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
 471                 goto err_dis;
 472         }
 473
 474         mem = pci_iomap(pdev, 0, 0);
 475         if (!mem) {
 476                 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
 477                 ret = -EIO;
 478                 goto err_reg;
 479         }
 480
 481         /*
 482          * Allocate hw (mac80211 main struct)
 483          * and hw->priv (driver private data)
 484          */
 485         hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
 486         if (hw == NULL) {
 487                 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
 488                 ret = -ENOMEM;
 489                 goto err_map;
 490         }
 491
 492         dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
 493
 494         /* Initialize driver private data */
 495         SET_IEEE80211_DEV(hw, &pdev->dev);
 496         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
 497                     IEEE80211_HW_SIGNAL_DBM |
 498                     IEEE80211_HW_NOISE_DBM;
 499
 500         hw->wiphy->interface_modes =
 501                 BIT(NL80211_IFTYPE_STATION) |
 502                 BIT(NL80211_IFTYPE_ADHOC) |
 503                 BIT(NL80211_IFTYPE_MESH_POINT);
 504
 505         hw->extra_tx_headroom = 2;
 506         hw->channel_change_time = 5000;
 507         sc = hw->priv;
 508         sc->hw = hw;
 509         sc->pdev = pdev;
 510
 511         ath5k_debug_init_device(sc);
 512
 513         /*
 514          * Mark the device as detached to avoid processing
 515          * interrupts until setup is complete.
 516          */
 517         __set_bit(ATH_STAT_INVALID, sc->status);
 518
 519         sc->iobase = mem; /* So we can unmap it on detach */
 520         sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
 521         sc->opmode = NL80211_IFTYPE_STATION;
 522         mutex_init(&sc->lock);
 523         spin_lock_init(&sc->rxbuflock);
 524         spin_lock_init(&sc->txbuflock);
 525         spin_lock_init(&sc->block);
 526
 527         /* Set private data */
 528         pci_set_drvdata(pdev, hw);
 529
 530         /* Setup interrupt handler */
 531         ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 532         if (ret) {
 533                 ATH5K_ERR(sc, "request_irq failed\n");
 534                 goto err_free;
 535         }
 536
 537         /* Initialize device */
 538         sc->ah = ath5k_hw_attach(sc, id->driver_data);
 539         if (IS_ERR(sc->ah)) {
 540                 ret = PTR_ERR(sc->ah);
 541                 goto err_irq;
 542         }
 543
 544         /* set up multi-rate retry capabilities */
 545         if (sc->ah->ah_version == AR5K_AR5212) {
 546                 hw->max_altrates = 3;
 547                 hw->max_altrate_tries = 11;
 548         }
 549
 550         /* Finish private driver data initialization */
 551         ret = ath5k_attach(pdev, hw);
 552         if (ret)
 553                 goto err_ah;
 554
 555         ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
 556                         ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
 557                                         sc->ah->ah_mac_srev,
 558                                         sc->ah->ah_phy_revision);
 559
 560         if (!sc->ah->ah_single_chip) {
 561                 /* Single chip radio (!RF5111) */
 562                 if (sc->ah->ah_radio_5ghz_revision &&
 563                         !sc->ah->ah_radio_2ghz_revision) {
 564                         /* No 5GHz support -> report 2GHz radio */
 565                         if (!test_bit(AR5K_MODE_11A,
 566                                 sc->ah->ah_capabilities.cap_mode)) {
 567                                 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 568                                         ath5k_chip_name(AR5K_VERSION_RAD,
 569                                                 sc->ah->ah_radio_5ghz_revision),
 570                                                 sc->ah->ah_radio_5ghz_revision);
 571                         /* No 2GHz support (5110 and some
 572                          * 5Ghz only cards) -> report 5Ghz radio */
 573                         } else if (!test_bit(AR5K_MODE_11B,
 574                                 sc->ah->ah_capabilities.cap_mode)) {
 575                                 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 576                                         ath5k_chip_name(AR5K_VERSION_RAD,
 577                                                 sc->ah->ah_radio_5ghz_revision),
 578                                                 sc->ah->ah_radio_5ghz_revision);
 579                         /* Multiband radio */
 580                         } else {
 581                                 ATH5K_INFO(sc, "RF%s multiband radio found"
 582                                         " (0x%x)\n",
 583                                         ath5k_chip_name(AR5K_VERSION_RAD,
 584                                                 sc->ah->ah_radio_5ghz_revision),
 585                                                 sc->ah->ah_radio_5ghz_revision);
 586                         }
 587                 }
 588                 /* Multi chip radio (RF5111 - RF2111) ->
 589                  * report both 2GHz/5GHz radios */
 590                 else if (sc->ah->ah_radio_5ghz_revision &&
 591                                 sc->ah->ah_radio_2ghz_revision){
 592                         ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 593                                 ath5k_chip_name(AR5K_VERSION_RAD,
 594                                         sc->ah->ah_radio_5ghz_revision),
 595                                         sc->ah->ah_radio_5ghz_revision);
 596                         ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 597                                 ath5k_chip_name(AR5K_VERSION_RAD,
 598                                         sc->ah->ah_radio_2ghz_revision),
 599                                         sc->ah->ah_radio_2ghz_revision);
 600                 }
 601         }
 602
 603
 604         /* ready to process interrupts */
 605         __clear_bit(ATH_STAT_INVALID, sc->status);
 606
 607         return 0;
 608 err_ah:
 609         ath5k_hw_detach(sc->ah);
 610 err_irq:
 611         free_irq(pdev->irq, sc);
 612 err_free:
 613         ieee80211_free_hw(hw);
 614 err_map:
 615         pci_iounmap(pdev, mem);
 616 err_reg:
 617         pci_release_region(pdev, 0);
 618 err_dis:
 619         pci_disable_device(pdev);
 620 err:
 621         return ret;
 622 }
 623
 624 static void __devexit
 625 ath5k_pci_remove(struct pci_dev *pdev)
 626 {
 627         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 628         struct ath5k_softc *sc = hw->priv;
 629
 630         ath5k_debug_finish_device(sc);
 631         ath5k_detach(pdev, hw);
 632         ath5k_hw_detach(sc->ah);
 633         free_irq(pdev->irq, sc);
 634         pci_iounmap(pdev, sc->iobase);
 635         pci_release_region(pdev, 0);
 636         pci_disable_device(pdev);
 637         ieee80211_free_hw(hw);
 638 }
 639
 640 #ifdef CONFIG_PM
 641 static int
 642 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 643 {
 644         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 645         struct ath5k_softc *sc = hw->priv;
 646
 647         ath5k_led_off(sc);
 648
 649         ath5k_stop_hw(sc);
 650
 651         free_irq(pdev->irq, sc);
 652         pci_save_state(pdev);
 653         pci_disable_device(pdev);
 654         pci_set_power_state(pdev, PCI_D3hot);
 655
 656         return 0;
 657 }
 658
 659 static int
 660 ath5k_pci_resume(struct pci_dev *pdev)
 661 {
 662         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 663         struct ath5k_softc *sc = hw->priv;
 664         struct ath5k_hw *ah = sc->ah;
 665         int i, err;
 666
 667         pci_restore_state(pdev);
 668
 669         err = pci_enable_device(pdev);
 670         if (err)
 671                 return err;
 672
 673         /*
 674          * Suspend/Resume resets the PCI configuration space, so we have to
 675          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 676          * PCI Tx retries from interfering with C3 CPU state
 677          */
 678         pci_write_config_byte(pdev, 0x41, 0);
 679
 680         err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 681         if (err) {
 682                 ATH5K_ERR(sc, "request_irq failed\n");
 683                 goto err_no_irq;
 684         }
 685
 686         err = ath5k_init(sc);
 687         if (err)
 688                 goto err_irq;
 689         ath5k_led_enable(sc);
 690
 691         /*
 692          * Reset the key cache since some parts do not
 693          * reset the contents on initial power up or resume.
 694          *
 695          * FIXME: This may need to be revisited when mac80211 becomes
 696          *        aware of suspend/resume.
 697          */
 698         for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
 699                 ath5k_hw_reset_key(ah, i);
 700
 701         return 0;
 702 err_irq:
 703         free_irq(pdev->irq, sc);
 704 err_no_irq:
 705         pci_disable_device(pdev);
 706         return err;
 707 }
 708 #endif /* CONFIG_PM */
 709
 710
 711 /***********************\
 712 * Driver Initialization *
 713 \***********************/
 714
 715 static int
 716 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 717 {
 718         struct ath5k_softc *sc = hw->priv;
 719         struct ath5k_hw *ah = sc->ah;
 720         u8 mac[ETH_ALEN];
 721         unsigned int i;
 722         int ret;
 723
 724         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
 725
 726         /*
 727          * Check if the MAC has multi-rate retry support.
 728          * We do this by trying to setup a fake extended
 729          * descriptor.  MAC's that don't have support will
 730          * return false w/o doing anything.  MAC's that do
 731          * support it will return true w/o doing anything.
 732          */
 733         ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
 734         if (ret < 0)
 735                 goto err;
 736         if (ret > 0)
 737                 __set_bit(ATH_STAT_MRRETRY, sc->status);
 738
 739         /*
 740          * Reset the key cache since some parts do not
 741          * reset the contents on initial power up.
 742          */
 743         for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
 744                 ath5k_hw_reset_key(ah, i);
 745
 746         /*
 747          * Collect the channel list.  The 802.11 layer
 748          * is resposible for filtering this list based
 749          * on settings like the phy mode and regulatory
 750          * domain restrictions.
 751          */
 752         ret = ath5k_setup_bands(hw);
 753         if (ret) {
 754                 ATH5K_ERR(sc, "can't get channels\n");
 755                 goto err;
 756         }
 757
 758         /* NB: setup here so ath5k_rate_update is happy */
 759         if (test_bit(AR5K_MODE_11A, ah->ah_modes))
 760                 ath5k_setcurmode(sc, AR5K_MODE_11A);
 761         else
 762                 ath5k_setcurmode(sc, AR5K_MODE_11B);
 763
 764         /*
 765          * Allocate tx+rx descriptors and populate the lists.
 766          */
 767         ret = ath5k_desc_alloc(sc, pdev);
 768         if (ret) {
 769                 ATH5K_ERR(sc, "can't allocate descriptors\n");
 770                 goto err;
 771         }
 772
 773         /*
 774          * Allocate hardware transmit queues: one queue for
 775          * beacon frames and one data queue for each QoS
 776          * priority.  Note that hw functions handle reseting
 777          * these queues at the needed time.
 778          */
 779         ret = ath5k_beaconq_setup(ah);
 780         if (ret < 0) {
 781                 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
 782                 goto err_desc;
 783         }
 784         sc->bhalq = ret;
 785
 786         sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
 787         if (IS_ERR(sc->txq)) {
 788                 ATH5K_ERR(sc, "can't setup xmit queue\n");
 789                 ret = PTR_ERR(sc->txq);
 790                 goto err_bhal;
 791         }
 792
 793         tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
 794         tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
 795         tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
 796         setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
 797
 798         ath5k_hw_get_lladdr(ah, mac);
 799         SET_IEEE80211_PERM_ADDR(hw, mac);
 800         /* All MAC address bits matter for ACKs */
 801         memset(sc->bssidmask, 0xff, ETH_ALEN);
 802         ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
 803
 804         ret = ieee80211_register_hw(hw);
 805         if (ret) {
 806                 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
 807                 goto err_queues;
 808         }
 809
 810         ath5k_init_leds(sc);
 811
 812         return 0;
 813 err_queues:
 814         ath5k_txq_release(sc);
 815 err_bhal:
 816         ath5k_hw_release_tx_queue(ah, sc->bhalq);
 817 err_desc:
 818         ath5k_desc_free(sc, pdev);
 819 err:
 820         return ret;
 821 }
 822
 823 static void
 824 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 825 {
 826         struct ath5k_softc *sc = hw->priv;
 827
 828         /*
 829          * NB: the order of these is important:
 830          * o call the 802.11 layer before detaching ath5k_hw to
 831          *   insure callbacks into the driver to delete global
 832          *   key cache entries can be handled
 833          * o reclaim the tx queue data structures after calling
 834          *   the 802.11 layer as we'll get called back to reclaim
 835          *   node state and potentially want to use them
 836          * o to cleanup the tx queues the hal is called, so detach
 837          *   it last
 838          * XXX: ??? detach ath5k_hw ???
 839          * Other than that, it's straightforward...
 840          */
 841         ieee80211_unregister_hw(hw);
 842         ath5k_desc_free(sc, pdev);
 843         ath5k_txq_release(sc);
 844         ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
 845         ath5k_unregister_leds(sc);
 846
 847         /*
 848          * NB: can't reclaim these until after ieee80211_ifdetach
 849          * returns because we'll get called back to reclaim node
 850          * state and potentially want to use them.
 851          */
 852 }
 853
 854
 855
 856
 857 /********************\
 858 * Channel/mode setup *
 859 \********************/
 860
 861 /*
 862  * Convert IEEE channel number to MHz frequency.
 863  */
 864 static inline short
 865 ath5k_ieee2mhz(short chan)
 866 {
 867         if (chan <= 14 || chan >= 27)
 868                 return ieee80211chan2mhz(chan);
 869         else
 870                 return 2212 + chan * 20;
 871 }
 872
 873 static unsigned int
 874 ath5k_copy_channels(struct ath5k_hw *ah,
 875                 struct ieee80211_channel *channels,
 876                 unsigned int mode,
 877                 unsigned int max)
 878 {
 879         unsigned int i, count, size, chfreq, freq, ch;
 880
 881         if (!test_bit(mode, ah->ah_modes))
 882                 return 0;
 883
 884         switch (mode) {
 885         case AR5K_MODE_11A:
 886         case AR5K_MODE_11A_TURBO:
 887                 /* 1..220, but 2GHz frequencies are filtered by check_channel */
 888                 size = 220 ;
 889                 chfreq = CHANNEL_5GHZ;
 890                 break;
 891         case AR5K_MODE_11B:
 892         case AR5K_MODE_11G:
 893         case AR5K_MODE_11G_TURBO:
 894                 size = 26;
 895                 chfreq = CHANNEL_2GHZ;
 896                 break;
 897         default:
 898                 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
 899                 return 0;
 900         }
 901
 902         for (i = 0, count = 0; i < size && max > 0; i++) {
 903                 ch = i + 1 ;
 904                 freq = ath5k_ieee2mhz(ch);
 905
 906                 /* Check if channel is supported by the chipset */
 907                 if (!ath5k_channel_ok(ah, freq, chfreq))
 908                         continue;
 909
 910                 /* Write channel info and increment counter */
 911                 channels[count].center_freq = freq;
 912                 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
 913                         IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 914                 switch (mode) {
 915                 case AR5K_MODE_11A:
 916                 case AR5K_MODE_11G:
 917                         channels[count].hw_value = chfreq | CHANNEL_OFDM;
 918                         break;
 919                 case AR5K_MODE_11A_TURBO:
 920                 case AR5K_MODE_11G_TURBO:
 921                         channels[count].hw_value = chfreq |
 922                                 CHANNEL_OFDM | CHANNEL_TURBO;
 923                         break;
 924                 case AR5K_MODE_11B:
 925                         channels[count].hw_value = CHANNEL_B;
 926                 }
 927
 928                 count++;
 929                 max--;
 930         }
 931
 932         return count;
 933 }
 934
 935 static void
 936 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
 937 {
 938         u8 i;
 939
 940         for (i = 0; i < AR5K_MAX_RATES; i++)
 941                 sc->rate_idx[b->band][i] = -1;
 942
 943         for (i = 0; i < b->n_bitrates; i++) {
 944                 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
 945                 if (b->bitrates[i].hw_value_short)
 946                         sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
 947         }
 948 }
 949
 950 static int
 951 ath5k_setup_bands(struct ieee80211_hw *hw)
 952 {
 953         struct ath5k_softc *sc = hw->priv;
 954         struct ath5k_hw *ah = sc->ah;
 955         struct ieee80211_supported_band *sband;
 956         int max_c, count_c = 0;
 957         int i;
 958
 959         BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
 960         max_c = ARRAY_SIZE(sc->channels);
 961
 962         /* 2GHz band */
 963         sband = &sc->sbands[IEEE80211_BAND_2GHZ];
 964         sband->band = IEEE80211_BAND_2GHZ;
 965         sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
 966
 967         if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
 968                 /* G mode */
 969                 memcpy(sband->bitrates, &ath5k_rates[0],
 970                        sizeof(struct ieee80211_rate) * 12);
 971                 sband->n_bitrates = 12;
 972
 973                 sband->channels = sc->channels;
 974                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
 975                                         AR5K_MODE_11G, max_c);
 976
 977                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
 978                 count_c = sband->n_channels;
 979                 max_c -= count_c;
 980         } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
 981                 /* B mode */
 982                 memcpy(sband->bitrates, &ath5k_rates[0],
 983                        sizeof(struct ieee80211_rate) * 4);
 984                 sband->n_bitrates = 4;
 985
 986                 /* 5211 only supports B rates and uses 4bit rate codes
 987                  * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
 988                  * fix them up here:
 989                  */
 990                 if (ah->ah_version == AR5K_AR5211) {
 991                         for (i = 0; i < 4; i++) {
 992                                 sband->bitrates[i].hw_value =
 993                                         sband->bitrates[i].hw_value & 0xF;
 994                                 sband->bitrates[i].hw_value_short =
 995                                         sband->bitrates[i].hw_value_short & 0xF;
 996                         }
 997                 }
 998
 999                 sband->channels = sc->channels;
1000                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1001                                         AR5K_MODE_11B, max_c);
1002
1003                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1004                 count_c = sband->n_channels;
1005                 max_c -= count_c;
1006         }
1007         ath5k_setup_rate_idx(sc, sband);
1008
1009         /* 5GHz band, A mode */
1010         if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1011                 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1012                 sband->band = IEEE80211_BAND_5GHZ;
1013                 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1014
1015                 memcpy(sband->bitrates, &ath5k_rates[4],
1016                        sizeof(struct ieee80211_rate) * 8);
1017                 sband->n_bitrates = 8;
1018
1019                 sband->channels = &sc->channels[count_c];
1020                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1021                                         AR5K_MODE_11A, max_c);
1022
1023                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1024         }
1025         ath5k_setup_rate_idx(sc, sband);
1026
1027         ath5k_debug_dump_bands(sc);
1028
1029         return 0;
1030 }
1031
1032 /*
1033  * Set/change channels.  If the channel is really being changed,
1034  * it's done by reseting the chip.  To accomplish this we must
1035  * first cleanup any pending DMA, then restart stuff after a la
1036  * ath5k_init.
1037  */
1038 static int
1039 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1040 {
1041         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1042                 sc->curchan->center_freq, chan->center_freq);
1043
1044         if (chan->center_freq != sc->curchan->center_freq ||
1045                 chan->hw_value != sc->curchan->hw_value) {
1046
1047                 sc->curchan = chan;
1048                 sc->curband = &sc->sbands[chan->band];
1049
1050                 /*
1051                  * To switch channels clear any pending DMA operations;
1052                  * wait long enough for the RX fifo to drain, reset the
1053                  * hardware at the new frequency, and then re-enable
1054                  * the relevant bits of the h/w.
1055                  */
1056                 return ath5k_reset(sc, true, true);
1057         }
1058
1059         return 0;
1060 }
1061
1062 static void
1063 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1064 {
1065         sc->curmode = mode;
1066
1067         if (mode == AR5K_MODE_11A) {
1068                 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1069         } else {
1070                 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1071         }
1072 }
1073
1074 static void
1075 ath5k_mode_setup(struct ath5k_softc *sc)
1076 {
1077         struct ath5k_hw *ah = sc->ah;
1078         u32 rfilt;
1079
1080         /* configure rx filter */
1081         rfilt = sc->filter_flags;
1082         ath5k_hw_set_rx_filter(ah, rfilt);
1083
1084         if (ath5k_hw_hasbssidmask(ah))
1085                 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1086
1087         /* configure operational mode */
1088         ath5k_hw_set_opmode(ah);
1089
1090         ath5k_hw_set_mcast_filter(ah, 0, 0);
1091         ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1092 }
1093
1094 static inline int
1095 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1096 {
1097         WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1098         return sc->rate_idx[sc->curband->band][hw_rix];
1099 }
1100
1101 /***************\
1102 * Buffers setup *
1103 \***************/
1104
1105 static int
1106 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1107 {
1108         struct ath5k_hw *ah = sc->ah;
1109         struct sk_buff *skb = bf->skb;
1110         struct ath5k_desc *ds;
1111
1112         if (likely(skb == NULL)) {
1113                 unsigned int off;
1114
1115                 /*
1116                  * Allocate buffer with headroom_needed space for the
1117                  * fake physical layer header at the start.
1118                  */
1119                 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1120                 if (unlikely(skb == NULL)) {
1121                         ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1122                                         sc->rxbufsize + sc->cachelsz - 1);
1123                         return -ENOMEM;
1124                 }
1125                 /*
1126                  * Cache-line-align.  This is important (for the
1127                  * 5210 at least) as not doing so causes bogus data
1128                  * in rx'd frames.
1129                  */
1130                 off = ((unsigned long)skb->data) % sc->cachelsz;
1131                 if (off != 0)
1132                         skb_reserve(skb, sc->cachelsz - off);
1133
1134                 bf->skb = skb;
1135                 bf->skbaddr = pci_map_single(sc->pdev,
1136                         skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1137                 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
1138                         ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1139                         dev_kfree_skb(skb);
1140                         bf->skb = NULL;
1141                         return -ENOMEM;
1142                 }
1143         }
1144
1145         /*
1146          * Setup descriptors.  For receive we always terminate
1147          * the descriptor list with a self-linked entry so we'll
1148          * not get overrun under high load (as can happen with a
1149          * 5212 when ANI processing enables PHY error frames).
1150          *
1151          * To insure the last descriptor is self-linked we create
1152          * each descriptor as self-linked and add it to the end.  As
1153          * each additional descriptor is added the previous self-linked
1154          * entry is ``fixed'' naturally.  This should be safe even
1155          * if DMA is happening.  When processing RX interrupts we
1156          * never remove/process the last, self-linked, entry on the
1157          * descriptor list.  This insures the hardware always has
1158          * someplace to write a new frame.
1159          */
1160         ds = bf->desc;
1161         ds->ds_link = bf->daddr;        /* link to self */
1162         ds->ds_data = bf->skbaddr;
1163         ah->ah_setup_rx_desc(ah, ds,
1164                 skb_tailroom(skb),      /* buffer size */
1165                 0);
1166
1167         if (sc->rxlink != NULL)
1168                 *sc->rxlink = bf->daddr;
1169         sc->rxlink = &ds->ds_link;
1170         return 0;
1171 }
1172
1173 static int
1174 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1175 {
1176         struct ath5k_hw *ah = sc->ah;
1177         struct ath5k_txq *txq = sc->txq;
1178         struct ath5k_desc *ds = bf->desc;
1179         struct sk_buff *skb = bf->skb;
1180         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1181         unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1182         struct ieee80211_rate *rate;
1183         unsigned int mrr_rate[3], mrr_tries[3];
1184         int i, ret;
1185
1186         flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1187
1188         /* XXX endianness */
1189         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1190                         PCI_DMA_TODEVICE);
1191
1192         if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1193                 flags |= AR5K_TXDESC_NOACK;
1194
1195         pktlen = skb->len;
1196
1197         if (info->control.hw_key) {
1198                 keyidx = info->control.hw_key->hw_key_idx;
1199                 pktlen += info->control.hw_key->icv_len;
1200         }
1201         ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1202                 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1203                 (sc->power_level * 2),
1204                 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1205                 info->control.retry_limit, keyidx, 0, flags, 0, 0);
1206         if (ret)
1207                 goto err_unmap;
1208
1209         memset(mrr_rate, 0, sizeof(mrr_rate));
1210         memset(mrr_tries, 0, sizeof(mrr_tries));
1211         for (i = 0; i < 3; i++) {
1212                 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1213                 if (!rate)
1214                         break;
1215
1216                 mrr_rate[i] = rate->hw_value;
1217                 mrr_tries[i] = info->control.retries[i].limit;
1218         }
1219
1220         ah->ah_setup_mrr_tx_desc(ah, ds,
1221                 mrr_rate[0], mrr_tries[0],
1222                 mrr_rate[1], mrr_tries[1],
1223                 mrr_rate[2], mrr_tries[2]);
1224
1225         ds->ds_link = 0;
1226         ds->ds_data = bf->skbaddr;
1227
1228         spin_lock_bh(&txq->lock);
1229         list_add_tail(&bf->list, &txq->q);
1230         sc->tx_stats[txq->qnum].len++;
1231         if (txq->link == NULL) /* is this first packet? */
1232                 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1233         else /* no, so only link it */
1234                 *txq->link = bf->daddr;
1235
1236         txq->link = &ds->ds_link;
1237         ath5k_hw_start_tx_dma(ah, txq->qnum);
1238         mmiowb();
1239         spin_unlock_bh(&txq->lock);
1240
1241         return 0;
1242 err_unmap:
1243         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1244         return ret;
1245 }
1246
1247 /*******************\
1248 * Descriptors setup *
1249 \*******************/
1250
1251 static int
1252 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1253 {
1254         struct ath5k_desc *ds;
1255         struct ath5k_buf *bf;
1256         dma_addr_t da;
1257         unsigned int i;
1258         int ret;
1259
1260         /* allocate descriptors */
1261         sc->desc_len = sizeof(struct ath5k_desc) *
1262                         (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1263         sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1264         if (sc->desc == NULL) {
1265                 ATH5K_ERR(sc, "can't allocate descriptors\n");
1266                 ret = -ENOMEM;
1267                 goto err;
1268         }
1269         ds = sc->desc;
1270         da = sc->desc_daddr;
1271         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1272                 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1273
1274         bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1275                         sizeof(struct ath5k_buf), GFP_KERNEL);
1276         if (bf == NULL) {
1277                 ATH5K_ERR(sc, "can't allocate bufptr\n");
1278                 ret = -ENOMEM;
1279                 goto err_free;
1280         }
1281         sc->bufptr = bf;
1282
1283         INIT_LIST_HEAD(&sc->rxbuf);
1284         for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1285                 bf->desc = ds;
1286                 bf->daddr = da;
1287                 list_add_tail(&bf->list, &sc->rxbuf);
1288         }
1289
1290         INIT_LIST_HEAD(&sc->txbuf);
1291         sc->txbuf_len = ATH_TXBUF;
1292         for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1293                         da += sizeof(*ds)) {
1294                 bf->desc = ds;
1295                 bf->daddr = da;
1296                 list_add_tail(&bf->list, &sc->txbuf);
1297         }
1298
1299         /* beacon buffer */
1300         bf->desc = ds;
1301         bf->daddr = da;
1302         sc->bbuf = bf;
1303
1304         return 0;
1305 err_free:
1306         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1307 err:
1308         sc->desc = NULL;
1309         return ret;
1310 }
1311
1312 static void
1313 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1314 {
1315         struct ath5k_buf *bf;
1316
1317         ath5k_txbuf_free(sc, sc->bbuf);
1318         list_for_each_entry(bf, &sc->txbuf, list)
1319                 ath5k_txbuf_free(sc, bf);
1320         list_for_each_entry(bf, &sc->rxbuf, list)
1321                 ath5k_txbuf_free(sc, bf);
1322
1323         /* Free memory associated with all descriptors */
1324         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1325
1326         kfree(sc->bufptr);
1327         sc->bufptr = NULL;
1328 }
1329
1330
1331
1332
1333
1334 /**************\
1335 * Queues setup *
1336 \**************/
1337
1338 static struct ath5k_txq *
1339 ath5k_txq_setup(struct ath5k_softc *sc,
1340                 int qtype, int subtype)
1341 {
1342         struct ath5k_hw *ah = sc->ah;
1343         struct ath5k_txq *txq;
1344         struct ath5k_txq_info qi = {
1345                 .tqi_subtype = subtype,
1346                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1347                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1348                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1349         };
1350         int qnum;
1351
1352         /*
1353          * Enable interrupts only for EOL and DESC conditions.
1354          * We mark tx descriptors to receive a DESC interrupt
1355          * when a tx queue gets deep; otherwise waiting for the
1356          * EOL to reap descriptors.  Note that this is done to
1357          * reduce interrupt load and this only defers reaping
1358          * descriptors, never transmitting frames.  Aside from
1359          * reducing interrupts this also permits more concurrency.
1360          * The only potential downside is if the tx queue backs
1361          * up in which case the top half of the kernel may backup
1362          * due to a lack of tx descriptors.
1363          */
1364         qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1365                                 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1366         qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1367         if (qnum < 0) {
1368                 /*
1369                  * NB: don't print a message, this happens
1370                  * normally on parts with too few tx queues
1371                  */
1372                 return ERR_PTR(qnum);
1373         }
1374         if (qnum >= ARRAY_SIZE(sc->txqs)) {
1375                 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1376                         qnum, ARRAY_SIZE(sc->txqs));
1377                 ath5k_hw_release_tx_queue(ah, qnum);
1378                 return ERR_PTR(-EINVAL);
1379         }
1380         txq = &sc->txqs[qnum];
1381         if (!txq->setup) {
1382                 txq->qnum = qnum;
1383                 txq->link = NULL;
1384                 INIT_LIST_HEAD(&txq->q);
1385                 spin_lock_init(&txq->lock);
1386                 txq->setup = true;
1387         }
1388         return &sc->txqs[qnum];
1389 }
1390
1391 static int
1392 ath5k_beaconq_setup(struct ath5k_hw *ah)
1393 {
1394         struct ath5k_txq_info qi = {
1395                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1396                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1397                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1398                 /* NB: for dynamic turbo, don't enable any other interrupts */
1399                 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1400         };
1401
1402         return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1403 }
1404
1405 static int
1406 ath5k_beaconq_config(struct ath5k_softc *sc)
1407 {
1408         struct ath5k_hw *ah = sc->ah;
1409         struct ath5k_txq_info qi;
1410         int ret;
1411
1412         ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1413         if (ret)
1414                 return ret;
1415         if (sc->opmode == NL80211_IFTYPE_AP ||
1416                 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1417                 /*
1418                  * Always burst out beacon and CAB traffic
1419                  * (aifs = cwmin = cwmax = 0)
1420                  */
1421                 qi.tqi_aifs = 0;
1422                 qi.tqi_cw_min = 0;
1423                 qi.tqi_cw_max = 0;
1424         } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1425                 /*
1426                  * Adhoc mode; backoff between 0 and (2 * cw_min).
1427                  */
1428                 qi.tqi_aifs = 0;
1429                 qi.tqi_cw_min = 0;
1430                 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1431         }
1432
1433         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1434                 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1435                 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1436
1437         ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1438         if (ret) {
1439                 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1440                         "hardware queue!\n", __func__);
1441                 return ret;
1442         }
1443
1444         return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1445 }
1446
1447 static void
1448 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1449 {
1450         struct ath5k_buf *bf, *bf0;
1451
1452         /*
1453          * NB: this assumes output has been stopped and
1454          *     we do not need to block ath5k_tx_tasklet
1455          */
1456         spin_lock_bh(&txq->lock);
1457         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1458                 ath5k_debug_printtxbuf(sc, bf);
1459
1460                 ath5k_txbuf_free(sc, bf);
1461
1462                 spin_lock_bh(&sc->txbuflock);
1463                 sc->tx_stats[txq->qnum].len--;
1464                 list_move_tail(&bf->list, &sc->txbuf);
1465                 sc->txbuf_len++;
1466                 spin_unlock_bh(&sc->txbuflock);
1467         }
1468         txq->link = NULL;
1469         spin_unlock_bh(&txq->lock);
1470 }
1471
1472 /*
1473  * Drain the transmit queues and reclaim resources.
1474  */
1475 static void
1476 ath5k_txq_cleanup(struct ath5k_softc *sc)
1477 {
1478         struct ath5k_hw *ah = sc->ah;
1479         unsigned int i;
1480
1481         /* XXX return value */
1482         if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1483                 /* don't touch the hardware if marked invalid */
1484                 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1485                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1486                         ath5k_hw_get_txdp(ah, sc->bhalq));
1487                 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1488                         if (sc->txqs[i].setup) {
1489                                 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1490                                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1491                                         "link %p\n",
1492                                         sc->txqs[i].qnum,
1493                                         ath5k_hw_get_txdp(ah,
1494                                                         sc->txqs[i].qnum),
1495                                         sc->txqs[i].link);
1496                         }
1497         }
1498         ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1499
1500         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1501                 if (sc->txqs[i].setup)
1502                         ath5k_txq_drainq(sc, &sc->txqs[i]);
1503 }
1504
1505 static void
1506 ath5k_txq_release(struct ath5k_softc *sc)
1507 {
1508         struct ath5k_txq *txq = sc->txqs;
1509         unsigned int i;
1510
1511         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1512                 if (txq->setup) {
1513                         ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1514                         txq->setup = false;
1515                 }
1516 }
1517
1518
1519
1520
1521 /*************\
1522 * RX Handling *
1523 \*************/
1524
1525 /*
1526  * Enable the receive h/w following a reset.
1527  */
1528 static int
1529 ath5k_rx_start(struct ath5k_softc *sc)
1530 {
1531         struct ath5k_hw *ah = sc->ah;
1532         struct ath5k_buf *bf;
1533         int ret;
1534
1535         sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1536
1537         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1538                 sc->cachelsz, sc->rxbufsize);
1539
1540         sc->rxlink = NULL;
1541
1542         spin_lock_bh(&sc->rxbuflock);
1543         list_for_each_entry(bf, &sc->rxbuf, list) {
1544                 ret = ath5k_rxbuf_setup(sc, bf);
1545                 if (ret != 0) {
1546                         spin_unlock_bh(&sc->rxbuflock);
1547                         goto err;
1548                 }
1549         }
1550         bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1551         spin_unlock_bh(&sc->rxbuflock);
1552
1553         ath5k_hw_set_rxdp(ah, bf->daddr);
1554         ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
1555         ath5k_mode_setup(sc);           /* set filters, etc. */
1556         ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
1557
1558         return 0;
1559 err:
1560         return ret;
1561 }
1562
1563 /*
1564  * Disable the receive h/w in preparation for a reset.
1565  */
1566 static void
1567 ath5k_rx_stop(struct ath5k_softc *sc)
1568 {
1569         struct ath5k_hw *ah = sc->ah;
1570
1571         ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
1572         ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
1573         ath5k_hw_stop_rx_dma(ah);       /* disable DMA engine */
1574
1575         ath5k_debug_printrxbuffs(sc, ah);
1576
1577         sc->rxlink = NULL;              /* just in case */
1578 }
1579
1580 static unsigned int
1581 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1582                 struct sk_buff *skb, struct ath5k_rx_status *rs)
1583 {
1584         struct ieee80211_hdr *hdr = (void *)skb->data;
1585         unsigned int keyix, hlen;
1586
1587         if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1588                         rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1589                 return RX_FLAG_DECRYPTED;
1590
1591         /* Apparently when a default key is used to decrypt the packet
1592            the hw does not set the index used to decrypt.  In such cases
1593            get the index from the packet. */
1594         hlen = ieee80211_hdrlen(hdr->frame_control);
1595         if (ieee80211_has_protected(hdr->frame_control) &&
1596             !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1597             skb->len >= hlen + 4) {
1598                 keyix = skb->data[hlen + 3] >> 6;
1599
1600                 if (test_bit(keyix, sc->keymap))
1601                         return RX_FLAG_DECRYPTED;
1602         }
1603
1604         return 0;
1605 }
1606
1607
1608 static void
1609 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1610                      struct ieee80211_rx_status *rxs)
1611 {
1612         u64 tsf, bc_tstamp;
1613         u32 hw_tu;
1614         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1615
1616         if (ieee80211_is_beacon(mgmt->frame_control) &&
1617             le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1618             memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1619                 /*
1620                  * Received an IBSS beacon with the same BSSID. Hardware *must*
1621                  * have updated the local TSF. We have to work around various
1622                  * hardware bugs, though...
1623                  */
1624                 tsf = ath5k_hw_get_tsf64(sc->ah);
1625                 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1626                 hw_tu = TSF_TO_TU(tsf);
1627
1628                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1629                         "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1630                         (unsigned long long)bc_tstamp,
1631                         (unsigned long long)rxs->mactime,
1632                         (unsigned long long)(rxs->mactime - bc_tstamp),
1633                         (unsigned long long)tsf);
1634
1635                 /*
1636                  * Sometimes the HW will give us a wrong tstamp in the rx
1637                  * status, causing the timestamp extension to go wrong.
1638                  * (This seems to happen especially with beacon frames bigger
1639                  * than 78 byte (incl. FCS))
1640                  * But we know that the receive timestamp must be later than the
1641                  * timestamp of the beacon since HW must have synced to that.
1642                  *
1643                  * NOTE: here we assume mactime to be after the frame was
1644                  * received, not like mac80211 which defines it at the start.
1645                  */
1646                 if (bc_tstamp > rxs->mactime) {
1647                         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1648                                 "fixing mactime from %llx to %llx\n",
1649                                 (unsigned long long)rxs->mactime,
1650                                 (unsigned long long)tsf);
1651                         rxs->mactime = tsf;
1652                 }
1653
1654                 /*
1655                  * Local TSF might have moved higher than our beacon timers,
1656                  * in that case we have to update them to continue sending
1657                  * beacons. This also takes care of synchronizing beacon sending
1658                  * times with other stations.
1659                  */
1660                 if (hw_tu >= sc->nexttbtt)
1661                         ath5k_beacon_update_timers(sc, bc_tstamp);
1662         }
1663 }
1664
1665
1666 static void
1667 ath5k_tasklet_rx(unsigned long data)
1668 {
1669         struct ieee80211_rx_status rxs = {};
1670         struct ath5k_rx_status rs = {};
1671         struct sk_buff *skb;
1672         struct ath5k_softc *sc = (void *)data;
1673         struct ath5k_buf *bf, *bf_last;
1674         struct ath5k_desc *ds;
1675         int ret;
1676         int hdrlen;
1677         int pad;
1678
1679         spin_lock(&sc->rxbuflock);
1680         if (list_empty(&sc->rxbuf)) {
1681                 ATH5K_WARN(sc, "empty rx buf pool\n");
1682                 goto unlock;
1683         }
1684         bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1685         do {
1686                 rxs.flag = 0;
1687
1688                 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1689                 BUG_ON(bf->skb == NULL);
1690                 skb = bf->skb;
1691                 ds = bf->desc;
1692
1693                 /*
1694                  * last buffer must not be freed to ensure proper hardware
1695                  * function. When the hardware finishes also a packet next to
1696                  * it, we are sure, it doesn't use it anymore and we can go on.
1697                  */
1698                 if (bf_last == bf)
1699                         bf->flags |= 1;
1700                 if (bf->flags) {
1701                         struct ath5k_buf *bf_next = list_entry(bf->list.next,
1702                                         struct ath5k_buf, list);
1703                         ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1704                                         &rs);
1705                         if (ret)
1706                                 break;
1707                         bf->flags &= ~1;
1708                         /* skip the overwritten one (even status is martian) */
1709                         goto next;
1710                 }
1711
1712                 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1713                 if (unlikely(ret == -EINPROGRESS))
1714                         break;
1715                 else if (unlikely(ret)) {
1716                         ATH5K_ERR(sc, "error in processing rx descriptor\n");
1717                         spin_unlock(&sc->rxbuflock);
1718                         return;
1719                 }
1720
1721                 if (unlikely(rs.rs_more)) {
1722                         ATH5K_WARN(sc, "unsupported jumbo\n");
1723                         goto next;
1724                 }
1725
1726                 if (unlikely(rs.rs_status)) {
1727                         if (rs.rs_status & AR5K_RXERR_PHY)
1728                                 goto next;
1729                         if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1730                                 /*
1731                                  * Decrypt error.  If the error occurred
1732                                  * because there was no hardware key, then
1733                                  * let the frame through so the upper layers
1734                                  * can process it.  This is necessary for 5210
1735                                  * parts which have no way to setup a ``clear''
1736                                  * key cache entry.
1737                                  *
1738                                  * XXX do key cache faulting
1739                                  */
1740                                 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1741                                     !(rs.rs_status & AR5K_RXERR_CRC))
1742                                         goto accept;
1743                         }
1744                         if (rs.rs_status & AR5K_RXERR_MIC) {
1745                                 rxs.flag |= RX_FLAG_MMIC_ERROR;
1746                                 goto accept;
1747                         }
1748
1749                         /* let crypto-error packets fall through in MNTR */
1750                         if ((rs.rs_status &
1751                                 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1752                                         sc->opmode != NL80211_IFTYPE_MONITOR)
1753                                 goto next;
1754                 }
1755 accept:
1756                 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1757                                 PCI_DMA_FROMDEVICE);
1758                 bf->skb = NULL;
1759
1760                 skb_put(skb, rs.rs_datalen);
1761
1762                 /*
1763                  * the hardware adds a padding to 4 byte boundaries between
1764                  * the header and the payload data if the header length is
1765                  * not multiples of 4 - remove it
1766                  */
1767                 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1768                 if (hdrlen & 3) {
1769                         pad = hdrlen % 4;
1770                         memmove(skb->data + pad, skb->data, hdrlen);
1771                         skb_pull(skb, pad);
1772                 }
1773
1774                 /*
1775                  * always extend the mac timestamp, since this information is
1776                  * also needed for proper IBSS merging.
1777                  *
1778                  * XXX: it might be too late to do it here, since rs_tstamp is
1779                  * 15bit only. that means TSF extension has to be done within
1780                  * 32768usec (about 32ms). it might be necessary to move this to
1781                  * the interrupt handler, like it is done in madwifi.
1782                  *
1783                  * Unfortunately we don't know when the hardware takes the rx
1784                  * timestamp (beginning of phy frame, data frame, end of rx?).
1785                  * The only thing we know is that it is hardware specific...
1786                  * On AR5213 it seems the rx timestamp is at the end of the
1787                  * frame, but i'm not sure.
1788                  *
1789                  * NOTE: mac80211 defines mactime at the beginning of the first
1790                  * data symbol. Since we don't have any time references it's
1791                  * impossible to comply to that. This affects IBSS merge only
1792                  * right now, so it's not too bad...
1793                  */
1794                 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1795                 rxs.flag |= RX_FLAG_TSFT;
1796
1797                 rxs.freq = sc->curchan->center_freq;
1798                 rxs.band = sc->curband->band;
1799
1800                 rxs.noise = sc->ah->ah_noise_floor;
1801                 rxs.signal = rxs.noise + rs.rs_rssi;
1802                 rxs.qual = rs.rs_rssi * 100 / 64;
1803
1804                 rxs.antenna = rs.rs_antenna;
1805                 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1806                 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1807
1808                 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1809                     sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1810                         rxs.flag |= RX_FLAG_SHORTPRE;
1811
1812                 ath5k_debug_dump_skb(sc, skb, "RX  ", 0);
1813
1814                 /* check beacons in IBSS mode */
1815                 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1816                         ath5k_check_ibss_tsf(sc, skb, &rxs);
1817
1818                 __ieee80211_rx(sc->hw, skb, &rxs);
1819 next:
1820                 list_move_tail(&bf->list, &sc->rxbuf);
1821         } while (ath5k_rxbuf_setup(sc, bf) == 0);
1822 unlock:
1823         spin_unlock(&sc->rxbuflock);
1824 }
1825
1826
1827
1828
1829 /*************\
1830 * TX Handling *
1831 \*************/
1832
1833 static void
1834 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1835 {
1836         struct ath5k_tx_status ts = {};
1837         struct ath5k_buf *bf, *bf0;
1838         struct ath5k_desc *ds;
1839         struct sk_buff *skb;
1840         struct ieee80211_tx_info *info;
1841         int i, ret;
1842
1843         spin_lock(&txq->lock);
1844         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1845                 ds = bf->desc;
1846
1847                 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1848                 if (unlikely(ret == -EINPROGRESS))
1849                         break;
1850                 else if (unlikely(ret)) {
1851                         ATH5K_ERR(sc, "error %d while processing queue %u\n",
1852                                 ret, txq->qnum);
1853                         break;
1854                 }
1855
1856                 skb = bf->skb;
1857                 info = IEEE80211_SKB_CB(skb);
1858                 bf->skb = NULL;
1859
1860                 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1861                                 PCI_DMA_TODEVICE);
1862
1863                 memset(&info->status, 0, sizeof(info->status));
1864                 info->tx_rate_idx = ath5k_hw_to_driver_rix(sc,
1865                                 ts.ts_rate[ts.ts_final_idx]);
1866                 info->status.retry_count = ts.ts_longretry;
1867
1868                 for (i = 0; i < 4; i++) {
1869                         struct ieee80211_tx_altrate *r =
1870                                 &info->status.retries[i];
1871
1872                         if (ts.ts_rate[i]) {
1873                                 r->rate_idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1874                                 r->limit = ts.ts_retry[i];
1875                         } else {
1876                                 r->rate_idx = -1;
1877                                 r->limit = 0;
1878                         }
1879                 }
1880
1881                 info->status.excessive_retries = 0;
1882                 if (unlikely(ts.ts_status)) {
1883                         sc->ll_stats.dot11ACKFailureCount++;
1884                         if (ts.ts_status & AR5K_TXERR_XRETRY)
1885                                 info->status.excessive_retries = 1;
1886                         else if (ts.ts_status & AR5K_TXERR_FILT)
1887                                 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1888                 } else {
1889                         info->flags |= IEEE80211_TX_STAT_ACK;
1890                         info->status.ack_signal = ts.ts_rssi;
1891                 }
1892
1893                 ieee80211_tx_status(sc->hw, skb);
1894                 sc->tx_stats[txq->qnum].count++;
1895
1896                 spin_lock(&sc->txbuflock);
1897                 sc->tx_stats[txq->qnum].len--;
1898                 list_move_tail(&bf->list, &sc->txbuf);
1899                 sc->txbuf_len++;
1900                 spin_unlock(&sc->txbuflock);
1901         }
1902         if (likely(list_empty(&txq->q)))
1903                 txq->link = NULL;
1904         spin_unlock(&txq->lock);
1905         if (sc->txbuf_len > ATH_TXBUF / 5)
1906                 ieee80211_wake_queues(sc->hw);
1907 }
1908
1909 static void
1910 ath5k_tasklet_tx(unsigned long data)
1911 {
1912         struct ath5k_softc *sc = (void *)data;
1913
1914         ath5k_tx_processq(sc, sc->txq);
1915 }
1916
1917
1918 /*****************\
1919 * Beacon handling *
1920 \*****************/
1921
1922 /*
1923  * Setup the beacon frame for transmit.
1924  */
1925 static int
1926 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1927 {
1928         struct sk_buff *skb = bf->skb;
1929         struct  ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1930         struct ath5k_hw *ah = sc->ah;
1931         struct ath5k_desc *ds;
1932         int ret, antenna = 0;
1933         u32 flags;
1934
1935         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1936                         PCI_DMA_TODEVICE);
1937         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1938                         "skbaddr %llx\n", skb, skb->data, skb->len,
1939                         (unsigned long long)bf->skbaddr);
1940         if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1941                 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1942                 return -EIO;
1943         }
1944
1945         ds = bf->desc;
1946
1947         flags = AR5K_TXDESC_NOACK;
1948         if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1949                 ds->ds_link = bf->daddr;        /* self-linked */
1950                 flags |= AR5K_TXDESC_VEOL;
1951                 /*
1952                  * Let hardware handle antenna switching if txantenna is not set
1953                  */
1954         } else {
1955                 ds->ds_link = 0;
1956                 /*
1957                  * Switch antenna every 4 beacons if txantenna is not set
1958                  * XXX assumes two antennas
1959                  */
1960                 if (antenna == 0)
1961                         antenna = sc->bsent & 4 ? 2 : 1;
1962         }
1963
1964         ds->ds_data = bf->skbaddr;
1965         ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1966                         ieee80211_get_hdrlen_from_skb(skb),
1967                         AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1968                         ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1969                         1, AR5K_TXKEYIX_INVALID,
1970                         antenna, flags, 0, 0);
1971         if (ret)
1972                 goto err_unmap;
1973
1974         return 0;
1975 err_unmap:
1976         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1977         return ret;
1978 }
1979
1980 /*
1981  * Transmit a beacon frame at SWBA.  Dynamic updates to the
1982  * frame contents are done as needed and the slot time is
1983  * also adjusted based on current state.
1984  *
1985  * this is usually called from interrupt context (ath5k_intr())
1986  * but also from ath5k_beacon_config() in IBSS mode which in turn
1987  * can be called from a tasklet and user context
1988  */
1989 static void
1990 ath5k_beacon_send(struct ath5k_softc *sc)
1991 {
1992         struct ath5k_buf *bf = sc->bbuf;
1993         struct ath5k_hw *ah = sc->ah;
1994
1995         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1996
1997         if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1998                         sc->opmode == NL80211_IFTYPE_MONITOR)) {
1999                 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2000                 return;
2001         }
2002         /*
2003          * Check if the previous beacon has gone out.  If
2004          * not don't don't try to post another, skip this
2005          * period and wait for the next.  Missed beacons
2006          * indicate a problem and should not occur.  If we
2007          * miss too many consecutive beacons reset the device.
2008          */
2009         if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2010                 sc->bmisscount++;
2011                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2012                         "missed %u consecutive beacons\n", sc->bmisscount);
2013                 if (sc->bmisscount > 3) {               /* NB: 3 is a guess */
2014                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2015                                 "stuck beacon time (%u missed)\n",
2016                                 sc->bmisscount);
2017                         tasklet_schedule(&sc->restq);
2018                 }
2019                 return;
2020         }
2021         if (unlikely(sc->bmisscount != 0)) {
2022                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2023                         "resume beacon xmit after %u misses\n",
2024                         sc->bmisscount);
2025                 sc->bmisscount = 0;
2026         }
2027
2028         /*
2029          * Stop any current dma and put the new frame on the queue.
2030          * This should never fail since we check above that no frames
2031          * are still pending on the queue.
2032          */
2033         if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2034                 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2035                 /* NB: hw still stops DMA, so proceed */
2036         }
2037
2038         ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2039         ath5k_hw_start_tx_dma(ah, sc->bhalq);
2040         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2041                 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2042
2043         sc->bsent++;
2044 }
2045
2046
2047 /**
2048  * ath5k_beacon_update_timers - update beacon timers
2049  *
2050  * @sc: struct ath5k_softc pointer we are operating on
2051  * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2052  *          beacon timer update based on the current HW TSF.
2053  *
2054  * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2055  * of a received beacon or the current local hardware TSF and write it to the
2056  * beacon timer registers.
2057  *
2058  * This is called in a variety of situations, e.g. when a beacon is received,
2059  * when a TSF update has been detected, but also when an new IBSS is created or
2060  * when we otherwise know we have to update the timers, but we keep it in this
2061  * function to have it all together in one place.
2062  */
2063 static void
2064 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2065 {
2066         struct ath5k_hw *ah = sc->ah;
2067         u32 nexttbtt, intval, hw_tu, bc_tu;
2068         u64 hw_tsf;
2069
2070         intval = sc->bintval & AR5K_BEACON_PERIOD;
2071         if (WARN_ON(!intval))
2072                 return;
2073
2074         /* beacon TSF converted to TU */
2075         bc_tu = TSF_TO_TU(bc_tsf);
2076
2077         /* current TSF converted to TU */
2078         hw_tsf = ath5k_hw_get_tsf64(ah);
2079         hw_tu = TSF_TO_TU(hw_tsf);
2080
2081 #define FUDGE 3
2082         /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2083         if (bc_tsf == -1) {
2084                 /*
2085                  * no beacons received, called internally.
2086                  * just need to refresh timers based on HW TSF.
2087                  */
2088                 nexttbtt = roundup(hw_tu + FUDGE, intval);
2089         } else if (bc_tsf == 0) {
2090                 /*
2091                  * no beacon received, probably called by ath5k_reset_tsf().
2092                  * reset TSF to start with 0.
2093                  */
2094                 nexttbtt = intval;
2095                 intval |= AR5K_BEACON_RESET_TSF;
2096         } else if (bc_tsf > hw_tsf) {
2097                 /*
2098                  * beacon received, SW merge happend but HW TSF not yet updated.
2099                  * not possible to reconfigure timers yet, but next time we
2100                  * receive a beacon with the same BSSID, the hardware will
2101                  * automatically update the TSF and then we need to reconfigure
2102                  * the timers.
2103                  */
2104                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2105                         "need to wait for HW TSF sync\n");
2106                 return;
2107         } else {
2108                 /*
2109                  * most important case for beacon synchronization between STA.
2110                  *
2111                  * beacon received and HW TSF has been already updated by HW.
2112                  * update next TBTT based on the TSF of the beacon, but make
2113                  * sure it is ahead of our local TSF timer.
2114                  */
2115                 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2116         }
2117 #undef FUDGE
2118
2119         sc->nexttbtt = nexttbtt;
2120
2121         intval |= AR5K_BEACON_ENA;
2122         ath5k_hw_init_beacon(ah, nexttbtt, intval);
2123
2124         /*
2125          * debugging output last in order to preserve the time critical aspect
2126          * of this function
2127          */
2128         if (bc_tsf == -1)
2129                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2130                         "reconfigured timers based on HW TSF\n");
2131         else if (bc_tsf == 0)
2132                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2133                         "reset HW TSF and timers\n");
2134         else
2135                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2136                         "updated timers based on beacon TSF\n");
2137
2138         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2139                           "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2140                           (unsigned long long) bc_tsf,
2141                           (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2142         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2143                 intval & AR5K_BEACON_PERIOD,
2144                 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2145                 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2146 }
2147
2148
2149 /**
2150  * ath5k_beacon_config - Configure the beacon queues and interrupts
2151  *
2152  * @sc: struct ath5k_softc pointer we are operating on
2153  *
2154  * When operating in station mode we want to receive a BMISS interrupt when we
2155  * stop seeing beacons from the AP we've associated with so we can look for
2156  * another AP to associate with.
2157  *
2158  * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2159  * interrupts to detect TSF updates only.
2160  *
2161  * AP mode is missing.
2162  */
2163 static void
2164 ath5k_beacon_config(struct ath5k_softc *sc)
2165 {
2166         struct ath5k_hw *ah = sc->ah;
2167
2168         ath5k_hw_set_imr(ah, 0);
2169         sc->bmisscount = 0;
2170         sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2171
2172         if (sc->opmode == NL80211_IFTYPE_STATION) {
2173                 sc->imask |= AR5K_INT_BMISS;
2174         } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2175                 /*
2176                  * In IBSS mode we use a self-linked tx descriptor and let the
2177                  * hardware send the beacons automatically. We have to load it
2178                  * only once here.
2179                  * We use the SWBA interrupt only to keep track of the beacon
2180                  * timers in order to detect automatic TSF updates.
2181                  */
2182                 ath5k_beaconq_config(sc);
2183
2184                 sc->imask |= AR5K_INT_SWBA;
2185
2186                 if (ath5k_hw_hasveol(ah)) {
2187                         spin_lock(&sc->block);
2188                         ath5k_beacon_send(sc);
2189                         spin_unlock(&sc->block);
2190                 }
2191         }
2192         /* TODO else AP */
2193
2194         ath5k_hw_set_imr(ah, sc->imask);
2195 }
2196
2197
2198 /********************\
2199 * Interrupt handling *
2200 \********************/
2201
2202 static int
2203 ath5k_init(struct ath5k_softc *sc)
2204 {
2205         int ret;
2206
2207         mutex_lock(&sc->lock);
2208
2209         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2210
2211         /*
2212          * Stop anything previously setup.  This is safe
2213          * no matter this is the first time through or not.
2214          */
2215         ath5k_stop_locked(sc);
2216
2217         /*
2218          * The basic interface to setting the hardware in a good
2219          * state is ``reset''.  On return the hardware is known to
2220          * be powered up and with interrupts disabled.  This must
2221          * be followed by initialization of the appropriate bits
2222          * and then setup of the interrupt mask.
2223          */
2224         sc->curchan = sc->hw->conf.channel;
2225         sc->curband = &sc->sbands[sc->curchan->band];
2226         sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2227                 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2228                 AR5K_INT_MIB;
2229         ret = ath5k_reset(sc, false, false);
2230         if (ret)
2231                 goto done;
2232
2233         /* Set ack to be sent at low bit-rates */
2234         ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2235
2236         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2237                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2238
2239         ret = 0;
2240 done:
2241         mmiowb();
2242         mutex_unlock(&sc->lock);
2243         return ret;
2244 }
2245
2246 static int
2247 ath5k_stop_locked(struct ath5k_softc *sc)
2248 {
2249         struct ath5k_hw *ah = sc->ah;
2250
2251         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2252                         test_bit(ATH_STAT_INVALID, sc->status));
2253
2254         /*
2255          * Shutdown the hardware and driver:
2256          *    stop output from above
2257          *    disable interrupts
2258          *    turn off timers
2259          *    turn off the radio
2260          *    clear transmit machinery
2261          *    clear receive machinery
2262          *    drain and release tx queues
2263          *    reclaim beacon resources
2264          *    power down hardware
2265          *
2266          * Note that some of this work is not possible if the
2267          * hardware is gone (invalid).
2268          */
2269         ieee80211_stop_queues(sc->hw);
2270
2271         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2272                 ath5k_led_off(sc);
2273                 ath5k_hw_set_imr(ah, 0);
2274                 synchronize_irq(sc->pdev->irq);
2275         }
2276         ath5k_txq_cleanup(sc);
2277         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2278                 ath5k_rx_stop(sc);
2279                 ath5k_hw_phy_disable(ah);
2280         } else
2281                 sc->rxlink = NULL;
2282
2283         return 0;
2284 }
2285
2286 /*
2287  * Stop the device, grabbing the top-level lock to protect
2288  * against concurrent entry through ath5k_init (which can happen
2289  * if another thread does a system call and the thread doing the
2290  * stop is preempted).
2291  */
2292 static int
2293 ath5k_stop_hw(struct ath5k_softc *sc)
2294 {
2295         int ret;
2296
2297         mutex_lock(&sc->lock);
2298         ret = ath5k_stop_locked(sc);
2299         if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2300                 /*
2301                  * Set the chip in full sleep mode.  Note that we are
2302                  * careful to do this only when bringing the interface
2303                  * completely to a stop.  When the chip is in this state
2304                  * it must be carefully woken up or references to
2305                  * registers in the PCI clock domain may freeze the bus
2306                  * (and system).  This varies by chip and is mostly an
2307                  * issue with newer parts that go to sleep more quickly.
2308                  */
2309                 if (sc->ah->ah_mac_srev >= 0x78) {
2310                         /*
2311                          * XXX
2312                          * don't put newer MAC revisions > 7.8 to sleep because
2313                          * of the above mentioned problems
2314                          */
2315                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2316                                 "not putting device to sleep\n");
2317                 } else {
2318                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2319                                 "putting device to full sleep\n");
2320                         ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2321                 }
2322         }
2323         ath5k_txbuf_free(sc, sc->bbuf);
2324         mmiowb();
2325         mutex_unlock(&sc->lock);
2326
2327         del_timer_sync(&sc->calib_tim);
2328         tasklet_kill(&sc->rxtq);
2329         tasklet_kill(&sc->txtq);
2330         tasklet_kill(&sc->restq);
2331
2332         return ret;
2333 }
2334
2335 static irqreturn_t
2336 ath5k_intr(int irq, void *dev_id)
2337 {
2338         struct ath5k_softc *sc = dev_id;
2339         struct ath5k_hw *ah = sc->ah;
2340         enum ath5k_int status;
2341         unsigned int counter = 1000;
2342
2343         if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2344                                 !ath5k_hw_is_intr_pending(ah)))
2345                 return IRQ_NONE;
2346
2347         do {
2348                 /*
2349                  * Figure out the reason(s) for the interrupt.  Note
2350                  * that get_isr returns a pseudo-ISR that may include
2351                  * bits we haven't explicitly enabled so we mask the
2352                  * value to insure we only process bits we requested.
2353                  */
2354                 ath5k_hw_get_isr(ah, &status);          /* NB: clears IRQ too */
2355                 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2356                                 status, sc->imask);
2357                 status &= sc->imask; /* discard unasked for bits */
2358                 if (unlikely(status & AR5K_INT_FATAL)) {
2359                         /*
2360                          * Fatal errors are unrecoverable.
2361                          * Typically these are caused by DMA errors.
2362                          */
2363                         tasklet_schedule(&sc->restq);
2364                 } else if (unlikely(status & AR5K_INT_RXORN)) {
2365                         tasklet_schedule(&sc->restq);
2366                 } else {
2367                         if (status & AR5K_INT_SWBA) {
2368                                 /*
2369                                 * Software beacon alert--time to send a beacon.
2370                                 * Handle beacon transmission directly; deferring
2371                                 * this is too slow to meet timing constraints
2372                                 * under load.
2373                                 *
2374                                 * In IBSS mode we use this interrupt just to
2375                                 * keep track of the next TBTT (target beacon
2376                                 * transmission time) in order to detect wether
2377                                 * automatic TSF updates happened.
2378                                 */
2379                                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2380                                          /* XXX: only if VEOL suppported */
2381                                         u64 tsf = ath5k_hw_get_tsf64(ah);
2382                                         sc->nexttbtt += sc->bintval;
2383                                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2384                                                   "SWBA nexttbtt: %x hw_tu: %x "
2385                                                   "TSF: %llx\n",
2386                                                   sc->nexttbtt,
2387                                                   TSF_TO_TU(tsf),
2388                                                   (unsigned long long) tsf);
2389                                 } else {
2390                                         spin_lock(&sc->block);
2391                                         ath5k_beacon_send(sc);
2392                                         spin_unlock(&sc->block);
2393                                 }
2394                         }
2395                         if (status & AR5K_INT_RXEOL) {
2396                                 /*
2397                                 * NB: the hardware should re-read the link when
2398                                 *     RXE bit is written, but it doesn't work at
2399                                 *     least on older hardware revs.
2400                                 */
2401                                 sc->rxlink = NULL;
2402                         }
2403                         if (status & AR5K_INT_TXURN) {
2404                                 /* bump tx trigger level */
2405                                 ath5k_hw_update_tx_triglevel(ah, true);
2406                         }
2407                         if (status & AR5K_INT_RX)
2408                                 tasklet_schedule(&sc->rxtq);
2409                         if (status & AR5K_INT_TX)
2410                                 tasklet_schedule(&sc->txtq);
2411                         if (status & AR5K_INT_BMISS) {
2412                         }
2413                         if (status & AR5K_INT_MIB) {
2414                                 /*
2415                                  * These stats are also used for ANI i think
2416                                  * so how about updating them more often ?
2417                                  */
2418                                 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2419                         }
2420                 }
2421         } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2422
2423         if (unlikely(!counter))
2424                 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2425
2426         return IRQ_HANDLED;
2427 }
2428
2429 static void
2430 ath5k_tasklet_reset(unsigned long data)
2431 {
2432         struct ath5k_softc *sc = (void *)data;
2433
2434         ath5k_reset_wake(sc);
2435 }
2436
2437 /*
2438  * Periodically recalibrate the PHY to account
2439  * for temperature/environment changes.
2440  */
2441 static void
2442 ath5k_calibrate(unsigned long data)
2443 {
2444         struct ath5k_softc *sc = (void *)data;
2445         struct ath5k_hw *ah = sc->ah;
2446
2447         ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2448                 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2449                 sc->curchan->hw_value);
2450
2451         if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2452                 /*
2453                  * Rfgain is out of bounds, reset the chip
2454                  * to load new gain values.
2455                  */
2456                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2457                 ath5k_reset_wake(sc);
2458         }
2459         if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2460                 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2461                         ieee80211_frequency_to_channel(
2462                                 sc->curchan->center_freq));
2463
2464         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2465                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2466 }
2467
2468
2469
2470 /***************\
2471 * LED functions *
2472 \***************/
2473
2474 static void
2475 ath5k_led_enable(struct ath5k_softc *sc)
2476 {
2477         if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2478                 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2479                 ath5k_led_off(sc);
2480         }
2481 }
2482
2483 static void
2484 ath5k_led_on(struct ath5k_softc *sc)
2485 {
2486         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2487                 return;
2488         ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2489 }
2490
2491 static void
2492 ath5k_led_off(struct ath5k_softc *sc)
2493 {
2494         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2495                 return;
2496         ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2497 }
2498
2499 static void
2500 ath5k_led_brightness_set(struct led_classdev *led_dev,
2501         enum led_brightness brightness)
2502 {
2503         struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2504                 led_dev);
2505
2506         if (brightness == LED_OFF)
2507                 ath5k_led_off(led->sc);
2508         else
2509                 ath5k_led_on(led->sc);
2510 }
2511
2512 static int
2513 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2514                    const char *name, char *trigger)
2515 {
2516         int err;
2517
2518         led->sc = sc;
2519         strncpy(led->name, name, sizeof(led->name));
2520         led->led_dev.name = led->name;
2521         led->led_dev.default_trigger = trigger;
2522         led->led_dev.brightness_set = ath5k_led_brightness_set;
2523
2524         err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2525         if (err)
2526         {
2527                 ATH5K_WARN(sc, "could not register LED %s\n", name);
2528                 led->sc = NULL;
2529         }
2530         return err;
2531 }
2532
2533 static void
2534 ath5k_unregister_led(struct ath5k_led *led)
2535 {
2536         if (!led->sc)
2537                 return;
2538         led_classdev_unregister(&led->led_dev);
2539         ath5k_led_off(led->sc);
2540         led->sc = NULL;
2541 }
2542
2543 static void
2544 ath5k_unregister_leds(struct ath5k_softc *sc)
2545 {
2546         ath5k_unregister_led(&sc->rx_led);
2547         ath5k_unregister_led(&sc->tx_led);
2548 }
2549
2550
2551 static int
2552 ath5k_init_leds(struct ath5k_softc *sc)
2553 {
2554         int ret = 0;
2555         struct ieee80211_hw *hw = sc->hw;
2556         struct pci_dev *pdev = sc->pdev;
2557         char name[ATH5K_LED_MAX_NAME_LEN + 1];
2558
2559         /*
2560          * Auto-enable soft led processing for IBM cards and for
2561          * 5211 minipci cards.
2562          */
2563         if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2564             pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2565                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2566                 sc->led_pin = 0;
2567                 sc->led_on = 0;  /* active low */
2568         }
2569         /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2570         if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2571                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2572                 sc->led_pin = 1;
2573                 sc->led_on = 1;  /* active high */
2574         }
2575         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2576                 goto out;
2577
2578         ath5k_led_enable(sc);
2579
2580         snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2581         ret = ath5k_register_led(sc, &sc->rx_led, name,
2582                 ieee80211_get_rx_led_name(hw));
2583         if (ret)
2584                 goto out;
2585
2586         snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2587         ret = ath5k_register_led(sc, &sc->tx_led, name,
2588                 ieee80211_get_tx_led_name(hw));
2589 out:
2590         return ret;
2591 }
2592
2593
2594 /********************\
2595 * Mac80211 functions *
2596 \********************/
2597
2598 static int
2599 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2600 {
2601         struct ath5k_softc *sc = hw->priv;
2602         struct ath5k_buf *bf;
2603         unsigned long flags;
2604         int hdrlen;
2605         int pad;
2606
2607         ath5k_debug_dump_skb(sc, skb, "TX  ", 1);
2608
2609         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2610                 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2611
2612         /*
2613          * the hardware expects the header padded to 4 byte boundaries
2614          * if this is not the case we add the padding after the header
2615          */
2616         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2617         if (hdrlen & 3) {
2618                 pad = hdrlen % 4;
2619                 if (skb_headroom(skb) < pad) {
2620                         ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2621                                 " headroom to pad %d\n", hdrlen, pad);
2622                         return -1;
2623                 }
2624                 skb_push(skb, pad);
2625                 memmove(skb->data, skb->data+pad, hdrlen);
2626         }
2627
2628         spin_lock_irqsave(&sc->txbuflock, flags);
2629         if (list_empty(&sc->txbuf)) {
2630                 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2631                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2632                 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2633                 return -1;
2634         }
2635         bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2636         list_del(&bf->list);
2637         sc->txbuf_len--;
2638         if (list_empty(&sc->txbuf))
2639                 ieee80211_stop_queues(hw);
2640         spin_unlock_irqrestore(&sc->txbuflock, flags);
2641
2642         bf->skb = skb;
2643
2644         if (ath5k_txbuf_setup(sc, bf)) {
2645                 bf->skb = NULL;
2646                 spin_lock_irqsave(&sc->txbuflock, flags);
2647                 list_add_tail(&bf->list, &sc->txbuf);
2648                 sc->txbuf_len++;
2649                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2650                 dev_kfree_skb_any(skb);
2651                 return 0;
2652         }
2653
2654         return 0;
2655 }
2656
2657 static int
2658 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2659 {
2660         struct ath5k_hw *ah = sc->ah;
2661         int ret;
2662
2663         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2664
2665         if (stop) {
2666                 ath5k_hw_set_imr(ah, 0);
2667                 ath5k_txq_cleanup(sc);
2668                 ath5k_rx_stop(sc);
2669         }
2670         ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2671         if (ret) {
2672                 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2673                 goto err;
2674         }
2675
2676         /*
2677          * This is needed only to setup initial state
2678          * but it's best done after a reset.
2679          */
2680         ath5k_hw_set_txpower_limit(sc->ah, 0);
2681
2682         ret = ath5k_rx_start(sc);
2683         if (ret) {
2684                 ATH5K_ERR(sc, "can't start recv logic\n");
2685                 goto err;
2686         }
2687
2688         /*
2689          * Change channels and update the h/w rate map if we're switching;
2690          * e.g. 11a to 11b/g.
2691          *
2692          * We may be doing a reset in response to an ioctl that changes the
2693          * channel so update any state that might change as a result.
2694          *
2695          * XXX needed?
2696          */
2697 /*      ath5k_chan_change(sc, c); */
2698
2699         ath5k_beacon_config(sc);
2700         /* intrs are enabled by ath5k_beacon_config */
2701
2702         return 0;
2703 err:
2704         return ret;
2705 }
2706
2707 static int
2708 ath5k_reset_wake(struct ath5k_softc *sc)
2709 {
2710         int ret;
2711
2712         ret = ath5k_reset(sc, true, true);
2713         if (!ret)
2714                 ieee80211_wake_queues(sc->hw);
2715
2716         return ret;
2717 }
2718
2719 static int ath5k_start(struct ieee80211_hw *hw)
2720 {
2721         return ath5k_init(hw->priv);
2722 }
2723
2724 static void ath5k_stop(struct ieee80211_hw *hw)
2725 {
2726         ath5k_stop_hw(hw->priv);
2727 }
2728
2729 static int ath5k_add_interface(struct ieee80211_hw *hw,
2730                 struct ieee80211_if_init_conf *conf)
2731 {
2732         struct ath5k_softc *sc = hw->priv;
2733         int ret;
2734
2735         mutex_lock(&sc->lock);
2736         if (sc->vif) {
2737                 ret = 0;
2738                 goto end;
2739         }
2740
2741         sc->vif = conf->vif;
2742
2743         switch (conf->type) {
2744         case NL80211_IFTYPE_STATION:
2745         case NL80211_IFTYPE_ADHOC:
2746         case NL80211_IFTYPE_MONITOR:
2747                 sc->opmode = conf->type;
2748                 break;
2749         default:
2750                 ret = -EOPNOTSUPP;
2751                 goto end;
2752         }
2753
2754         /* Set to a reasonable value. Note that this will
2755          * be set to mac80211's value at ath5k_config(). */
2756         sc->bintval = 1000;
2757
2758         ret = 0;
2759 end:
2760         mutex_unlock(&sc->lock);
2761         return ret;
2762 }
2763
2764 static void
2765 ath5k_remove_interface(struct ieee80211_hw *hw,
2766                         struct ieee80211_if_init_conf *conf)
2767 {
2768         struct ath5k_softc *sc = hw->priv;
2769
2770         mutex_lock(&sc->lock);
2771         if (sc->vif != conf->vif)
2772                 goto end;
2773
2774         sc->vif = NULL;
2775 end:
2776         mutex_unlock(&sc->lock);
2777 }
2778
2779 /*
2780  * TODO: Phy disable/diversity etc
2781  */
2782 static int
2783 ath5k_config(struct ieee80211_hw *hw,
2784                         struct ieee80211_conf *conf)
2785 {
2786         struct ath5k_softc *sc = hw->priv;
2787
2788         sc->bintval = conf->beacon_int;
2789         sc->power_level = conf->power_level;
2790
2791         return ath5k_chan_set(sc, conf->channel);
2792 }
2793
2794 static int
2795 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2796                         struct ieee80211_if_conf *conf)
2797 {
2798         struct ath5k_softc *sc = hw->priv;
2799         struct ath5k_hw *ah = sc->ah;
2800         int ret;
2801
2802         mutex_lock(&sc->lock);
2803         if (sc->vif != vif) {
2804                 ret = -EIO;
2805                 goto unlock;
2806         }
2807         if (conf->bssid) {
2808                 /* Cache for later use during resets */
2809                 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2810                 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2811                  * a clean way of letting us retrieve this yet. */
2812                 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2813                 mmiowb();
2814         }
2815
2816         if (conf->changed & IEEE80211_IFCC_BEACON &&
2817             vif->type == NL80211_IFTYPE_ADHOC) {
2818                 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2819                 if (!beacon) {
2820                         ret = -ENOMEM;
2821                         goto unlock;
2822                 }
2823                 /* call old handler for now */
2824                 ath5k_beacon_update(hw, beacon);
2825         }
2826
2827         mutex_unlock(&sc->lock);
2828
2829         return ath5k_reset_wake(sc);
2830 unlock:
2831         mutex_unlock(&sc->lock);
2832         return ret;
2833 }
2834
2835 #define SUPPORTED_FIF_FLAGS \
2836         FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
2837         FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2838         FIF_BCN_PRBRESP_PROMISC
2839 /*
2840  * o always accept unicast, broadcast, and multicast traffic
2841  * o multicast traffic for all BSSIDs will be enabled if mac80211
2842  *   says it should be
2843  * o maintain current state of phy ofdm or phy cck error reception.
2844  *   If the hardware detects any of these type of errors then
2845  *   ath5k_hw_get_rx_filter() will pass to us the respective
2846  *   hardware filters to be able to receive these type of frames.
2847  * o probe request frames are accepted only when operating in
2848  *   hostap, adhoc, or monitor modes
2849  * o enable promiscuous mode according to the interface state
2850  * o accept beacons:
2851  *   - when operating in adhoc mode so the 802.11 layer creates
2852  *     node table entries for peers,
2853  *   - when operating in station mode for collecting rssi data when
2854  *     the station is otherwise quiet, or
2855  *   - when scanning
2856  */
2857 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2858                 unsigned int changed_flags,
2859                 unsigned int *new_flags,
2860                 int mc_count, struct dev_mc_list *mclist)
2861 {
2862         struct ath5k_softc *sc = hw->priv;
2863         struct ath5k_hw *ah = sc->ah;
2864         u32 mfilt[2], val, rfilt;
2865         u8 pos;
2866         int i;
2867
2868         mfilt[0] = 0;
2869         mfilt[1] = 0;
2870
2871         /* Only deal with supported flags */
2872         changed_flags &= SUPPORTED_FIF_FLAGS;
2873         *new_flags &= SUPPORTED_FIF_FLAGS;
2874
2875         /* If HW detects any phy or radar errors, leave those filters on.
2876          * Also, always enable Unicast, Broadcasts and Multicast
2877          * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2878         rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2879                 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2880                 AR5K_RX_FILTER_MCAST);
2881
2882         if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2883                 if (*new_flags & FIF_PROMISC_IN_BSS) {
2884                         rfilt |= AR5K_RX_FILTER_PROM;
2885                         __set_bit(ATH_STAT_PROMISC, sc->status);
2886                 }
2887                 else
2888                         __clear_bit(ATH_STAT_PROMISC, sc->status);
2889         }
2890
2891         /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2892         if (*new_flags & FIF_ALLMULTI) {
2893                 mfilt[0] =  ~0;
2894                 mfilt[1] =  ~0;
2895         } else {
2896                 for (i = 0; i < mc_count; i++) {
2897                         if (!mclist)
2898                                 break;
2899                         /* calculate XOR of eight 6-bit values */
2900                         val = get_unaligned_le32(mclist->dmi_addr + 0);
2901                         pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2902                         val = get_unaligned_le32(mclist->dmi_addr + 3);
2903                         pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2904                         pos &= 0x3f;
2905                         mfilt[pos / 32] |= (1 << (pos % 32));
2906                         /* XXX: we might be able to just do this instead,
2907                         * but not sure, needs testing, if we do use this we'd
2908                         * neet to inform below to not reset the mcast */
2909                         /* ath5k_hw_set_mcast_filterindex(ah,
2910                          *      mclist->dmi_addr[5]); */
2911                         mclist = mclist->next;
2912                 }
2913         }
2914
2915         /* This is the best we can do */
2916         if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2917                 rfilt |= AR5K_RX_FILTER_PHYERR;
2918
2919         /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2920         * and probes for any BSSID, this needs testing */
2921         if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2922                 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2923
2924         /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2925          * set we should only pass on control frames for this
2926          * station. This needs testing. I believe right now this
2927          * enables *all* control frames, which is OK.. but
2928          * but we should see if we can improve on granularity */
2929         if (*new_flags & FIF_CONTROL)
2930                 rfilt |= AR5K_RX_FILTER_CONTROL;
2931
2932         /* Additional settings per mode -- this is per ath5k */
2933
2934         /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2935
2936         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2937                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2938                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2939         if (sc->opmode != NL80211_IFTYPE_STATION)
2940                 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2941         if (sc->opmode != NL80211_IFTYPE_AP &&
2942                 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2943                 test_bit(ATH_STAT_PROMISC, sc->status))
2944                 rfilt |= AR5K_RX_FILTER_PROM;
2945         if (sc->opmode == NL80211_IFTYPE_STATION ||
2946                 sc->opmode == NL80211_IFTYPE_ADHOC) {
2947                 rfilt |= AR5K_RX_FILTER_BEACON;
2948         }
2949
2950         /* Set filters */
2951         ath5k_hw_set_rx_filter(ah,rfilt);
2952
2953         /* Set multicast bits */
2954         ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2955         /* Set the cached hw filter flags, this will alter actually
2956          * be set in HW */
2957         sc->filter_flags = rfilt;
2958 }
2959
2960 static int
2961 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2962                 const u8 *local_addr, const u8 *addr,
2963                 struct ieee80211_key_conf *key)
2964 {
2965         struct ath5k_softc *sc = hw->priv;
2966         int ret = 0;
2967
2968         switch(key->alg) {
2969         case ALG_WEP:
2970         /* XXX: fix hardware encryption, its not working. For now
2971          * allow software encryption */
2972                 /* break; */
2973         case ALG_TKIP:
2974         case ALG_CCMP:
2975                 return -EOPNOTSUPP;
2976         default:
2977                 WARN_ON(1);
2978                 return -EINVAL;
2979         }
2980
2981         mutex_lock(&sc->lock);
2982
2983         switch (cmd) {
2984         case SET_KEY:
2985                 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2986                 if (ret) {
2987                         ATH5K_ERR(sc, "can't set the key\n");
2988                         goto unlock;
2989                 }
2990                 __set_bit(key->keyidx, sc->keymap);
2991                 key->hw_key_idx = key->keyidx;
2992                 break;
2993         case DISABLE_KEY:
2994                 ath5k_hw_reset_key(sc->ah, key->keyidx);
2995                 __clear_bit(key->keyidx, sc->keymap);
2996                 break;
2997         default:
2998                 ret = -EINVAL;
2999                 goto unlock;
3000         }
3001
3002 unlock:
3003         mmiowb();
3004         mutex_unlock(&sc->lock);
3005         return ret;
3006 }
3007
3008 static int
3009 ath5k_get_stats(struct ieee80211_hw *hw,
3010                 struct ieee80211_low_level_stats *stats)
3011 {
3012         struct ath5k_softc *sc = hw->priv;
3013         struct ath5k_hw *ah = sc->ah;
3014
3015         /* Force update */
3016         ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3017
3018         memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3019
3020         return 0;
3021 }
3022
3023 static int
3024 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3025                 struct ieee80211_tx_queue_stats *stats)
3026 {
3027         struct ath5k_softc *sc = hw->priv;
3028
3029         memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3030
3031         return 0;
3032 }
3033
3034 static u64
3035 ath5k_get_tsf(struct ieee80211_hw *hw)
3036 {
3037         struct ath5k_softc *sc = hw->priv;
3038
3039         return ath5k_hw_get_tsf64(sc->ah);
3040 }
3041
3042 static void
3043 ath5k_reset_tsf(struct ieee80211_hw *hw)
3044 {
3045         struct ath5k_softc *sc = hw->priv;
3046
3047         /*
3048          * in IBSS mode we need to update the beacon timers too.
3049          * this will also reset the TSF if we call it with 0
3050          */
3051         if (sc->opmode == NL80211_IFTYPE_ADHOC)
3052                 ath5k_beacon_update_timers(sc, 0);
3053         else
3054                 ath5k_hw_reset_tsf(sc->ah);
3055 }
3056
3057 static int
3058 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
3059 {
3060         struct ath5k_softc *sc = hw->priv;
3061         unsigned long flags;
3062         int ret;
3063
3064         ath5k_debug_dump_skb(sc, skb, "BC  ", 1);
3065
3066         if (sc->opmode != NL80211_IFTYPE_ADHOC) {
3067                 ret = -EIO;
3068                 goto end;
3069         }
3070
3071         spin_lock_irqsave(&sc->block, flags);
3072         ath5k_txbuf_free(sc, sc->bbuf);
3073         sc->bbuf->skb = skb;
3074         ret = ath5k_beacon_setup(sc, sc->bbuf);
3075         if (ret)
3076                 sc->bbuf->skb = NULL;
3077         spin_unlock_irqrestore(&sc->block, flags);
3078         if (!ret) {
3079                 ath5k_beacon_config(sc);
3080                 mmiowb();
3081         }
3082
3083 end:
3084         return ret;
3085 }
3086