2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
42 #include <net/checksum.h>
45 #include <asm/system.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
51 #include <asm/idprom.h>
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
58 #define TG3_VLAN_TAG_USED 0
61 #define TG3_TSO_SUPPORT 1
65 #define DRV_MODULE_NAME "tg3"
66 #define PFX DRV_MODULE_NAME ": "
67 #define DRV_MODULE_VERSION "3.81"
68 #define DRV_MODULE_RELDATE "September 5, 2007"
70 #define TG3_DEF_MAC_MODE 0
71 #define TG3_DEF_RX_MODE 0
72 #define TG3_DEF_TX_MODE 0
73 #define TG3_DEF_MSG_ENABLE \
83 /* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
86 #define TG3_TX_TIMEOUT (5 * HZ)
88 /* hardware minimum and maximum for a single frame's data payload */
89 #define TG3_MIN_MTU 60
90 #define TG3_MAX_MTU(tp) \
91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
93 /* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
97 #define TG3_RX_RING_SIZE 512
98 #define TG3_DEF_RX_RING_PENDING 200
99 #define TG3_RX_JUMBO_RING_SIZE 256
100 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
102 /* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
108 #define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
111 #define TG3_TX_RING_SIZE 512
112 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
114 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
122 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
124 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
127 /* minimum number of free TX descriptors required to wake up TX process */
128 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
130 /* number of ETHTOOL_GSTATS u64's */
131 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
133 #define TG3_NUM_TEST 6
135 static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_MODULE_VERSION);
143 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144 module_param(tg3_debug, int, 0);
145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
147 static struct pci_device_id tg3_pci_tbl[] = {
148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
213 static const struct {
214 const char string[ETH_GSTRING_LEN];
215 } ethtool_stats_keys[TG3_NUM_STATS] = {
218 { "rx_ucast_packets" },
219 { "rx_mcast_packets" },
220 { "rx_bcast_packets" },
222 { "rx_align_errors" },
223 { "rx_xon_pause_rcvd" },
224 { "rx_xoff_pause_rcvd" },
225 { "rx_mac_ctrl_rcvd" },
226 { "rx_xoff_entered" },
227 { "rx_frame_too_long_errors" },
229 { "rx_undersize_packets" },
230 { "rx_in_length_errors" },
231 { "rx_out_length_errors" },
232 { "rx_64_or_less_octet_packets" },
233 { "rx_65_to_127_octet_packets" },
234 { "rx_128_to_255_octet_packets" },
235 { "rx_256_to_511_octet_packets" },
236 { "rx_512_to_1023_octet_packets" },
237 { "rx_1024_to_1522_octet_packets" },
238 { "rx_1523_to_2047_octet_packets" },
239 { "rx_2048_to_4095_octet_packets" },
240 { "rx_4096_to_8191_octet_packets" },
241 { "rx_8192_to_9022_octet_packets" },
248 { "tx_flow_control" },
250 { "tx_single_collisions" },
251 { "tx_mult_collisions" },
253 { "tx_excessive_collisions" },
254 { "tx_late_collisions" },
255 { "tx_collide_2times" },
256 { "tx_collide_3times" },
257 { "tx_collide_4times" },
258 { "tx_collide_5times" },
259 { "tx_collide_6times" },
260 { "tx_collide_7times" },
261 { "tx_collide_8times" },
262 { "tx_collide_9times" },
263 { "tx_collide_10times" },
264 { "tx_collide_11times" },
265 { "tx_collide_12times" },
266 { "tx_collide_13times" },
267 { "tx_collide_14times" },
268 { "tx_collide_15times" },
269 { "tx_ucast_packets" },
270 { "tx_mcast_packets" },
271 { "tx_bcast_packets" },
272 { "tx_carrier_sense_errors" },
276 { "dma_writeq_full" },
277 { "dma_write_prioq_full" },
281 { "rx_threshold_hit" },
283 { "dma_readq_full" },
284 { "dma_read_prioq_full" },
285 { "tx_comp_queue_full" },
287 { "ring_set_send_prod_index" },
288 { "ring_status_update" },
290 { "nic_avoided_irqs" },
291 { "nic_tx_threshold_hit" }
294 static const struct {
295 const char string[ETH_GSTRING_LEN];
296 } ethtool_test_keys[TG3_NUM_TEST] = {
297 { "nvram test (online) " },
298 { "link test (online) " },
299 { "register test (offline)" },
300 { "memory test (offline)" },
301 { "loopback test (offline)" },
302 { "interrupt test (offline)" },
305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
307 writel(val, tp->regs + off);
310 static u32 tg3_read32(struct tg3 *tp, u32 off)
312 return (readl(tp->regs + off));
315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
319 spin_lock_irqsave(&tp->indirect_lock, flags);
320 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
322 spin_unlock_irqrestore(&tp->indirect_lock, flags);
325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
327 writel(val, tp->regs + off);
328 readl(tp->regs + off);
331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
347 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349 TG3_64BIT_REG_LOW, val);
352 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354 TG3_64BIT_REG_LOW, val);
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
363 /* In indirect mode when disabling interrupts, we also need
364 * to clear the interrupt bit in the GRC local ctrl register.
366 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
368 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
378 spin_lock_irqsave(&tp->indirect_lock, flags);
379 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381 spin_unlock_irqrestore(&tp->indirect_lock, flags);
385 /* usec_wait specifies the wait time in usec when writing to certain registers
386 * where it is unsafe to read back the register without some delay.
387 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
392 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394 /* Non-posted methods */
395 tp->write32(tp, off, val);
398 tg3_write32(tp, off, val);
403 /* Wait again after the read for the posted method to guarantee that
404 * the wait time is met.
410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
412 tp->write32_mbox(tp, off, val);
413 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32_mbox(tp, off);
418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
420 void __iomem *mbox = tp->regs + off;
422 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
424 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
430 return (readl(tp->regs + off + GRCMBOX_BASE));
433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
435 writel(val, tp->regs + off + GRCMBOX_BASE);
438 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
439 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
440 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
441 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
442 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
444 #define tw32(reg,val) tp->write32(tp, reg, val)
445 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
447 #define tr32(reg) tp->read32(tp, reg)
449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
462 /* Always leave this as zero. */
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
465 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466 tw32_f(TG3PCI_MEM_WIN_DATA, val);
468 /* Always leave this as zero. */
469 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
471 spin_unlock_irqrestore(&tp->indirect_lock, flags);
474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
478 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
484 spin_lock_irqsave(&tp->indirect_lock, flags);
485 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
489 /* Always leave this as zero. */
490 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
492 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493 *val = tr32(TG3PCI_MEM_WIN_DATA);
495 /* Always leave this as zero. */
496 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
501 static void tg3_disable_ints(struct tg3 *tp)
503 tw32(TG3PCI_MISC_HOST_CTRL,
504 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
505 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
508 static inline void tg3_cond_int(struct tg3 *tp)
510 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511 (tp->hw_status->status & SD_STATUS_UPDATED))
512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
514 tw32(HOSTCC_MODE, tp->coalesce_mode |
515 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
518 static void tg3_enable_ints(struct tg3 *tp)
523 tw32(TG3PCI_MISC_HOST_CTRL,
524 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526 (tp->last_tag << 24));
527 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
533 static inline unsigned int tg3_has_work(struct tg3 *tp)
535 struct tg3_hw_status *sblk = tp->hw_status;
536 unsigned int work_exists = 0;
538 /* check for phy events */
539 if (!(tp->tg3_flags &
540 (TG3_FLAG_USE_LINKCHG_REG |
541 TG3_FLAG_POLL_SERDES))) {
542 if (sblk->status & SD_STATUS_LINK_CHG)
545 /* check for RX/TX work to do */
546 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
554 * similar to tg3_enable_ints, but it accurately determines whether there
555 * is new work pending and can return without flushing the PIO write
556 * which reenables interrupts
558 static void tg3_restart_ints(struct tg3 *tp)
560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
564 /* When doing tagged status, this work check is unnecessary.
565 * The last_tag we write above tells the chip which piece of
566 * work we've completed.
568 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
570 tw32(HOSTCC_MODE, tp->coalesce_mode |
571 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
574 static inline void tg3_netif_stop(struct tg3 *tp)
576 tp->dev->trans_start = jiffies; /* prevent tx timeout */
577 napi_disable(&tp->napi);
578 netif_tx_disable(tp->dev);
581 static inline void tg3_netif_start(struct tg3 *tp)
583 netif_wake_queue(tp->dev);
584 /* NOTE: unconditional netif_wake_queue is only appropriate
585 * so long as all callers are assured to have free tx slots
586 * (such as after tg3_init_hw)
588 napi_enable(&tp->napi);
589 tp->hw_status->status |= SD_STATUS_UPDATED;
593 static void tg3_switch_clocks(struct tg3 *tp)
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
601 orig_clock_ctrl = clock_ctrl;
602 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603 CLOCK_CTRL_CLKRUN_OENABLE |
605 tp->pci_clock_ctrl = clock_ctrl;
607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
609 tw32_wait_f(TG3PCI_CLOCK_CTRL,
610 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
612 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
613 tw32_wait_f(TG3PCI_CLOCK_CTRL,
615 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618 clock_ctrl | (CLOCK_CTRL_ALTCLK),
621 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
624 #define PHY_BUSY_LOOPS 5000
626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
632 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
634 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
640 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641 MI_COM_PHY_ADDR_MASK);
642 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643 MI_COM_REG_ADDR_MASK);
644 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
646 tw32_f(MAC_MI_COM, frame_val);
648 loops = PHY_BUSY_LOOPS;
651 frame_val = tr32(MAC_MI_COM);
653 if ((frame_val & MI_COM_BUSY) == 0) {
655 frame_val = tr32(MAC_MI_COM);
663 *val = frame_val & MI_COM_DATA_MASK;
667 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668 tw32_f(MAC_MI_MODE, tp->mi_mode);
675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
685 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
687 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
691 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692 MI_COM_PHY_ADDR_MASK);
693 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694 MI_COM_REG_ADDR_MASK);
695 frame_val |= (val & MI_COM_DATA_MASK);
696 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
698 tw32_f(MAC_MI_COM, frame_val);
700 loops = PHY_BUSY_LOOPS;
703 frame_val = tr32(MAC_MI_COM);
704 if ((frame_val & MI_COM_BUSY) == 0) {
706 frame_val = tr32(MAC_MI_COM);
716 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 tw32_f(MAC_MI_MODE, tp->mi_mode);
724 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
728 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
729 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
735 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
736 tg3_writephy(tp, MII_TG3_EPHY_TEST,
737 ephy | MII_TG3_EPHY_SHADOW_EN);
738 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
740 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
742 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
743 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
745 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
748 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
749 MII_TG3_AUXCTL_SHDWSEL_MISC;
750 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
751 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
753 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
755 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
756 phy |= MII_TG3_AUXCTL_MISC_WREN;
757 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
762 static void tg3_phy_set_wirespeed(struct tg3 *tp)
766 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
769 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
770 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
771 tg3_writephy(tp, MII_TG3_AUX_CTRL,
772 (val | (1 << 15) | (1 << 4)));
775 static int tg3_bmcr_reset(struct tg3 *tp)
780 /* OK, reset it, and poll the BMCR_RESET bit until it
781 * clears or we time out.
783 phy_control = BMCR_RESET;
784 err = tg3_writephy(tp, MII_BMCR, phy_control);
790 err = tg3_readphy(tp, MII_BMCR, &phy_control);
794 if ((phy_control & BMCR_RESET) == 0) {
806 static int tg3_wait_macro_done(struct tg3 *tp)
813 if (!tg3_readphy(tp, 0x16, &tmp32)) {
814 if ((tmp32 & 0x1000) == 0)
824 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
826 static const u32 test_pat[4][6] = {
827 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
828 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
829 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
830 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
834 for (chan = 0; chan < 4; chan++) {
837 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
838 (chan * 0x2000) | 0x0200);
839 tg3_writephy(tp, 0x16, 0x0002);
841 for (i = 0; i < 6; i++)
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
845 tg3_writephy(tp, 0x16, 0x0202);
846 if (tg3_wait_macro_done(tp)) {
851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
852 (chan * 0x2000) | 0x0200);
853 tg3_writephy(tp, 0x16, 0x0082);
854 if (tg3_wait_macro_done(tp)) {
859 tg3_writephy(tp, 0x16, 0x0802);
860 if (tg3_wait_macro_done(tp)) {
865 for (i = 0; i < 6; i += 2) {
868 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
869 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
870 tg3_wait_macro_done(tp)) {
876 if (low != test_pat[chan][i] ||
877 high != test_pat[chan][i+1]) {
878 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
880 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
890 static int tg3_phy_reset_chanpat(struct tg3 *tp)
894 for (chan = 0; chan < 4; chan++) {
897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
898 (chan * 0x2000) | 0x0200);
899 tg3_writephy(tp, 0x16, 0x0002);
900 for (i = 0; i < 6; i++)
901 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
902 tg3_writephy(tp, 0x16, 0x0202);
903 if (tg3_wait_macro_done(tp))
910 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
912 u32 reg32, phy9_orig;
913 int retries, do_phy_reset, err;
919 err = tg3_bmcr_reset(tp);
925 /* Disable transmitter and interrupt. */
926 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
930 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
932 /* Set full-duplex, 1000 mbps. */
933 tg3_writephy(tp, MII_BMCR,
934 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
936 /* Set to master mode. */
937 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
940 tg3_writephy(tp, MII_TG3_CTRL,
941 (MII_TG3_CTRL_AS_MASTER |
942 MII_TG3_CTRL_ENABLE_AS_MASTER));
944 /* Enable SM_DSP_CLOCK and 6dB. */
945 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
947 /* Block the PHY control access. */
948 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
949 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
951 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
956 err = tg3_phy_reset_chanpat(tp);
960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
963 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
964 tg3_writephy(tp, 0x16, 0x0000);
966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
968 /* Set Extended packet length bit for jumbo frames */
969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
975 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
977 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
979 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
986 static void tg3_link_report(struct tg3 *);
988 /* This will reset the tigon3 PHY if there is no valid
989 * link unless the FORCE argument is non-zero.
991 static int tg3_phy_reset(struct tg3 *tp)
996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
999 val = tr32(GRC_MISC_CFG);
1000 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1003 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1004 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1008 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1009 netif_carrier_off(tp->dev);
1010 tg3_link_report(tp);
1013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1016 err = tg3_phy_reset_5703_4_5(tp);
1022 err = tg3_bmcr_reset(tp);
1027 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1028 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1029 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1030 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1031 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1032 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1033 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1035 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1036 tg3_writephy(tp, 0x1c, 0x8d68);
1037 tg3_writephy(tp, 0x1c, 0x8d68);
1039 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1040 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1041 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1042 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1044 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1045 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1046 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1047 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1049 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1050 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1051 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1052 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1053 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1054 tg3_writephy(tp, MII_TG3_TEST1,
1055 MII_TG3_TEST1_TRIM_EN | 0x4);
1057 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1058 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1060 /* Set Extended packet length bit (bit 14) on all chips that */
1061 /* support jumbo frames */
1062 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1063 /* Cannot do read-modify-write on 5401 */
1064 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1065 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1068 /* Set bit 14 with read-modify-write to preserve other bits */
1069 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1070 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1071 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1074 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1075 * jumbo frames transmission.
1077 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1080 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1081 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1082 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1086 /* adjust output voltage */
1087 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1090 tg3_phy_toggle_automdix(tp, 1);
1091 tg3_phy_set_wirespeed(tp);
1095 static void tg3_frob_aux_power(struct tg3 *tp)
1097 struct tg3 *tp_peer = tp;
1099 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1102 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1103 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1104 struct net_device *dev_peer;
1106 dev_peer = pci_get_drvdata(tp->pdev_peer);
1107 /* remove_one() may have been run on the peer. */
1111 tp_peer = netdev_priv(dev_peer);
1114 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1115 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1116 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1117 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1119 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1120 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1121 (GRC_LCLCTRL_GPIO_OE0 |
1122 GRC_LCLCTRL_GPIO_OE1 |
1123 GRC_LCLCTRL_GPIO_OE2 |
1124 GRC_LCLCTRL_GPIO_OUTPUT0 |
1125 GRC_LCLCTRL_GPIO_OUTPUT1),
1129 u32 grc_local_ctrl = 0;
1131 if (tp_peer != tp &&
1132 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1135 /* Workaround to prevent overdrawing Amps. */
1136 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1138 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1140 grc_local_ctrl, 100);
1143 /* On 5753 and variants, GPIO2 cannot be used. */
1144 no_gpio2 = tp->nic_sram_data_cfg &
1145 NIC_SRAM_DATA_CFG_NO_GPIO2;
1147 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1148 GRC_LCLCTRL_GPIO_OE1 |
1149 GRC_LCLCTRL_GPIO_OE2 |
1150 GRC_LCLCTRL_GPIO_OUTPUT1 |
1151 GRC_LCLCTRL_GPIO_OUTPUT2;
1153 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1154 GRC_LCLCTRL_GPIO_OUTPUT2);
1156 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1157 grc_local_ctrl, 100);
1159 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1161 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1162 grc_local_ctrl, 100);
1165 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1166 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1167 grc_local_ctrl, 100);
1171 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1172 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1173 if (tp_peer != tp &&
1174 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1177 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1178 (GRC_LCLCTRL_GPIO_OE1 |
1179 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1181 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1182 GRC_LCLCTRL_GPIO_OE1, 100);
1184 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1185 (GRC_LCLCTRL_GPIO_OE1 |
1186 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1191 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1193 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1195 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1196 if (speed != SPEED_10)
1198 } else if (speed == SPEED_10)
1204 static int tg3_setup_phy(struct tg3 *, int);
1206 #define RESET_KIND_SHUTDOWN 0
1207 #define RESET_KIND_INIT 1
1208 #define RESET_KIND_SUSPEND 2
1210 static void tg3_write_sig_post_reset(struct tg3 *, int);
1211 static int tg3_halt_cpu(struct tg3 *, u32);
1212 static int tg3_nvram_lock(struct tg3 *);
1213 static void tg3_nvram_unlock(struct tg3 *);
1215 static void tg3_power_down_phy(struct tg3 *tp)
1217 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1219 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1220 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1223 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1224 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1225 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1230 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1234 val = tr32(GRC_MISC_CFG);
1235 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1239 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1240 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1241 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1244 /* The PHY should not be powered down on some chips because
1247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1249 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1250 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1252 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1255 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1258 u16 power_control, power_caps;
1259 int pm = tp->pm_cap;
1261 /* Make sure register accesses (indirect or otherwise)
1262 * will function correctly.
1264 pci_write_config_dword(tp->pdev,
1265 TG3PCI_MISC_HOST_CTRL,
1266 tp->misc_host_ctrl);
1268 pci_read_config_word(tp->pdev,
1271 power_control |= PCI_PM_CTRL_PME_STATUS;
1272 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1276 pci_write_config_word(tp->pdev,
1279 udelay(100); /* Delay after power state change */
1281 /* Switch out of Vaux if it is a NIC */
1282 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1283 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1300 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1302 tp->dev->name, state);
1306 power_control |= PCI_PM_CTRL_PME_ENABLE;
1308 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1309 tw32(TG3PCI_MISC_HOST_CTRL,
1310 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1312 if (tp->link_config.phy_is_low_power == 0) {
1313 tp->link_config.phy_is_low_power = 1;
1314 tp->link_config.orig_speed = tp->link_config.speed;
1315 tp->link_config.orig_duplex = tp->link_config.duplex;
1316 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1319 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1320 tp->link_config.speed = SPEED_10;
1321 tp->link_config.duplex = DUPLEX_HALF;
1322 tp->link_config.autoneg = AUTONEG_ENABLE;
1323 tg3_setup_phy(tp, 0);
1326 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1329 val = tr32(GRC_VCPU_EXT_CTRL);
1330 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1331 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1335 for (i = 0; i < 200; i++) {
1336 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1337 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1342 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1343 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1344 WOL_DRV_STATE_SHUTDOWN |
1348 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1350 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1353 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1354 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1357 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1358 mac_mode = MAC_MODE_PORT_MODE_GMII;
1360 mac_mode = MAC_MODE_PORT_MODE_MII;
1362 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1363 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1365 u32 speed = (tp->tg3_flags &
1366 TG3_FLAG_WOL_SPEED_100MB) ?
1367 SPEED_100 : SPEED_10;
1368 if (tg3_5700_link_polarity(tp, speed))
1369 mac_mode |= MAC_MODE_LINK_POLARITY;
1371 mac_mode &= ~MAC_MODE_LINK_POLARITY;
1374 mac_mode = MAC_MODE_PORT_MODE_TBI;
1377 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1378 tw32(MAC_LED_CTRL, tp->led_ctrl);
1380 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1381 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1382 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1384 tw32_f(MAC_MODE, mac_mode);
1387 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1391 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1392 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1393 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1396 base_val = tp->pci_clock_ctrl;
1397 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1398 CLOCK_CTRL_TXCLK_DISABLE);
1400 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1401 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1402 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1403 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1405 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1406 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1407 u32 newbits1, newbits2;
1409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1411 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1412 CLOCK_CTRL_TXCLK_DISABLE |
1414 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1415 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1416 newbits1 = CLOCK_CTRL_625_CORE;
1417 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1419 newbits1 = CLOCK_CTRL_ALTCLK;
1420 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1423 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1426 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1429 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1432 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1433 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1434 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1435 CLOCK_CTRL_TXCLK_DISABLE |
1436 CLOCK_CTRL_44MHZ_CORE);
1438 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1441 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1442 tp->pci_clock_ctrl | newbits3, 40);
1446 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1447 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1448 tg3_power_down_phy(tp);
1450 tg3_frob_aux_power(tp);
1452 /* Workaround for unstable PLL clock */
1453 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1454 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1455 u32 val = tr32(0x7d00);
1457 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1459 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1462 err = tg3_nvram_lock(tp);
1463 tg3_halt_cpu(tp, RX_CPU_BASE);
1465 tg3_nvram_unlock(tp);
1469 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1471 /* Finally, set the new power state. */
1472 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1473 udelay(100); /* Delay after power state change */
1478 static void tg3_link_report(struct tg3 *tp)
1480 if (!netif_carrier_ok(tp->dev)) {
1481 if (netif_msg_link(tp))
1482 printk(KERN_INFO PFX "%s: Link is down.\n",
1484 } else if (netif_msg_link(tp)) {
1485 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1487 (tp->link_config.active_speed == SPEED_1000 ?
1489 (tp->link_config.active_speed == SPEED_100 ?
1491 (tp->link_config.active_duplex == DUPLEX_FULL ?
1494 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1497 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1498 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1502 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1504 u32 new_tg3_flags = 0;
1505 u32 old_rx_mode = tp->rx_mode;
1506 u32 old_tx_mode = tp->tx_mode;
1508 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1510 /* Convert 1000BaseX flow control bits to 1000BaseT
1511 * bits before resolving flow control.
1513 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1514 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1515 ADVERTISE_PAUSE_ASYM);
1516 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1518 if (local_adv & ADVERTISE_1000XPAUSE)
1519 local_adv |= ADVERTISE_PAUSE_CAP;
1520 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1521 local_adv |= ADVERTISE_PAUSE_ASYM;
1522 if (remote_adv & LPA_1000XPAUSE)
1523 remote_adv |= LPA_PAUSE_CAP;
1524 if (remote_adv & LPA_1000XPAUSE_ASYM)
1525 remote_adv |= LPA_PAUSE_ASYM;
1528 if (local_adv & ADVERTISE_PAUSE_CAP) {
1529 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1530 if (remote_adv & LPA_PAUSE_CAP)
1532 (TG3_FLAG_RX_PAUSE |
1534 else if (remote_adv & LPA_PAUSE_ASYM)
1536 (TG3_FLAG_RX_PAUSE);
1538 if (remote_adv & LPA_PAUSE_CAP)
1540 (TG3_FLAG_RX_PAUSE |
1543 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1544 if ((remote_adv & LPA_PAUSE_CAP) &&
1545 (remote_adv & LPA_PAUSE_ASYM))
1546 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1549 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1550 tp->tg3_flags |= new_tg3_flags;
1552 new_tg3_flags = tp->tg3_flags;
1555 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1556 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1558 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1560 if (old_rx_mode != tp->rx_mode) {
1561 tw32_f(MAC_RX_MODE, tp->rx_mode);
1564 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1565 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1567 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1569 if (old_tx_mode != tp->tx_mode) {
1570 tw32_f(MAC_TX_MODE, tp->tx_mode);
1574 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1576 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1577 case MII_TG3_AUX_STAT_10HALF:
1579 *duplex = DUPLEX_HALF;
1582 case MII_TG3_AUX_STAT_10FULL:
1584 *duplex = DUPLEX_FULL;
1587 case MII_TG3_AUX_STAT_100HALF:
1589 *duplex = DUPLEX_HALF;
1592 case MII_TG3_AUX_STAT_100FULL:
1594 *duplex = DUPLEX_FULL;
1597 case MII_TG3_AUX_STAT_1000HALF:
1598 *speed = SPEED_1000;
1599 *duplex = DUPLEX_HALF;
1602 case MII_TG3_AUX_STAT_1000FULL:
1603 *speed = SPEED_1000;
1604 *duplex = DUPLEX_FULL;
1608 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1609 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1611 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1615 *speed = SPEED_INVALID;
1616 *duplex = DUPLEX_INVALID;
1621 static void tg3_phy_copper_begin(struct tg3 *tp)
1626 if (tp->link_config.phy_is_low_power) {
1627 /* Entering low power mode. Disable gigabit and
1628 * 100baseT advertisements.
1630 tg3_writephy(tp, MII_TG3_CTRL, 0);
1632 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1633 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1634 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1635 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1637 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1638 } else if (tp->link_config.speed == SPEED_INVALID) {
1639 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1640 tp->link_config.advertising &=
1641 ~(ADVERTISED_1000baseT_Half |
1642 ADVERTISED_1000baseT_Full);
1644 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1645 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1646 new_adv |= ADVERTISE_10HALF;
1647 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1648 new_adv |= ADVERTISE_10FULL;
1649 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1650 new_adv |= ADVERTISE_100HALF;
1651 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1652 new_adv |= ADVERTISE_100FULL;
1653 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1655 if (tp->link_config.advertising &
1656 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1658 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1659 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1660 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1661 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1662 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1663 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1664 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1665 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1666 MII_TG3_CTRL_ENABLE_AS_MASTER);
1667 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1669 tg3_writephy(tp, MII_TG3_CTRL, 0);
1672 /* Asking for a specific link mode. */
1673 if (tp->link_config.speed == SPEED_1000) {
1674 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1675 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1677 if (tp->link_config.duplex == DUPLEX_FULL)
1678 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1680 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1681 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1682 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1683 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1684 MII_TG3_CTRL_ENABLE_AS_MASTER);
1685 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1687 tg3_writephy(tp, MII_TG3_CTRL, 0);
1689 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1690 if (tp->link_config.speed == SPEED_100) {
1691 if (tp->link_config.duplex == DUPLEX_FULL)
1692 new_adv |= ADVERTISE_100FULL;
1694 new_adv |= ADVERTISE_100HALF;
1696 if (tp->link_config.duplex == DUPLEX_FULL)
1697 new_adv |= ADVERTISE_10FULL;
1699 new_adv |= ADVERTISE_10HALF;
1701 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1705 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1706 tp->link_config.speed != SPEED_INVALID) {
1707 u32 bmcr, orig_bmcr;
1709 tp->link_config.active_speed = tp->link_config.speed;
1710 tp->link_config.active_duplex = tp->link_config.duplex;
1713 switch (tp->link_config.speed) {
1719 bmcr |= BMCR_SPEED100;
1723 bmcr |= TG3_BMCR_SPEED1000;
1727 if (tp->link_config.duplex == DUPLEX_FULL)
1728 bmcr |= BMCR_FULLDPLX;
1730 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1731 (bmcr != orig_bmcr)) {
1732 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1733 for (i = 0; i < 1500; i++) {
1737 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1738 tg3_readphy(tp, MII_BMSR, &tmp))
1740 if (!(tmp & BMSR_LSTATUS)) {
1745 tg3_writephy(tp, MII_BMCR, bmcr);
1749 tg3_writephy(tp, MII_BMCR,
1750 BMCR_ANENABLE | BMCR_ANRESTART);
1754 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1758 /* Turn off tap power management. */
1759 /* Set Extended packet length bit */
1760 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1762 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1763 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1765 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1766 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1768 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1769 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1771 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1772 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1774 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1775 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1782 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1784 u32 adv_reg, all_mask = 0;
1786 if (mask & ADVERTISED_10baseT_Half)
1787 all_mask |= ADVERTISE_10HALF;
1788 if (mask & ADVERTISED_10baseT_Full)
1789 all_mask |= ADVERTISE_10FULL;
1790 if (mask & ADVERTISED_100baseT_Half)
1791 all_mask |= ADVERTISE_100HALF;
1792 if (mask & ADVERTISED_100baseT_Full)
1793 all_mask |= ADVERTISE_100FULL;
1795 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1798 if ((adv_reg & all_mask) != all_mask)
1800 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1804 if (mask & ADVERTISED_1000baseT_Half)
1805 all_mask |= ADVERTISE_1000HALF;
1806 if (mask & ADVERTISED_1000baseT_Full)
1807 all_mask |= ADVERTISE_1000FULL;
1809 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1812 if ((tg3_ctrl & all_mask) != all_mask)
1818 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1820 int current_link_up;
1829 (MAC_STATUS_SYNC_CHANGED |
1830 MAC_STATUS_CFG_CHANGED |
1831 MAC_STATUS_MI_COMPLETION |
1832 MAC_STATUS_LNKSTATE_CHANGED));
1835 tp->mi_mode = MAC_MI_MODE_BASE;
1836 tw32_f(MAC_MI_MODE, tp->mi_mode);
1839 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1841 /* Some third-party PHYs need to be reset on link going
1844 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1847 netif_carrier_ok(tp->dev)) {
1848 tg3_readphy(tp, MII_BMSR, &bmsr);
1849 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1850 !(bmsr & BMSR_LSTATUS))
1856 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1857 tg3_readphy(tp, MII_BMSR, &bmsr);
1858 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1859 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1862 if (!(bmsr & BMSR_LSTATUS)) {
1863 err = tg3_init_5401phy_dsp(tp);
1867 tg3_readphy(tp, MII_BMSR, &bmsr);
1868 for (i = 0; i < 1000; i++) {
1870 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1871 (bmsr & BMSR_LSTATUS)) {
1877 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1878 !(bmsr & BMSR_LSTATUS) &&
1879 tp->link_config.active_speed == SPEED_1000) {
1880 err = tg3_phy_reset(tp);
1882 err = tg3_init_5401phy_dsp(tp);
1887 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1888 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1889 /* 5701 {A0,B0} CRC bug workaround */
1890 tg3_writephy(tp, 0x15, 0x0a75);
1891 tg3_writephy(tp, 0x1c, 0x8c68);
1892 tg3_writephy(tp, 0x1c, 0x8d68);
1893 tg3_writephy(tp, 0x1c, 0x8c68);
1896 /* Clear pending interrupts... */
1897 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1898 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1900 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1901 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1902 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1903 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1907 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1908 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1909 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1911 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1914 current_link_up = 0;
1915 current_speed = SPEED_INVALID;
1916 current_duplex = DUPLEX_INVALID;
1918 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1921 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1922 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1923 if (!(val & (1 << 10))) {
1925 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1931 for (i = 0; i < 100; i++) {
1932 tg3_readphy(tp, MII_BMSR, &bmsr);
1933 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1934 (bmsr & BMSR_LSTATUS))
1939 if (bmsr & BMSR_LSTATUS) {
1942 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1943 for (i = 0; i < 2000; i++) {
1945 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1950 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1955 for (i = 0; i < 200; i++) {
1956 tg3_readphy(tp, MII_BMCR, &bmcr);
1957 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1959 if (bmcr && bmcr != 0x7fff)
1964 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1965 if (bmcr & BMCR_ANENABLE) {
1966 current_link_up = 1;
1968 /* Force autoneg restart if we are exiting
1971 if (!tg3_copper_is_advertising_all(tp,
1972 tp->link_config.advertising))
1973 current_link_up = 0;
1975 current_link_up = 0;
1978 if (!(bmcr & BMCR_ANENABLE) &&
1979 tp->link_config.speed == current_speed &&
1980 tp->link_config.duplex == current_duplex) {
1981 current_link_up = 1;
1983 current_link_up = 0;
1987 tp->link_config.active_speed = current_speed;
1988 tp->link_config.active_duplex = current_duplex;
1991 if (current_link_up == 1 &&
1992 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1993 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1994 u32 local_adv, remote_adv;
1996 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1998 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2000 if (tg3_readphy(tp, MII_LPA, &remote_adv))
2003 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
2005 /* If we are not advertising full pause capability,
2006 * something is wrong. Bring the link down and reconfigure.
2008 if (local_adv != ADVERTISE_PAUSE_CAP) {
2009 current_link_up = 0;
2011 tg3_setup_flow_control(tp, local_adv, remote_adv);
2015 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2018 tg3_phy_copper_begin(tp);
2020 tg3_readphy(tp, MII_BMSR, &tmp);
2021 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2022 (tmp & BMSR_LSTATUS))
2023 current_link_up = 1;
2026 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2027 if (current_link_up == 1) {
2028 if (tp->link_config.active_speed == SPEED_100 ||
2029 tp->link_config.active_speed == SPEED_10)
2030 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2032 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2034 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2036 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2037 if (tp->link_config.active_duplex == DUPLEX_HALF)
2038 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2041 if (current_link_up == 1 &&
2042 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2043 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2045 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2048 /* ??? Without this setting Netgear GA302T PHY does not
2049 * ??? send/receive packets...
2051 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2052 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2053 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2054 tw32_f(MAC_MI_MODE, tp->mi_mode);
2058 tw32_f(MAC_MODE, tp->mac_mode);
2061 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2062 /* Polled via timer. */
2063 tw32_f(MAC_EVENT, 0);
2065 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2070 current_link_up == 1 &&
2071 tp->link_config.active_speed == SPEED_1000 &&
2072 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2073 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2076 (MAC_STATUS_SYNC_CHANGED |
2077 MAC_STATUS_CFG_CHANGED));
2080 NIC_SRAM_FIRMWARE_MBOX,
2081 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2084 if (current_link_up != netif_carrier_ok(tp->dev)) {
2085 if (current_link_up)
2086 netif_carrier_on(tp->dev);
2088 netif_carrier_off(tp->dev);
2089 tg3_link_report(tp);
2095 struct tg3_fiber_aneginfo {
2097 #define ANEG_STATE_UNKNOWN 0
2098 #define ANEG_STATE_AN_ENABLE 1
2099 #define ANEG_STATE_RESTART_INIT 2
2100 #define ANEG_STATE_RESTART 3
2101 #define ANEG_STATE_DISABLE_LINK_OK 4
2102 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2103 #define ANEG_STATE_ABILITY_DETECT 6
2104 #define ANEG_STATE_ACK_DETECT_INIT 7
2105 #define ANEG_STATE_ACK_DETECT 8
2106 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2107 #define ANEG_STATE_COMPLETE_ACK 10
2108 #define ANEG_STATE_IDLE_DETECT_INIT 11
2109 #define ANEG_STATE_IDLE_DETECT 12
2110 #define ANEG_STATE_LINK_OK 13
2111 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2112 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2115 #define MR_AN_ENABLE 0x00000001
2116 #define MR_RESTART_AN 0x00000002
2117 #define MR_AN_COMPLETE 0x00000004
2118 #define MR_PAGE_RX 0x00000008
2119 #define MR_NP_LOADED 0x00000010
2120 #define MR_TOGGLE_TX 0x00000020
2121 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2122 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2123 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2124 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2125 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2126 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2127 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2128 #define MR_TOGGLE_RX 0x00002000
2129 #define MR_NP_RX 0x00004000
2131 #define MR_LINK_OK 0x80000000
2133 unsigned long link_time, cur_time;
2135 u32 ability_match_cfg;
2136 int ability_match_count;
2138 char ability_match, idle_match, ack_match;
2140 u32 txconfig, rxconfig;
2141 #define ANEG_CFG_NP 0x00000080
2142 #define ANEG_CFG_ACK 0x00000040
2143 #define ANEG_CFG_RF2 0x00000020
2144 #define ANEG_CFG_RF1 0x00000010
2145 #define ANEG_CFG_PS2 0x00000001
2146 #define ANEG_CFG_PS1 0x00008000
2147 #define ANEG_CFG_HD 0x00004000
2148 #define ANEG_CFG_FD 0x00002000
2149 #define ANEG_CFG_INVAL 0x00001f06
2154 #define ANEG_TIMER_ENAB 2
2155 #define ANEG_FAILED -1
2157 #define ANEG_STATE_SETTLE_TIME 10000
2159 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2160 struct tg3_fiber_aneginfo *ap)
2162 unsigned long delta;
2166 if (ap->state == ANEG_STATE_UNKNOWN) {
2170 ap->ability_match_cfg = 0;
2171 ap->ability_match_count = 0;
2172 ap->ability_match = 0;
2178 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2179 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2181 if (rx_cfg_reg != ap->ability_match_cfg) {
2182 ap->ability_match_cfg = rx_cfg_reg;
2183 ap->ability_match = 0;
2184 ap->ability_match_count = 0;
2186 if (++ap->ability_match_count > 1) {
2187 ap->ability_match = 1;
2188 ap->ability_match_cfg = rx_cfg_reg;
2191 if (rx_cfg_reg & ANEG_CFG_ACK)
2199 ap->ability_match_cfg = 0;
2200 ap->ability_match_count = 0;
2201 ap->ability_match = 0;
2207 ap->rxconfig = rx_cfg_reg;
2211 case ANEG_STATE_UNKNOWN:
2212 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2213 ap->state = ANEG_STATE_AN_ENABLE;
2216 case ANEG_STATE_AN_ENABLE:
2217 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2218 if (ap->flags & MR_AN_ENABLE) {
2221 ap->ability_match_cfg = 0;
2222 ap->ability_match_count = 0;
2223 ap->ability_match = 0;
2227 ap->state = ANEG_STATE_RESTART_INIT;
2229 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2233 case ANEG_STATE_RESTART_INIT:
2234 ap->link_time = ap->cur_time;
2235 ap->flags &= ~(MR_NP_LOADED);
2237 tw32(MAC_TX_AUTO_NEG, 0);
2238 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2239 tw32_f(MAC_MODE, tp->mac_mode);
2242 ret = ANEG_TIMER_ENAB;
2243 ap->state = ANEG_STATE_RESTART;
2246 case ANEG_STATE_RESTART:
2247 delta = ap->cur_time - ap->link_time;
2248 if (delta > ANEG_STATE_SETTLE_TIME) {
2249 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2251 ret = ANEG_TIMER_ENAB;
2255 case ANEG_STATE_DISABLE_LINK_OK:
2259 case ANEG_STATE_ABILITY_DETECT_INIT:
2260 ap->flags &= ~(MR_TOGGLE_TX);
2261 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2262 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2263 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2264 tw32_f(MAC_MODE, tp->mac_mode);
2267 ap->state = ANEG_STATE_ABILITY_DETECT;
2270 case ANEG_STATE_ABILITY_DETECT:
2271 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2272 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2276 case ANEG_STATE_ACK_DETECT_INIT:
2277 ap->txconfig |= ANEG_CFG_ACK;
2278 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2279 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2280 tw32_f(MAC_MODE, tp->mac_mode);
2283 ap->state = ANEG_STATE_ACK_DETECT;
2286 case ANEG_STATE_ACK_DETECT:
2287 if (ap->ack_match != 0) {
2288 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2289 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2290 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2292 ap->state = ANEG_STATE_AN_ENABLE;
2294 } else if (ap->ability_match != 0 &&
2295 ap->rxconfig == 0) {
2296 ap->state = ANEG_STATE_AN_ENABLE;
2300 case ANEG_STATE_COMPLETE_ACK_INIT:
2301 if (ap->rxconfig & ANEG_CFG_INVAL) {
2305 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2306 MR_LP_ADV_HALF_DUPLEX |
2307 MR_LP_ADV_SYM_PAUSE |
2308 MR_LP_ADV_ASYM_PAUSE |
2309 MR_LP_ADV_REMOTE_FAULT1 |
2310 MR_LP_ADV_REMOTE_FAULT2 |
2311 MR_LP_ADV_NEXT_PAGE |
2314 if (ap->rxconfig & ANEG_CFG_FD)
2315 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2316 if (ap->rxconfig & ANEG_CFG_HD)
2317 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2318 if (ap->rxconfig & ANEG_CFG_PS1)
2319 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2320 if (ap->rxconfig & ANEG_CFG_PS2)
2321 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2322 if (ap->rxconfig & ANEG_CFG_RF1)
2323 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2324 if (ap->rxconfig & ANEG_CFG_RF2)
2325 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2326 if (ap->rxconfig & ANEG_CFG_NP)
2327 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2329 ap->link_time = ap->cur_time;
2331 ap->flags ^= (MR_TOGGLE_TX);
2332 if (ap->rxconfig & 0x0008)
2333 ap->flags |= MR_TOGGLE_RX;
2334 if (ap->rxconfig & ANEG_CFG_NP)
2335 ap->flags |= MR_NP_RX;
2336 ap->flags |= MR_PAGE_RX;
2338 ap->state = ANEG_STATE_COMPLETE_ACK;
2339 ret = ANEG_TIMER_ENAB;
2342 case ANEG_STATE_COMPLETE_ACK:
2343 if (ap->ability_match != 0 &&
2344 ap->rxconfig == 0) {
2345 ap->state = ANEG_STATE_AN_ENABLE;
2348 delta = ap->cur_time - ap->link_time;
2349 if (delta > ANEG_STATE_SETTLE_TIME) {
2350 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2351 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2353 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2354 !(ap->flags & MR_NP_RX)) {
2355 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2363 case ANEG_STATE_IDLE_DETECT_INIT:
2364 ap->link_time = ap->cur_time;
2365 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2366 tw32_f(MAC_MODE, tp->mac_mode);
2369 ap->state = ANEG_STATE_IDLE_DETECT;
2370 ret = ANEG_TIMER_ENAB;
2373 case ANEG_STATE_IDLE_DETECT:
2374 if (ap->ability_match != 0 &&
2375 ap->rxconfig == 0) {
2376 ap->state = ANEG_STATE_AN_ENABLE;
2379 delta = ap->cur_time - ap->link_time;
2380 if (delta > ANEG_STATE_SETTLE_TIME) {
2381 /* XXX another gem from the Broadcom driver :( */
2382 ap->state = ANEG_STATE_LINK_OK;
2386 case ANEG_STATE_LINK_OK:
2387 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2391 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2392 /* ??? unimplemented */
2395 case ANEG_STATE_NEXT_PAGE_WAIT:
2396 /* ??? unimplemented */
2407 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2410 struct tg3_fiber_aneginfo aninfo;
2411 int status = ANEG_FAILED;
2415 tw32_f(MAC_TX_AUTO_NEG, 0);
2417 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2418 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2421 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2424 memset(&aninfo, 0, sizeof(aninfo));
2425 aninfo.flags |= MR_AN_ENABLE;
2426 aninfo.state = ANEG_STATE_UNKNOWN;
2427 aninfo.cur_time = 0;
2429 while (++tick < 195000) {
2430 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2431 if (status == ANEG_DONE || status == ANEG_FAILED)
2437 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2438 tw32_f(MAC_MODE, tp->mac_mode);
2441 *flags = aninfo.flags;
2443 if (status == ANEG_DONE &&
2444 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2445 MR_LP_ADV_FULL_DUPLEX)))
2451 static void tg3_init_bcm8002(struct tg3 *tp)
2453 u32 mac_status = tr32(MAC_STATUS);
2456 /* Reset when initting first time or we have a link. */
2457 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2458 !(mac_status & MAC_STATUS_PCS_SYNCED))
2461 /* Set PLL lock range. */
2462 tg3_writephy(tp, 0x16, 0x8007);
2465 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2467 /* Wait for reset to complete. */
2468 /* XXX schedule_timeout() ... */
2469 for (i = 0; i < 500; i++)
2472 /* Config mode; select PMA/Ch 1 regs. */
2473 tg3_writephy(tp, 0x10, 0x8411);
2475 /* Enable auto-lock and comdet, select txclk for tx. */
2476 tg3_writephy(tp, 0x11, 0x0a10);
2478 tg3_writephy(tp, 0x18, 0x00a0);
2479 tg3_writephy(tp, 0x16, 0x41ff);
2481 /* Assert and deassert POR. */
2482 tg3_writephy(tp, 0x13, 0x0400);
2484 tg3_writephy(tp, 0x13, 0x0000);
2486 tg3_writephy(tp, 0x11, 0x0a50);
2488 tg3_writephy(tp, 0x11, 0x0a10);
2490 /* Wait for signal to stabilize */
2491 /* XXX schedule_timeout() ... */
2492 for (i = 0; i < 15000; i++)
2495 /* Deselect the channel register so we can read the PHYID
2498 tg3_writephy(tp, 0x10, 0x8011);
2501 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2503 u32 sg_dig_ctrl, sg_dig_status;
2504 u32 serdes_cfg, expected_sg_dig_ctrl;
2505 int workaround, port_a;
2506 int current_link_up;
2509 expected_sg_dig_ctrl = 0;
2512 current_link_up = 0;
2514 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2515 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2517 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2520 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2521 /* preserve bits 20-23 for voltage regulator */
2522 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2525 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2527 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2528 if (sg_dig_ctrl & (1 << 31)) {
2530 u32 val = serdes_cfg;
2536 tw32_f(MAC_SERDES_CFG, val);
2538 tw32_f(SG_DIG_CTRL, 0x01388400);
2540 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2541 tg3_setup_flow_control(tp, 0, 0);
2542 current_link_up = 1;
2547 /* Want auto-negotiation. */
2548 expected_sg_dig_ctrl = 0x81388400;
2550 /* Pause capability */
2551 expected_sg_dig_ctrl |= (1 << 11);
2553 /* Asymettric pause */
2554 expected_sg_dig_ctrl |= (1 << 12);
2556 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2557 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2558 tp->serdes_counter &&
2559 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2560 MAC_STATUS_RCVD_CFG)) ==
2561 MAC_STATUS_PCS_SYNCED)) {
2562 tp->serdes_counter--;
2563 current_link_up = 1;
2568 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2569 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2571 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2573 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2574 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2575 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2576 MAC_STATUS_SIGNAL_DET)) {
2577 sg_dig_status = tr32(SG_DIG_STATUS);
2578 mac_status = tr32(MAC_STATUS);
2580 if ((sg_dig_status & (1 << 1)) &&
2581 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2582 u32 local_adv, remote_adv;
2584 local_adv = ADVERTISE_PAUSE_CAP;
2586 if (sg_dig_status & (1 << 19))
2587 remote_adv |= LPA_PAUSE_CAP;
2588 if (sg_dig_status & (1 << 20))
2589 remote_adv |= LPA_PAUSE_ASYM;
2591 tg3_setup_flow_control(tp, local_adv, remote_adv);
2592 current_link_up = 1;
2593 tp->serdes_counter = 0;
2594 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2595 } else if (!(sg_dig_status & (1 << 1))) {
2596 if (tp->serdes_counter)
2597 tp->serdes_counter--;
2600 u32 val = serdes_cfg;
2607 tw32_f(MAC_SERDES_CFG, val);
2610 tw32_f(SG_DIG_CTRL, 0x01388400);
2613 /* Link parallel detection - link is up */
2614 /* only if we have PCS_SYNC and not */
2615 /* receiving config code words */
2616 mac_status = tr32(MAC_STATUS);
2617 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2618 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2619 tg3_setup_flow_control(tp, 0, 0);
2620 current_link_up = 1;
2622 TG3_FLG2_PARALLEL_DETECT;
2623 tp->serdes_counter =
2624 SERDES_PARALLEL_DET_TIMEOUT;
2626 goto restart_autoneg;
2630 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2631 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2635 return current_link_up;
2638 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2640 int current_link_up = 0;
2642 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2645 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2649 if (fiber_autoneg(tp, &flags)) {
2650 u32 local_adv, remote_adv;
2652 local_adv = ADVERTISE_PAUSE_CAP;
2654 if (flags & MR_LP_ADV_SYM_PAUSE)
2655 remote_adv |= LPA_PAUSE_CAP;
2656 if (flags & MR_LP_ADV_ASYM_PAUSE)
2657 remote_adv |= LPA_PAUSE_ASYM;
2659 tg3_setup_flow_control(tp, local_adv, remote_adv);
2661 current_link_up = 1;
2663 for (i = 0; i < 30; i++) {
2666 (MAC_STATUS_SYNC_CHANGED |
2667 MAC_STATUS_CFG_CHANGED));
2669 if ((tr32(MAC_STATUS) &
2670 (MAC_STATUS_SYNC_CHANGED |
2671 MAC_STATUS_CFG_CHANGED)) == 0)
2675 mac_status = tr32(MAC_STATUS);
2676 if (current_link_up == 0 &&
2677 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2678 !(mac_status & MAC_STATUS_RCVD_CFG))
2679 current_link_up = 1;
2681 /* Forcing 1000FD link up. */
2682 current_link_up = 1;
2684 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2687 tw32_f(MAC_MODE, tp->mac_mode);
2692 return current_link_up;
2695 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2698 u16 orig_active_speed;
2699 u8 orig_active_duplex;
2701 int current_link_up;
2705 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2706 TG3_FLAG_TX_PAUSE));
2707 orig_active_speed = tp->link_config.active_speed;
2708 orig_active_duplex = tp->link_config.active_duplex;
2710 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2711 netif_carrier_ok(tp->dev) &&
2712 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2713 mac_status = tr32(MAC_STATUS);
2714 mac_status &= (MAC_STATUS_PCS_SYNCED |
2715 MAC_STATUS_SIGNAL_DET |
2716 MAC_STATUS_CFG_CHANGED |
2717 MAC_STATUS_RCVD_CFG);
2718 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2719 MAC_STATUS_SIGNAL_DET)) {
2720 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2721 MAC_STATUS_CFG_CHANGED));
2726 tw32_f(MAC_TX_AUTO_NEG, 0);
2728 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2729 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2730 tw32_f(MAC_MODE, tp->mac_mode);
2733 if (tp->phy_id == PHY_ID_BCM8002)
2734 tg3_init_bcm8002(tp);
2736 /* Enable link change event even when serdes polling. */
2737 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2740 current_link_up = 0;
2741 mac_status = tr32(MAC_STATUS);
2743 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2744 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2746 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2748 tp->hw_status->status =
2749 (SD_STATUS_UPDATED |
2750 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2752 for (i = 0; i < 100; i++) {
2753 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2754 MAC_STATUS_CFG_CHANGED));
2756 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2757 MAC_STATUS_CFG_CHANGED |
2758 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2762 mac_status = tr32(MAC_STATUS);
2763 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2764 current_link_up = 0;
2765 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2766 tp->serdes_counter == 0) {
2767 tw32_f(MAC_MODE, (tp->mac_mode |
2768 MAC_MODE_SEND_CONFIGS));
2770 tw32_f(MAC_MODE, tp->mac_mode);
2774 if (current_link_up == 1) {
2775 tp->link_config.active_speed = SPEED_1000;
2776 tp->link_config.active_duplex = DUPLEX_FULL;
2777 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2778 LED_CTRL_LNKLED_OVERRIDE |
2779 LED_CTRL_1000MBPS_ON));
2781 tp->link_config.active_speed = SPEED_INVALID;
2782 tp->link_config.active_duplex = DUPLEX_INVALID;
2783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2784 LED_CTRL_LNKLED_OVERRIDE |
2785 LED_CTRL_TRAFFIC_OVERRIDE));
2788 if (current_link_up != netif_carrier_ok(tp->dev)) {
2789 if (current_link_up)
2790 netif_carrier_on(tp->dev);
2792 netif_carrier_off(tp->dev);
2793 tg3_link_report(tp);
2796 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2798 if (orig_pause_cfg != now_pause_cfg ||
2799 orig_active_speed != tp->link_config.active_speed ||
2800 orig_active_duplex != tp->link_config.active_duplex)
2801 tg3_link_report(tp);
2807 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2809 int current_link_up, err = 0;
2814 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2815 tw32_f(MAC_MODE, tp->mac_mode);
2821 (MAC_STATUS_SYNC_CHANGED |
2822 MAC_STATUS_CFG_CHANGED |
2823 MAC_STATUS_MI_COMPLETION |
2824 MAC_STATUS_LNKSTATE_CHANGED));
2830 current_link_up = 0;
2831 current_speed = SPEED_INVALID;
2832 current_duplex = DUPLEX_INVALID;
2834 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2835 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2837 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2838 bmsr |= BMSR_LSTATUS;
2840 bmsr &= ~BMSR_LSTATUS;
2843 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2845 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2846 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2847 /* do nothing, just check for link up at the end */
2848 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2851 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2852 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2853 ADVERTISE_1000XPAUSE |
2854 ADVERTISE_1000XPSE_ASYM |
2857 /* Always advertise symmetric PAUSE just like copper */
2858 new_adv |= ADVERTISE_1000XPAUSE;
2860 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2861 new_adv |= ADVERTISE_1000XHALF;
2862 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2863 new_adv |= ADVERTISE_1000XFULL;
2865 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2866 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2867 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2868 tg3_writephy(tp, MII_BMCR, bmcr);
2870 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2871 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2872 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2879 bmcr &= ~BMCR_SPEED1000;
2880 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2882 if (tp->link_config.duplex == DUPLEX_FULL)
2883 new_bmcr |= BMCR_FULLDPLX;
2885 if (new_bmcr != bmcr) {
2886 /* BMCR_SPEED1000 is a reserved bit that needs
2887 * to be set on write.
2889 new_bmcr |= BMCR_SPEED1000;
2891 /* Force a linkdown */
2892 if (netif_carrier_ok(tp->dev)) {
2895 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2896 adv &= ~(ADVERTISE_1000XFULL |
2897 ADVERTISE_1000XHALF |
2899 tg3_writephy(tp, MII_ADVERTISE, adv);
2900 tg3_writephy(tp, MII_BMCR, bmcr |
2904 netif_carrier_off(tp->dev);
2906 tg3_writephy(tp, MII_BMCR, new_bmcr);
2908 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2909 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2910 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2912 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2913 bmsr |= BMSR_LSTATUS;
2915 bmsr &= ~BMSR_LSTATUS;
2917 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2921 if (bmsr & BMSR_LSTATUS) {
2922 current_speed = SPEED_1000;
2923 current_link_up = 1;
2924 if (bmcr & BMCR_FULLDPLX)
2925 current_duplex = DUPLEX_FULL;
2927 current_duplex = DUPLEX_HALF;
2929 if (bmcr & BMCR_ANENABLE) {
2930 u32 local_adv, remote_adv, common;
2932 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2933 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2934 common = local_adv & remote_adv;
2935 if (common & (ADVERTISE_1000XHALF |
2936 ADVERTISE_1000XFULL)) {
2937 if (common & ADVERTISE_1000XFULL)
2938 current_duplex = DUPLEX_FULL;
2940 current_duplex = DUPLEX_HALF;
2942 tg3_setup_flow_control(tp, local_adv,
2946 current_link_up = 0;
2950 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2951 if (tp->link_config.active_duplex == DUPLEX_HALF)
2952 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2954 tw32_f(MAC_MODE, tp->mac_mode);
2957 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2959 tp->link_config.active_speed = current_speed;
2960 tp->link_config.active_duplex = current_duplex;
2962 if (current_link_up != netif_carrier_ok(tp->dev)) {
2963 if (current_link_up)
2964 netif_carrier_on(tp->dev);
2966 netif_carrier_off(tp->dev);
2967 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2969 tg3_link_report(tp);
2974 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2976 if (tp->serdes_counter) {
2977 /* Give autoneg time to complete. */
2978 tp->serdes_counter--;
2981 if (!netif_carrier_ok(tp->dev) &&
2982 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2985 tg3_readphy(tp, MII_BMCR, &bmcr);
2986 if (bmcr & BMCR_ANENABLE) {
2989 /* Select shadow register 0x1f */
2990 tg3_writephy(tp, 0x1c, 0x7c00);
2991 tg3_readphy(tp, 0x1c, &phy1);
2993 /* Select expansion interrupt status register */
2994 tg3_writephy(tp, 0x17, 0x0f01);
2995 tg3_readphy(tp, 0x15, &phy2);
2996 tg3_readphy(tp, 0x15, &phy2);
2998 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2999 /* We have signal detect and not receiving
3000 * config code words, link is up by parallel
3004 bmcr &= ~BMCR_ANENABLE;
3005 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3006 tg3_writephy(tp, MII_BMCR, bmcr);
3007 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3011 else if (netif_carrier_ok(tp->dev) &&
3012 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3013 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3016 /* Select expansion interrupt status register */
3017 tg3_writephy(tp, 0x17, 0x0f01);
3018 tg3_readphy(tp, 0x15, &phy2);
3022 /* Config code words received, turn on autoneg. */
3023 tg3_readphy(tp, MII_BMCR, &bmcr);
3024 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3026 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3032 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3036 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3037 err = tg3_setup_fiber_phy(tp, force_reset);
3038 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3039 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3041 err = tg3_setup_copper_phy(tp, force_reset);
3044 if (tp->link_config.active_speed == SPEED_1000 &&
3045 tp->link_config.active_duplex == DUPLEX_HALF)
3046 tw32(MAC_TX_LENGTHS,
3047 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3048 (6 << TX_LENGTHS_IPG_SHIFT) |
3049 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3051 tw32(MAC_TX_LENGTHS,
3052 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3053 (6 << TX_LENGTHS_IPG_SHIFT) |
3054 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3056 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3057 if (netif_carrier_ok(tp->dev)) {
3058 tw32(HOSTCC_STAT_COAL_TICKS,
3059 tp->coal.stats_block_coalesce_usecs);
3061 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3065 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3066 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3067 if (!netif_carrier_ok(tp->dev))
3068 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3071 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3072 tw32(PCIE_PWR_MGMT_THRESH, val);
3078 /* This is called whenever we suspect that the system chipset is re-
3079 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3080 * is bogus tx completions. We try to recover by setting the
3081 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3084 static void tg3_tx_recover(struct tg3 *tp)
3086 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3087 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3089 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3090 "mapped I/O cycles to the network device, attempting to "
3091 "recover. Please report the problem to the driver maintainer "
3092 "and include system chipset information.\n", tp->dev->name);
3094 spin_lock(&tp->lock);
3095 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3096 spin_unlock(&tp->lock);
3099 static inline u32 tg3_tx_avail(struct tg3 *tp)
3102 return (tp->tx_pending -
3103 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3106 /* Tigon3 never reports partial packet sends. So we do not
3107 * need special logic to handle SKBs that have not had all
3108 * of their frags sent yet, like SunGEM does.
3110 static void tg3_tx(struct tg3 *tp)
3112 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3113 u32 sw_idx = tp->tx_cons;
3115 while (sw_idx != hw_idx) {
3116 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3117 struct sk_buff *skb = ri->skb;
3120 if (unlikely(skb == NULL)) {
3125 pci_unmap_single(tp->pdev,
3126 pci_unmap_addr(ri, mapping),
3132 sw_idx = NEXT_TX(sw_idx);
3134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3135 ri = &tp->tx_buffers[sw_idx];
3136 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3139 pci_unmap_page(tp->pdev,
3140 pci_unmap_addr(ri, mapping),
3141 skb_shinfo(skb)->frags[i].size,
3144 sw_idx = NEXT_TX(sw_idx);
3149 if (unlikely(tx_bug)) {
3155 tp->tx_cons = sw_idx;
3157 /* Need to make the tx_cons update visible to tg3_start_xmit()
3158 * before checking for netif_queue_stopped(). Without the
3159 * memory barrier, there is a small possibility that tg3_start_xmit()
3160 * will miss it and cause the queue to be stopped forever.
3164 if (unlikely(netif_queue_stopped(tp->dev) &&
3165 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3166 netif_tx_lock(tp->dev);
3167 if (netif_queue_stopped(tp->dev) &&
3168 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3169 netif_wake_queue(tp->dev);
3170 netif_tx_unlock(tp->dev);
3174 /* Returns size of skb allocated or < 0 on error.
3176 * We only need to fill in the address because the other members
3177 * of the RX descriptor are invariant, see tg3_init_rings.
3179 * Note the purposeful assymetry of cpu vs. chip accesses. For
3180 * posting buffers we only dirty the first cache line of the RX
3181 * descriptor (containing the address). Whereas for the RX status
3182 * buffers the cpu only reads the last cacheline of the RX descriptor
3183 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3185 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3186 int src_idx, u32 dest_idx_unmasked)
3188 struct tg3_rx_buffer_desc *desc;
3189 struct ring_info *map, *src_map;
3190 struct sk_buff *skb;
3192 int skb_size, dest_idx;
3195 switch (opaque_key) {
3196 case RXD_OPAQUE_RING_STD:
3197 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3198 desc = &tp->rx_std[dest_idx];
3199 map = &tp->rx_std_buffers[dest_idx];
3201 src_map = &tp->rx_std_buffers[src_idx];
3202 skb_size = tp->rx_pkt_buf_sz;
3205 case RXD_OPAQUE_RING_JUMBO:
3206 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3207 desc = &tp->rx_jumbo[dest_idx];
3208 map = &tp->rx_jumbo_buffers[dest_idx];
3210 src_map = &tp->rx_jumbo_buffers[src_idx];
3211 skb_size = RX_JUMBO_PKT_BUF_SZ;
3218 /* Do not overwrite any of the map or rp information
3219 * until we are sure we can commit to a new buffer.
3221 * Callers depend upon this behavior and assume that
3222 * we leave everything unchanged if we fail.
3224 skb = netdev_alloc_skb(tp->dev, skb_size);
3228 skb_reserve(skb, tp->rx_offset);
3230 mapping = pci_map_single(tp->pdev, skb->data,
3231 skb_size - tp->rx_offset,
3232 PCI_DMA_FROMDEVICE);
3235 pci_unmap_addr_set(map, mapping, mapping);
3237 if (src_map != NULL)
3238 src_map->skb = NULL;
3240 desc->addr_hi = ((u64)mapping >> 32);
3241 desc->addr_lo = ((u64)mapping & 0xffffffff);
3246 /* We only need to move over in the address because the other
3247 * members of the RX descriptor are invariant. See notes above
3248 * tg3_alloc_rx_skb for full details.
3250 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3251 int src_idx, u32 dest_idx_unmasked)
3253 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3254 struct ring_info *src_map, *dest_map;
3257 switch (opaque_key) {
3258 case RXD_OPAQUE_RING_STD:
3259 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3260 dest_desc = &tp->rx_std[dest_idx];
3261 dest_map = &tp->rx_std_buffers[dest_idx];
3262 src_desc = &tp->rx_std[src_idx];
3263 src_map = &tp->rx_std_buffers[src_idx];
3266 case RXD_OPAQUE_RING_JUMBO:
3267 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3268 dest_desc = &tp->rx_jumbo[dest_idx];
3269 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3270 src_desc = &tp->rx_jumbo[src_idx];
3271 src_map = &tp->rx_jumbo_buffers[src_idx];
3278 dest_map->skb = src_map->skb;
3279 pci_unmap_addr_set(dest_map, mapping,
3280 pci_unmap_addr(src_map, mapping));
3281 dest_desc->addr_hi = src_desc->addr_hi;
3282 dest_desc->addr_lo = src_desc->addr_lo;
3284 src_map->skb = NULL;
3287 #if TG3_VLAN_TAG_USED
3288 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3290 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3294 /* The RX ring scheme is composed of multiple rings which post fresh
3295 * buffers to the chip, and one special ring the chip uses to report
3296 * status back to the host.
3298 * The special ring reports the status of received packets to the
3299 * host. The chip does not write into the original descriptor the
3300 * RX buffer was obtained from. The chip simply takes the original
3301 * descriptor as provided by the host, updates the status and length
3302 * field, then writes this into the next status ring entry.
3304 * Each ring the host uses to post buffers to the chip is described
3305 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3306 * it is first placed into the on-chip ram. When the packet's length
3307 * is known, it walks down the TG3_BDINFO entries to select the ring.
3308 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3309 * which is within the range of the new packet's length is chosen.
3311 * The "separate ring for rx status" scheme may sound queer, but it makes
3312 * sense from a cache coherency perspective. If only the host writes
3313 * to the buffer post rings, and only the chip writes to the rx status
3314 * rings, then cache lines never move beyond shared-modified state.
3315 * If both the host and chip were to write into the same ring, cache line
3316 * eviction could occur since both entities want it in an exclusive state.
3318 static int tg3_rx(struct tg3 *tp, int budget)
3320 u32 work_mask, rx_std_posted = 0;
3321 u32 sw_idx = tp->rx_rcb_ptr;
3325 hw_idx = tp->hw_status->idx[0].rx_producer;
3327 * We need to order the read of hw_idx and the read of
3328 * the opaque cookie.
3333 while (sw_idx != hw_idx && budget > 0) {
3334 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3336 struct sk_buff *skb;
3337 dma_addr_t dma_addr;
3338 u32 opaque_key, desc_idx, *post_ptr;
3340 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3341 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3342 if (opaque_key == RXD_OPAQUE_RING_STD) {
3343 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3345 skb = tp->rx_std_buffers[desc_idx].skb;
3346 post_ptr = &tp->rx_std_ptr;
3348 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3349 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3351 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3352 post_ptr = &tp->rx_jumbo_ptr;
3355 goto next_pkt_nopost;
3358 work_mask |= opaque_key;
3360 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3361 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3363 tg3_recycle_rx(tp, opaque_key,
3364 desc_idx, *post_ptr);
3366 /* Other statistics kept track of by card. */
3367 tp->net_stats.rx_dropped++;
3371 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3373 if (len > RX_COPY_THRESHOLD
3374 && tp->rx_offset == 2
3375 /* rx_offset != 2 iff this is a 5701 card running
3376 * in PCI-X mode [see tg3_get_invariants()] */
3380 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3381 desc_idx, *post_ptr);
3385 pci_unmap_single(tp->pdev, dma_addr,
3386 skb_size - tp->rx_offset,
3387 PCI_DMA_FROMDEVICE);
3391 struct sk_buff *copy_skb;
3393 tg3_recycle_rx(tp, opaque_key,
3394 desc_idx, *post_ptr);
3396 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3397 if (copy_skb == NULL)
3398 goto drop_it_no_recycle;
3400 skb_reserve(copy_skb, 2);
3401 skb_put(copy_skb, len);
3402 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3403 skb_copy_from_linear_data(skb, copy_skb->data, len);
3404 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3406 /* We'll reuse the original ring buffer. */
3410 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3411 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3412 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3413 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3414 skb->ip_summed = CHECKSUM_UNNECESSARY;
3416 skb->ip_summed = CHECKSUM_NONE;
3418 skb->protocol = eth_type_trans(skb, tp->dev);
3419 #if TG3_VLAN_TAG_USED
3420 if (tp->vlgrp != NULL &&
3421 desc->type_flags & RXD_FLAG_VLAN) {
3422 tg3_vlan_rx(tp, skb,
3423 desc->err_vlan & RXD_VLAN_MASK);
3426 netif_receive_skb(skb);
3428 tp->dev->last_rx = jiffies;
3435 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3436 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3438 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3439 TG3_64BIT_REG_LOW, idx);
3440 work_mask &= ~RXD_OPAQUE_RING_STD;
3445 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3447 /* Refresh hw_idx to see if there is new work */
3448 if (sw_idx == hw_idx) {
3449 hw_idx = tp->hw_status->idx[0].rx_producer;
3454 /* ACK the status ring. */
3455 tp->rx_rcb_ptr = sw_idx;
3456 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3458 /* Refill RX ring(s). */
3459 if (work_mask & RXD_OPAQUE_RING_STD) {
3460 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3461 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3464 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3465 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3466 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3474 static int tg3_poll(struct napi_struct *napi, int budget)
3476 struct tg3 *tp = container_of(napi, struct tg3, napi);
3477 struct net_device *netdev = tp->dev;
3478 struct tg3_hw_status *sblk = tp->hw_status;
3481 /* handle link change and other phy events */
3482 if (!(tp->tg3_flags &
3483 (TG3_FLAG_USE_LINKCHG_REG |
3484 TG3_FLAG_POLL_SERDES))) {
3485 if (sblk->status & SD_STATUS_LINK_CHG) {
3486 sblk->status = SD_STATUS_UPDATED |
3487 (sblk->status & ~SD_STATUS_LINK_CHG);
3488 spin_lock(&tp->lock);
3489 tg3_setup_phy(tp, 0);
3490 spin_unlock(&tp->lock);
3494 /* run TX completion thread */
3495 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3497 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3498 netif_rx_complete(netdev, napi);
3499 schedule_work(&tp->reset_task);
3504 /* run RX thread, within the bounds set by NAPI.
3505 * All RX "locking" is done by ensuring outside
3506 * code synchronizes with tg3->napi.poll()
3508 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
3509 work_done = tg3_rx(tp, budget);
3511 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3512 tp->last_tag = sblk->status_tag;
3515 sblk->status &= ~SD_STATUS_UPDATED;
3517 /* if no more work, tell net stack and NIC we're done */
3518 if (!tg3_has_work(tp)) {
3519 netif_rx_complete(netdev, napi);
3520 tg3_restart_ints(tp);
3526 static void tg3_irq_quiesce(struct tg3 *tp)
3528 BUG_ON(tp->irq_sync);
3533 synchronize_irq(tp->pdev->irq);
3536 static inline int tg3_irq_sync(struct tg3 *tp)
3538 return tp->irq_sync;
3541 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3542 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3543 * with as well. Most of the time, this is not necessary except when
3544 * shutting down the device.
3546 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3548 spin_lock_bh(&tp->lock);
3550 tg3_irq_quiesce(tp);
3553 static inline void tg3_full_unlock(struct tg3 *tp)
3555 spin_unlock_bh(&tp->lock);
3558 /* One-shot MSI handler - Chip automatically disables interrupt
3559 * after sending MSI so driver doesn't have to do it.
3561 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3563 struct net_device *dev = dev_id;
3564 struct tg3 *tp = netdev_priv(dev);
3566 prefetch(tp->hw_status);
3567 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3569 if (likely(!tg3_irq_sync(tp)))
3570 netif_rx_schedule(dev, &tp->napi);
3575 /* MSI ISR - No need to check for interrupt sharing and no need to
3576 * flush status block and interrupt mailbox. PCI ordering rules
3577 * guarantee that MSI will arrive after the status block.
3579 static irqreturn_t tg3_msi(int irq, void *dev_id)
3581 struct net_device *dev = dev_id;
3582 struct tg3 *tp = netdev_priv(dev);
3584 prefetch(tp->hw_status);
3585 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3587 * Writing any value to intr-mbox-0 clears PCI INTA# and
3588 * chip-internal interrupt pending events.
3589 * Writing non-zero to intr-mbox-0 additional tells the
3590 * NIC to stop sending us irqs, engaging "in-intr-handler"
3593 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3594 if (likely(!tg3_irq_sync(tp)))
3595 netif_rx_schedule(dev, &tp->napi);
3597 return IRQ_RETVAL(1);
3600 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3602 struct net_device *dev = dev_id;
3603 struct tg3 *tp = netdev_priv(dev);
3604 struct tg3_hw_status *sblk = tp->hw_status;
3605 unsigned int handled = 1;
3607 /* In INTx mode, it is possible for the interrupt to arrive at
3608 * the CPU before the status block posted prior to the interrupt.
3609 * Reading the PCI State register will confirm whether the
3610 * interrupt is ours and will flush the status block.
3612 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3613 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3614 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3621 * Writing any value to intr-mbox-0 clears PCI INTA# and
3622 * chip-internal interrupt pending events.
3623 * Writing non-zero to intr-mbox-0 additional tells the
3624 * NIC to stop sending us irqs, engaging "in-intr-handler"
3627 * Flush the mailbox to de-assert the IRQ immediately to prevent
3628 * spurious interrupts. The flush impacts performance but
3629 * excessive spurious interrupts can be worse in some cases.
3631 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3632 if (tg3_irq_sync(tp))
3634 sblk->status &= ~SD_STATUS_UPDATED;
3635 if (likely(tg3_has_work(tp))) {
3636 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3637 netif_rx_schedule(dev, &tp->napi);
3639 /* No work, shared interrupt perhaps? re-enable
3640 * interrupts, and flush that PCI write
3642 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3646 return IRQ_RETVAL(handled);
3649 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3651 struct net_device *dev = dev_id;
3652 struct tg3 *tp = netdev_priv(dev);
3653 struct tg3_hw_status *sblk = tp->hw_status;
3654 unsigned int handled = 1;
3656 /* In INTx mode, it is possible for the interrupt to arrive at
3657 * the CPU before the status block posted prior to the interrupt.
3658 * Reading the PCI State register will confirm whether the
3659 * interrupt is ours and will flush the status block.
3661 if (unlikely(sblk->status_tag == tp->last_tag)) {
3662 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3663 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3670 * writing any value to intr-mbox-0 clears PCI INTA# and
3671 * chip-internal interrupt pending events.
3672 * writing non-zero to intr-mbox-0 additional tells the
3673 * NIC to stop sending us irqs, engaging "in-intr-handler"
3676 * Flush the mailbox to de-assert the IRQ immediately to prevent
3677 * spurious interrupts. The flush impacts performance but
3678 * excessive spurious interrupts can be worse in some cases.
3680 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3681 if (tg3_irq_sync(tp))
3683 if (netif_rx_schedule_prep(dev, &tp->napi)) {
3684 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3685 /* Update last_tag to mark that this status has been
3686 * seen. Because interrupt may be shared, we may be
3687 * racing with tg3_poll(), so only update last_tag
3688 * if tg3_poll() is not scheduled.
3690 tp->last_tag = sblk->status_tag;
3691 __netif_rx_schedule(dev, &tp->napi);
3694 return IRQ_RETVAL(handled);
3697 /* ISR for interrupt test */
3698 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3700 struct net_device *dev = dev_id;
3701 struct tg3 *tp = netdev_priv(dev);
3702 struct tg3_hw_status *sblk = tp->hw_status;
3704 if ((sblk->status & SD_STATUS_UPDATED) ||
3705 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3706 tg3_disable_ints(tp);
3707 return IRQ_RETVAL(1);
3709 return IRQ_RETVAL(0);
3712 static int tg3_init_hw(struct tg3 *, int);
3713 static int tg3_halt(struct tg3 *, int, int);
3715 /* Restart hardware after configuration changes, self-test, etc.
3716 * Invoked with tp->lock held.
3718 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3722 err = tg3_init_hw(tp, reset_phy);
3724 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3725 "aborting.\n", tp->dev->name);
3726 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3727 tg3_full_unlock(tp);
3728 del_timer_sync(&tp->timer);
3730 napi_enable(&tp->napi);
3732 tg3_full_lock(tp, 0);
3737 #ifdef CONFIG_NET_POLL_CONTROLLER
3738 static void tg3_poll_controller(struct net_device *dev)
3740 struct tg3 *tp = netdev_priv(dev);
3742 tg3_interrupt(tp->pdev->irq, dev);
3746 static void tg3_reset_task(struct work_struct *work)
3748 struct tg3 *tp = container_of(work, struct tg3, reset_task);
3749 unsigned int restart_timer;
3751 tg3_full_lock(tp, 0);
3753 if (!netif_running(tp->dev)) {
3754 tg3_full_unlock(tp);
3758 tg3_full_unlock(tp);
3762 tg3_full_lock(tp, 1);
3764 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3765 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3767 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3768 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3769 tp->write32_rx_mbox = tg3_write_flush_reg32;
3770 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3771 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3774 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3775 if (tg3_init_hw(tp, 1))
3778 tg3_netif_start(tp);
3781 mod_timer(&tp->timer, jiffies + 1);
3784 tg3_full_unlock(tp);
3787 static void tg3_dump_short_state(struct tg3 *tp)
3789 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3790 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3791 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3792 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3795 static void tg3_tx_timeout(struct net_device *dev)
3797 struct tg3 *tp = netdev_priv(dev);
3799 if (netif_msg_tx_err(tp)) {
3800 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3802 tg3_dump_short_state(tp);
3805 schedule_work(&tp->reset_task);
3808 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3809 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3811 u32 base = (u32) mapping & 0xffffffff;
3813 return ((base > 0xffffdcc0) &&
3814 (base + len + 8 < base));
3817 /* Test for DMA addresses > 40-bit */
3818 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3821 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3822 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3823 return (((u64) mapping + len) > DMA_40BIT_MASK);
3830 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3832 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3833 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3834 u32 last_plus_one, u32 *start,
3835 u32 base_flags, u32 mss)
3837 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3838 dma_addr_t new_addr = 0;
3845 /* New SKB is guaranteed to be linear. */
3847 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3849 /* Make sure new skb does not cross any 4G boundaries.
3850 * Drop the packet if it does.
3852 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3854 dev_kfree_skb(new_skb);
3857 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3858 base_flags, 1 | (mss << 1));
3859 *start = NEXT_TX(entry);
3863 /* Now clean up the sw ring entries. */
3865 while (entry != last_plus_one) {
3869 len = skb_headlen(skb);
3871 len = skb_shinfo(skb)->frags[i-1].size;
3872 pci_unmap_single(tp->pdev,
3873 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3874 len, PCI_DMA_TODEVICE);
3876 tp->tx_buffers[entry].skb = new_skb;
3877 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3879 tp->tx_buffers[entry].skb = NULL;
3881 entry = NEXT_TX(entry);
3890 static void tg3_set_txd(struct tg3 *tp, int entry,
3891 dma_addr_t mapping, int len, u32 flags,
3894 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3895 int is_end = (mss_and_is_end & 0x1);
3896 u32 mss = (mss_and_is_end >> 1);
3900 flags |= TXD_FLAG_END;
3901 if (flags & TXD_FLAG_VLAN) {
3902 vlan_tag = flags >> 16;
3905 vlan_tag |= (mss << TXD_MSS_SHIFT);
3907 txd->addr_hi = ((u64) mapping >> 32);
3908 txd->addr_lo = ((u64) mapping & 0xffffffff);
3909 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3910 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3913 /* hard_start_xmit for devices that don't have any bugs and
3914 * support TG3_FLG2_HW_TSO_2 only.
3916 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3918 struct tg3 *tp = netdev_priv(dev);
3920 u32 len, entry, base_flags, mss;
3922 len = skb_headlen(skb);
3924 /* We are running in BH disabled context with netif_tx_lock
3925 * and TX reclaim runs via tp->napi.poll inside of a software
3926 * interrupt. Furthermore, IRQ processing runs lockless so we have
3927 * no IRQ context deadlocks to worry about either. Rejoice!
3929 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3930 if (!netif_queue_stopped(dev)) {
3931 netif_stop_queue(dev);
3933 /* This is a hard error, log it. */
3934 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3935 "queue awake!\n", dev->name);
3937 return NETDEV_TX_BUSY;
3940 entry = tp->tx_prod;
3943 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
3944 int tcp_opt_len, ip_tcp_len;
3946 if (skb_header_cloned(skb) &&
3947 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3952 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3953 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3955 struct iphdr *iph = ip_hdr(skb);
3957 tcp_opt_len = tcp_optlen(skb);
3958 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3961 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3962 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3965 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3966 TXD_FLAG_CPU_POST_DMA);
3968 tcp_hdr(skb)->check = 0;
3971 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3972 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3973 #if TG3_VLAN_TAG_USED
3974 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3975 base_flags |= (TXD_FLAG_VLAN |
3976 (vlan_tx_tag_get(skb) << 16));
3979 /* Queue skb data, a.k.a. the main skb fragment. */
3980 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3982 tp->tx_buffers[entry].skb = skb;
3983 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3985 tg3_set_txd(tp, entry, mapping, len, base_flags,
3986 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3988 entry = NEXT_TX(entry);
3990 /* Now loop through additional data fragments, and queue them. */
3991 if (skb_shinfo(skb)->nr_frags > 0) {
3992 unsigned int i, last;
3994 last = skb_shinfo(skb)->nr_frags - 1;
3995 for (i = 0; i <= last; i++) {
3996 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3999 mapping = pci_map_page(tp->pdev,
4002 len, PCI_DMA_TODEVICE);
4004 tp->tx_buffers[entry].skb = NULL;
4005 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4007 tg3_set_txd(tp, entry, mapping, len,
4008 base_flags, (i == last) | (mss << 1));
4010 entry = NEXT_TX(entry);
4014 /* Packets are ready, update Tx producer idx local and on card. */
4015 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4017 tp->tx_prod = entry;
4018 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4019 netif_stop_queue(dev);
4020 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4021 netif_wake_queue(tp->dev);
4027 dev->trans_start = jiffies;
4029 return NETDEV_TX_OK;
4032 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4034 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4035 * TSO header is greater than 80 bytes.
4037 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4039 struct sk_buff *segs, *nskb;
4041 /* Estimate the number of fragments in the worst case */
4042 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4043 netif_stop_queue(tp->dev);
4044 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4045 return NETDEV_TX_BUSY;
4047 netif_wake_queue(tp->dev);
4050 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4051 if (unlikely(IS_ERR(segs)))
4052 goto tg3_tso_bug_end;
4058 tg3_start_xmit_dma_bug(nskb, tp->dev);
4064 return NETDEV_TX_OK;
4067 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4068 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4070 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4072 struct tg3 *tp = netdev_priv(dev);
4074 u32 len, entry, base_flags, mss;
4075 int would_hit_hwbug;
4077 len = skb_headlen(skb);
4079 /* We are running in BH disabled context with netif_tx_lock
4080 * and TX reclaim runs via tp->napi.poll inside of a software
4081 * interrupt. Furthermore, IRQ processing runs lockless so we have
4082 * no IRQ context deadlocks to worry about either. Rejoice!
4084 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4085 if (!netif_queue_stopped(dev)) {
4086 netif_stop_queue(dev);
4088 /* This is a hard error, log it. */
4089 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4090 "queue awake!\n", dev->name);
4092 return NETDEV_TX_BUSY;
4095 entry = tp->tx_prod;
4097 if (skb->ip_summed == CHECKSUM_PARTIAL)
4098 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4100 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4102 int tcp_opt_len, ip_tcp_len, hdr_len;
4104 if (skb_header_cloned(skb) &&
4105 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4110 tcp_opt_len = tcp_optlen(skb);
4111 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4113 hdr_len = ip_tcp_len + tcp_opt_len;
4114 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4115 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4116 return (tg3_tso_bug(tp, skb));
4118 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4119 TXD_FLAG_CPU_POST_DMA);
4123 iph->tot_len = htons(mss + hdr_len);
4124 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4125 tcp_hdr(skb)->check = 0;
4126 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4128 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4133 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4134 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4135 if (tcp_opt_len || iph->ihl > 5) {
4138 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4139 mss |= (tsflags << 11);
4142 if (tcp_opt_len || iph->ihl > 5) {
4145 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4146 base_flags |= tsflags << 12;
4150 #if TG3_VLAN_TAG_USED
4151 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4152 base_flags |= (TXD_FLAG_VLAN |
4153 (vlan_tx_tag_get(skb) << 16));
4156 /* Queue skb data, a.k.a. the main skb fragment. */
4157 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4159 tp->tx_buffers[entry].skb = skb;
4160 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4162 would_hit_hwbug = 0;
4164 if (tg3_4g_overflow_test(mapping, len))
4165 would_hit_hwbug = 1;
4167 tg3_set_txd(tp, entry, mapping, len, base_flags,
4168 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4170 entry = NEXT_TX(entry);
4172 /* Now loop through additional data fragments, and queue them. */
4173 if (skb_shinfo(skb)->nr_frags > 0) {
4174 unsigned int i, last;
4176 last = skb_shinfo(skb)->nr_frags - 1;
4177 for (i = 0; i <= last; i++) {
4178 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4181 mapping = pci_map_page(tp->pdev,
4184 len, PCI_DMA_TODEVICE);
4186 tp->tx_buffers[entry].skb = NULL;
4187 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4189 if (tg3_4g_overflow_test(mapping, len))
4190 would_hit_hwbug = 1;
4192 if (tg3_40bit_overflow_test(tp, mapping, len))
4193 would_hit_hwbug = 1;
4195 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4196 tg3_set_txd(tp, entry, mapping, len,
4197 base_flags, (i == last)|(mss << 1));
4199 tg3_set_txd(tp, entry, mapping, len,
4200 base_flags, (i == last));
4202 entry = NEXT_TX(entry);
4206 if (would_hit_hwbug) {
4207 u32 last_plus_one = entry;
4210 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4211 start &= (TG3_TX_RING_SIZE - 1);
4213 /* If the workaround fails due to memory/mapping
4214 * failure, silently drop this packet.
4216 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4217 &start, base_flags, mss))
4223 /* Packets are ready, update Tx producer idx local and on card. */
4224 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4226 tp->tx_prod = entry;
4227 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4228 netif_stop_queue(dev);
4229 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4230 netif_wake_queue(tp->dev);
4236 dev->trans_start = jiffies;
4238 return NETDEV_TX_OK;
4241 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4246 if (new_mtu > ETH_DATA_LEN) {
4247 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4248 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4249 ethtool_op_set_tso(dev, 0);
4252 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4254 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4255 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4256 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4260 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4262 struct tg3 *tp = netdev_priv(dev);
4265 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4268 if (!netif_running(dev)) {
4269 /* We'll just catch it later when the
4272 tg3_set_mtu(dev, tp, new_mtu);
4278 tg3_full_lock(tp, 1);
4280 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4282 tg3_set_mtu(dev, tp, new_mtu);
4284 err = tg3_restart_hw(tp, 0);
4287 tg3_netif_start(tp);
4289 tg3_full_unlock(tp);
4294 /* Free up pending packets in all rx/tx rings.
4296 * The chip has been shut down and the driver detached from
4297 * the networking, so no interrupts or new tx packets will
4298 * end up in the driver. tp->{tx,}lock is not held and we are not
4299 * in an interrupt context and thus may sleep.
4301 static void tg3_free_rings(struct tg3 *tp)
4303 struct ring_info *rxp;
4306 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4307 rxp = &tp->rx_std_buffers[i];
4309 if (rxp->skb == NULL)
4311 pci_unmap_single(tp->pdev,
4312 pci_unmap_addr(rxp, mapping),
4313 tp->rx_pkt_buf_sz - tp->rx_offset,
4314 PCI_DMA_FROMDEVICE);
4315 dev_kfree_skb_any(rxp->skb);
4319 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4320 rxp = &tp->rx_jumbo_buffers[i];
4322 if (rxp->skb == NULL)
4324 pci_unmap_single(tp->pdev,
4325 pci_unmap_addr(rxp, mapping),
4326 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4327 PCI_DMA_FROMDEVICE);
4328 dev_kfree_skb_any(rxp->skb);
4332 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4333 struct tx_ring_info *txp;
4334 struct sk_buff *skb;
4337 txp = &tp->tx_buffers[i];
4345 pci_unmap_single(tp->pdev,
4346 pci_unmap_addr(txp, mapping),
4353 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4354 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4355 pci_unmap_page(tp->pdev,
4356 pci_unmap_addr(txp, mapping),
4357 skb_shinfo(skb)->frags[j].size,
4362 dev_kfree_skb_any(skb);
4366 /* Initialize tx/rx rings for packet processing.
4368 * The chip has been shut down and the driver detached from
4369 * the networking, so no interrupts or new tx packets will
4370 * end up in the driver. tp->{tx,}lock are held and thus
4373 static int tg3_init_rings(struct tg3 *tp)
4377 /* Free up all the SKBs. */
4380 /* Zero out all descriptors. */
4381 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4382 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4383 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4384 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4386 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4387 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4388 (tp->dev->mtu > ETH_DATA_LEN))
4389 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4391 /* Initialize invariants of the rings, we only set this
4392 * stuff once. This works because the card does not
4393 * write into the rx buffer posting rings.
4395 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4396 struct tg3_rx_buffer_desc *rxd;
4398 rxd = &tp->rx_std[i];
4399 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4401 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4402 rxd->opaque = (RXD_OPAQUE_RING_STD |
4403 (i << RXD_OPAQUE_INDEX_SHIFT));
4406 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4407 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4408 struct tg3_rx_buffer_desc *rxd;
4410 rxd = &tp->rx_jumbo[i];
4411 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4413 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4415 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4416 (i << RXD_OPAQUE_INDEX_SHIFT));
4420 /* Now allocate fresh SKBs for each rx ring. */
4421 for (i = 0; i < tp->rx_pending; i++) {
4422 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4423 printk(KERN_WARNING PFX
4424 "%s: Using a smaller RX standard ring, "
4425 "only %d out of %d buffers were allocated "
4427 tp->dev->name, i, tp->rx_pending);
4435 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4436 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4437 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4439 printk(KERN_WARNING PFX
4440 "%s: Using a smaller RX jumbo ring, "
4441 "only %d out of %d buffers were "
4442 "allocated successfully.\n",
4443 tp->dev->name, i, tp->rx_jumbo_pending);
4448 tp->rx_jumbo_pending = i;
4457 * Must not be invoked with interrupt sources disabled and
4458 * the hardware shutdown down.
4460 static void tg3_free_consistent(struct tg3 *tp)
4462 kfree(tp->rx_std_buffers);
4463 tp->rx_std_buffers = NULL;
4465 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4466 tp->rx_std, tp->rx_std_mapping);
4470 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4471 tp->rx_jumbo, tp->rx_jumbo_mapping);
4472 tp->rx_jumbo = NULL;
4475 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4476 tp->rx_rcb, tp->rx_rcb_mapping);
4480 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4481 tp->tx_ring, tp->tx_desc_mapping);
4484 if (tp->hw_status) {
4485 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4486 tp->hw_status, tp->status_mapping);
4487 tp->hw_status = NULL;
4490 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4491 tp->hw_stats, tp->stats_mapping);
4492 tp->hw_stats = NULL;
4497 * Must not be invoked with interrupt sources disabled and
4498 * the hardware shutdown down. Can sleep.
4500 static int tg3_alloc_consistent(struct tg3 *tp)
4502 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4504 TG3_RX_JUMBO_RING_SIZE)) +
4505 (sizeof(struct tx_ring_info) *
4508 if (!tp->rx_std_buffers)
4511 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4512 tp->tx_buffers = (struct tx_ring_info *)
4513 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4515 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4516 &tp->rx_std_mapping);
4520 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4521 &tp->rx_jumbo_mapping);
4526 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4527 &tp->rx_rcb_mapping);
4531 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4532 &tp->tx_desc_mapping);
4536 tp->hw_status = pci_alloc_consistent(tp->pdev,
4538 &tp->status_mapping);
4542 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4543 sizeof(struct tg3_hw_stats),
4544 &tp->stats_mapping);
4548 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4549 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4554 tg3_free_consistent(tp);
4558 #define MAX_WAIT_CNT 1000
4560 /* To stop a block, clear the enable bit and poll till it
4561 * clears. tp->lock is held.
4563 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4568 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4575 /* We can't enable/disable these bits of the
4576 * 5705/5750, just say success.
4589 for (i = 0; i < MAX_WAIT_CNT; i++) {
4592 if ((val & enable_bit) == 0)
4596 if (i == MAX_WAIT_CNT && !silent) {
4597 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4598 "ofs=%lx enable_bit=%x\n",
4606 /* tp->lock is held. */
4607 static int tg3_abort_hw(struct tg3 *tp, int silent)
4611 tg3_disable_ints(tp);
4613 tp->rx_mode &= ~RX_MODE_ENABLE;
4614 tw32_f(MAC_RX_MODE, tp->rx_mode);
4617 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4618 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4619 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4620 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4621 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4622 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4624 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4625 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4626 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4627 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4628 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4629 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4630 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4632 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4633 tw32_f(MAC_MODE, tp->mac_mode);
4636 tp->tx_mode &= ~TX_MODE_ENABLE;
4637 tw32_f(MAC_TX_MODE, tp->tx_mode);
4639 for (i = 0; i < MAX_WAIT_CNT; i++) {
4641 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4644 if (i >= MAX_WAIT_CNT) {
4645 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4646 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4647 tp->dev->name, tr32(MAC_TX_MODE));
4651 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4652 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4653 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4655 tw32(FTQ_RESET, 0xffffffff);
4656 tw32(FTQ_RESET, 0x00000000);
4658 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4659 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4662 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4664 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4669 /* tp->lock is held. */
4670 static int tg3_nvram_lock(struct tg3 *tp)
4672 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4675 if (tp->nvram_lock_cnt == 0) {
4676 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4677 for (i = 0; i < 8000; i++) {
4678 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4683 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4687 tp->nvram_lock_cnt++;
4692 /* tp->lock is held. */
4693 static void tg3_nvram_unlock(struct tg3 *tp)
4695 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4696 if (tp->nvram_lock_cnt > 0)
4697 tp->nvram_lock_cnt--;
4698 if (tp->nvram_lock_cnt == 0)
4699 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4703 /* tp->lock is held. */
4704 static void tg3_enable_nvram_access(struct tg3 *tp)
4706 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4707 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4708 u32 nvaccess = tr32(NVRAM_ACCESS);
4710 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4714 /* tp->lock is held. */
4715 static void tg3_disable_nvram_access(struct tg3 *tp)
4717 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4718 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4719 u32 nvaccess = tr32(NVRAM_ACCESS);
4721 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4725 /* tp->lock is held. */
4726 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4728 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4729 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4731 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4733 case RESET_KIND_INIT:
4734 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4738 case RESET_KIND_SHUTDOWN:
4739 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4743 case RESET_KIND_SUSPEND:
4744 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4754 /* tp->lock is held. */
4755 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4757 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4759 case RESET_KIND_INIT:
4760 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4761 DRV_STATE_START_DONE);
4764 case RESET_KIND_SHUTDOWN:
4765 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4766 DRV_STATE_UNLOAD_DONE);
4775 /* tp->lock is held. */
4776 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4778 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4780 case RESET_KIND_INIT:
4781 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4785 case RESET_KIND_SHUTDOWN:
4786 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4790 case RESET_KIND_SUSPEND:
4791 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4801 static int tg3_poll_fw(struct tg3 *tp)
4806 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4807 /* Wait up to 20ms for init done. */
4808 for (i = 0; i < 200; i++) {
4809 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4816 /* Wait for firmware initialization to complete. */
4817 for (i = 0; i < 100000; i++) {
4818 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4819 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4824 /* Chip might not be fitted with firmware. Some Sun onboard
4825 * parts are configured like that. So don't signal the timeout
4826 * of the above loop as an error, but do report the lack of
4827 * running firmware once.
4830 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4831 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4833 printk(KERN_INFO PFX "%s: No firmware running.\n",
4840 /* Save PCI command register before chip reset */
4841 static void tg3_save_pci_state(struct tg3 *tp)
4845 pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);
4849 /* Restore PCI state after chip reset */
4850 static void tg3_restore_pci_state(struct tg3 *tp)
4854 /* Re-enable indirect register accesses. */
4855 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4856 tp->misc_host_ctrl);
4858 /* Set MAX PCI retry to zero. */
4859 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4860 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4861 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4862 val |= PCISTATE_RETRY_SAME_DMA;
4863 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4865 pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
4867 /* Make sure PCI-X relaxed ordering bit is clear. */
4868 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4869 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4870 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4872 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4875 /* Chip reset on 5780 will reset MSI enable bit,
4876 * so need to restore it.
4878 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4881 pci_read_config_word(tp->pdev,
4882 tp->msi_cap + PCI_MSI_FLAGS,
4884 pci_write_config_word(tp->pdev,
4885 tp->msi_cap + PCI_MSI_FLAGS,
4886 ctrl | PCI_MSI_FLAGS_ENABLE);
4887 val = tr32(MSGINT_MODE);
4888 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4893 static void tg3_stop_fw(struct tg3 *);
4895 /* tp->lock is held. */
4896 static int tg3_chip_reset(struct tg3 *tp)
4899 void (*write_op)(struct tg3 *, u32, u32);
4904 /* No matching tg3_nvram_unlock() after this because
4905 * chip reset below will undo the nvram lock.
4907 tp->nvram_lock_cnt = 0;
4909 /* GRC_MISC_CFG core clock reset will clear the memory
4910 * enable bit in PCI register 4 and the MSI enable bit
4911 * on some chips, so we save relevant registers here.
4913 tg3_save_pci_state(tp);
4915 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4916 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4917 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4918 tw32(GRC_FASTBOOT_PC, 0);
4921 * We must avoid the readl() that normally takes place.
4922 * It locks machines, causes machine checks, and other
4923 * fun things. So, temporarily disable the 5701
4924 * hardware workaround, while we do the reset.
4926 write_op = tp->write32;
4927 if (write_op == tg3_write_flush_reg32)
4928 tp->write32 = tg3_write32;
4930 /* Prevent the irq handler from reading or writing PCI registers
4931 * during chip reset when the memory enable bit in the PCI command
4932 * register may be cleared. The chip does not generate interrupt
4933 * at this time, but the irq handler may still be called due to irq
4934 * sharing or irqpoll.
4936 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4937 if (tp->hw_status) {
4938 tp->hw_status->status = 0;
4939 tp->hw_status->status_tag = 0;
4943 synchronize_irq(tp->pdev->irq);
4946 val = GRC_MISC_CFG_CORECLK_RESET;
4948 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4949 if (tr32(0x7e2c) == 0x60) {
4952 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4953 tw32(GRC_MISC_CFG, (1 << 29));
4958 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4959 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4960 tw32(GRC_VCPU_EXT_CTRL,
4961 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4964 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4965 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4966 tw32(GRC_MISC_CFG, val);
4968 /* restore 5701 hardware bug workaround write method */
4969 tp->write32 = write_op;
4971 /* Unfortunately, we have to delay before the PCI read back.
4972 * Some 575X chips even will not respond to a PCI cfg access
4973 * when the reset command is given to the chip.
4975 * How do these hardware designers expect things to work
4976 * properly if the PCI write is posted for a long period
4977 * of time? It is always necessary to have some method by
4978 * which a register read back can occur to push the write
4979 * out which does the reset.
4981 * For most tg3 variants the trick below was working.
4986 /* Flush PCI posted writes. The normal MMIO registers
4987 * are inaccessible at this time so this is the only
4988 * way to make this reliably (actually, this is no longer
4989 * the case, see above). I tried to use indirect
4990 * register read/write but this upset some 5701 variants.
4992 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4996 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4997 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5001 /* Wait for link training to complete. */
5002 for (i = 0; i < 5000; i++)
5005 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5006 pci_write_config_dword(tp->pdev, 0xc4,
5007 cfg_val | (1 << 15));
5009 /* Set PCIE max payload size and clear error status. */
5010 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5013 tg3_restore_pci_state(tp);
5015 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5018 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5019 val = tr32(MEMARB_MODE);
5020 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5022 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5024 tw32(0x5000, 0x400);
5027 tw32(GRC_MODE, tp->grc_mode);
5029 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5030 u32 val = tr32(0xc4);
5032 tw32(0xc4, val | (1 << 15));
5035 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5037 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5038 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5039 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5040 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5043 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5044 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5045 tw32_f(MAC_MODE, tp->mac_mode);
5046 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5047 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5048 tw32_f(MAC_MODE, tp->mac_mode);
5050 tw32_f(MAC_MODE, 0);
5053 err = tg3_poll_fw(tp);
5057 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5058 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5059 u32 val = tr32(0x7c00);
5061 tw32(0x7c00, val | (1 << 25));
5064 /* Reprobe ASF enable state. */
5065 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5066 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5067 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5068 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5071 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5072 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5073 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5074 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5075 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5082 /* tp->lock is held. */
5083 static void tg3_stop_fw(struct tg3 *tp)
5085 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5089 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5090 val = tr32(GRC_RX_CPU_EVENT);
5092 tw32(GRC_RX_CPU_EVENT, val);
5094 /* Wait for RX cpu to ACK the event. */
5095 for (i = 0; i < 100; i++) {
5096 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5103 /* tp->lock is held. */
5104 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5110 tg3_write_sig_pre_reset(tp, kind);
5112 tg3_abort_hw(tp, silent);
5113 err = tg3_chip_reset(tp);
5115 tg3_write_sig_legacy(tp, kind);
5116 tg3_write_sig_post_reset(tp, kind);
5124 #define TG3_FW_RELEASE_MAJOR 0x0
5125 #define TG3_FW_RELASE_MINOR 0x0
5126 #define TG3_FW_RELEASE_FIX 0x0
5127 #define TG3_FW_START_ADDR 0x08000000
5128 #define TG3_FW_TEXT_ADDR 0x08000000
5129 #define TG3_FW_TEXT_LEN 0x9c0
5130 #define TG3_FW_RODATA_ADDR 0x080009c0
5131 #define TG3_FW_RODATA_LEN 0x60
5132 #define TG3_FW_DATA_ADDR 0x08000a40
5133 #define TG3_FW_DATA_LEN 0x20
5134 #define TG3_FW_SBSS_ADDR 0x08000a60
5135 #define TG3_FW_SBSS_LEN 0xc
5136 #define TG3_FW_BSS_ADDR 0x08000a70
5137 #define TG3_FW_BSS_LEN 0x10
5139 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5140 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5141 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5142 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5143 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5144 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5145 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5146 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5147 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5148 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5149 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5150 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5151 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5152 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5153 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5154 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5155 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5156 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5157 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5158 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5159 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5160 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5161 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5162 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5163 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5164 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5166 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5167 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5168 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5169 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5170 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5171 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5172 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5173 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5174 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5175 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5176 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5177 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5178 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5179 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5180 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5181 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5182 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5183 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5184 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5185 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5186 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5187 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5188 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5189 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5190 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5191 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5192 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5193 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5194 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5195 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5196 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5197 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5198 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5199 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5200 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5201 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5202 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5203 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5204 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5205 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5206 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5207 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5208 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5209 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5210 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5211 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5212 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5213 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5214 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5215 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5216 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5217 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5218 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5219 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5220 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5221 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5222 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5223 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5224 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5225 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5226 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5227 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5228 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5229 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5230 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5233 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5234 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5235 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5236 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5237 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5241 #if 0 /* All zeros, don't eat up space with it. */
5242 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5243 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5244 0x00000000, 0x00000000, 0x00000000, 0x00000000
5248 #define RX_CPU_SCRATCH_BASE 0x30000
5249 #define RX_CPU_SCRATCH_SIZE 0x04000
5250 #define TX_CPU_SCRATCH_BASE 0x34000
5251 #define TX_CPU_SCRATCH_SIZE 0x04000
5253 /* tp->lock is held. */
5254 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5258 BUG_ON(offset == TX_CPU_BASE &&
5259 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5261 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5262 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5264 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5267 if (offset == RX_CPU_BASE) {
5268 for (i = 0; i < 10000; i++) {
5269 tw32(offset + CPU_STATE, 0xffffffff);
5270 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5271 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5275 tw32(offset + CPU_STATE, 0xffffffff);
5276 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5279 for (i = 0; i < 10000; i++) {
5280 tw32(offset + CPU_STATE, 0xffffffff);
5281 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5282 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5288 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5291 (offset == RX_CPU_BASE ? "RX" : "TX"));
5295 /* Clear firmware's nvram arbitration. */
5296 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5297 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5302 unsigned int text_base;
5303 unsigned int text_len;
5304 const u32 *text_data;
5305 unsigned int rodata_base;
5306 unsigned int rodata_len;
5307 const u32 *rodata_data;
5308 unsigned int data_base;
5309 unsigned int data_len;
5310 const u32 *data_data;
5313 /* tp->lock is held. */
5314 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5315 int cpu_scratch_size, struct fw_info *info)
5317 int err, lock_err, i;
5318 void (*write_op)(struct tg3 *, u32, u32);
5320 if (cpu_base == TX_CPU_BASE &&
5321 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5322 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5323 "TX cpu firmware on %s which is 5705.\n",
5328 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5329 write_op = tg3_write_mem;
5331 write_op = tg3_write_indirect_reg32;
5333 /* It is possible that bootcode is still loading at this point.
5334 * Get the nvram lock first before halting the cpu.
5336 lock_err = tg3_nvram_lock(tp);
5337 err = tg3_halt_cpu(tp, cpu_base);
5339 tg3_nvram_unlock(tp);
5343 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5344 write_op(tp, cpu_scratch_base + i, 0);
5345 tw32(cpu_base + CPU_STATE, 0xffffffff);
5346 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5347 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5348 write_op(tp, (cpu_scratch_base +
5349 (info->text_base & 0xffff) +
5352 info->text_data[i] : 0));
5353 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5354 write_op(tp, (cpu_scratch_base +
5355 (info->rodata_base & 0xffff) +
5357 (info->rodata_data ?
5358 info->rodata_data[i] : 0));
5359 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5360 write_op(tp, (cpu_scratch_base +
5361 (info->data_base & 0xffff) +
5364 info->data_data[i] : 0));
5372 /* tp->lock is held. */
5373 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5375 struct fw_info info;
5378 info.text_base = TG3_FW_TEXT_ADDR;
5379 info.text_len = TG3_FW_TEXT_LEN;
5380 info.text_data = &tg3FwText[0];
5381 info.rodata_base = TG3_FW_RODATA_ADDR;
5382 info.rodata_len = TG3_FW_RODATA_LEN;
5383 info.rodata_data = &tg3FwRodata[0];
5384 info.data_base = TG3_FW_DATA_ADDR;
5385 info.data_len = TG3_FW_DATA_LEN;
5386 info.data_data = NULL;
5388 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5389 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5394 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5395 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5400 /* Now startup only the RX cpu. */
5401 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5402 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5404 for (i = 0; i < 5; i++) {
5405 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5407 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5408 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5409 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5413 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5414 "to set RX CPU PC, is %08x should be %08x\n",
5415 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5419 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5420 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5426 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5427 #define TG3_TSO_FW_RELASE_MINOR 0x6
5428 #define TG3_TSO_FW_RELEASE_FIX 0x0
5429 #define TG3_TSO_FW_START_ADDR 0x08000000
5430 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5431 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5432 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5433 #define TG3_TSO_FW_RODATA_LEN 0x60
5434 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5435 #define TG3_TSO_FW_DATA_LEN 0x30
5436 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5437 #define TG3_TSO_FW_SBSS_LEN 0x2c
5438 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5439 #define TG3_TSO_FW_BSS_LEN 0x894
5441 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5442 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5443 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5444 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5445 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5446 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5447 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5448 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5449 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5450 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5451 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5452 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5453 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5454 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5455 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5456 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5457 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5458 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5459 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5460 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5461 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5462 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5463 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5464 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5465 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5466 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5467 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5468 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5469 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5470 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5471 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5472 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5473 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5474 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5475 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5476 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5477 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5478 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5479 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5480 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5481 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5482 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5483 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5484 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5485 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5486 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5487 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5488 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5489 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5490 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5491 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5492 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5493 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5494 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5495 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5496 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5497 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5498 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5499 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5500 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5501 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5502 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5503 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5504 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5505 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5506 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5507 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5508 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5509 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5510 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5511 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5512 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5513 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5514 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5515 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5516 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5517 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5518 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5519 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5520 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5521 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5522 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5523 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5524 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5525 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5526 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5527 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5528 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5529 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5530 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5531 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5532 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5533 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5534 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5535 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5536 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5537 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5538 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5539 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5540 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5541 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5542 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5543 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5544 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5545 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5546 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5547 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5548 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5549 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5550 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5551 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5552 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5553 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5554 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5555 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5556 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5557 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5558 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5559 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5560 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5561 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5562 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5563 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5564 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5565 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5566 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5567 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5568 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5569 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5570 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5571 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5572 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5573 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5574 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5575 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5576 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5577 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5578 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5579 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5580 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5581 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5582 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5583 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5584 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5585 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5586 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5587 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5588 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5589 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5590 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5591 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5592 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5593 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5594 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5595 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5596 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5597 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5598 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5599 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5600 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5601 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5602 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5603 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5604 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5605 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5606 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5607 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5608 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5609 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5610 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5611 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5612 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5613 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5614 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5615 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5616 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5617 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5618 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5619 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5620 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5621 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5622 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5623 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5624 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5625 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5626 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5627 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5628 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5629 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5630 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5631 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5632 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5633 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5634 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5635 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5636 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5637 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5638 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5639 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5640 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5641 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5642 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5643 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5644 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5645 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5646 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5647 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5648 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5649 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5650 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5651 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5652 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5653 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5654 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5655 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5656 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5657 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5658 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5659 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5660 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5661 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5662 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5663 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5664 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5665 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5666 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5667 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5668 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5669 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5670 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5671 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5672 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5673 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5674 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5675 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5676 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5677 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5678 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5679 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5680 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5681 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5682 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5683 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5684 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5685 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5686 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5687 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5688 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5689 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5690 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5691 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5692 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5693 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5694 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5695 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5696 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5697 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5698 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5699 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5700 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5701 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5702 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5703 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5704 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5705 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5706 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5707 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5708 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5709 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5710 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5711 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5712 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5713 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5714 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5715 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5716 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5717 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5718 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5719 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5720 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5721 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5722 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5723 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5724 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5725 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5728 static const u32 tg3TsoFwRodata[] = {
5729 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5730 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5731 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5732 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5736 static const u32 tg3TsoFwData[] = {
5737 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5738 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5742 /* 5705 needs a special version of the TSO firmware. */
5743 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5744 #define TG3_TSO5_FW_RELASE_MINOR 0x2
5745 #define TG3_TSO5_FW_RELEASE_FIX 0x0
5746 #define TG3_TSO5_FW_START_ADDR 0x00010000
5747 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5748 #define TG3_TSO5_FW_TEXT_LEN 0xe90
5749 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5750 #define TG3_TSO5_FW_RODATA_LEN 0x50
5751 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5752 #define TG3_TSO5_FW_DATA_LEN 0x20
5753 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5754 #define TG3_TSO5_FW_SBSS_LEN 0x28
5755 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5756 #define TG3_TSO5_FW_BSS_LEN 0x88
5758 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5759 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5760 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5761 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5762 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5763 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5764 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5765 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5766 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5767 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5768 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5769 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5770 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5771 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5772 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5773 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5774 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5775 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5776 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5777 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5778 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5779 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5780 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5781 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5782 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5783 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5784 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5785 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5786 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5787 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5788 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5789 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5790 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5791 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5792 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5793 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5794 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5795 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5796 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5797 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5798 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5799 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5800 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5801 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5802 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5803 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5804 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5805 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5806 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5807 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5808 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5809 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5810 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5811 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5812 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5813 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5814 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5815 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5816 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5817 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5818 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5819 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5820 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5821 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5822 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5823 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5824 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5825 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5826 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5827 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5828 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5829 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5830 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5831 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5832 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5833 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5834 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5835 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5836 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5837 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5838 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5839 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5840 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5841 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5842 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5843 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5844 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5845 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5846 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5847 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5848 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5849 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5850 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5851 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5852 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5853 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5854 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5855 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5856 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5857 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5858 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5859 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5860 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5861 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5862 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5863 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5864 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5865 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5866 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5867 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5868 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5869 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5870 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5871 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5872 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5873 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5874 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5875 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5876 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5877 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5878 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5879 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5880 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5881 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5882 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5883 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5884 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5885 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5886 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5887 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5888 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5889 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5890 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5891 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5892 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5893 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5894 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5895 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5896 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5897 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5898 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5899 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5900 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5901 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5902 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5903 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5904 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5905 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5906 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5907 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5908 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5909 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5910 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5911 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5912 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5913 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5914 0x00000000, 0x00000000, 0x00000000,
5917 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5918 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5919 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5920 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5921 0x00000000, 0x00000000, 0x00000000,
5924 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5925 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5926 0x00000000, 0x00000000, 0x00000000,
5929 /* tp->lock is held. */
5930 static int tg3_load_tso_firmware(struct tg3 *tp)
5932 struct fw_info info;
5933 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5936 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5940 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5941 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5942 info.text_data = &tg3Tso5FwText[0];
5943 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5944 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5945 info.rodata_data = &tg3Tso5FwRodata[0];
5946 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5947 info.data_len = TG3_TSO5_FW_DATA_LEN;
5948 info.data_data = &tg3Tso5FwData[0];
5949 cpu_base = RX_CPU_BASE;
5950 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5951 cpu_scratch_size = (info.text_len +
5954 TG3_TSO5_FW_SBSS_LEN +
5955 TG3_TSO5_FW_BSS_LEN);
5957 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5958 info.text_len = TG3_TSO_FW_TEXT_LEN;
5959 info.text_data = &tg3TsoFwText[0];
5960 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5961 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5962 info.rodata_data = &tg3TsoFwRodata[0];
5963 info.data_base = TG3_TSO_FW_DATA_ADDR;
5964 info.data_len = TG3_TSO_FW_DATA_LEN;
5965 info.data_data = &tg3TsoFwData[0];
5966 cpu_base = TX_CPU_BASE;
5967 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5968 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5971 err = tg3_load_firmware_cpu(tp, cpu_base,
5972 cpu_scratch_base, cpu_scratch_size,
5977 /* Now startup the cpu. */
5978 tw32(cpu_base + CPU_STATE, 0xffffffff);
5979 tw32_f(cpu_base + CPU_PC, info.text_base);
5981 for (i = 0; i < 5; i++) {
5982 if (tr32(cpu_base + CPU_PC) == info.text_base)
5984 tw32(cpu_base + CPU_STATE, 0xffffffff);
5985 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5986 tw32_f(cpu_base + CPU_PC, info.text_base);
5990 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5991 "to set CPU PC, is %08x should be %08x\n",
5992 tp->dev->name, tr32(cpu_base + CPU_PC),
5996 tw32(cpu_base + CPU_STATE, 0xffffffff);
5997 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6002 /* tp->lock is held. */
6003 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6005 u32 addr_high, addr_low;
6008 addr_high = ((tp->dev->dev_addr[0] << 8) |
6009 tp->dev->dev_addr[1]);
6010 addr_low = ((tp->dev->dev_addr[2] << 24) |
6011 (tp->dev->dev_addr[3] << 16) |
6012 (tp->dev->dev_addr[4] << 8) |
6013 (tp->dev->dev_addr[5] << 0));
6014 for (i = 0; i < 4; i++) {
6015 if (i == 1 && skip_mac_1)
6017 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6018 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6023 for (i = 0; i < 12; i++) {
6024 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6025 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6029 addr_high = (tp->dev->dev_addr[0] +
6030 tp->dev->dev_addr[1] +
6031 tp->dev->dev_addr[2] +
6032 tp->dev->dev_addr[3] +
6033 tp->dev->dev_addr[4] +
6034 tp->dev->dev_addr[5]) &
6035 TX_BACKOFF_SEED_MASK;
6036 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6039 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6041 struct tg3 *tp = netdev_priv(dev);
6042 struct sockaddr *addr = p;
6043 int err = 0, skip_mac_1 = 0;
6045 if (!is_valid_ether_addr(addr->sa_data))
6048 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6050 if (!netif_running(dev))
6053 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6054 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6056 addr0_high = tr32(MAC_ADDR_0_HIGH);
6057 addr0_low = tr32(MAC_ADDR_0_LOW);
6058 addr1_high = tr32(MAC_ADDR_1_HIGH);
6059 addr1_low = tr32(MAC_ADDR_1_LOW);
6061 /* Skip MAC addr 1 if ASF is using it. */
6062 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6063 !(addr1_high == 0 && addr1_low == 0))
6066 spin_lock_bh(&tp->lock);
6067 __tg3_set_mac_addr(tp, skip_mac_1);
6068 spin_unlock_bh(&tp->lock);
6073 /* tp->lock is held. */
6074 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6075 dma_addr_t mapping, u32 maxlen_flags,
6079 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6080 ((u64) mapping >> 32));
6082 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6083 ((u64) mapping & 0xffffffff));
6085 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6088 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6090 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6094 static void __tg3_set_rx_mode(struct net_device *);
6095 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6097 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6098 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6099 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6100 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6101 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6102 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6103 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6105 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6106 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6107 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6108 u32 val = ec->stats_block_coalesce_usecs;
6110 if (!netif_carrier_ok(tp->dev))
6113 tw32(HOSTCC_STAT_COAL_TICKS, val);
6117 /* tp->lock is held. */
6118 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6120 u32 val, rdmac_mode;
6123 tg3_disable_ints(tp);
6127 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6129 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6130 tg3_abort_hw(tp, 1);
6136 err = tg3_chip_reset(tp);
6140 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6142 /* This works around an issue with Athlon chipsets on
6143 * B3 tigon3 silicon. This bit has no effect on any
6144 * other revision. But do not set this on PCI Express
6147 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6148 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6149 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6151 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6152 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6153 val = tr32(TG3PCI_PCISTATE);
6154 val |= PCISTATE_RETRY_SAME_DMA;
6155 tw32(TG3PCI_PCISTATE, val);
6158 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6159 /* Enable some hw fixes. */
6160 val = tr32(TG3PCI_MSI_DATA);
6161 val |= (1 << 26) | (1 << 28) | (1 << 29);
6162 tw32(TG3PCI_MSI_DATA, val);
6165 /* Descriptor ring init may make accesses to the
6166 * NIC SRAM area to setup the TX descriptors, so we
6167 * can only do this after the hardware has been
6168 * successfully reset.
6170 err = tg3_init_rings(tp);
6174 /* This value is determined during the probe time DMA
6175 * engine test, tg3_test_dma.
6177 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6179 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6180 GRC_MODE_4X_NIC_SEND_RINGS |
6181 GRC_MODE_NO_TX_PHDR_CSUM |
6182 GRC_MODE_NO_RX_PHDR_CSUM);
6183 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6185 /* Pseudo-header checksum is done by hardware logic and not
6186 * the offload processers, so make the chip do the pseudo-
6187 * header checksums on receive. For transmit it is more
6188 * convenient to do the pseudo-header checksum in software
6189 * as Linux does that on transmit for us in all cases.
6191 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6195 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6197 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6198 val = tr32(GRC_MISC_CFG);
6200 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6201 tw32(GRC_MISC_CFG, val);
6203 /* Initialize MBUF/DESC pool. */
6204 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6206 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6207 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6208 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6209 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6211 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6212 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6213 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6215 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6218 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6219 TG3_TSO5_FW_RODATA_LEN +
6220 TG3_TSO5_FW_DATA_LEN +
6221 TG3_TSO5_FW_SBSS_LEN +
6222 TG3_TSO5_FW_BSS_LEN);
6223 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6224 tw32(BUFMGR_MB_POOL_ADDR,
6225 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6226 tw32(BUFMGR_MB_POOL_SIZE,
6227 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6230 if (tp->dev->mtu <= ETH_DATA_LEN) {
6231 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6232 tp->bufmgr_config.mbuf_read_dma_low_water);
6233 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6234 tp->bufmgr_config.mbuf_mac_rx_low_water);
6235 tw32(BUFMGR_MB_HIGH_WATER,
6236 tp->bufmgr_config.mbuf_high_water);
6238 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6239 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6240 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6241 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6242 tw32(BUFMGR_MB_HIGH_WATER,
6243 tp->bufmgr_config.mbuf_high_water_jumbo);
6245 tw32(BUFMGR_DMA_LOW_WATER,
6246 tp->bufmgr_config.dma_low_water);
6247 tw32(BUFMGR_DMA_HIGH_WATER,
6248 tp->bufmgr_config.dma_high_water);
6250 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6251 for (i = 0; i < 2000; i++) {
6252 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6257 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6262 /* Setup replenish threshold. */
6263 val = tp->rx_pending / 8;
6266 else if (val > tp->rx_std_max_post)
6267 val = tp->rx_std_max_post;
6268 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6269 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6270 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6272 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6273 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6276 tw32(RCVBDI_STD_THRESH, val);
6278 /* Initialize TG3_BDINFO's at:
6279 * RCVDBDI_STD_BD: standard eth size rx ring
6280 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6281 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6284 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6285 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6286 * ring attribute flags
6287 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6289 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6290 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6292 * The size of each ring is fixed in the firmware, but the location is
6295 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6296 ((u64) tp->rx_std_mapping >> 32));
6297 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6298 ((u64) tp->rx_std_mapping & 0xffffffff));
6299 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6300 NIC_SRAM_RX_BUFFER_DESC);
6302 /* Don't even try to program the JUMBO/MINI buffer descriptor
6305 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6306 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6307 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6309 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6310 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6312 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6313 BDINFO_FLAGS_DISABLED);
6315 /* Setup replenish threshold. */
6316 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6318 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6319 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6320 ((u64) tp->rx_jumbo_mapping >> 32));
6321 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6322 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6323 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6324 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6325 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6326 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6328 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6329 BDINFO_FLAGS_DISABLED);
6334 /* There is only one send ring on 5705/5750, no need to explicitly
6335 * disable the others.
6337 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6338 /* Clear out send RCB ring in SRAM. */
6339 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6340 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6341 BDINFO_FLAGS_DISABLED);
6346 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6347 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6349 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6350 tp->tx_desc_mapping,
6351 (TG3_TX_RING_SIZE <<
6352 BDINFO_FLAGS_MAXLEN_SHIFT),
6353 NIC_SRAM_TX_BUFFER_DESC);
6355 /* There is only one receive return ring on 5705/5750, no need
6356 * to explicitly disable the others.
6358 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6359 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6360 i += TG3_BDINFO_SIZE) {
6361 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6362 BDINFO_FLAGS_DISABLED);
6367 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6369 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6371 (TG3_RX_RCB_RING_SIZE(tp) <<
6372 BDINFO_FLAGS_MAXLEN_SHIFT),
6375 tp->rx_std_ptr = tp->rx_pending;
6376 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6379 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6380 tp->rx_jumbo_pending : 0;
6381 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6384 /* Initialize MAC address and backoff seed. */
6385 __tg3_set_mac_addr(tp, 0);
6387 /* MTU + ethernet header + FCS + optional VLAN tag */
6388 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6390 /* The slot time is changed by tg3_setup_phy if we
6391 * run at gigabit with half duplex.
6393 tw32(MAC_TX_LENGTHS,
6394 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6395 (6 << TX_LENGTHS_IPG_SHIFT) |
6396 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6398 /* Receive rules. */
6399 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6400 tw32(RCVLPC_CONFIG, 0x0181);
6402 /* Calculate RDMAC_MODE setting early, we need it to determine
6403 * the RCVLPC_STATE_ENABLE mask.
6405 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6406 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6407 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6408 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6409 RDMAC_MODE_LNGREAD_ENAB);
6411 /* If statement applies to 5705 and 5750 PCI devices only */
6412 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6413 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6414 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6415 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6416 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6417 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6418 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6419 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6420 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6424 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6425 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6427 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6428 rdmac_mode |= (1 << 27);
6430 /* Receive/send statistics. */
6431 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6432 val = tr32(RCVLPC_STATS_ENABLE);
6433 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6434 tw32(RCVLPC_STATS_ENABLE, val);
6435 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6436 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6437 val = tr32(RCVLPC_STATS_ENABLE);
6438 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6439 tw32(RCVLPC_STATS_ENABLE, val);
6441 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6443 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6444 tw32(SNDDATAI_STATSENAB, 0xffffff);
6445 tw32(SNDDATAI_STATSCTRL,
6446 (SNDDATAI_SCTRL_ENABLE |
6447 SNDDATAI_SCTRL_FASTUPD));
6449 /* Setup host coalescing engine. */
6450 tw32(HOSTCC_MODE, 0);
6451 for (i = 0; i < 2000; i++) {
6452 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6457 __tg3_set_coalesce(tp, &tp->coal);
6459 /* set status block DMA address */
6460 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6461 ((u64) tp->status_mapping >> 32));
6462 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6463 ((u64) tp->status_mapping & 0xffffffff));
6465 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6466 /* Status/statistics block address. See tg3_timer,
6467 * the tg3_periodic_fetch_stats call there, and
6468 * tg3_get_stats to see how this works for 5705/5750 chips.
6470 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6471 ((u64) tp->stats_mapping >> 32));
6472 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6473 ((u64) tp->stats_mapping & 0xffffffff));
6474 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6475 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6478 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6480 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6481 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6482 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6483 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6485 /* Clear statistics/status block in chip, and status block in ram. */
6486 for (i = NIC_SRAM_STATS_BLK;
6487 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6489 tg3_write_mem(tp, i, 0);
6492 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6494 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6495 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6496 /* reset to prevent losing 1st rx packet intermittently */
6497 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6501 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6502 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6503 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6504 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6505 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6506 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6507 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6510 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6511 * If TG3_FLG2_IS_NIC is zero, we should read the
6512 * register to preserve the GPIO settings for LOMs. The GPIOs,
6513 * whether used as inputs or outputs, are set by boot code after
6516 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6519 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6520 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6521 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6523 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6524 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6525 GRC_LCLCTRL_GPIO_OUTPUT3;
6527 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6528 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6530 tp->grc_local_ctrl &= ~gpio_mask;
6531 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6533 /* GPIO1 must be driven high for eeprom write protect */
6534 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6535 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6536 GRC_LCLCTRL_GPIO_OUTPUT1);
6538 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6541 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6544 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6545 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6549 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6550 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6551 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6552 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6553 WDMAC_MODE_LNGREAD_ENAB);
6555 /* If statement applies to 5705 and 5750 PCI devices only */
6556 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6557 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6558 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6559 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6560 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6561 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6563 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6564 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6565 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6566 val |= WDMAC_MODE_RX_ACCEL;
6570 /* Enable host coalescing bug fix */
6571 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6572 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6575 tw32_f(WDMAC_MODE, val);
6578 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6579 val = tr32(TG3PCI_X_CAPS);
6580 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6581 val &= ~PCIX_CAPS_BURST_MASK;
6582 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6583 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6584 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6585 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6587 tw32(TG3PCI_X_CAPS, val);
6590 tw32_f(RDMAC_MODE, rdmac_mode);
6593 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6594 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6595 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6596 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6597 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6598 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6599 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6600 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6601 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6602 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6603 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6604 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6606 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6607 err = tg3_load_5701_a0_firmware_fix(tp);
6612 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6613 err = tg3_load_tso_firmware(tp);
6618 tp->tx_mode = TX_MODE_ENABLE;
6619 tw32_f(MAC_TX_MODE, tp->tx_mode);
6622 tp->rx_mode = RX_MODE_ENABLE;
6623 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6624 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6626 tw32_f(MAC_RX_MODE, tp->rx_mode);
6629 if (tp->link_config.phy_is_low_power) {
6630 tp->link_config.phy_is_low_power = 0;
6631 tp->link_config.speed = tp->link_config.orig_speed;
6632 tp->link_config.duplex = tp->link_config.orig_duplex;
6633 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6636 tp->mi_mode = MAC_MI_MODE_BASE;
6637 tw32_f(MAC_MI_MODE, tp->mi_mode);
6640 tw32(MAC_LED_CTRL, tp->led_ctrl);
6642 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6643 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6644 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6647 tw32_f(MAC_RX_MODE, tp->rx_mode);
6650 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6651 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6652 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6653 /* Set drive transmission level to 1.2V */
6654 /* only if the signal pre-emphasis bit is not set */
6655 val = tr32(MAC_SERDES_CFG);
6658 tw32(MAC_SERDES_CFG, val);
6660 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6661 tw32(MAC_SERDES_CFG, 0x616000);
6664 /* Prevent chip from dropping frames when flow control
6667 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6669 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6670 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6671 /* Use hardware link auto-negotiation */
6672 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6675 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6676 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6679 tmp = tr32(SERDES_RX_CTRL);
6680 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6681 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6682 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6683 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6686 err = tg3_setup_phy(tp, 0);
6690 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6691 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6694 /* Clear CRC stats. */
6695 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6696 tg3_writephy(tp, MII_TG3_TEST1,
6697 tmp | MII_TG3_TEST1_CRC_EN);
6698 tg3_readphy(tp, 0x14, &tmp);
6702 __tg3_set_rx_mode(tp->dev);
6704 /* Initialize receive rules. */
6705 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6706 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6707 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6708 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6710 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6711 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6715 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6719 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6721 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6723 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6725 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6727 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6729 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6731 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6733 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6735 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6737 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6739 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6741 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6743 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6745 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6753 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6758 /* Called at device open time to get the chip ready for
6759 * packet processing. Invoked with tp->lock held.
6761 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6765 /* Force the chip into D0. */
6766 err = tg3_set_power_state(tp, PCI_D0);
6770 tg3_switch_clocks(tp);
6772 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6774 err = tg3_reset_hw(tp, reset_phy);
6780 #define TG3_STAT_ADD32(PSTAT, REG) \
6781 do { u32 __val = tr32(REG); \
6782 (PSTAT)->low += __val; \
6783 if ((PSTAT)->low < __val) \
6784 (PSTAT)->high += 1; \
6787 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6789 struct tg3_hw_stats *sp = tp->hw_stats;
6791 if (!netif_carrier_ok(tp->dev))
6794 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6795 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6796 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6797 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6798 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6799 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6800 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6801 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6802 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6803 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6804 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6805 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6806 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6808 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6809 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6810 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6811 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6812 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6813 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6814 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6815 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6816 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6817 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6818 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6819 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6820 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6821 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6823 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6824 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6825 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6828 static void tg3_timer(unsigned long __opaque)
6830 struct tg3 *tp = (struct tg3 *) __opaque;
6835 spin_lock(&tp->lock);
6837 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6838 /* All of this garbage is because when using non-tagged
6839 * IRQ status the mailbox/status_block protocol the chip
6840 * uses with the cpu is race prone.
6842 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6843 tw32(GRC_LOCAL_CTRL,
6844 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6846 tw32(HOSTCC_MODE, tp->coalesce_mode |
6847 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6850 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6851 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6852 spin_unlock(&tp->lock);
6853 schedule_work(&tp->reset_task);
6858 /* This part only runs once per second. */
6859 if (!--tp->timer_counter) {
6860 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6861 tg3_periodic_fetch_stats(tp);
6863 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6867 mac_stat = tr32(MAC_STATUS);
6870 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6871 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6873 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6877 tg3_setup_phy(tp, 0);
6878 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6879 u32 mac_stat = tr32(MAC_STATUS);
6882 if (netif_carrier_ok(tp->dev) &&
6883 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6886 if (! netif_carrier_ok(tp->dev) &&
6887 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6888 MAC_STATUS_SIGNAL_DET))) {
6892 if (!tp->serdes_counter) {
6895 ~MAC_MODE_PORT_MODE_MASK));
6897 tw32_f(MAC_MODE, tp->mac_mode);
6900 tg3_setup_phy(tp, 0);
6902 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6903 tg3_serdes_parallel_detect(tp);
6905 tp->timer_counter = tp->timer_multiplier;
6908 /* Heartbeat is only sent once every 2 seconds.
6910 * The heartbeat is to tell the ASF firmware that the host
6911 * driver is still alive. In the event that the OS crashes,
6912 * ASF needs to reset the hardware to free up the FIFO space
6913 * that may be filled with rx packets destined for the host.
6914 * If the FIFO is full, ASF will no longer function properly.
6916 * Unintended resets have been reported on real time kernels
6917 * where the timer doesn't run on time. Netpoll will also have
6920 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6921 * to check the ring condition when the heartbeat is expiring
6922 * before doing the reset. This will prevent most unintended
6925 if (!--tp->asf_counter) {
6926 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6929 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6930 FWCMD_NICDRV_ALIVE3);
6931 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6932 /* 5 seconds timeout */
6933 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6934 val = tr32(GRC_RX_CPU_EVENT);
6936 tw32(GRC_RX_CPU_EVENT, val);
6938 tp->asf_counter = tp->asf_multiplier;
6941 spin_unlock(&tp->lock);
6944 tp->timer.expires = jiffies + tp->timer_offset;
6945 add_timer(&tp->timer);
6948 static int tg3_request_irq(struct tg3 *tp)
6951 unsigned long flags;
6952 struct net_device *dev = tp->dev;
6954 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6956 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6958 flags = IRQF_SAMPLE_RANDOM;
6961 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6962 fn = tg3_interrupt_tagged;
6963 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6965 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6968 static int tg3_test_interrupt(struct tg3 *tp)
6970 struct net_device *dev = tp->dev;
6971 int err, i, intr_ok = 0;
6973 if (!netif_running(dev))
6976 tg3_disable_ints(tp);
6978 free_irq(tp->pdev->irq, dev);
6980 err = request_irq(tp->pdev->irq, tg3_test_isr,
6981 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6985 tp->hw_status->status &= ~SD_STATUS_UPDATED;
6986 tg3_enable_ints(tp);
6988 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6991 for (i = 0; i < 5; i++) {
6992 u32 int_mbox, misc_host_ctrl;
6994 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6996 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6998 if ((int_mbox != 0) ||
6999 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7007 tg3_disable_ints(tp);
7009 free_irq(tp->pdev->irq, dev);
7011 err = tg3_request_irq(tp);
7022 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7023 * successfully restored
7025 static int tg3_test_msi(struct tg3 *tp)
7027 struct net_device *dev = tp->dev;
7031 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7034 /* Turn off SERR reporting in case MSI terminates with Master
7037 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7038 pci_write_config_word(tp->pdev, PCI_COMMAND,
7039 pci_cmd & ~PCI_COMMAND_SERR);
7041 err = tg3_test_interrupt(tp);
7043 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7048 /* other failures */
7052 /* MSI test failed, go back to INTx mode */
7053 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7054 "switching to INTx mode. Please report this failure to "
7055 "the PCI maintainer and include system chipset information.\n",
7058 free_irq(tp->pdev->irq, dev);
7059 pci_disable_msi(tp->pdev);
7061 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7063 err = tg3_request_irq(tp);
7067 /* Need to reset the chip because the MSI cycle may have terminated
7068 * with Master Abort.
7070 tg3_full_lock(tp, 1);
7072 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7073 err = tg3_init_hw(tp, 1);
7075 tg3_full_unlock(tp);
7078 free_irq(tp->pdev->irq, dev);
7083 static int tg3_open(struct net_device *dev)
7085 struct tg3 *tp = netdev_priv(dev);
7088 netif_carrier_off(tp->dev);
7090 tg3_full_lock(tp, 0);
7092 err = tg3_set_power_state(tp, PCI_D0);
7094 tg3_full_unlock(tp);
7098 tg3_disable_ints(tp);
7099 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7101 tg3_full_unlock(tp);
7103 /* The placement of this call is tied
7104 * to the setup and use of Host TX descriptors.
7106 err = tg3_alloc_consistent(tp);
7110 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7111 /* All MSI supporting chips should support tagged
7112 * status. Assert that this is the case.
7114 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7115 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7116 "Not using MSI.\n", tp->dev->name);
7117 } else if (pci_enable_msi(tp->pdev) == 0) {
7120 /* Hardware bug - MSI won't work if INTX disabled. */
7121 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7122 pci_intx(tp->pdev, 1);
7124 msi_mode = tr32(MSGINT_MODE);
7125 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7126 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7129 err = tg3_request_irq(tp);
7132 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7133 pci_disable_msi(tp->pdev);
7134 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7136 tg3_free_consistent(tp);
7140 napi_enable(&tp->napi);
7142 tg3_full_lock(tp, 0);
7144 err = tg3_init_hw(tp, 1);
7146 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7149 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7150 tp->timer_offset = HZ;
7152 tp->timer_offset = HZ / 10;
7154 BUG_ON(tp->timer_offset > HZ);
7155 tp->timer_counter = tp->timer_multiplier =
7156 (HZ / tp->timer_offset);
7157 tp->asf_counter = tp->asf_multiplier =
7158 ((HZ / tp->timer_offset) * 2);
7160 init_timer(&tp->timer);
7161 tp->timer.expires = jiffies + tp->timer_offset;
7162 tp->timer.data = (unsigned long) tp;
7163 tp->timer.function = tg3_timer;
7166 tg3_full_unlock(tp);
7169 napi_disable(&tp->napi);
7170 free_irq(tp->pdev->irq, dev);
7171 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7172 pci_disable_msi(tp->pdev);
7173 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7175 tg3_free_consistent(tp);
7179 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7180 err = tg3_test_msi(tp);
7183 tg3_full_lock(tp, 0);
7185 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7186 pci_disable_msi(tp->pdev);
7187 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7189 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7191 tg3_free_consistent(tp);
7193 tg3_full_unlock(tp);
7195 napi_disable(&tp->napi);
7200 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7201 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7202 u32 val = tr32(PCIE_TRANSACTION_CFG);
7204 tw32(PCIE_TRANSACTION_CFG,
7205 val | PCIE_TRANS_CFG_1SHOT_MSI);
7210 tg3_full_lock(tp, 0);
7212 add_timer(&tp->timer);
7213 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7214 tg3_enable_ints(tp);
7216 tg3_full_unlock(tp);
7218 netif_start_queue(dev);
7224 /*static*/ void tg3_dump_state(struct tg3 *tp)
7226 u32 val32, val32_2, val32_3, val32_4, val32_5;
7230 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7231 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7232 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7236 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7237 tr32(MAC_MODE), tr32(MAC_STATUS));
7238 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7239 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7240 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7241 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7242 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7243 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7245 /* Send data initiator control block */
7246 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7247 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7248 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7249 tr32(SNDDATAI_STATSCTRL));
7251 /* Send data completion control block */
7252 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7254 /* Send BD ring selector block */
7255 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7256 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7258 /* Send BD initiator control block */
7259 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7260 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7262 /* Send BD completion control block */
7263 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7265 /* Receive list placement control block */
7266 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7267 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7268 printk(" RCVLPC_STATSCTRL[%08x]\n",
7269 tr32(RCVLPC_STATSCTRL));
7271 /* Receive data and receive BD initiator control block */
7272 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7273 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7275 /* Receive data completion control block */
7276 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7279 /* Receive BD initiator control block */
7280 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7281 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7283 /* Receive BD completion control block */
7284 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7285 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7287 /* Receive list selector control block */
7288 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7289 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7291 /* Mbuf cluster free block */
7292 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7293 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7295 /* Host coalescing control block */
7296 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7297 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7298 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7299 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7300 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7301 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7302 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7303 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7304 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7305 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7306 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7307 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7309 /* Memory arbiter control block */
7310 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7311 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7313 /* Buffer manager control block */
7314 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7315 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7316 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7317 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7318 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7319 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7320 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7321 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7323 /* Read DMA control block */
7324 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7325 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7327 /* Write DMA control block */
7328 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7329 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7331 /* DMA completion block */
7332 printk("DEBUG: DMAC_MODE[%08x]\n",
7336 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7337 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7338 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7339 tr32(GRC_LOCAL_CTRL));
7342 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7343 tr32(RCVDBDI_JUMBO_BD + 0x0),
7344 tr32(RCVDBDI_JUMBO_BD + 0x4),
7345 tr32(RCVDBDI_JUMBO_BD + 0x8),
7346 tr32(RCVDBDI_JUMBO_BD + 0xc));
7347 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7348 tr32(RCVDBDI_STD_BD + 0x0),
7349 tr32(RCVDBDI_STD_BD + 0x4),
7350 tr32(RCVDBDI_STD_BD + 0x8),
7351 tr32(RCVDBDI_STD_BD + 0xc));
7352 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7353 tr32(RCVDBDI_MINI_BD + 0x0),
7354 tr32(RCVDBDI_MINI_BD + 0x4),
7355 tr32(RCVDBDI_MINI_BD + 0x8),
7356 tr32(RCVDBDI_MINI_BD + 0xc));
7358 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7359 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7360 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7361 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7362 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7363 val32, val32_2, val32_3, val32_4);
7365 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7366 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7367 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7368 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7369 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7370 val32, val32_2, val32_3, val32_4);
7372 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7373 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7374 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7375 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7376 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7377 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7378 val32, val32_2, val32_3, val32_4, val32_5);
7380 /* SW status block */
7381 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7382 tp->hw_status->status,
7383 tp->hw_status->status_tag,
7384 tp->hw_status->rx_jumbo_consumer,
7385 tp->hw_status->rx_consumer,
7386 tp->hw_status->rx_mini_consumer,
7387 tp->hw_status->idx[0].rx_producer,
7388 tp->hw_status->idx[0].tx_consumer);
7390 /* SW statistics block */
7391 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7392 ((u32 *)tp->hw_stats)[0],
7393 ((u32 *)tp->hw_stats)[1],
7394 ((u32 *)tp->hw_stats)[2],
7395 ((u32 *)tp->hw_stats)[3]);
7398 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7399 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7400 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7401 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7402 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7404 /* NIC side send descriptors. */
7405 for (i = 0; i < 6; i++) {
7408 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7409 + (i * sizeof(struct tg3_tx_buffer_desc));
7410 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7412 readl(txd + 0x0), readl(txd + 0x4),
7413 readl(txd + 0x8), readl(txd + 0xc));
7416 /* NIC side RX descriptors. */
7417 for (i = 0; i < 6; i++) {
7420 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7421 + (i * sizeof(struct tg3_rx_buffer_desc));
7422 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7424 readl(rxd + 0x0), readl(rxd + 0x4),
7425 readl(rxd + 0x8), readl(rxd + 0xc));
7426 rxd += (4 * sizeof(u32));
7427 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7429 readl(rxd + 0x0), readl(rxd + 0x4),
7430 readl(rxd + 0x8), readl(rxd + 0xc));
7433 for (i = 0; i < 6; i++) {
7436 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7437 + (i * sizeof(struct tg3_rx_buffer_desc));
7438 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7440 readl(rxd + 0x0), readl(rxd + 0x4),
7441 readl(rxd + 0x8), readl(rxd + 0xc));
7442 rxd += (4 * sizeof(u32));
7443 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7445 readl(rxd + 0x0), readl(rxd + 0x4),
7446 readl(rxd + 0x8), readl(rxd + 0xc));
7451 static struct net_device_stats *tg3_get_stats(struct net_device *);
7452 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7454 static int tg3_close(struct net_device *dev)
7456 struct tg3 *tp = netdev_priv(dev);
7458 napi_disable(&tp->napi);
7459 cancel_work_sync(&tp->reset_task);
7461 netif_stop_queue(dev);
7463 del_timer_sync(&tp->timer);
7465 tg3_full_lock(tp, 1);
7470 tg3_disable_ints(tp);
7472 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7474 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7476 tg3_full_unlock(tp);
7478 free_irq(tp->pdev->irq, dev);
7479 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7480 pci_disable_msi(tp->pdev);
7481 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7484 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7485 sizeof(tp->net_stats_prev));
7486 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7487 sizeof(tp->estats_prev));
7489 tg3_free_consistent(tp);
7491 tg3_set_power_state(tp, PCI_D3hot);
7493 netif_carrier_off(tp->dev);
7498 static inline unsigned long get_stat64(tg3_stat64_t *val)
7502 #if (BITS_PER_LONG == 32)
7505 ret = ((u64)val->high << 32) | ((u64)val->low);
7510 static unsigned long calc_crc_errors(struct tg3 *tp)
7512 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7514 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7515 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7516 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7519 spin_lock_bh(&tp->lock);
7520 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7521 tg3_writephy(tp, MII_TG3_TEST1,
7522 val | MII_TG3_TEST1_CRC_EN);
7523 tg3_readphy(tp, 0x14, &val);
7526 spin_unlock_bh(&tp->lock);
7528 tp->phy_crc_errors += val;
7530 return tp->phy_crc_errors;
7533 return get_stat64(&hw_stats->rx_fcs_errors);
7536 #define ESTAT_ADD(member) \
7537 estats->member = old_estats->member + \
7538 get_stat64(&hw_stats->member)
7540 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7542 struct tg3_ethtool_stats *estats = &tp->estats;
7543 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7544 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7549 ESTAT_ADD(rx_octets);
7550 ESTAT_ADD(rx_fragments);
7551 ESTAT_ADD(rx_ucast_packets);
7552 ESTAT_ADD(rx_mcast_packets);
7553 ESTAT_ADD(rx_bcast_packets);
7554 ESTAT_ADD(rx_fcs_errors);
7555 ESTAT_ADD(rx_align_errors);
7556 ESTAT_ADD(rx_xon_pause_rcvd);
7557 ESTAT_ADD(rx_xoff_pause_rcvd);
7558 ESTAT_ADD(rx_mac_ctrl_rcvd);
7559 ESTAT_ADD(rx_xoff_entered);
7560 ESTAT_ADD(rx_frame_too_long_errors);
7561 ESTAT_ADD(rx_jabbers);
7562 ESTAT_ADD(rx_undersize_packets);
7563 ESTAT_ADD(rx_in_length_errors);
7564 ESTAT_ADD(rx_out_length_errors);
7565 ESTAT_ADD(rx_64_or_less_octet_packets);
7566 ESTAT_ADD(rx_65_to_127_octet_packets);
7567 ESTAT_ADD(rx_128_to_255_octet_packets);
7568 ESTAT_ADD(rx_256_to_511_octet_packets);
7569 ESTAT_ADD(rx_512_to_1023_octet_packets);
7570 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7571 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7572 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7573 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7574 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7576 ESTAT_ADD(tx_octets);
7577 ESTAT_ADD(tx_collisions);
7578 ESTAT_ADD(tx_xon_sent);
7579 ESTAT_ADD(tx_xoff_sent);
7580 ESTAT_ADD(tx_flow_control);
7581 ESTAT_ADD(tx_mac_errors);
7582 ESTAT_ADD(tx_single_collisions);
7583 ESTAT_ADD(tx_mult_collisions);
7584 ESTAT_ADD(tx_deferred);
7585 ESTAT_ADD(tx_excessive_collisions);
7586 ESTAT_ADD(tx_late_collisions);
7587 ESTAT_ADD(tx_collide_2times);
7588 ESTAT_ADD(tx_collide_3times);
7589 ESTAT_ADD(tx_collide_4times);
7590 ESTAT_ADD(tx_collide_5times);
7591 ESTAT_ADD(tx_collide_6times);
7592 ESTAT_ADD(tx_collide_7times);
7593 ESTAT_ADD(tx_collide_8times);
7594 ESTAT_ADD(tx_collide_9times);
7595 ESTAT_ADD(tx_collide_10times);
7596 ESTAT_ADD(tx_collide_11times);
7597 ESTAT_ADD(tx_collide_12times);
7598 ESTAT_ADD(tx_collide_13times);
7599 ESTAT_ADD(tx_collide_14times);
7600 ESTAT_ADD(tx_collide_15times);
7601 ESTAT_ADD(tx_ucast_packets);
7602 ESTAT_ADD(tx_mcast_packets);
7603 ESTAT_ADD(tx_bcast_packets);
7604 ESTAT_ADD(tx_carrier_sense_errors);
7605 ESTAT_ADD(tx_discards);
7606 ESTAT_ADD(tx_errors);
7608 ESTAT_ADD(dma_writeq_full);
7609 ESTAT_ADD(dma_write_prioq_full);
7610 ESTAT_ADD(rxbds_empty);
7611 ESTAT_ADD(rx_discards);
7612 ESTAT_ADD(rx_errors);
7613 ESTAT_ADD(rx_threshold_hit);
7615 ESTAT_ADD(dma_readq_full);
7616 ESTAT_ADD(dma_read_prioq_full);
7617 ESTAT_ADD(tx_comp_queue_full);
7619 ESTAT_ADD(ring_set_send_prod_index);
7620 ESTAT_ADD(ring_status_update);
7621 ESTAT_ADD(nic_irqs);
7622 ESTAT_ADD(nic_avoided_irqs);
7623 ESTAT_ADD(nic_tx_threshold_hit);
7628 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7630 struct tg3 *tp = netdev_priv(dev);
7631 struct net_device_stats *stats = &tp->net_stats;
7632 struct net_device_stats *old_stats = &tp->net_stats_prev;
7633 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7638 stats->rx_packets = old_stats->rx_packets +
7639 get_stat64(&hw_stats->rx_ucast_packets) +
7640 get_stat64(&hw_stats->rx_mcast_packets) +
7641 get_stat64(&hw_stats->rx_bcast_packets);
7643 stats->tx_packets = old_stats->tx_packets +
7644 get_stat64(&hw_stats->tx_ucast_packets) +
7645 get_stat64(&hw_stats->tx_mcast_packets) +
7646 get_stat64(&hw_stats->tx_bcast_packets);
7648 stats->rx_bytes = old_stats->rx_bytes +
7649 get_stat64(&hw_stats->rx_octets);
7650 stats->tx_bytes = old_stats->tx_bytes +
7651 get_stat64(&hw_stats->tx_octets);
7653 stats->rx_errors = old_stats->rx_errors +
7654 get_stat64(&hw_stats->rx_errors);
7655 stats->tx_errors = old_stats->tx_errors +
7656 get_stat64(&hw_stats->tx_errors) +
7657 get_stat64(&hw_stats->tx_mac_errors) +
7658 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7659 get_stat64(&hw_stats->tx_discards);
7661 stats->multicast = old_stats->multicast +
7662 get_stat64(&hw_stats->rx_mcast_packets);
7663 stats->collisions = old_stats->collisions +
7664 get_stat64(&hw_stats->tx_collisions);
7666 stats->rx_length_errors = old_stats->rx_length_errors +
7667 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7668 get_stat64(&hw_stats->rx_undersize_packets);
7670 stats->rx_over_errors = old_stats->rx_over_errors +
7671 get_stat64(&hw_stats->rxbds_empty);
7672 stats->rx_frame_errors = old_stats->rx_frame_errors +
7673 get_stat64(&hw_stats->rx_align_errors);
7674 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7675 get_stat64(&hw_stats->tx_discards);
7676 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7677 get_stat64(&hw_stats->tx_carrier_sense_errors);
7679 stats->rx_crc_errors = old_stats->rx_crc_errors +
7680 calc_crc_errors(tp);
7682 stats->rx_missed_errors = old_stats->rx_missed_errors +
7683 get_stat64(&hw_stats->rx_discards);
7688 static inline u32 calc_crc(unsigned char *buf, int len)
7696 for (j = 0; j < len; j++) {
7699 for (k = 0; k < 8; k++) {
7713 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7715 /* accept or reject all multicast frames */
7716 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7717 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7718 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7719 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7722 static void __tg3_set_rx_mode(struct net_device *dev)
7724 struct tg3 *tp = netdev_priv(dev);
7727 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7728 RX_MODE_KEEP_VLAN_TAG);
7730 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7733 #if TG3_VLAN_TAG_USED
7735 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7736 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7738 /* By definition, VLAN is disabled always in this
7741 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7742 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7745 if (dev->flags & IFF_PROMISC) {
7746 /* Promiscuous mode. */
7747 rx_mode |= RX_MODE_PROMISC;
7748 } else if (dev->flags & IFF_ALLMULTI) {
7749 /* Accept all multicast. */
7750 tg3_set_multi (tp, 1);
7751 } else if (dev->mc_count < 1) {
7752 /* Reject all multicast. */
7753 tg3_set_multi (tp, 0);
7755 /* Accept one or more multicast(s). */
7756 struct dev_mc_list *mclist;
7758 u32 mc_filter[4] = { 0, };
7763 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7764 i++, mclist = mclist->next) {
7766 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7768 regidx = (bit & 0x60) >> 5;
7770 mc_filter[regidx] |= (1 << bit);
7773 tw32(MAC_HASH_REG_0, mc_filter[0]);
7774 tw32(MAC_HASH_REG_1, mc_filter[1]);
7775 tw32(MAC_HASH_REG_2, mc_filter[2]);
7776 tw32(MAC_HASH_REG_3, mc_filter[3]);
7779 if (rx_mode != tp->rx_mode) {
7780 tp->rx_mode = rx_mode;
7781 tw32_f(MAC_RX_MODE, rx_mode);
7786 static void tg3_set_rx_mode(struct net_device *dev)
7788 struct tg3 *tp = netdev_priv(dev);
7790 if (!netif_running(dev))
7793 tg3_full_lock(tp, 0);
7794 __tg3_set_rx_mode(dev);
7795 tg3_full_unlock(tp);
7798 #define TG3_REGDUMP_LEN (32 * 1024)
7800 static int tg3_get_regs_len(struct net_device *dev)
7802 return TG3_REGDUMP_LEN;
7805 static void tg3_get_regs(struct net_device *dev,
7806 struct ethtool_regs *regs, void *_p)
7809 struct tg3 *tp = netdev_priv(dev);
7815 memset(p, 0, TG3_REGDUMP_LEN);
7817 if (tp->link_config.phy_is_low_power)
7820 tg3_full_lock(tp, 0);
7822 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
7823 #define GET_REG32_LOOP(base,len) \
7824 do { p = (u32 *)(orig_p + (base)); \
7825 for (i = 0; i < len; i += 4) \
7826 __GET_REG32((base) + i); \
7828 #define GET_REG32_1(reg) \
7829 do { p = (u32 *)(orig_p + (reg)); \
7830 __GET_REG32((reg)); \
7833 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7834 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7835 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7836 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7837 GET_REG32_1(SNDDATAC_MODE);
7838 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7839 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7840 GET_REG32_1(SNDBDC_MODE);
7841 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7842 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7843 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7844 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7845 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7846 GET_REG32_1(RCVDCC_MODE);
7847 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7848 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7849 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7850 GET_REG32_1(MBFREE_MODE);
7851 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7852 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7853 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7854 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7855 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7856 GET_REG32_1(RX_CPU_MODE);
7857 GET_REG32_1(RX_CPU_STATE);
7858 GET_REG32_1(RX_CPU_PGMCTR);
7859 GET_REG32_1(RX_CPU_HWBKPT);
7860 GET_REG32_1(TX_CPU_MODE);
7861 GET_REG32_1(TX_CPU_STATE);
7862 GET_REG32_1(TX_CPU_PGMCTR);
7863 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7864 GET_REG32_LOOP(FTQ_RESET, 0x120);
7865 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7866 GET_REG32_1(DMAC_MODE);
7867 GET_REG32_LOOP(GRC_MODE, 0x4c);
7868 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7869 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7872 #undef GET_REG32_LOOP
7875 tg3_full_unlock(tp);
7878 static int tg3_get_eeprom_len(struct net_device *dev)
7880 struct tg3 *tp = netdev_priv(dev);
7882 return tp->nvram_size;
7885 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7886 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7888 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7890 struct tg3 *tp = netdev_priv(dev);
7893 u32 i, offset, len, val, b_offset, b_count;
7895 if (tp->link_config.phy_is_low_power)
7898 offset = eeprom->offset;
7902 eeprom->magic = TG3_EEPROM_MAGIC;
7905 /* adjustments to start on required 4 byte boundary */
7906 b_offset = offset & 3;
7907 b_count = 4 - b_offset;
7908 if (b_count > len) {
7909 /* i.e. offset=1 len=2 */
7912 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7915 val = cpu_to_le32(val);
7916 memcpy(data, ((char*)&val) + b_offset, b_count);
7919 eeprom->len += b_count;
7922 /* read bytes upto the last 4 byte boundary */
7923 pd = &data[eeprom->len];
7924 for (i = 0; i < (len - (len & 3)); i += 4) {
7925 ret = tg3_nvram_read(tp, offset + i, &val);
7930 val = cpu_to_le32(val);
7931 memcpy(pd + i, &val, 4);
7936 /* read last bytes not ending on 4 byte boundary */
7937 pd = &data[eeprom->len];
7939 b_offset = offset + len - b_count;
7940 ret = tg3_nvram_read(tp, b_offset, &val);
7943 val = cpu_to_le32(val);
7944 memcpy(pd, ((char*)&val), b_count);
7945 eeprom->len += b_count;
7950 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7952 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7954 struct tg3 *tp = netdev_priv(dev);
7956 u32 offset, len, b_offset, odd_len, start, end;
7959 if (tp->link_config.phy_is_low_power)
7962 if (eeprom->magic != TG3_EEPROM_MAGIC)
7965 offset = eeprom->offset;
7968 if ((b_offset = (offset & 3))) {
7969 /* adjustments to start on required 4 byte boundary */
7970 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7973 start = cpu_to_le32(start);
7982 /* adjustments to end on required 4 byte boundary */
7984 len = (len + 3) & ~3;
7985 ret = tg3_nvram_read(tp, offset+len-4, &end);
7988 end = cpu_to_le32(end);
7992 if (b_offset || odd_len) {
7993 buf = kmalloc(len, GFP_KERNEL);
7997 memcpy(buf, &start, 4);
7999 memcpy(buf+len-4, &end, 4);
8000 memcpy(buf + b_offset, data, eeprom->len);
8003 ret = tg3_nvram_write_block(tp, offset, len, buf);
8011 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8013 struct tg3 *tp = netdev_priv(dev);
8015 cmd->supported = (SUPPORTED_Autoneg);
8017 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8018 cmd->supported |= (SUPPORTED_1000baseT_Half |
8019 SUPPORTED_1000baseT_Full);
8021 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8022 cmd->supported |= (SUPPORTED_100baseT_Half |
8023 SUPPORTED_100baseT_Full |
8024 SUPPORTED_10baseT_Half |
8025 SUPPORTED_10baseT_Full |
8027 cmd->port = PORT_TP;
8029 cmd->supported |= SUPPORTED_FIBRE;
8030 cmd->port = PORT_FIBRE;
8033 cmd->advertising = tp->link_config.advertising;
8034 if (netif_running(dev)) {
8035 cmd->speed = tp->link_config.active_speed;
8036 cmd->duplex = tp->link_config.active_duplex;
8038 cmd->phy_address = PHY_ADDR;
8039 cmd->transceiver = 0;
8040 cmd->autoneg = tp->link_config.autoneg;
8046 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8048 struct tg3 *tp = netdev_priv(dev);
8050 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8051 /* These are the only valid advertisement bits allowed. */
8052 if (cmd->autoneg == AUTONEG_ENABLE &&
8053 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8054 ADVERTISED_1000baseT_Full |
8055 ADVERTISED_Autoneg |
8058 /* Fiber can only do SPEED_1000. */
8059 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8060 (cmd->speed != SPEED_1000))
8062 /* Copper cannot force SPEED_1000. */
8063 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8064 (cmd->speed == SPEED_1000))
8066 else if ((cmd->speed == SPEED_1000) &&
8067 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8070 tg3_full_lock(tp, 0);
8072 tp->link_config.autoneg = cmd->autoneg;
8073 if (cmd->autoneg == AUTONEG_ENABLE) {
8074 tp->link_config.advertising = cmd->advertising;
8075 tp->link_config.speed = SPEED_INVALID;
8076 tp->link_config.duplex = DUPLEX_INVALID;
8078 tp->link_config.advertising = 0;
8079 tp->link_config.speed = cmd->speed;
8080 tp->link_config.duplex = cmd->duplex;
8083 tp->link_config.orig_speed = tp->link_config.speed;
8084 tp->link_config.orig_duplex = tp->link_config.duplex;
8085 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8087 if (netif_running(dev))
8088 tg3_setup_phy(tp, 1);
8090 tg3_full_unlock(tp);
8095 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8097 struct tg3 *tp = netdev_priv(dev);
8099 strcpy(info->driver, DRV_MODULE_NAME);
8100 strcpy(info->version, DRV_MODULE_VERSION);
8101 strcpy(info->fw_version, tp->fw_ver);
8102 strcpy(info->bus_info, pci_name(tp->pdev));
8105 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8107 struct tg3 *tp = netdev_priv(dev);
8109 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8110 wol->supported = WAKE_MAGIC;
8114 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8115 wol->wolopts = WAKE_MAGIC;
8116 memset(&wol->sopass, 0, sizeof(wol->sopass));
8119 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8121 struct tg3 *tp = netdev_priv(dev);
8123 if (wol->wolopts & ~WAKE_MAGIC)
8125 if ((wol->wolopts & WAKE_MAGIC) &&
8126 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8129 spin_lock_bh(&tp->lock);
8130 if (wol->wolopts & WAKE_MAGIC)
8131 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8133 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8134 spin_unlock_bh(&tp->lock);
8139 static u32 tg3_get_msglevel(struct net_device *dev)
8141 struct tg3 *tp = netdev_priv(dev);
8142 return tp->msg_enable;
8145 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8147 struct tg3 *tp = netdev_priv(dev);
8148 tp->msg_enable = value;
8151 static int tg3_set_tso(struct net_device *dev, u32 value)
8153 struct tg3 *tp = netdev_priv(dev);
8155 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8160 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8161 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8163 dev->features |= NETIF_F_TSO6;
8165 dev->features &= ~NETIF_F_TSO6;
8167 return ethtool_op_set_tso(dev, value);
8170 static int tg3_nway_reset(struct net_device *dev)
8172 struct tg3 *tp = netdev_priv(dev);
8176 if (!netif_running(dev))
8179 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8182 spin_lock_bh(&tp->lock);
8184 tg3_readphy(tp, MII_BMCR, &bmcr);
8185 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8186 ((bmcr & BMCR_ANENABLE) ||
8187 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8188 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8192 spin_unlock_bh(&tp->lock);
8197 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8199 struct tg3 *tp = netdev_priv(dev);
8201 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8202 ering->rx_mini_max_pending = 0;
8203 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8204 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8206 ering->rx_jumbo_max_pending = 0;
8208 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8210 ering->rx_pending = tp->rx_pending;
8211 ering->rx_mini_pending = 0;
8212 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8213 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8215 ering->rx_jumbo_pending = 0;
8217 ering->tx_pending = tp->tx_pending;
8220 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8222 struct tg3 *tp = netdev_priv(dev);
8223 int irq_sync = 0, err = 0;
8225 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8226 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8227 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8228 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8229 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8230 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8233 if (netif_running(dev)) {
8238 tg3_full_lock(tp, irq_sync);
8240 tp->rx_pending = ering->rx_pending;
8242 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8243 tp->rx_pending > 63)
8244 tp->rx_pending = 63;
8245 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8246 tp->tx_pending = ering->tx_pending;
8248 if (netif_running(dev)) {
8249 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8250 err = tg3_restart_hw(tp, 1);
8252 tg3_netif_start(tp);
8255 tg3_full_unlock(tp);
8260 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8262 struct tg3 *tp = netdev_priv(dev);
8264 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8265 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8266 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8269 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8271 struct tg3 *tp = netdev_priv(dev);
8272 int irq_sync = 0, err = 0;
8274 if (netif_running(dev)) {
8279 tg3_full_lock(tp, irq_sync);
8281 if (epause->autoneg)
8282 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8284 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8285 if (epause->rx_pause)
8286 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8288 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8289 if (epause->tx_pause)
8290 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8292 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8294 if (netif_running(dev)) {
8295 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8296 err = tg3_restart_hw(tp, 1);
8298 tg3_netif_start(tp);
8301 tg3_full_unlock(tp);
8306 static u32 tg3_get_rx_csum(struct net_device *dev)
8308 struct tg3 *tp = netdev_priv(dev);
8309 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8312 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8314 struct tg3 *tp = netdev_priv(dev);
8316 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8322 spin_lock_bh(&tp->lock);
8324 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8326 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8327 spin_unlock_bh(&tp->lock);
8332 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8334 struct tg3 *tp = netdev_priv(dev);
8336 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8343 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8344 ethtool_op_set_tx_ipv6_csum(dev, data);
8346 ethtool_op_set_tx_csum(dev, data);
8351 static int tg3_get_stats_count (struct net_device *dev)
8353 return TG3_NUM_STATS;
8356 static int tg3_get_test_count (struct net_device *dev)
8358 return TG3_NUM_TEST;
8361 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8363 switch (stringset) {
8365 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
8368 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
8371 WARN_ON(1); /* we need a WARN() */
8376 static int tg3_phys_id(struct net_device *dev, u32 data)
8378 struct tg3 *tp = netdev_priv(dev);
8381 if (!netif_running(tp->dev))
8387 for (i = 0; i < (data * 2); i++) {
8389 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8390 LED_CTRL_1000MBPS_ON |
8391 LED_CTRL_100MBPS_ON |
8392 LED_CTRL_10MBPS_ON |
8393 LED_CTRL_TRAFFIC_OVERRIDE |
8394 LED_CTRL_TRAFFIC_BLINK |
8395 LED_CTRL_TRAFFIC_LED);
8398 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8399 LED_CTRL_TRAFFIC_OVERRIDE);
8401 if (msleep_interruptible(500))
8404 tw32(MAC_LED_CTRL, tp->led_ctrl);
8408 static void tg3_get_ethtool_stats (struct net_device *dev,
8409 struct ethtool_stats *estats, u64 *tmp_stats)
8411 struct tg3 *tp = netdev_priv(dev);
8412 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8415 #define NVRAM_TEST_SIZE 0x100
8416 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8417 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8418 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8420 static int tg3_test_nvram(struct tg3 *tp)
8422 u32 *buf, csum, magic;
8423 int i, j, err = 0, size;
8425 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8428 if (magic == TG3_EEPROM_MAGIC)
8429 size = NVRAM_TEST_SIZE;
8430 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8431 if ((magic & 0xe00000) == 0x200000)
8432 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8435 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8436 size = NVRAM_SELFBOOT_HW_SIZE;
8440 buf = kmalloc(size, GFP_KERNEL);
8445 for (i = 0, j = 0; i < size; i += 4, j++) {
8448 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8450 buf[j] = cpu_to_le32(val);
8455 /* Selfboot format */
8456 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8457 TG3_EEPROM_MAGIC_FW) {
8458 u8 *buf8 = (u8 *) buf, csum8 = 0;
8460 for (i = 0; i < size; i++)
8472 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8473 TG3_EEPROM_MAGIC_HW) {
8474 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8475 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8476 u8 *buf8 = (u8 *) buf;
8479 /* Separate the parity bits and the data bytes. */
8480 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8481 if ((i == 0) || (i == 8)) {
8485 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8486 parity[k++] = buf8[i] & msk;
8493 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8494 parity[k++] = buf8[i] & msk;
8497 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8498 parity[k++] = buf8[i] & msk;
8501 data[j++] = buf8[i];
8505 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8506 u8 hw8 = hweight8(data[i]);
8508 if ((hw8 & 0x1) && parity[i])
8510 else if (!(hw8 & 0x1) && !parity[i])
8517 /* Bootstrap checksum at offset 0x10 */
8518 csum = calc_crc((unsigned char *) buf, 0x10);
8519 if(csum != cpu_to_le32(buf[0x10/4]))
8522 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8523 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8524 if (csum != cpu_to_le32(buf[0xfc/4]))
8534 #define TG3_SERDES_TIMEOUT_SEC 2
8535 #define TG3_COPPER_TIMEOUT_SEC 6
8537 static int tg3_test_link(struct tg3 *tp)
8541 if (!netif_running(tp->dev))
8544 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8545 max = TG3_SERDES_TIMEOUT_SEC;
8547 max = TG3_COPPER_TIMEOUT_SEC;
8549 for (i = 0; i < max; i++) {
8550 if (netif_carrier_ok(tp->dev))
8553 if (msleep_interruptible(1000))
8560 /* Only test the commonly used registers */
8561 static int tg3_test_registers(struct tg3 *tp)
8563 int i, is_5705, is_5750;
8564 u32 offset, read_mask, write_mask, val, save_val, read_val;
8568 #define TG3_FL_5705 0x1
8569 #define TG3_FL_NOT_5705 0x2
8570 #define TG3_FL_NOT_5788 0x4
8571 #define TG3_FL_NOT_5750 0x8
8575 /* MAC Control Registers */
8576 { MAC_MODE, TG3_FL_NOT_5705,
8577 0x00000000, 0x00ef6f8c },
8578 { MAC_MODE, TG3_FL_5705,
8579 0x00000000, 0x01ef6b8c },
8580 { MAC_STATUS, TG3_FL_NOT_5705,
8581 0x03800107, 0x00000000 },
8582 { MAC_STATUS, TG3_FL_5705,
8583 0x03800100, 0x00000000 },
8584 { MAC_ADDR_0_HIGH, 0x0000,
8585 0x00000000, 0x0000ffff },
8586 { MAC_ADDR_0_LOW, 0x0000,
8587 0x00000000, 0xffffffff },
8588 { MAC_RX_MTU_SIZE, 0x0000,
8589 0x00000000, 0x0000ffff },
8590 { MAC_TX_MODE, 0x0000,
8591 0x00000000, 0x00000070 },
8592 { MAC_TX_LENGTHS, 0x0000,
8593 0x00000000, 0x00003fff },
8594 { MAC_RX_MODE, TG3_FL_NOT_5705,
8595 0x00000000, 0x000007fc },
8596 { MAC_RX_MODE, TG3_FL_5705,
8597 0x00000000, 0x000007dc },
8598 { MAC_HASH_REG_0, 0x0000,
8599 0x00000000, 0xffffffff },
8600 { MAC_HASH_REG_1, 0x0000,
8601 0x00000000, 0xffffffff },
8602 { MAC_HASH_REG_2, 0x0000,
8603 0x00000000, 0xffffffff },
8604 { MAC_HASH_REG_3, 0x0000,
8605 0x00000000, 0xffffffff },
8607 /* Receive Data and Receive BD Initiator Control Registers. */
8608 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8609 0x00000000, 0xffffffff },
8610 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8611 0x00000000, 0xffffffff },
8612 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8613 0x00000000, 0x00000003 },
8614 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8615 0x00000000, 0xffffffff },
8616 { RCVDBDI_STD_BD+0, 0x0000,
8617 0x00000000, 0xffffffff },
8618 { RCVDBDI_STD_BD+4, 0x0000,
8619 0x00000000, 0xffffffff },
8620 { RCVDBDI_STD_BD+8, 0x0000,
8621 0x00000000, 0xffff0002 },
8622 { RCVDBDI_STD_BD+0xc, 0x0000,
8623 0x00000000, 0xffffffff },
8625 /* Receive BD Initiator Control Registers. */
8626 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8627 0x00000000, 0xffffffff },
8628 { RCVBDI_STD_THRESH, TG3_FL_5705,
8629 0x00000000, 0x000003ff },
8630 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8631 0x00000000, 0xffffffff },
8633 /* Host Coalescing Control Registers. */
8634 { HOSTCC_MODE, TG3_FL_NOT_5705,
8635 0x00000000, 0x00000004 },
8636 { HOSTCC_MODE, TG3_FL_5705,
8637 0x00000000, 0x000000f6 },
8638 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8639 0x00000000, 0xffffffff },
8640 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8641 0x00000000, 0x000003ff },
8642 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8643 0x00000000, 0xffffffff },
8644 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8645 0x00000000, 0x000003ff },
8646 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8647 0x00000000, 0xffffffff },
8648 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8649 0x00000000, 0x000000ff },
8650 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8651 0x00000000, 0xffffffff },
8652 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8653 0x00000000, 0x000000ff },
8654 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8655 0x00000000, 0xffffffff },
8656 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8657 0x00000000, 0xffffffff },
8658 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8659 0x00000000, 0xffffffff },
8660 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8661 0x00000000, 0x000000ff },
8662 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8663 0x00000000, 0xffffffff },
8664 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8665 0x00000000, 0x000000ff },
8666 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8667 0x00000000, 0xffffffff },
8668 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8669 0x00000000, 0xffffffff },
8670 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8671 0x00000000, 0xffffffff },
8672 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8673 0x00000000, 0xffffffff },
8674 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8675 0x00000000, 0xffffffff },
8676 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8677 0xffffffff, 0x00000000 },
8678 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8679 0xffffffff, 0x00000000 },
8681 /* Buffer Manager Control Registers. */
8682 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8683 0x00000000, 0x007fff80 },
8684 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8685 0x00000000, 0x007fffff },
8686 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8687 0x00000000, 0x0000003f },
8688 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8689 0x00000000, 0x000001ff },
8690 { BUFMGR_MB_HIGH_WATER, 0x0000,
8691 0x00000000, 0x000001ff },
8692 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8693 0xffffffff, 0x00000000 },
8694 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8695 0xffffffff, 0x00000000 },
8697 /* Mailbox Registers */
8698 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8699 0x00000000, 0x000001ff },
8700 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8701 0x00000000, 0x000001ff },
8702 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8703 0x00000000, 0x000007ff },
8704 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8705 0x00000000, 0x000001ff },
8707 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8710 is_5705 = is_5750 = 0;
8711 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8713 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8717 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8718 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8721 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8724 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8725 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8728 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8731 offset = (u32) reg_tbl[i].offset;
8732 read_mask = reg_tbl[i].read_mask;
8733 write_mask = reg_tbl[i].write_mask;
8735 /* Save the original register content */
8736 save_val = tr32(offset);
8738 /* Determine the read-only value. */
8739 read_val = save_val & read_mask;
8741 /* Write zero to the register, then make sure the read-only bits
8742 * are not changed and the read/write bits are all zeros.
8748 /* Test the read-only and read/write bits. */
8749 if (((val & read_mask) != read_val) || (val & write_mask))
8752 /* Write ones to all the bits defined by RdMask and WrMask, then
8753 * make sure the read-only bits are not changed and the
8754 * read/write bits are all ones.
8756 tw32(offset, read_mask | write_mask);
8760 /* Test the read-only bits. */
8761 if ((val & read_mask) != read_val)
8764 /* Test the read/write bits. */
8765 if ((val & write_mask) != write_mask)
8768 tw32(offset, save_val);
8774 if (netif_msg_hw(tp))
8775 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8777 tw32(offset, save_val);
8781 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8783 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8787 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8788 for (j = 0; j < len; j += 4) {
8791 tg3_write_mem(tp, offset + j, test_pattern[i]);
8792 tg3_read_mem(tp, offset + j, &val);
8793 if (val != test_pattern[i])
8800 static int tg3_test_memory(struct tg3 *tp)
8802 static struct mem_entry {
8805 } mem_tbl_570x[] = {
8806 { 0x00000000, 0x00b50},
8807 { 0x00002000, 0x1c000},
8808 { 0xffffffff, 0x00000}
8809 }, mem_tbl_5705[] = {
8810 { 0x00000100, 0x0000c},
8811 { 0x00000200, 0x00008},
8812 { 0x00004000, 0x00800},
8813 { 0x00006000, 0x01000},
8814 { 0x00008000, 0x02000},
8815 { 0x00010000, 0x0e000},
8816 { 0xffffffff, 0x00000}
8817 }, mem_tbl_5755[] = {
8818 { 0x00000200, 0x00008},
8819 { 0x00004000, 0x00800},
8820 { 0x00006000, 0x00800},
8821 { 0x00008000, 0x02000},
8822 { 0x00010000, 0x0c000},
8823 { 0xffffffff, 0x00000}
8824 }, mem_tbl_5906[] = {
8825 { 0x00000200, 0x00008},
8826 { 0x00004000, 0x00400},
8827 { 0x00006000, 0x00400},
8828 { 0x00008000, 0x01000},
8829 { 0x00010000, 0x01000},
8830 { 0xffffffff, 0x00000}
8832 struct mem_entry *mem_tbl;
8836 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8838 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8839 mem_tbl = mem_tbl_5755;
8840 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8841 mem_tbl = mem_tbl_5906;
8843 mem_tbl = mem_tbl_5705;
8845 mem_tbl = mem_tbl_570x;
8847 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8848 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8849 mem_tbl[i].len)) != 0)
8856 #define TG3_MAC_LOOPBACK 0
8857 #define TG3_PHY_LOOPBACK 1
8859 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8861 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8863 struct sk_buff *skb, *rx_skb;
8866 int num_pkts, tx_len, rx_len, i, err;
8867 struct tg3_rx_buffer_desc *desc;
8869 if (loopback_mode == TG3_MAC_LOOPBACK) {
8870 /* HW errata - mac loopback fails in some cases on 5780.
8871 * Normal traffic and PHY loopback are not affected by
8874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8877 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8878 MAC_MODE_PORT_INT_LPBACK;
8879 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8880 mac_mode |= MAC_MODE_LINK_POLARITY;
8881 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8882 mac_mode |= MAC_MODE_PORT_MODE_MII;
8884 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8885 tw32(MAC_MODE, mac_mode);
8886 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8892 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8895 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8896 phytest | MII_TG3_EPHY_SHADOW_EN);
8897 if (!tg3_readphy(tp, 0x1b, &phy))
8898 tg3_writephy(tp, 0x1b, phy & ~0x20);
8899 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8901 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8903 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8905 tg3_phy_toggle_automdix(tp, 0);
8907 tg3_writephy(tp, MII_BMCR, val);
8910 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
8911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8912 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8913 mac_mode |= MAC_MODE_PORT_MODE_MII;
8915 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8917 /* reset to prevent losing 1st rx packet intermittently */
8918 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8919 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8921 tw32_f(MAC_RX_MODE, tp->rx_mode);
8923 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
8924 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8925 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8926 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
8927 mac_mode |= MAC_MODE_LINK_POLARITY;
8928 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8929 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8931 tw32(MAC_MODE, mac_mode);
8939 skb = netdev_alloc_skb(tp->dev, tx_len);
8943 tx_data = skb_put(skb, tx_len);
8944 memcpy(tx_data, tp->dev->dev_addr, 6);
8945 memset(tx_data + 6, 0x0, 8);
8947 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8949 for (i = 14; i < tx_len; i++)
8950 tx_data[i] = (u8) (i & 0xff);
8952 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8954 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8959 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8963 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8968 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8970 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8974 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8975 for (i = 0; i < 25; i++) {
8976 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8981 tx_idx = tp->hw_status->idx[0].tx_consumer;
8982 rx_idx = tp->hw_status->idx[0].rx_producer;
8983 if ((tx_idx == tp->tx_prod) &&
8984 (rx_idx == (rx_start_idx + num_pkts)))
8988 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8991 if (tx_idx != tp->tx_prod)
8994 if (rx_idx != rx_start_idx + num_pkts)
8997 desc = &tp->rx_rcb[rx_start_idx];
8998 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8999 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9000 if (opaque_key != RXD_OPAQUE_RING_STD)
9003 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9004 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9007 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9008 if (rx_len != tx_len)
9011 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9013 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9014 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9016 for (i = 14; i < tx_len; i++) {
9017 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9022 /* tg3_free_rings will unmap and free the rx_skb */
9027 #define TG3_MAC_LOOPBACK_FAILED 1
9028 #define TG3_PHY_LOOPBACK_FAILED 2
9029 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9030 TG3_PHY_LOOPBACK_FAILED)
9032 static int tg3_test_loopback(struct tg3 *tp)
9036 if (!netif_running(tp->dev))
9037 return TG3_LOOPBACK_FAILED;
9039 err = tg3_reset_hw(tp, 1);
9041 return TG3_LOOPBACK_FAILED;
9043 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9044 err |= TG3_MAC_LOOPBACK_FAILED;
9045 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9046 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9047 err |= TG3_PHY_LOOPBACK_FAILED;
9053 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9056 struct tg3 *tp = netdev_priv(dev);
9058 if (tp->link_config.phy_is_low_power)
9059 tg3_set_power_state(tp, PCI_D0);
9061 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9063 if (tg3_test_nvram(tp) != 0) {
9064 etest->flags |= ETH_TEST_FL_FAILED;
9067 if (tg3_test_link(tp) != 0) {
9068 etest->flags |= ETH_TEST_FL_FAILED;
9071 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9072 int err, irq_sync = 0;
9074 if (netif_running(dev)) {
9079 tg3_full_lock(tp, irq_sync);
9081 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9082 err = tg3_nvram_lock(tp);
9083 tg3_halt_cpu(tp, RX_CPU_BASE);
9084 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9085 tg3_halt_cpu(tp, TX_CPU_BASE);
9087 tg3_nvram_unlock(tp);
9089 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9092 if (tg3_test_registers(tp) != 0) {
9093 etest->flags |= ETH_TEST_FL_FAILED;
9096 if (tg3_test_memory(tp) != 0) {
9097 etest->flags |= ETH_TEST_FL_FAILED;
9100 if ((data[4] = tg3_test_loopback(tp)) != 0)
9101 etest->flags |= ETH_TEST_FL_FAILED;
9103 tg3_full_unlock(tp);
9105 if (tg3_test_interrupt(tp) != 0) {
9106 etest->flags |= ETH_TEST_FL_FAILED;
9110 tg3_full_lock(tp, 0);
9112 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9113 if (netif_running(dev)) {
9114 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9115 if (!tg3_restart_hw(tp, 1))
9116 tg3_netif_start(tp);
9119 tg3_full_unlock(tp);
9121 if (tp->link_config.phy_is_low_power)
9122 tg3_set_power_state(tp, PCI_D3hot);
9126 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9128 struct mii_ioctl_data *data = if_mii(ifr);
9129 struct tg3 *tp = netdev_priv(dev);
9134 data->phy_id = PHY_ADDR;
9140 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9141 break; /* We have no PHY */
9143 if (tp->link_config.phy_is_low_power)
9146 spin_lock_bh(&tp->lock);
9147 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9148 spin_unlock_bh(&tp->lock);
9150 data->val_out = mii_regval;
9156 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9157 break; /* We have no PHY */
9159 if (!capable(CAP_NET_ADMIN))
9162 if (tp->link_config.phy_is_low_power)
9165 spin_lock_bh(&tp->lock);
9166 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9167 spin_unlock_bh(&tp->lock);
9178 #if TG3_VLAN_TAG_USED
9179 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9181 struct tg3 *tp = netdev_priv(dev);
9183 if (netif_running(dev))
9186 tg3_full_lock(tp, 0);
9190 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9191 __tg3_set_rx_mode(dev);
9193 if (netif_running(dev))
9194 tg3_netif_start(tp);
9196 tg3_full_unlock(tp);
9200 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9202 struct tg3 *tp = netdev_priv(dev);
9204 memcpy(ec, &tp->coal, sizeof(*ec));
9208 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9210 struct tg3 *tp = netdev_priv(dev);
9211 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9212 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9214 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9215 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9216 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9217 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9218 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9221 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9222 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9223 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9224 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9225 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9226 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9227 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9228 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9229 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9230 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9233 /* No rx interrupts will be generated if both are zero */
9234 if ((ec->rx_coalesce_usecs == 0) &&
9235 (ec->rx_max_coalesced_frames == 0))
9238 /* No tx interrupts will be generated if both are zero */
9239 if ((ec->tx_coalesce_usecs == 0) &&
9240 (ec->tx_max_coalesced_frames == 0))
9243 /* Only copy relevant parameters, ignore all others. */
9244 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9245 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9246 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9247 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9248 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9249 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9250 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9251 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9252 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9254 if (netif_running(dev)) {
9255 tg3_full_lock(tp, 0);
9256 __tg3_set_coalesce(tp, &tp->coal);
9257 tg3_full_unlock(tp);
9262 static const struct ethtool_ops tg3_ethtool_ops = {
9263 .get_settings = tg3_get_settings,
9264 .set_settings = tg3_set_settings,
9265 .get_drvinfo = tg3_get_drvinfo,
9266 .get_regs_len = tg3_get_regs_len,
9267 .get_regs = tg3_get_regs,
9268 .get_wol = tg3_get_wol,
9269 .set_wol = tg3_set_wol,
9270 .get_msglevel = tg3_get_msglevel,
9271 .set_msglevel = tg3_set_msglevel,
9272 .nway_reset = tg3_nway_reset,
9273 .get_link = ethtool_op_get_link,
9274 .get_eeprom_len = tg3_get_eeprom_len,
9275 .get_eeprom = tg3_get_eeprom,
9276 .set_eeprom = tg3_set_eeprom,
9277 .get_ringparam = tg3_get_ringparam,
9278 .set_ringparam = tg3_set_ringparam,
9279 .get_pauseparam = tg3_get_pauseparam,
9280 .set_pauseparam = tg3_set_pauseparam,
9281 .get_rx_csum = tg3_get_rx_csum,
9282 .set_rx_csum = tg3_set_rx_csum,
9283 .get_tx_csum = ethtool_op_get_tx_csum,
9284 .set_tx_csum = tg3_set_tx_csum,
9285 .get_sg = ethtool_op_get_sg,
9286 .set_sg = ethtool_op_set_sg,
9287 .get_tso = ethtool_op_get_tso,
9288 .set_tso = tg3_set_tso,
9289 .self_test_count = tg3_get_test_count,
9290 .self_test = tg3_self_test,
9291 .get_strings = tg3_get_strings,
9292 .phys_id = tg3_phys_id,
9293 .get_stats_count = tg3_get_stats_count,
9294 .get_ethtool_stats = tg3_get_ethtool_stats,
9295 .get_coalesce = tg3_get_coalesce,
9296 .set_coalesce = tg3_set_coalesce,
9299 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9301 u32 cursize, val, magic;
9303 tp->nvram_size = EEPROM_CHIP_SIZE;
9305 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9308 if ((magic != TG3_EEPROM_MAGIC) &&
9309 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9310 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9314 * Size the chip by reading offsets at increasing powers of two.
9315 * When we encounter our validation signature, we know the addressing
9316 * has wrapped around, and thus have our chip size.
9320 while (cursize < tp->nvram_size) {
9321 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9330 tp->nvram_size = cursize;
9333 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9337 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9340 /* Selfboot format */
9341 if (val != TG3_EEPROM_MAGIC) {
9342 tg3_get_eeprom_size(tp);
9346 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9348 tp->nvram_size = (val >> 16) * 1024;
9352 tp->nvram_size = 0x80000;
9355 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9359 nvcfg1 = tr32(NVRAM_CFG1);
9360 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9361 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9364 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9365 tw32(NVRAM_CFG1, nvcfg1);
9368 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9369 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9370 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9371 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9372 tp->nvram_jedecnum = JEDEC_ATMEL;
9373 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9374 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9376 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9377 tp->nvram_jedecnum = JEDEC_ATMEL;
9378 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9380 case FLASH_VENDOR_ATMEL_EEPROM:
9381 tp->nvram_jedecnum = JEDEC_ATMEL;
9382 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9383 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9385 case FLASH_VENDOR_ST:
9386 tp->nvram_jedecnum = JEDEC_ST;
9387 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9388 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9390 case FLASH_VENDOR_SAIFUN:
9391 tp->nvram_jedecnum = JEDEC_SAIFUN;
9392 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9394 case FLASH_VENDOR_SST_SMALL:
9395 case FLASH_VENDOR_SST_LARGE:
9396 tp->nvram_jedecnum = JEDEC_SST;
9397 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9402 tp->nvram_jedecnum = JEDEC_ATMEL;
9403 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9404 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9408 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9412 nvcfg1 = tr32(NVRAM_CFG1);
9414 /* NVRAM protection for TPM */
9415 if (nvcfg1 & (1 << 27))
9416 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9418 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9419 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9420 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9421 tp->nvram_jedecnum = JEDEC_ATMEL;
9422 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9424 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9425 tp->nvram_jedecnum = JEDEC_ATMEL;
9426 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9427 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9429 case FLASH_5752VENDOR_ST_M45PE10:
9430 case FLASH_5752VENDOR_ST_M45PE20:
9431 case FLASH_5752VENDOR_ST_M45PE40:
9432 tp->nvram_jedecnum = JEDEC_ST;
9433 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9434 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9438 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9439 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9440 case FLASH_5752PAGE_SIZE_256:
9441 tp->nvram_pagesize = 256;
9443 case FLASH_5752PAGE_SIZE_512:
9444 tp->nvram_pagesize = 512;
9446 case FLASH_5752PAGE_SIZE_1K:
9447 tp->nvram_pagesize = 1024;
9449 case FLASH_5752PAGE_SIZE_2K:
9450 tp->nvram_pagesize = 2048;
9452 case FLASH_5752PAGE_SIZE_4K:
9453 tp->nvram_pagesize = 4096;
9455 case FLASH_5752PAGE_SIZE_264:
9456 tp->nvram_pagesize = 264;
9461 /* For eeprom, set pagesize to maximum eeprom size */
9462 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9464 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9465 tw32(NVRAM_CFG1, nvcfg1);
9469 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9471 u32 nvcfg1, protect = 0;
9473 nvcfg1 = tr32(NVRAM_CFG1);
9475 /* NVRAM protection for TPM */
9476 if (nvcfg1 & (1 << 27)) {
9477 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9481 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9483 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9484 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9485 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9486 case FLASH_5755VENDOR_ATMEL_FLASH_5:
9487 tp->nvram_jedecnum = JEDEC_ATMEL;
9488 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9489 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9490 tp->nvram_pagesize = 264;
9491 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
9492 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
9493 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9494 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9495 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9497 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
9499 case FLASH_5752VENDOR_ST_M45PE10:
9500 case FLASH_5752VENDOR_ST_M45PE20:
9501 case FLASH_5752VENDOR_ST_M45PE40:
9502 tp->nvram_jedecnum = JEDEC_ST;
9503 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9504 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9505 tp->nvram_pagesize = 256;
9506 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9507 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9508 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9509 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9511 tp->nvram_size = (protect ? 0x20000 : 0x80000);
9516 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9520 nvcfg1 = tr32(NVRAM_CFG1);
9522 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9523 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9524 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9525 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9526 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9527 tp->nvram_jedecnum = JEDEC_ATMEL;
9528 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9529 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9531 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9532 tw32(NVRAM_CFG1, nvcfg1);
9534 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9535 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9536 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9537 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9538 tp->nvram_jedecnum = JEDEC_ATMEL;
9539 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9540 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9541 tp->nvram_pagesize = 264;
9543 case FLASH_5752VENDOR_ST_M45PE10:
9544 case FLASH_5752VENDOR_ST_M45PE20:
9545 case FLASH_5752VENDOR_ST_M45PE40:
9546 tp->nvram_jedecnum = JEDEC_ST;
9547 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9548 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9549 tp->nvram_pagesize = 256;
9554 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9556 tp->nvram_jedecnum = JEDEC_ATMEL;
9557 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9558 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9561 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9562 static void __devinit tg3_nvram_init(struct tg3 *tp)
9564 tw32_f(GRC_EEPROM_ADDR,
9565 (EEPROM_ADDR_FSM_RESET |
9566 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9567 EEPROM_ADDR_CLKPERD_SHIFT)));
9571 /* Enable seeprom accesses. */
9572 tw32_f(GRC_LOCAL_CTRL,
9573 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9576 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9577 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9578 tp->tg3_flags |= TG3_FLAG_NVRAM;
9580 if (tg3_nvram_lock(tp)) {
9581 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9582 "tg3_nvram_init failed.\n", tp->dev->name);
9585 tg3_enable_nvram_access(tp);
9589 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9590 tg3_get_5752_nvram_info(tp);
9591 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9592 tg3_get_5755_nvram_info(tp);
9593 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9594 tg3_get_5787_nvram_info(tp);
9595 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9596 tg3_get_5906_nvram_info(tp);
9598 tg3_get_nvram_info(tp);
9600 if (tp->nvram_size == 0)
9601 tg3_get_nvram_size(tp);
9603 tg3_disable_nvram_access(tp);
9604 tg3_nvram_unlock(tp);
9607 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9609 tg3_get_eeprom_size(tp);
9613 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9614 u32 offset, u32 *val)
9619 if (offset > EEPROM_ADDR_ADDR_MASK ||
9623 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9624 EEPROM_ADDR_DEVID_MASK |
9626 tw32(GRC_EEPROM_ADDR,
9628 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9629 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9630 EEPROM_ADDR_ADDR_MASK) |
9631 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9633 for (i = 0; i < 1000; i++) {
9634 tmp = tr32(GRC_EEPROM_ADDR);
9636 if (tmp & EEPROM_ADDR_COMPLETE)
9640 if (!(tmp & EEPROM_ADDR_COMPLETE))
9643 *val = tr32(GRC_EEPROM_DATA);
9647 #define NVRAM_CMD_TIMEOUT 10000
9649 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9653 tw32(NVRAM_CMD, nvram_cmd);
9654 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9656 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9661 if (i == NVRAM_CMD_TIMEOUT) {
9667 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9669 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9670 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9671 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9672 (tp->nvram_jedecnum == JEDEC_ATMEL))
9674 addr = ((addr / tp->nvram_pagesize) <<
9675 ATMEL_AT45DB0X1B_PAGE_POS) +
9676 (addr % tp->nvram_pagesize);
9681 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9683 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9684 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9685 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9686 (tp->nvram_jedecnum == JEDEC_ATMEL))
9688 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9689 tp->nvram_pagesize) +
9690 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9695 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9699 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9700 return tg3_nvram_read_using_eeprom(tp, offset, val);
9702 offset = tg3_nvram_phys_addr(tp, offset);
9704 if (offset > NVRAM_ADDR_MSK)
9707 ret = tg3_nvram_lock(tp);
9711 tg3_enable_nvram_access(tp);
9713 tw32(NVRAM_ADDR, offset);
9714 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9715 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9718 *val = swab32(tr32(NVRAM_RDDATA));
9720 tg3_disable_nvram_access(tp);
9722 tg3_nvram_unlock(tp);
9727 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9732 err = tg3_nvram_read(tp, offset, &tmp);
9737 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9738 u32 offset, u32 len, u8 *buf)
9743 for (i = 0; i < len; i += 4) {
9748 memcpy(&data, buf + i, 4);
9750 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9752 val = tr32(GRC_EEPROM_ADDR);
9753 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9755 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9757 tw32(GRC_EEPROM_ADDR, val |
9758 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9759 (addr & EEPROM_ADDR_ADDR_MASK) |
9763 for (j = 0; j < 1000; j++) {
9764 val = tr32(GRC_EEPROM_ADDR);
9766 if (val & EEPROM_ADDR_COMPLETE)
9770 if (!(val & EEPROM_ADDR_COMPLETE)) {
9779 /* offset and length are dword aligned */
9780 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9784 u32 pagesize = tp->nvram_pagesize;
9785 u32 pagemask = pagesize - 1;
9789 tmp = kmalloc(pagesize, GFP_KERNEL);
9795 u32 phy_addr, page_off, size;
9797 phy_addr = offset & ~pagemask;
9799 for (j = 0; j < pagesize; j += 4) {
9800 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9801 (u32 *) (tmp + j))))
9807 page_off = offset & pagemask;
9814 memcpy(tmp + page_off, buf, size);
9816 offset = offset + (pagesize - page_off);
9818 tg3_enable_nvram_access(tp);
9821 * Before we can erase the flash page, we need
9822 * to issue a special "write enable" command.
9824 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9826 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9829 /* Erase the target page */
9830 tw32(NVRAM_ADDR, phy_addr);
9832 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9833 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9835 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9838 /* Issue another write enable to start the write. */
9839 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9841 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9844 for (j = 0; j < pagesize; j += 4) {
9847 data = *((u32 *) (tmp + j));
9848 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9850 tw32(NVRAM_ADDR, phy_addr + j);
9852 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9856 nvram_cmd |= NVRAM_CMD_FIRST;
9857 else if (j == (pagesize - 4))
9858 nvram_cmd |= NVRAM_CMD_LAST;
9860 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9867 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9868 tg3_nvram_exec_cmd(tp, nvram_cmd);
9875 /* offset and length are dword aligned */
9876 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9881 for (i = 0; i < len; i += 4, offset += 4) {
9882 u32 data, page_off, phy_addr, nvram_cmd;
9884 memcpy(&data, buf + i, 4);
9885 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9887 page_off = offset % tp->nvram_pagesize;
9889 phy_addr = tg3_nvram_phys_addr(tp, offset);
9891 tw32(NVRAM_ADDR, phy_addr);
9893 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9895 if ((page_off == 0) || (i == 0))
9896 nvram_cmd |= NVRAM_CMD_FIRST;
9897 if (page_off == (tp->nvram_pagesize - 4))
9898 nvram_cmd |= NVRAM_CMD_LAST;
9901 nvram_cmd |= NVRAM_CMD_LAST;
9903 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9904 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9905 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9906 (tp->nvram_jedecnum == JEDEC_ST) &&
9907 (nvram_cmd & NVRAM_CMD_FIRST)) {
9909 if ((ret = tg3_nvram_exec_cmd(tp,
9910 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9915 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9916 /* We always do complete word writes to eeprom. */
9917 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9920 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9926 /* offset and length are dword aligned */
9927 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9931 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9932 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9933 ~GRC_LCLCTRL_GPIO_OUTPUT1);
9937 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9938 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9943 ret = tg3_nvram_lock(tp);
9947 tg3_enable_nvram_access(tp);
9948 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9949 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9950 tw32(NVRAM_WRITE1, 0x406);
9952 grc_mode = tr32(GRC_MODE);
9953 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9955 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9956 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9958 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9962 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9966 grc_mode = tr32(GRC_MODE);
9967 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9969 tg3_disable_nvram_access(tp);
9970 tg3_nvram_unlock(tp);
9973 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9974 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9981 struct subsys_tbl_ent {
9982 u16 subsys_vendor, subsys_devid;
9986 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9987 /* Broadcom boards. */
9988 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9989 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9990 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9991 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9992 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9993 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9994 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9995 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9996 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9997 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9998 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10001 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10002 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10003 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10004 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10005 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10008 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10009 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10010 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10011 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10013 /* Compaq boards. */
10014 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10015 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10016 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10017 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10018 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10021 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10024 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10028 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10029 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10030 tp->pdev->subsystem_vendor) &&
10031 (subsys_id_to_phy_id[i].subsys_devid ==
10032 tp->pdev->subsystem_device))
10033 return &subsys_id_to_phy_id[i];
10038 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10043 /* On some early chips the SRAM cannot be accessed in D3hot state,
10044 * so need make sure we're in D0.
10046 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10047 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10048 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10051 /* Make sure register accesses (indirect or otherwise)
10052 * will function correctly.
10054 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10055 tp->misc_host_ctrl);
10057 /* The memory arbiter has to be enabled in order for SRAM accesses
10058 * to succeed. Normally on powerup the tg3 chip firmware will make
10059 * sure it is enabled, but other entities such as system netboot
10060 * code might disable it.
10062 val = tr32(MEMARB_MODE);
10063 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10065 tp->phy_id = PHY_ID_INVALID;
10066 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10068 /* Assume an onboard device and WOL capable by default. */
10069 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10071 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10072 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10073 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10074 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10076 if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
10077 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10081 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10082 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10083 u32 nic_cfg, led_cfg;
10084 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10085 int eeprom_phy_serdes = 0;
10087 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10088 tp->nic_sram_data_cfg = nic_cfg;
10090 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10091 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10092 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10093 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10094 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10095 (ver > 0) && (ver < 0x100))
10096 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10098 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10099 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10100 eeprom_phy_serdes = 1;
10102 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10103 if (nic_phy_id != 0) {
10104 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10105 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10107 eeprom_phy_id = (id1 >> 16) << 10;
10108 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10109 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10113 tp->phy_id = eeprom_phy_id;
10114 if (eeprom_phy_serdes) {
10115 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10116 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10118 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10121 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10122 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10123 SHASTA_EXT_LED_MODE_MASK);
10125 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10129 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10130 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10133 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10134 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10137 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10138 tp->led_ctrl = LED_CTRL_MODE_MAC;
10140 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10141 * read on some older 5700/5701 bootcode.
10143 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10145 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10147 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10151 case SHASTA_EXT_LED_SHARED:
10152 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10153 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10154 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10155 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10156 LED_CTRL_MODE_PHY_2);
10159 case SHASTA_EXT_LED_MAC:
10160 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10163 case SHASTA_EXT_LED_COMBO:
10164 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10165 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10166 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10167 LED_CTRL_MODE_PHY_2);
10172 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10173 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10174 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10175 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10177 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10178 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10179 if ((tp->pdev->subsystem_vendor ==
10180 PCI_VENDOR_ID_ARIMA) &&
10181 (tp->pdev->subsystem_device == 0x205a ||
10182 tp->pdev->subsystem_device == 0x2063))
10183 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10185 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10186 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10189 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10190 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10191 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10192 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10194 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10195 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10196 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10198 if (cfg2 & (1 << 17))
10199 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10201 /* serdes signal pre-emphasis in register 0x590 set by */
10202 /* bootcode if bit 18 is set */
10203 if (cfg2 & (1 << 18))
10204 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10206 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10209 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10210 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10211 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10216 static int __devinit tg3_phy_probe(struct tg3 *tp)
10218 u32 hw_phy_id_1, hw_phy_id_2;
10219 u32 hw_phy_id, hw_phy_id_masked;
10222 /* Reading the PHY ID register can conflict with ASF
10223 * firwmare access to the PHY hardware.
10226 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10227 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10229 /* Now read the physical PHY_ID from the chip and verify
10230 * that it is sane. If it doesn't look good, we fall back
10231 * to either the hard-coded table based PHY_ID and failing
10232 * that the value found in the eeprom area.
10234 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10235 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10237 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10238 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10239 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10241 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10244 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10245 tp->phy_id = hw_phy_id;
10246 if (hw_phy_id_masked == PHY_ID_BCM8002)
10247 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10249 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10251 if (tp->phy_id != PHY_ID_INVALID) {
10252 /* Do nothing, phy ID already set up in
10253 * tg3_get_eeprom_hw_cfg().
10256 struct subsys_tbl_ent *p;
10258 /* No eeprom signature? Try the hardcoded
10259 * subsys device table.
10261 p = lookup_by_subsys(tp);
10265 tp->phy_id = p->phy_id;
10267 tp->phy_id == PHY_ID_BCM8002)
10268 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10272 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10273 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10274 u32 bmsr, adv_reg, tg3_ctrl, mask;
10276 tg3_readphy(tp, MII_BMSR, &bmsr);
10277 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10278 (bmsr & BMSR_LSTATUS))
10279 goto skip_phy_reset;
10281 err = tg3_phy_reset(tp);
10285 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10286 ADVERTISE_100HALF | ADVERTISE_100FULL |
10287 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10289 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10290 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10291 MII_TG3_CTRL_ADV_1000_FULL);
10292 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10293 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10294 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10295 MII_TG3_CTRL_ENABLE_AS_MASTER);
10298 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10299 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10300 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10301 if (!tg3_copper_is_advertising_all(tp, mask)) {
10302 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10304 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10305 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10307 tg3_writephy(tp, MII_BMCR,
10308 BMCR_ANENABLE | BMCR_ANRESTART);
10310 tg3_phy_set_wirespeed(tp);
10312 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10313 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10314 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10318 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10319 err = tg3_init_5401phy_dsp(tp);
10324 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10325 err = tg3_init_5401phy_dsp(tp);
10328 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10329 tp->link_config.advertising =
10330 (ADVERTISED_1000baseT_Half |
10331 ADVERTISED_1000baseT_Full |
10332 ADVERTISED_Autoneg |
10334 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10335 tp->link_config.advertising &=
10336 ~(ADVERTISED_1000baseT_Half |
10337 ADVERTISED_1000baseT_Full);
10342 static void __devinit tg3_read_partno(struct tg3 *tp)
10344 unsigned char vpd_data[256];
10348 if (tg3_nvram_read_swab(tp, 0x0, &magic))
10349 goto out_not_found;
10351 if (magic == TG3_EEPROM_MAGIC) {
10352 for (i = 0; i < 256; i += 4) {
10355 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10356 goto out_not_found;
10358 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10359 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10360 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10361 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10366 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10367 for (i = 0; i < 256; i += 4) {
10371 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10373 while (j++ < 100) {
10374 pci_read_config_word(tp->pdev, vpd_cap +
10375 PCI_VPD_ADDR, &tmp16);
10376 if (tmp16 & 0x8000)
10380 if (!(tmp16 & 0x8000))
10381 goto out_not_found;
10383 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10385 tmp = cpu_to_le32(tmp);
10386 memcpy(&vpd_data[i], &tmp, 4);
10390 /* Now parse and find the part number. */
10391 for (i = 0; i < 254; ) {
10392 unsigned char val = vpd_data[i];
10393 unsigned int block_end;
10395 if (val == 0x82 || val == 0x91) {
10398 (vpd_data[i + 2] << 8)));
10403 goto out_not_found;
10405 block_end = (i + 3 +
10407 (vpd_data[i + 2] << 8)));
10410 if (block_end > 256)
10411 goto out_not_found;
10413 while (i < (block_end - 2)) {
10414 if (vpd_data[i + 0] == 'P' &&
10415 vpd_data[i + 1] == 'N') {
10416 int partno_len = vpd_data[i + 2];
10419 if (partno_len > 24 || (partno_len + i) > 256)
10420 goto out_not_found;
10422 memcpy(tp->board_part_number,
10423 &vpd_data[i], partno_len);
10428 i += 3 + vpd_data[i + 2];
10431 /* Part number not found. */
10432 goto out_not_found;
10436 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10437 strcpy(tp->board_part_number, "BCM95906");
10439 strcpy(tp->board_part_number, "none");
10442 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10444 u32 val, offset, start;
10446 if (tg3_nvram_read_swab(tp, 0, &val))
10449 if (val != TG3_EEPROM_MAGIC)
10452 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10453 tg3_nvram_read_swab(tp, 0x4, &start))
10456 offset = tg3_nvram_logical_addr(tp, offset);
10457 if (tg3_nvram_read_swab(tp, offset, &val))
10460 if ((val & 0xfc000000) == 0x0c000000) {
10461 u32 ver_offset, addr;
10464 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10465 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10471 addr = offset + ver_offset - start;
10472 for (i = 0; i < 16; i += 4) {
10473 if (tg3_nvram_read(tp, addr + i, &val))
10476 val = cpu_to_le32(val);
10477 memcpy(tp->fw_ver + i, &val, 4);
10482 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
10484 static int __devinit tg3_get_invariants(struct tg3 *tp)
10486 static struct pci_device_id write_reorder_chipsets[] = {
10487 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10488 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10489 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10490 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10491 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10492 PCI_DEVICE_ID_VIA_8385_0) },
10496 u32 cacheline_sz_reg;
10497 u32 pci_state_reg, grc_misc_cfg;
10502 /* Force memory write invalidate off. If we leave it on,
10503 * then on 5700_BX chips we have to enable a workaround.
10504 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10505 * to match the cacheline size. The Broadcom driver have this
10506 * workaround but turns MWI off all the times so never uses
10507 * it. This seems to suggest that the workaround is insufficient.
10509 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10510 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10511 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10513 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10514 * has the register indirect write enable bit set before
10515 * we try to access any of the MMIO registers. It is also
10516 * critical that the PCI-X hw workaround situation is decided
10517 * before that as well.
10519 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10522 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10523 MISC_HOST_CTRL_CHIPREV_SHIFT);
10525 /* Wrong chip ID in 5752 A0. This code can be removed later
10526 * as A0 is not in production.
10528 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10529 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10531 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10532 * we need to disable memory and use config. cycles
10533 * only to access all registers. The 5702/03 chips
10534 * can mistakenly decode the special cycles from the
10535 * ICH chipsets as memory write cycles, causing corruption
10536 * of register and memory space. Only certain ICH bridges
10537 * will drive special cycles with non-zero data during the
10538 * address phase which can fall within the 5703's address
10539 * range. This is not an ICH bug as the PCI spec allows
10540 * non-zero address during special cycles. However, only
10541 * these ICH bridges are known to drive non-zero addresses
10542 * during special cycles.
10544 * Since special cycles do not cross PCI bridges, we only
10545 * enable this workaround if the 5703 is on the secondary
10546 * bus of these ICH bridges.
10548 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10549 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10550 static struct tg3_dev_id {
10554 } ich_chipsets[] = {
10555 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10557 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10559 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10561 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10565 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10566 struct pci_dev *bridge = NULL;
10568 while (pci_id->vendor != 0) {
10569 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10575 if (pci_id->rev != PCI_ANY_ID) {
10576 if (bridge->revision > pci_id->rev)
10579 if (bridge->subordinate &&
10580 (bridge->subordinate->number ==
10581 tp->pdev->bus->number)) {
10583 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10584 pci_dev_put(bridge);
10590 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10591 * DMA addresses > 40-bit. This bridge may have other additional
10592 * 57xx devices behind it in some 4-port NIC designs for example.
10593 * Any tg3 device found behind the bridge will also need the 40-bit
10596 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10597 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10598 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10599 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10600 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10603 struct pci_dev *bridge = NULL;
10606 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10607 PCI_DEVICE_ID_SERVERWORKS_EPB,
10609 if (bridge && bridge->subordinate &&
10610 (bridge->subordinate->number <=
10611 tp->pdev->bus->number) &&
10612 (bridge->subordinate->subordinate >=
10613 tp->pdev->bus->number)) {
10614 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10615 pci_dev_put(bridge);
10621 /* Initialize misc host control in PCI block. */
10622 tp->misc_host_ctrl |= (misc_ctrl_reg &
10623 MISC_HOST_CTRL_CHIPREV);
10624 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10625 tp->misc_host_ctrl);
10627 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10628 &cacheline_sz_reg);
10630 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10631 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10632 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10633 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10635 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10636 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10637 tp->pdev_peer = tg3_find_peer(tp);
10639 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10641 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10642 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10643 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10644 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10645 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10647 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10648 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10649 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10651 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10652 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
10653 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
10654 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
10655 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
10656 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
10657 tp->pdev_peer == tp->pdev))
10658 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
10660 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10661 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10663 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10664 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10666 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10667 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10669 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10670 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10674 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10675 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10676 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10677 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10678 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10679 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10680 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10682 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10683 if (pcie_cap != 0) {
10684 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10685 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10688 pci_read_config_word(tp->pdev,
10689 pcie_cap + PCI_EXP_LNKCTL,
10691 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10692 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10696 /* If we have an AMD 762 or VIA K8T800 chipset, write
10697 * reordering to the mailbox registers done by the host
10698 * controller can cause major troubles. We read back from
10699 * every mailbox register write to force the writes to be
10700 * posted to the chip in order.
10702 if (pci_dev_present(write_reorder_chipsets) &&
10703 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10704 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10706 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10707 tp->pci_lat_timer < 64) {
10708 tp->pci_lat_timer = 64;
10710 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10711 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10712 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10713 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10715 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10719 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10722 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10723 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10725 /* If this is a 5700 BX chipset, and we are in PCI-X
10726 * mode, enable register write workaround.
10728 * The workaround is to use indirect register accesses
10729 * for all chip writes not to mailbox registers.
10731 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10735 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10737 /* The chip can have it's power management PCI config
10738 * space registers clobbered due to this bug.
10739 * So explicitly force the chip into D0 here.
10741 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10743 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10744 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10745 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10748 /* Also, force SERR#/PERR# in PCI command. */
10749 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10750 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10751 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10755 /* 5700 BX chips need to have their TX producer index mailboxes
10756 * written twice to workaround a bug.
10758 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10759 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10761 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10762 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10763 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10764 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10766 /* Chip-specific fixup from Broadcom driver */
10767 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10768 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10769 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10770 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10773 /* Default fast path register access methods */
10774 tp->read32 = tg3_read32;
10775 tp->write32 = tg3_write32;
10776 tp->read32_mbox = tg3_read32;
10777 tp->write32_mbox = tg3_write32;
10778 tp->write32_tx_mbox = tg3_write32;
10779 tp->write32_rx_mbox = tg3_write32;
10781 /* Various workaround register access methods */
10782 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10783 tp->write32 = tg3_write_indirect_reg32;
10784 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10785 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10786 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
10788 * Back to back register writes can cause problems on these
10789 * chips, the workaround is to read back all reg writes
10790 * except those to mailbox regs.
10792 * See tg3_write_indirect_reg32().
10794 tp->write32 = tg3_write_flush_reg32;
10798 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10799 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10800 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10801 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10802 tp->write32_rx_mbox = tg3_write_flush_reg32;
10805 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10806 tp->read32 = tg3_read_indirect_reg32;
10807 tp->write32 = tg3_write_indirect_reg32;
10808 tp->read32_mbox = tg3_read_indirect_mbox;
10809 tp->write32_mbox = tg3_write_indirect_mbox;
10810 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10811 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10816 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10817 pci_cmd &= ~PCI_COMMAND_MEMORY;
10818 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10820 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10821 tp->read32_mbox = tg3_read32_mbox_5906;
10822 tp->write32_mbox = tg3_write32_mbox_5906;
10823 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10824 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10827 if (tp->write32 == tg3_write_indirect_reg32 ||
10828 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10829 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10830 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10831 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10833 /* Get eeprom hw config before calling tg3_set_power_state().
10834 * In particular, the TG3_FLG2_IS_NIC flag must be
10835 * determined before calling tg3_set_power_state() so that
10836 * we know whether or not to switch out of Vaux power.
10837 * When the flag is set, it means that GPIO1 is used for eeprom
10838 * write protect and also implies that it is a LOM where GPIOs
10839 * are not used to switch power.
10841 tg3_get_eeprom_hw_cfg(tp);
10843 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10844 * GPIO1 driven high will bring 5700's external PHY out of reset.
10845 * It is also used as eeprom write protect on LOMs.
10847 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10848 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10849 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10850 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10851 GRC_LCLCTRL_GPIO_OUTPUT1);
10852 /* Unused GPIO3 must be driven as output on 5752 because there
10853 * are no pull-up resistors on unused GPIO pins.
10855 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10856 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10859 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10861 /* Force the chip into D0. */
10862 err = tg3_set_power_state(tp, PCI_D0);
10864 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10865 pci_name(tp->pdev));
10869 /* 5700 B0 chips do not support checksumming correctly due
10870 * to hardware bugs.
10872 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10873 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10875 /* Derive initial jumbo mode from MTU assigned in
10876 * ether_setup() via the alloc_etherdev() call
10878 if (tp->dev->mtu > ETH_DATA_LEN &&
10879 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10880 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10882 /* Determine WakeOnLan speed to use. */
10883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10884 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10885 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10886 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10887 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10889 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10892 /* A few boards don't want Ethernet@WireSpeed phy feature */
10893 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10894 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10895 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10896 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10897 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10898 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10899 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10901 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10902 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10903 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10904 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10905 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10907 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10908 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10909 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10910 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10911 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10912 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10913 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10914 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10915 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10916 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10919 tp->coalesce_mode = 0;
10920 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10921 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10922 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10924 /* Initialize MAC MI mode, polling disabled. */
10925 tw32_f(MAC_MI_MODE, tp->mi_mode);
10928 /* Initialize data/descriptor byte/word swapping. */
10929 val = tr32(GRC_MODE);
10930 val &= GRC_MODE_HOST_STACKUP;
10931 tw32(GRC_MODE, val | tp->grc_mode);
10933 tg3_switch_clocks(tp);
10935 /* Clear this out for sanity. */
10936 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10938 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10940 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10941 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10942 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10944 if (chiprevid == CHIPREV_ID_5701_A0 ||
10945 chiprevid == CHIPREV_ID_5701_B0 ||
10946 chiprevid == CHIPREV_ID_5701_B2 ||
10947 chiprevid == CHIPREV_ID_5701_B5) {
10948 void __iomem *sram_base;
10950 /* Write some dummy words into the SRAM status block
10951 * area, see if it reads back correctly. If the return
10952 * value is bad, force enable the PCIX workaround.
10954 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10956 writel(0x00000000, sram_base);
10957 writel(0x00000000, sram_base + 4);
10958 writel(0xffffffff, sram_base + 4);
10959 if (readl(sram_base) != 0x00000000)
10960 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10965 tg3_nvram_init(tp);
10967 grc_misc_cfg = tr32(GRC_MISC_CFG);
10968 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10970 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10971 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10972 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10973 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10975 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10976 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10977 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10978 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10979 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10980 HOSTCC_MODE_CLRTICK_TXBD);
10982 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10983 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10984 tp->misc_host_ctrl);
10987 /* these are limited to 10/100 only */
10988 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10989 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10990 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10991 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10992 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10993 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10994 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10995 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10996 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10997 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10998 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11000 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
11002 err = tg3_phy_probe(tp);
11004 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
11005 pci_name(tp->pdev), err);
11006 /* ... but do not return immediately ... */
11009 tg3_read_partno(tp);
11010 tg3_read_fw_ver(tp);
11012 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
11013 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11015 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11016 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
11018 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11021 /* 5700 {AX,BX} chips have a broken status block link
11022 * change bit implementation, so we must use the
11023 * status register in those cases.
11025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11026 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
11028 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
11030 /* The led_ctrl is set during tg3_phy_probe, here we might
11031 * have to force the link status polling mechanism based
11032 * upon subsystem IDs.
11034 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
11035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11036 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
11037 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
11038 TG3_FLAG_USE_LINKCHG_REG);
11041 /* For all SERDES we poll the MAC status register. */
11042 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11043 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
11045 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
11047 /* All chips before 5787 can get confused if TX buffers
11048 * straddle the 4GB address boundary in some cases.
11050 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11052 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11053 tp->dev->hard_start_xmit = tg3_start_xmit;
11055 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
11058 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11059 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11062 tp->rx_std_max_post = TG3_RX_RING_SIZE;
11064 /* Increment the rx prod index on the rx std ring by at most
11065 * 8 for these chips to workaround hw errata.
11067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11068 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11070 tp->rx_std_max_post = 8;
11072 /* By default, disable wake-on-lan. User can change this
11073 * using ETHTOOL_SWOL.
11075 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
11077 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11078 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11079 PCIE_PWR_MGMT_L1_THRESH_MSK;
11084 #ifdef CONFIG_SPARC
11085 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11087 struct net_device *dev = tp->dev;
11088 struct pci_dev *pdev = tp->pdev;
11089 struct device_node *dp = pci_device_to_OF_node(pdev);
11090 const unsigned char *addr;
11093 addr = of_get_property(dp, "local-mac-address", &len);
11094 if (addr && len == 6) {
11095 memcpy(dev->dev_addr, addr, 6);
11096 memcpy(dev->perm_addr, dev->dev_addr, 6);
11102 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11104 struct net_device *dev = tp->dev;
11106 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11107 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11112 static int __devinit tg3_get_device_address(struct tg3 *tp)
11114 struct net_device *dev = tp->dev;
11115 u32 hi, lo, mac_offset;
11118 #ifdef CONFIG_SPARC
11119 if (!tg3_get_macaddr_sparc(tp))
11124 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11125 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11126 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11128 if (tg3_nvram_lock(tp))
11129 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11131 tg3_nvram_unlock(tp);
11133 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11136 /* First try to get it from MAC address mailbox. */
11137 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11138 if ((hi >> 16) == 0x484b) {
11139 dev->dev_addr[0] = (hi >> 8) & 0xff;
11140 dev->dev_addr[1] = (hi >> 0) & 0xff;
11142 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11143 dev->dev_addr[2] = (lo >> 24) & 0xff;
11144 dev->dev_addr[3] = (lo >> 16) & 0xff;
11145 dev->dev_addr[4] = (lo >> 8) & 0xff;
11146 dev->dev_addr[5] = (lo >> 0) & 0xff;
11148 /* Some old bootcode may report a 0 MAC address in SRAM */
11149 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11152 /* Next, try NVRAM. */
11153 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11154 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11155 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11156 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11157 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11158 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11159 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11160 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11162 /* Finally just fetch it out of the MAC control regs. */
11164 hi = tr32(MAC_ADDR_0_HIGH);
11165 lo = tr32(MAC_ADDR_0_LOW);
11167 dev->dev_addr[5] = lo & 0xff;
11168 dev->dev_addr[4] = (lo >> 8) & 0xff;
11169 dev->dev_addr[3] = (lo >> 16) & 0xff;
11170 dev->dev_addr[2] = (lo >> 24) & 0xff;
11171 dev->dev_addr[1] = hi & 0xff;
11172 dev->dev_addr[0] = (hi >> 8) & 0xff;
11176 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11177 #ifdef CONFIG_SPARC64
11178 if (!tg3_get_default_macaddr_sparc(tp))
11183 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11187 #define BOUNDARY_SINGLE_CACHELINE 1
11188 #define BOUNDARY_MULTI_CACHELINE 2
11190 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11192 int cacheline_size;
11196 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11198 cacheline_size = 1024;
11200 cacheline_size = (int) byte * 4;
11202 /* On 5703 and later chips, the boundary bits have no
11205 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11206 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11207 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11210 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11211 goal = BOUNDARY_MULTI_CACHELINE;
11213 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11214 goal = BOUNDARY_SINGLE_CACHELINE;
11223 /* PCI controllers on most RISC systems tend to disconnect
11224 * when a device tries to burst across a cache-line boundary.
11225 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11227 * Unfortunately, for PCI-E there are only limited
11228 * write-side controls for this, and thus for reads
11229 * we will still get the disconnects. We'll also waste
11230 * these PCI cycles for both read and write for chips
11231 * other than 5700 and 5701 which do not implement the
11234 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11235 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11236 switch (cacheline_size) {
11241 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11242 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11243 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11245 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11246 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11251 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11252 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11256 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11257 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11260 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11261 switch (cacheline_size) {
11265 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11266 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11267 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11273 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11274 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11278 switch (cacheline_size) {
11280 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11281 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11282 DMA_RWCTRL_WRITE_BNDRY_16);
11287 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11288 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11289 DMA_RWCTRL_WRITE_BNDRY_32);
11294 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11295 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11296 DMA_RWCTRL_WRITE_BNDRY_64);
11301 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11302 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11303 DMA_RWCTRL_WRITE_BNDRY_128);
11308 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11309 DMA_RWCTRL_WRITE_BNDRY_256);
11312 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11313 DMA_RWCTRL_WRITE_BNDRY_512);
11317 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11318 DMA_RWCTRL_WRITE_BNDRY_1024);
11327 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11329 struct tg3_internal_buffer_desc test_desc;
11330 u32 sram_dma_descs;
11333 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11335 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11336 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11337 tw32(RDMAC_STATUS, 0);
11338 tw32(WDMAC_STATUS, 0);
11340 tw32(BUFMGR_MODE, 0);
11341 tw32(FTQ_RESET, 0);
11343 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11344 test_desc.addr_lo = buf_dma & 0xffffffff;
11345 test_desc.nic_mbuf = 0x00002100;
11346 test_desc.len = size;
11349 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11350 * the *second* time the tg3 driver was getting loaded after an
11353 * Broadcom tells me:
11354 * ...the DMA engine is connected to the GRC block and a DMA
11355 * reset may affect the GRC block in some unpredictable way...
11356 * The behavior of resets to individual blocks has not been tested.
11358 * Broadcom noted the GRC reset will also reset all sub-components.
11361 test_desc.cqid_sqid = (13 << 8) | 2;
11363 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11366 test_desc.cqid_sqid = (16 << 8) | 7;
11368 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11371 test_desc.flags = 0x00000005;
11373 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11376 val = *(((u32 *)&test_desc) + i);
11377 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11378 sram_dma_descs + (i * sizeof(u32)));
11379 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11381 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11384 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11386 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11390 for (i = 0; i < 40; i++) {
11394 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11396 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11397 if ((val & 0xffff) == sram_dma_descs) {
11408 #define TEST_BUFFER_SIZE 0x2000
11410 static int __devinit tg3_test_dma(struct tg3 *tp)
11412 dma_addr_t buf_dma;
11413 u32 *buf, saved_dma_rwctrl;
11416 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11422 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11423 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11425 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11427 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11428 /* DMA read watermark not used on PCIE */
11429 tp->dma_rwctrl |= 0x00180000;
11430 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11431 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11432 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11433 tp->dma_rwctrl |= 0x003f0000;
11435 tp->dma_rwctrl |= 0x003f000f;
11437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11438 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11439 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11440 u32 read_water = 0x7;
11442 /* If the 5704 is behind the EPB bridge, we can
11443 * do the less restrictive ONE_DMA workaround for
11444 * better performance.
11446 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11447 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11448 tp->dma_rwctrl |= 0x8000;
11449 else if (ccval == 0x6 || ccval == 0x7)
11450 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11452 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11454 /* Set bit 23 to enable PCIX hw bug fix */
11456 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11457 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11459 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11460 /* 5780 always in PCIX mode */
11461 tp->dma_rwctrl |= 0x00144000;
11462 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11463 /* 5714 always in PCIX mode */
11464 tp->dma_rwctrl |= 0x00148000;
11466 tp->dma_rwctrl |= 0x001b000f;
11470 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11471 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11472 tp->dma_rwctrl &= 0xfffffff0;
11474 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11475 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11476 /* Remove this if it causes problems for some boards. */
11477 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11479 /* On 5700/5701 chips, we need to set this bit.
11480 * Otherwise the chip will issue cacheline transactions
11481 * to streamable DMA memory with not all the byte
11482 * enables turned on. This is an error on several
11483 * RISC PCI controllers, in particular sparc64.
11485 * On 5703/5704 chips, this bit has been reassigned
11486 * a different meaning. In particular, it is used
11487 * on those chips to enable a PCI-X workaround.
11489 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11492 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11495 /* Unneeded, already done by tg3_get_invariants. */
11496 tg3_switch_clocks(tp);
11500 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11501 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11504 /* It is best to perform DMA test with maximum write burst size
11505 * to expose the 5700/5701 write DMA bug.
11507 saved_dma_rwctrl = tp->dma_rwctrl;
11508 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11509 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11514 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11517 /* Send the buffer to the chip. */
11518 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11520 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11525 /* validate data reached card RAM correctly. */
11526 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11528 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11529 if (le32_to_cpu(val) != p[i]) {
11530 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11531 /* ret = -ENODEV here? */
11536 /* Now read it back. */
11537 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11539 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11545 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11549 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11550 DMA_RWCTRL_WRITE_BNDRY_16) {
11551 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11552 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11553 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11556 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11562 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11568 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11569 DMA_RWCTRL_WRITE_BNDRY_16) {
11570 static struct pci_device_id dma_wait_state_chipsets[] = {
11571 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11572 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11576 /* DMA test passed without adjusting DMA boundary,
11577 * now look for chipsets that are known to expose the
11578 * DMA bug without failing the test.
11580 if (pci_dev_present(dma_wait_state_chipsets)) {
11581 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11582 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11585 /* Safe to use the calculated DMA boundary. */
11586 tp->dma_rwctrl = saved_dma_rwctrl;
11588 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11592 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11597 static void __devinit tg3_init_link_config(struct tg3 *tp)
11599 tp->link_config.advertising =
11600 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11601 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11602 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11603 ADVERTISED_Autoneg | ADVERTISED_MII);
11604 tp->link_config.speed = SPEED_INVALID;
11605 tp->link_config.duplex = DUPLEX_INVALID;
11606 tp->link_config.autoneg = AUTONEG_ENABLE;
11607 tp->link_config.active_speed = SPEED_INVALID;
11608 tp->link_config.active_duplex = DUPLEX_INVALID;
11609 tp->link_config.phy_is_low_power = 0;
11610 tp->link_config.orig_speed = SPEED_INVALID;
11611 tp->link_config.orig_duplex = DUPLEX_INVALID;
11612 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11615 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11617 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11618 tp->bufmgr_config.mbuf_read_dma_low_water =
11619 DEFAULT_MB_RDMA_LOW_WATER_5705;
11620 tp->bufmgr_config.mbuf_mac_rx_low_water =
11621 DEFAULT_MB_MACRX_LOW_WATER_5705;
11622 tp->bufmgr_config.mbuf_high_water =
11623 DEFAULT_MB_HIGH_WATER_5705;
11624 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11625 tp->bufmgr_config.mbuf_mac_rx_low_water =
11626 DEFAULT_MB_MACRX_LOW_WATER_5906;
11627 tp->bufmgr_config.mbuf_high_water =
11628 DEFAULT_MB_HIGH_WATER_5906;
11631 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11632 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11633 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11634 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11635 tp->bufmgr_config.mbuf_high_water_jumbo =
11636 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11638 tp->bufmgr_config.mbuf_read_dma_low_water =
11639 DEFAULT_MB_RDMA_LOW_WATER;
11640 tp->bufmgr_config.mbuf_mac_rx_low_water =
11641 DEFAULT_MB_MACRX_LOW_WATER;
11642 tp->bufmgr_config.mbuf_high_water =
11643 DEFAULT_MB_HIGH_WATER;
11645 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11646 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11647 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11648 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11649 tp->bufmgr_config.mbuf_high_water_jumbo =
11650 DEFAULT_MB_HIGH_WATER_JUMBO;
11653 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11654 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11657 static char * __devinit tg3_phy_string(struct tg3 *tp)
11659 switch (tp->phy_id & PHY_ID_MASK) {
11660 case PHY_ID_BCM5400: return "5400";
11661 case PHY_ID_BCM5401: return "5401";
11662 case PHY_ID_BCM5411: return "5411";
11663 case PHY_ID_BCM5701: return "5701";
11664 case PHY_ID_BCM5703: return "5703";
11665 case PHY_ID_BCM5704: return "5704";
11666 case PHY_ID_BCM5705: return "5705";
11667 case PHY_ID_BCM5750: return "5750";
11668 case PHY_ID_BCM5752: return "5752";
11669 case PHY_ID_BCM5714: return "5714";
11670 case PHY_ID_BCM5780: return "5780";
11671 case PHY_ID_BCM5755: return "5755";
11672 case PHY_ID_BCM5787: return "5787";
11673 case PHY_ID_BCM5756: return "5722/5756";
11674 case PHY_ID_BCM5906: return "5906";
11675 case PHY_ID_BCM8002: return "8002/serdes";
11676 case 0: return "serdes";
11677 default: return "unknown";
11681 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11683 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11684 strcpy(str, "PCI Express");
11686 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11687 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11689 strcpy(str, "PCIX:");
11691 if ((clock_ctrl == 7) ||
11692 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11693 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11694 strcat(str, "133MHz");
11695 else if (clock_ctrl == 0)
11696 strcat(str, "33MHz");
11697 else if (clock_ctrl == 2)
11698 strcat(str, "50MHz");
11699 else if (clock_ctrl == 4)
11700 strcat(str, "66MHz");
11701 else if (clock_ctrl == 6)
11702 strcat(str, "100MHz");
11704 strcpy(str, "PCI:");
11705 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11706 strcat(str, "66MHz");
11708 strcat(str, "33MHz");
11710 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11711 strcat(str, ":32-bit");
11713 strcat(str, ":64-bit");
11717 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11719 struct pci_dev *peer;
11720 unsigned int func, devnr = tp->pdev->devfn & ~7;
11722 for (func = 0; func < 8; func++) {
11723 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11724 if (peer && peer != tp->pdev)
11728 /* 5704 can be configured in single-port mode, set peer to
11729 * tp->pdev in that case.
11737 * We don't need to keep the refcount elevated; there's no way
11738 * to remove one half of this device without removing the other
11745 static void __devinit tg3_init_coal(struct tg3 *tp)
11747 struct ethtool_coalesce *ec = &tp->coal;
11749 memset(ec, 0, sizeof(*ec));
11750 ec->cmd = ETHTOOL_GCOALESCE;
11751 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11752 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11753 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11754 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11755 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11756 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11757 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11758 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11759 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11761 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11762 HOSTCC_MODE_CLRTICK_TXBD)) {
11763 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11764 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11765 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11766 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11769 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11770 ec->rx_coalesce_usecs_irq = 0;
11771 ec->tx_coalesce_usecs_irq = 0;
11772 ec->stats_block_coalesce_usecs = 0;
11776 static int __devinit tg3_init_one(struct pci_dev *pdev,
11777 const struct pci_device_id *ent)
11779 static int tg3_version_printed = 0;
11780 unsigned long tg3reg_base, tg3reg_len;
11781 struct net_device *dev;
11783 int i, err, pm_cap;
11785 u64 dma_mask, persist_dma_mask;
11787 if (tg3_version_printed++ == 0)
11788 printk(KERN_INFO "%s", version);
11790 err = pci_enable_device(pdev);
11792 printk(KERN_ERR PFX "Cannot enable PCI device, "
11797 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11798 printk(KERN_ERR PFX "Cannot find proper PCI device "
11799 "base address, aborting.\n");
11801 goto err_out_disable_pdev;
11804 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11806 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11808 goto err_out_disable_pdev;
11811 pci_set_master(pdev);
11813 /* Find power-management capability. */
11814 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11816 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11819 goto err_out_free_res;
11822 tg3reg_base = pci_resource_start(pdev, 0);
11823 tg3reg_len = pci_resource_len(pdev, 0);
11825 dev = alloc_etherdev(sizeof(*tp));
11827 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11829 goto err_out_free_res;
11832 SET_MODULE_OWNER(dev);
11833 SET_NETDEV_DEV(dev, &pdev->dev);
11835 #if TG3_VLAN_TAG_USED
11836 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11837 dev->vlan_rx_register = tg3_vlan_rx_register;
11840 tp = netdev_priv(dev);
11843 tp->pm_cap = pm_cap;
11844 tp->mac_mode = TG3_DEF_MAC_MODE;
11845 tp->rx_mode = TG3_DEF_RX_MODE;
11846 tp->tx_mode = TG3_DEF_TX_MODE;
11847 tp->mi_mode = MAC_MI_MODE_BASE;
11849 tp->msg_enable = tg3_debug;
11851 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11853 /* The word/byte swap controls here control register access byte
11854 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11857 tp->misc_host_ctrl =
11858 MISC_HOST_CTRL_MASK_PCI_INT |
11859 MISC_HOST_CTRL_WORD_SWAP |
11860 MISC_HOST_CTRL_INDIR_ACCESS |
11861 MISC_HOST_CTRL_PCISTATE_RW;
11863 /* The NONFRM (non-frame) byte/word swap controls take effect
11864 * on descriptor entries, anything which isn't packet data.
11866 * The StrongARM chips on the board (one for tx, one for rx)
11867 * are running in big-endian mode.
11869 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11870 GRC_MODE_WSWAP_NONFRM_DATA);
11871 #ifdef __BIG_ENDIAN
11872 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11874 spin_lock_init(&tp->lock);
11875 spin_lock_init(&tp->indirect_lock);
11876 INIT_WORK(&tp->reset_task, tg3_reset_task);
11878 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11879 if (tp->regs == 0UL) {
11880 printk(KERN_ERR PFX "Cannot map device registers, "
11883 goto err_out_free_dev;
11886 tg3_init_link_config(tp);
11888 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11889 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11890 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11892 dev->open = tg3_open;
11893 dev->stop = tg3_close;
11894 dev->get_stats = tg3_get_stats;
11895 dev->set_multicast_list = tg3_set_rx_mode;
11896 dev->set_mac_address = tg3_set_mac_addr;
11897 dev->do_ioctl = tg3_ioctl;
11898 dev->tx_timeout = tg3_tx_timeout;
11899 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
11900 dev->ethtool_ops = &tg3_ethtool_ops;
11901 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11902 dev->change_mtu = tg3_change_mtu;
11903 dev->irq = pdev->irq;
11904 #ifdef CONFIG_NET_POLL_CONTROLLER
11905 dev->poll_controller = tg3_poll_controller;
11908 err = tg3_get_invariants(tp);
11910 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11912 goto err_out_iounmap;
11915 /* The EPB bridge inside 5714, 5715, and 5780 and any
11916 * device behind the EPB cannot support DMA addresses > 40-bit.
11917 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11918 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11919 * do DMA address check in tg3_start_xmit().
11921 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11922 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11923 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11924 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11925 #ifdef CONFIG_HIGHMEM
11926 dma_mask = DMA_64BIT_MASK;
11929 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11931 /* Configure DMA attributes. */
11932 if (dma_mask > DMA_32BIT_MASK) {
11933 err = pci_set_dma_mask(pdev, dma_mask);
11935 dev->features |= NETIF_F_HIGHDMA;
11936 err = pci_set_consistent_dma_mask(pdev,
11939 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11940 "DMA for consistent allocations\n");
11941 goto err_out_iounmap;
11945 if (err || dma_mask == DMA_32BIT_MASK) {
11946 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11948 printk(KERN_ERR PFX "No usable DMA configuration, "
11950 goto err_out_iounmap;
11954 tg3_init_bufmgr_config(tp);
11956 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11957 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11959 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11960 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11961 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11962 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11963 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11964 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11966 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11969 /* TSO is on by default on chips that support hardware TSO.
11970 * Firmware TSO on older chips gives lower performance, so it
11971 * is off by default, but can be enabled using ethtool.
11973 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11974 dev->features |= NETIF_F_TSO;
11975 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11976 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11977 dev->features |= NETIF_F_TSO6;
11981 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11982 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11983 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11984 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11985 tp->rx_pending = 63;
11988 err = tg3_get_device_address(tp);
11990 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11992 goto err_out_iounmap;
11996 * Reset chip in case UNDI or EFI driver did not shutdown
11997 * DMA self test will enable WDMAC and we'll see (spurious)
11998 * pending DMA on the PCI bus at that point.
12000 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
12001 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
12002 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
12003 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12006 err = tg3_test_dma(tp);
12008 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
12009 goto err_out_iounmap;
12012 /* Tigon3 can do ipv4 only... and some chips have buggy
12015 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
12016 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12017 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12018 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
12019 dev->features |= NETIF_F_IPV6_CSUM;
12021 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12023 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
12025 /* flow control autonegotiation is default behavior */
12026 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12030 pci_set_drvdata(pdev, dev);
12032 err = register_netdev(dev);
12034 printk(KERN_ERR PFX "Cannot register net device, "
12036 goto err_out_iounmap;
12039 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
12041 tp->board_part_number,
12042 tp->pci_chip_rev_id,
12043 tg3_phy_string(tp),
12044 tg3_bus_string(tp, str),
12045 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12046 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
12047 "10/100/1000Base-T")));
12049 for (i = 0; i < 6; i++)
12050 printk("%2.2x%c", dev->dev_addr[i],
12051 i == 5 ? '\n' : ':');
12053 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
12054 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
12056 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
12057 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
12058 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
12059 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
12060 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
12061 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
12062 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12063 dev->name, tp->dma_rwctrl,
12064 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12065 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
12079 pci_release_regions(pdev);
12081 err_out_disable_pdev:
12082 pci_disable_device(pdev);
12083 pci_set_drvdata(pdev, NULL);
12087 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12089 struct net_device *dev = pci_get_drvdata(pdev);
12092 struct tg3 *tp = netdev_priv(dev);
12094 flush_scheduled_work();
12095 unregister_netdev(dev);
12101 pci_release_regions(pdev);
12102 pci_disable_device(pdev);
12103 pci_set_drvdata(pdev, NULL);
12107 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12109 struct net_device *dev = pci_get_drvdata(pdev);
12110 struct tg3 *tp = netdev_priv(dev);
12113 /* PCI register 4 needs to be saved whether netif_running() or not.
12114 * MSI address and data need to be saved if using MSI and
12117 pci_save_state(pdev);
12119 if (!netif_running(dev))
12122 flush_scheduled_work();
12123 tg3_netif_stop(tp);
12125 del_timer_sync(&tp->timer);
12127 tg3_full_lock(tp, 1);
12128 tg3_disable_ints(tp);
12129 tg3_full_unlock(tp);
12131 netif_device_detach(dev);
12133 tg3_full_lock(tp, 0);
12134 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12135 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12136 tg3_full_unlock(tp);
12138 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12140 tg3_full_lock(tp, 0);
12142 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12143 if (tg3_restart_hw(tp, 1))
12146 tp->timer.expires = jiffies + tp->timer_offset;
12147 add_timer(&tp->timer);
12149 netif_device_attach(dev);
12150 tg3_netif_start(tp);
12153 tg3_full_unlock(tp);
12159 static int tg3_resume(struct pci_dev *pdev)
12161 struct net_device *dev = pci_get_drvdata(pdev);
12162 struct tg3 *tp = netdev_priv(dev);
12165 pci_restore_state(tp->pdev);
12167 if (!netif_running(dev))
12170 err = tg3_set_power_state(tp, PCI_D0);
12174 /* Hardware bug - MSI won't work if INTX disabled. */
12175 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
12176 (tp->tg3_flags2 & TG3_FLG2_USING_MSI))
12177 pci_intx(tp->pdev, 1);
12179 netif_device_attach(dev);
12181 tg3_full_lock(tp, 0);
12183 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12184 err = tg3_restart_hw(tp, 1);
12188 tp->timer.expires = jiffies + tp->timer_offset;
12189 add_timer(&tp->timer);
12191 tg3_netif_start(tp);
12194 tg3_full_unlock(tp);
12199 static struct pci_driver tg3_driver = {
12200 .name = DRV_MODULE_NAME,
12201 .id_table = tg3_pci_tbl,
12202 .probe = tg3_init_one,
12203 .remove = __devexit_p(tg3_remove_one),
12204 .suspend = tg3_suspend,
12205 .resume = tg3_resume
12208 static int __init tg3_init(void)
12210 return pci_register_driver(&tg3_driver);
12213 static void __exit tg3_cleanup(void)
12215 pci_unregister_driver(&tg3_driver);
12218 module_init(tg3_init);
12219 module_exit(tg3_cleanup);