drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18 #include <linux/config.h>
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40
  41 #include <net/checksum.h>
  42
  43 #include <asm/system.h>
  44 #include <asm/io.h>
  45 #include <asm/byteorder.h>
  46 #include <asm/uaccess.h>
  47
  48 #ifdef CONFIG_SPARC64
  49 #include <asm/idprom.h>
  50 #include <asm/oplib.h>
  51 #include <asm/pbm.h>
  52 #endif
  53
  54 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  55 #define TG3_VLAN_TAG_USED 1
  56 #else
  57 #define TG3_VLAN_TAG_USED 0
  58 #endif
  59
  60 #ifdef NETIF_F_TSO
  61 #define TG3_TSO_SUPPORT 1
  62 #else
  63 #define TG3_TSO_SUPPORT 0
  64 #endif
  65
  66 #include "tg3.h"
  67
  68 #define DRV_MODULE_NAME         "tg3"
  69 #define PFX DRV_MODULE_NAME     ": "
  70 #define DRV_MODULE_VERSION      "3.38"
  71 #define DRV_MODULE_RELDATE      "September 1, 2005"
  72
  73 #define TG3_DEF_MAC_MODE        0
  74 #define TG3_DEF_RX_MODE         0
  75 #define TG3_DEF_TX_MODE         0
  76 #define TG3_DEF_MSG_ENABLE        \
  77         (NETIF_MSG_DRV          | \
  78          NETIF_MSG_PROBE        | \
  79          NETIF_MSG_LINK         | \
  80          NETIF_MSG_TIMER        | \
  81          NETIF_MSG_IFDOWN       | \
  82          NETIF_MSG_IFUP         | \
  83          NETIF_MSG_RX_ERR       | \
  84          NETIF_MSG_TX_ERR)
  85
  86 /* length of time before we decide the hardware is borked,
  87  * and dev->tx_timeout() should be called to fix the problem
  88  */
  89 #define TG3_TX_TIMEOUT                  (5 * HZ)
  90
  91 /* hardware minimum and maximum for a single frame's data payload */
  92 #define TG3_MIN_MTU                     60
  93 #define TG3_MAX_MTU(tp) \
  94         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  95
  96 /* These numbers seem to be hard coded in the NIC firmware somehow.
  97  * You can't change the ring sizes, but you can change where you place
  98  * them in the NIC onboard memory.
  99  */
 100 #define TG3_RX_RING_SIZE                512
 101 #define TG3_DEF_RX_RING_PENDING         200
 102 #define TG3_RX_JUMBO_RING_SIZE          256
 103 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 104
 105 /* Do not place this n-ring entries value into the tp struct itself,
 106  * we really want to expose these constants to GCC so that modulo et
 107  * al.  operations are done with shifts and masks instead of with
 108  * hw multiply/modulo instructions.  Another solution would be to
 109  * replace things like '% foo' with '& (foo - 1)'.
 110  */
 111 #define TG3_RX_RCB_RING_SIZE(tp)        \
 112         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 113
 114 #define TG3_TX_RING_SIZE                512
 115 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 116
 117 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 118                                  TG3_RX_RING_SIZE)
 119 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 120                                  TG3_RX_JUMBO_RING_SIZE)
 121 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 122                                    TG3_RX_RCB_RING_SIZE(tp))
 123 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 124                                  TG3_TX_RING_SIZE)
 125 #define TX_BUFFS_AVAIL(TP)                                              \
 126         ((TP)->tx_pending -                                             \
 127          (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 131 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 132
 133 /* minimum number of free TX descriptors required to wake up TX process */
 134 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
 135
 136 /* number of ETHTOOL_GSTATS u64's */
 137 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 138
 139 #define TG3_NUM_TEST            6
 140
 141 static char version[] __devinitdata =
 142         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 143
 144 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 145 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 146 MODULE_LICENSE("GPL");
 147 MODULE_VERSION(DRV_MODULE_VERSION);
 148
 149 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 150 module_param(tg3_debug, int, 0);
 151 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 152
 153 static struct pci_device_id tg3_pci_tbl[] = {
 154         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
 155           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 156         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
 157           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 158         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
 159           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 160         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
 161           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 162         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
 163           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 164         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
 165           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 166         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
 167           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 168         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
 169           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 170         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
 171           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 172         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
 173           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 174         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
 175           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 176         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
 177           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 178         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
 179           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 180         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
 181           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 182         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
 183           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 184         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
 185           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 186         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
 187           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 188         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
 189           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 190         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
 191           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 192         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
 193           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 194         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
 195           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 196         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
 197           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 198         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
 199           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 200         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
 201           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 202         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
 203           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 204         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
 205           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 206         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
 207           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 208         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
 209           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 210         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 211           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 212         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
 213           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 214         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
 215           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 216         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 217           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 218         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
 219           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 220         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
 221           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 222         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
 223           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 224         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
 225           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 226         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
 227           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 228         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
 229           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 230         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
 231           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 232         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
 233           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 234         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
 235           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 236         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
 237           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 238         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
 239           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 240         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
 241           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 242         { 0, }
 243 };
 244
 245 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 246
 247 static struct {
 248         const char string[ETH_GSTRING_LEN];
 249 } ethtool_stats_keys[TG3_NUM_STATS] = {
 250         { "rx_octets" },
 251         { "rx_fragments" },
 252         { "rx_ucast_packets" },
 253         { "rx_mcast_packets" },
 254         { "rx_bcast_packets" },
 255         { "rx_fcs_errors" },
 256         { "rx_align_errors" },
 257         { "rx_xon_pause_rcvd" },
 258         { "rx_xoff_pause_rcvd" },
 259         { "rx_mac_ctrl_rcvd" },
 260         { "rx_xoff_entered" },
 261         { "rx_frame_too_long_errors" },
 262         { "rx_jabbers" },
 263         { "rx_undersize_packets" },
 264         { "rx_in_length_errors" },
 265         { "rx_out_length_errors" },
 266         { "rx_64_or_less_octet_packets" },
 267         { "rx_65_to_127_octet_packets" },
 268         { "rx_128_to_255_octet_packets" },
 269         { "rx_256_to_511_octet_packets" },
 270         { "rx_512_to_1023_octet_packets" },
 271         { "rx_1024_to_1522_octet_packets" },
 272         { "rx_1523_to_2047_octet_packets" },
 273         { "rx_2048_to_4095_octet_packets" },
 274         { "rx_4096_to_8191_octet_packets" },
 275         { "rx_8192_to_9022_octet_packets" },
 276
 277         { "tx_octets" },
 278         { "tx_collisions" },
 279
 280         { "tx_xon_sent" },
 281         { "tx_xoff_sent" },
 282         { "tx_flow_control" },
 283         { "tx_mac_errors" },
 284         { "tx_single_collisions" },
 285         { "tx_mult_collisions" },
 286         { "tx_deferred" },
 287         { "tx_excessive_collisions" },
 288         { "tx_late_collisions" },
 289         { "tx_collide_2times" },
 290         { "tx_collide_3times" },
 291         { "tx_collide_4times" },
 292         { "tx_collide_5times" },
 293         { "tx_collide_6times" },
 294         { "tx_collide_7times" },
 295         { "tx_collide_8times" },
 296         { "tx_collide_9times" },
 297         { "tx_collide_10times" },
 298         { "tx_collide_11times" },
 299         { "tx_collide_12times" },
 300         { "tx_collide_13times" },
 301         { "tx_collide_14times" },
 302         { "tx_collide_15times" },
 303         { "tx_ucast_packets" },
 304         { "tx_mcast_packets" },
 305         { "tx_bcast_packets" },
 306         { "tx_carrier_sense_errors" },
 307         { "tx_discards" },
 308         { "tx_errors" },
 309
 310         { "dma_writeq_full" },
 311         { "dma_write_prioq_full" },
 312         { "rxbds_empty" },
 313         { "rx_discards" },
 314         { "rx_errors" },
 315         { "rx_threshold_hit" },
 316
 317         { "dma_readq_full" },
 318         { "dma_read_prioq_full" },
 319         { "tx_comp_queue_full" },
 320
 321         { "ring_set_send_prod_index" },
 322         { "ring_status_update" },
 323         { "nic_irqs" },
 324         { "nic_avoided_irqs" },
 325         { "nic_tx_threshold_hit" }
 326 };
 327
 328 static struct {
 329         const char string[ETH_GSTRING_LEN];
 330 } ethtool_test_keys[TG3_NUM_TEST] = {
 331         { "nvram test     (online) " },
 332         { "link test      (online) " },
 333         { "register test  (offline)" },
 334         { "memory test    (offline)" },
 335         { "loopback test  (offline)" },
 336         { "interrupt test (offline)" },
 337 };
 338
 339 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 340 {
 341         unsigned long flags;
 342
 343         spin_lock_irqsave(&tp->indirect_lock, flags);
 344         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 345         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 346         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 347 }
 348
 349 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 350 {
 351         writel(val, tp->regs + off);
 352         readl(tp->regs + off);
 353 }
 354
 355 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 356 {
 357         unsigned long flags;
 358         u32 val;
 359
 360         spin_lock_irqsave(&tp->indirect_lock, flags);
 361         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 362         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 363         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 364         return val;
 365 }
 366
 367 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 368 {
 369         unsigned long flags;
 370
 371         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 372                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 373                                        TG3_64BIT_REG_LOW, val);
 374                 return;
 375         }
 376         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 377                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 378                                        TG3_64BIT_REG_LOW, val);
 379                 return;
 380         }
 381
 382         spin_lock_irqsave(&tp->indirect_lock, flags);
 383         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 384         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 385         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 386
 387         /* In indirect mode when disabling interrupts, we also need
 388          * to clear the interrupt bit in the GRC local ctrl register.
 389          */
 390         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 391             (val == 0x1)) {
 392                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 393                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 394         }
 395 }
 396
 397 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 398 {
 399         unsigned long flags;
 400         u32 val;
 401
 402         spin_lock_irqsave(&tp->indirect_lock, flags);
 403         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 404         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 405         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 406         return val;
 407 }
 408
 409 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
 410 {
 411         tp->write32(tp, off, val);
 412         if (!(tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) &&
 413             !(tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) &&
 414             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 415                 tp->read32(tp, off);    /* flush */
 416 }
 417
 418 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 419 {
 420         tp->write32_mbox(tp, off, val);
 421         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 422             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 423                 tp->read32_mbox(tp, off);
 424 }
 425
 426 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 427 {
 428         void __iomem *mbox = tp->regs + off;
 429         writel(val, mbox);
 430         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 431                 writel(val, mbox);
 432         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 433                 readl(mbox);
 434 }
 435
 436 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 437 {
 438         writel(val, tp->regs + off);
 439 }
 440
 441 static u32 tg3_read32(struct tg3 *tp, u32 off)
 442 {
 443         return (readl(tp->regs + off));
 444 }
 445
 446 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 447 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 448 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 449 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 450 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 451
 452 #define tw32(reg,val)           tp->write32(tp, reg, val)
 453 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val))
 454 #define tr32(reg)               tp->read32(tp, reg)
 455
 456 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 457 {
 458         unsigned long flags;
 459
 460         spin_lock_irqsave(&tp->indirect_lock, flags);
 461         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 462         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 463
 464         /* Always leave this as zero. */
 465         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 466         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 467 }
 468
 469 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 470 {
 471         unsigned long flags;
 472
 473         spin_lock_irqsave(&tp->indirect_lock, flags);
 474         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 475         pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 476
 477         /* Always leave this as zero. */
 478         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 479         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 480 }
 481
 482 static void tg3_disable_ints(struct tg3 *tp)
 483 {
 484         tw32(TG3PCI_MISC_HOST_CTRL,
 485              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 486         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 487 }
 488
 489 static inline void tg3_cond_int(struct tg3 *tp)
 490 {
 491         if (tp->hw_status->status & SD_STATUS_UPDATED)
 492                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 493 }
 494
 495 static void tg3_enable_ints(struct tg3 *tp)
 496 {
 497         tp->irq_sync = 0;
 498         wmb();
 499
 500         tw32(TG3PCI_MISC_HOST_CTRL,
 501              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 502         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 503                        (tp->last_tag << 24));
 504         tg3_cond_int(tp);
 505 }
 506
 507 static inline unsigned int tg3_has_work(struct tg3 *tp)
 508 {
 509         struct tg3_hw_status *sblk = tp->hw_status;
 510         unsigned int work_exists = 0;
 511
 512         /* check for phy events */
 513         if (!(tp->tg3_flags &
 514               (TG3_FLAG_USE_LINKCHG_REG |
 515                TG3_FLAG_POLL_SERDES))) {
 516                 if (sblk->status & SD_STATUS_LINK_CHG)
 517                         work_exists = 1;
 518         }
 519         /* check for RX/TX work to do */
 520         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 521             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 522                 work_exists = 1;
 523
 524         return work_exists;
 525 }
 526
 527 /* tg3_restart_ints
 528  *  similar to tg3_enable_ints, but it accurately determines whether there
 529  *  is new work pending and can return without flushing the PIO write
 530  *  which reenables interrupts
 531  */
 532 static void tg3_restart_ints(struct tg3 *tp)
 533 {
 534         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 535                      tp->last_tag << 24);
 536         mmiowb();
 537
 538         /* When doing tagged status, this work check is unnecessary.
 539          * The last_tag we write above tells the chip which piece of
 540          * work we've completed.
 541          */
 542         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 543             tg3_has_work(tp))
 544                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 545                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 546 }
 547
 548 static inline void tg3_netif_stop(struct tg3 *tp)
 549 {
 550         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 551         netif_poll_disable(tp->dev);
 552         netif_tx_disable(tp->dev);
 553 }
 554
 555 static inline void tg3_netif_start(struct tg3 *tp)
 556 {
 557         netif_wake_queue(tp->dev);
 558         /* NOTE: unconditional netif_wake_queue is only appropriate
 559          * so long as all callers are assured to have free tx slots
 560          * (such as after tg3_init_hw)
 561          */
 562         netif_poll_enable(tp->dev);
 563         tp->hw_status->status |= SD_STATUS_UPDATED;
 564         tg3_enable_ints(tp);
 565 }
 566
 567 static void tg3_switch_clocks(struct tg3 *tp)
 568 {
 569         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 570         u32 orig_clock_ctrl;
 571
 572         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
 573                 return;
 574
 575         orig_clock_ctrl = clock_ctrl;
 576         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 577                        CLOCK_CTRL_CLKRUN_OENABLE |
 578                        0x1f);
 579         tp->pci_clock_ctrl = clock_ctrl;
 580
 581         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 582                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 583                         tw32_f(TG3PCI_CLOCK_CTRL,
 584                                clock_ctrl | CLOCK_CTRL_625_CORE);
 585                         udelay(40);
 586                 }
 587         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 588                 tw32_f(TG3PCI_CLOCK_CTRL,
 589                      clock_ctrl |
 590                      (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
 591                 udelay(40);
 592                 tw32_f(TG3PCI_CLOCK_CTRL,
 593                      clock_ctrl | (CLOCK_CTRL_ALTCLK));
 594                 udelay(40);
 595         }
 596         tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
 597         udelay(40);
 598 }
 599
 600 #define PHY_BUSY_LOOPS  5000
 601
 602 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 603 {
 604         u32 frame_val;
 605         unsigned int loops;
 606         int ret;
 607
 608         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 609                 tw32_f(MAC_MI_MODE,
 610                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 611                 udelay(80);
 612         }
 613
 614         *val = 0x0;
 615
 616         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 617                       MI_COM_PHY_ADDR_MASK);
 618         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 619                       MI_COM_REG_ADDR_MASK);
 620         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 621
 622         tw32_f(MAC_MI_COM, frame_val);
 623
 624         loops = PHY_BUSY_LOOPS;
 625         while (loops != 0) {
 626                 udelay(10);
 627                 frame_val = tr32(MAC_MI_COM);
 628
 629                 if ((frame_val & MI_COM_BUSY) == 0) {
 630                         udelay(5);
 631                         frame_val = tr32(MAC_MI_COM);
 632                         break;
 633                 }
 634                 loops -= 1;
 635         }
 636
 637         ret = -EBUSY;
 638         if (loops != 0) {
 639                 *val = frame_val & MI_COM_DATA_MASK;
 640                 ret = 0;
 641         }
 642
 643         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 644                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 645                 udelay(80);
 646         }
 647
 648         return ret;
 649 }
 650
 651 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 652 {
 653         u32 frame_val;
 654         unsigned int loops;
 655         int ret;
 656
 657         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 658                 tw32_f(MAC_MI_MODE,
 659                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 660                 udelay(80);
 661         }
 662
 663         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 664                       MI_COM_PHY_ADDR_MASK);
 665         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 666                       MI_COM_REG_ADDR_MASK);
 667         frame_val |= (val & MI_COM_DATA_MASK);
 668         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 669
 670         tw32_f(MAC_MI_COM, frame_val);
 671
 672         loops = PHY_BUSY_LOOPS;
 673         while (loops != 0) {
 674                 udelay(10);
 675                 frame_val = tr32(MAC_MI_COM);
 676                 if ((frame_val & MI_COM_BUSY) == 0) {
 677                         udelay(5);
 678                         frame_val = tr32(MAC_MI_COM);
 679                         break;
 680                 }
 681                 loops -= 1;
 682         }
 683
 684         ret = -EBUSY;
 685         if (loops != 0)
 686                 ret = 0;
 687
 688         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 689                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 690                 udelay(80);
 691         }
 692
 693         return ret;
 694 }
 695
 696 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 697 {
 698         u32 val;
 699
 700         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 701                 return;
 702
 703         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 704             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 705                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 706                              (val | (1 << 15) | (1 << 4)));
 707 }
 708
 709 static int tg3_bmcr_reset(struct tg3 *tp)
 710 {
 711         u32 phy_control;
 712         int limit, err;
 713
 714         /* OK, reset it, and poll the BMCR_RESET bit until it
 715          * clears or we time out.
 716          */
 717         phy_control = BMCR_RESET;
 718         err = tg3_writephy(tp, MII_BMCR, phy_control);
 719         if (err != 0)
 720                 return -EBUSY;
 721
 722         limit = 5000;
 723         while (limit--) {
 724                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 725                 if (err != 0)
 726                         return -EBUSY;
 727
 728                 if ((phy_control & BMCR_RESET) == 0) {
 729                         udelay(40);
 730                         break;
 731                 }
 732                 udelay(10);
 733         }
 734         if (limit <= 0)
 735                 return -EBUSY;
 736
 737         return 0;
 738 }
 739
 740 static int tg3_wait_macro_done(struct tg3 *tp)
 741 {
 742         int limit = 100;
 743
 744         while (limit--) {
 745                 u32 tmp32;
 746
 747                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 748                         if ((tmp32 & 0x1000) == 0)
 749                                 break;
 750                 }
 751         }
 752         if (limit <= 0)
 753                 return -EBUSY;
 754
 755         return 0;
 756 }
 757
 758 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 759 {
 760         static const u32 test_pat[4][6] = {
 761         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 762         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 763         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 764         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 765         };
 766         int chan;
 767
 768         for (chan = 0; chan < 4; chan++) {
 769                 int i;
 770
 771                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 772                              (chan * 0x2000) | 0x0200);
 773                 tg3_writephy(tp, 0x16, 0x0002);
 774
 775                 for (i = 0; i < 6; i++)
 776                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 777                                      test_pat[chan][i]);
 778
 779                 tg3_writephy(tp, 0x16, 0x0202);
 780                 if (tg3_wait_macro_done(tp)) {
 781                         *resetp = 1;
 782                         return -EBUSY;
 783                 }
 784
 785                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 786                              (chan * 0x2000) | 0x0200);
 787                 tg3_writephy(tp, 0x16, 0x0082);
 788                 if (tg3_wait_macro_done(tp)) {
 789                         *resetp = 1;
 790                         return -EBUSY;
 791                 }
 792
 793                 tg3_writephy(tp, 0x16, 0x0802);
 794                 if (tg3_wait_macro_done(tp)) {
 795                         *resetp = 1;
 796                         return -EBUSY;
 797                 }
 798
 799                 for (i = 0; i < 6; i += 2) {
 800                         u32 low, high;
 801
 802                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 803                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 804                             tg3_wait_macro_done(tp)) {
 805                                 *resetp = 1;
 806                                 return -EBUSY;
 807                         }
 808                         low &= 0x7fff;
 809                         high &= 0x000f;
 810                         if (low != test_pat[chan][i] ||
 811                             high != test_pat[chan][i+1]) {
 812                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 813                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 814                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 815
 816                                 return -EBUSY;
 817                         }
 818                 }
 819         }
 820
 821         return 0;
 822 }
 823
 824 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 825 {
 826         int chan;
 827
 828         for (chan = 0; chan < 4; chan++) {
 829                 int i;
 830
 831                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 832                              (chan * 0x2000) | 0x0200);
 833                 tg3_writephy(tp, 0x16, 0x0002);
 834                 for (i = 0; i < 6; i++)
 835                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 836                 tg3_writephy(tp, 0x16, 0x0202);
 837                 if (tg3_wait_macro_done(tp))
 838                         return -EBUSY;
 839         }
 840
 841         return 0;
 842 }
 843
 844 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 845 {
 846         u32 reg32, phy9_orig;
 847         int retries, do_phy_reset, err;
 848
 849         retries = 10;
 850         do_phy_reset = 1;
 851         do {
 852                 if (do_phy_reset) {
 853                         err = tg3_bmcr_reset(tp);
 854                         if (err)
 855                                 return err;
 856                         do_phy_reset = 0;
 857                 }
 858
 859                 /* Disable transmitter and interrupt.  */
 860                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 861                         continue;
 862
 863                 reg32 |= 0x3000;
 864                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 865
 866                 /* Set full-duplex, 1000 mbps.  */
 867                 tg3_writephy(tp, MII_BMCR,
 868                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 869
 870                 /* Set to master mode.  */
 871                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 872                         continue;
 873
 874                 tg3_writephy(tp, MII_TG3_CTRL,
 875                              (MII_TG3_CTRL_AS_MASTER |
 876                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 877
 878                 /* Enable SM_DSP_CLOCK and 6dB.  */
 879                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 880
 881                 /* Block the PHY control access.  */
 882                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 883                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 884
 885                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 886                 if (!err)
 887                         break;
 888         } while (--retries);
 889
 890         err = tg3_phy_reset_chanpat(tp);
 891         if (err)
 892                 return err;
 893
 894         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 895         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 896
 897         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 898         tg3_writephy(tp, 0x16, 0x0000);
 899
 900         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 901             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 902                 /* Set Extended packet length bit for jumbo frames */
 903                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 904         }
 905         else {
 906                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 907         }
 908
 909         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 910
 911         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 912                 reg32 &= ~0x3000;
 913                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 914         } else if (!err)
 915                 err = -EBUSY;
 916
 917         return err;
 918 }
 919
 920 /* This will reset the tigon3 PHY if there is no valid
 921  * link unless the FORCE argument is non-zero.
 922  */
 923 static int tg3_phy_reset(struct tg3 *tp)
 924 {
 925         u32 phy_status;
 926         int err;
 927
 928         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 929         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 930         if (err != 0)
 931                 return -EBUSY;
 932
 933         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 934             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 935             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 936                 err = tg3_phy_reset_5703_4_5(tp);
 937                 if (err)
 938                         return err;
 939                 goto out;
 940         }
 941
 942         err = tg3_bmcr_reset(tp);
 943         if (err)
 944                 return err;
 945
 946 out:
 947         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 948                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 949                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 950                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 951                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 952                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 953                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 954         }
 955         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 956                 tg3_writephy(tp, 0x1c, 0x8d68);
 957                 tg3_writephy(tp, 0x1c, 0x8d68);
 958         }
 959         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
 960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 961                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 962                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
 963                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 964                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
 965                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
 966                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
 967                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 968         }
 969         /* Set Extended packet length bit (bit 14) on all chips that */
 970         /* support jumbo frames */
 971         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
 972                 /* Cannot do read-modify-write on 5401 */
 973                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
 974         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
 975                 u32 phy_reg;
 976
 977                 /* Set bit 14 with read-modify-write to preserve other bits */
 978                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
 979                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
 980                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
 981         }
 982
 983         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
 984          * jumbo frames transmission.
 985          */
 986         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
 987                 u32 phy_reg;
 988
 989                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
 990                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
 991                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
 992         }
 993
 994         tg3_phy_set_wirespeed(tp);
 995         return 0;
 996 }
 997
 998 static void tg3_frob_aux_power(struct tg3 *tp)
 999 {
1000         struct tg3 *tp_peer = tp;
1001
1002         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1003                 return;
1004
1005         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1006                 tp_peer = pci_get_drvdata(tp->pdev_peer);
1007                 if (!tp_peer)
1008                         BUG();
1009         }
1010
1011
1012         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1013             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
1014                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1015                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1016                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1017                              (GRC_LCLCTRL_GPIO_OE0 |
1018                               GRC_LCLCTRL_GPIO_OE1 |
1019                               GRC_LCLCTRL_GPIO_OE2 |
1020                               GRC_LCLCTRL_GPIO_OUTPUT0 |
1021                               GRC_LCLCTRL_GPIO_OUTPUT1));
1022                         udelay(100);
1023                 } else {
1024                         u32 no_gpio2;
1025                         u32 grc_local_ctrl;
1026
1027                         if (tp_peer != tp &&
1028                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1029                                 return;
1030
1031                         /* On 5753 and variants, GPIO2 cannot be used. */
1032                         no_gpio2 = tp->nic_sram_data_cfg &
1033                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1034
1035                         grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1036                                          GRC_LCLCTRL_GPIO_OE1 |
1037                                          GRC_LCLCTRL_GPIO_OE2 |
1038                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1039                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1040                         if (no_gpio2) {
1041                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1042                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1043                         }
1044                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1045                                                 grc_local_ctrl);
1046                         udelay(100);
1047
1048                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1049
1050                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1051                                                 grc_local_ctrl);
1052                         udelay(100);
1053
1054                         if (!no_gpio2) {
1055                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1056                                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1057                                        grc_local_ctrl);
1058                                 udelay(100);
1059                         }
1060                 }
1061         } else {
1062                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1063                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1064                         if (tp_peer != tp &&
1065                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1066                                 return;
1067
1068                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1069                              (GRC_LCLCTRL_GPIO_OE1 |
1070                               GRC_LCLCTRL_GPIO_OUTPUT1));
1071                         udelay(100);
1072
1073                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1074                              (GRC_LCLCTRL_GPIO_OE1));
1075                         udelay(100);
1076
1077                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1078                              (GRC_LCLCTRL_GPIO_OE1 |
1079                               GRC_LCLCTRL_GPIO_OUTPUT1));
1080                         udelay(100);
1081                 }
1082         }
1083 }
1084
1085 static int tg3_setup_phy(struct tg3 *, int);
1086
1087 #define RESET_KIND_SHUTDOWN     0
1088 #define RESET_KIND_INIT         1
1089 #define RESET_KIND_SUSPEND      2
1090
1091 static void tg3_write_sig_post_reset(struct tg3 *, int);
1092 static int tg3_halt_cpu(struct tg3 *, u32);
1093
1094 static int tg3_set_power_state(struct tg3 *tp, int state)
1095 {
1096         u32 misc_host_ctrl;
1097         u16 power_control, power_caps;
1098         int pm = tp->pm_cap;
1099
1100         /* Make sure register accesses (indirect or otherwise)
1101          * will function correctly.
1102          */
1103         pci_write_config_dword(tp->pdev,
1104                                TG3PCI_MISC_HOST_CTRL,
1105                                tp->misc_host_ctrl);
1106
1107         pci_read_config_word(tp->pdev,
1108                              pm + PCI_PM_CTRL,
1109                              &power_control);
1110         power_control |= PCI_PM_CTRL_PME_STATUS;
1111         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1112         switch (state) {
1113         case 0:
1114                 power_control |= 0;
1115                 pci_write_config_word(tp->pdev,
1116                                       pm + PCI_PM_CTRL,
1117                                       power_control);
1118                 udelay(100);    /* Delay after power state change */
1119
1120                 /* Switch out of Vaux if it is not a LOM */
1121                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1122                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1123                         udelay(100);
1124                 }
1125
1126                 return 0;
1127
1128         case 1:
1129                 power_control |= 1;
1130                 break;
1131
1132         case 2:
1133                 power_control |= 2;
1134                 break;
1135
1136         case 3:
1137                 power_control |= 3;
1138                 break;
1139
1140         default:
1141                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1142                        "requested.\n",
1143                        tp->dev->name, state);
1144                 return -EINVAL;
1145         };
1146
1147         power_control |= PCI_PM_CTRL_PME_ENABLE;
1148
1149         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1150         tw32(TG3PCI_MISC_HOST_CTRL,
1151              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1152
1153         if (tp->link_config.phy_is_low_power == 0) {
1154                 tp->link_config.phy_is_low_power = 1;
1155                 tp->link_config.orig_speed = tp->link_config.speed;
1156                 tp->link_config.orig_duplex = tp->link_config.duplex;
1157                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1158         }
1159
1160         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1161                 tp->link_config.speed = SPEED_10;
1162                 tp->link_config.duplex = DUPLEX_HALF;
1163                 tp->link_config.autoneg = AUTONEG_ENABLE;
1164                 tg3_setup_phy(tp, 0);
1165         }
1166
1167         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1168
1169         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1170                 u32 mac_mode;
1171
1172                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1173                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1174                         udelay(40);
1175
1176                         mac_mode = MAC_MODE_PORT_MODE_MII;
1177
1178                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1179                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1180                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1181                 } else {
1182                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1183                 }
1184
1185                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1186                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1187
1188                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1189                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1190                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1191
1192                 tw32_f(MAC_MODE, mac_mode);
1193                 udelay(100);
1194
1195                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1196                 udelay(10);
1197         }
1198
1199         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1200             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1201              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1202                 u32 base_val;
1203
1204                 base_val = tp->pci_clock_ctrl;
1205                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1206                              CLOCK_CTRL_TXCLK_DISABLE);
1207
1208                 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1209                      CLOCK_CTRL_ALTCLK |
1210                      CLOCK_CTRL_PWRDOWN_PLL133);
1211                 udelay(40);
1212         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
1213                 /* do nothing */
1214         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1215                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1216                 u32 newbits1, newbits2;
1217
1218                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1219                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1220                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1221                                     CLOCK_CTRL_TXCLK_DISABLE |
1222                                     CLOCK_CTRL_ALTCLK);
1223                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1224                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1225                         newbits1 = CLOCK_CTRL_625_CORE;
1226                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1227                 } else {
1228                         newbits1 = CLOCK_CTRL_ALTCLK;
1229                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1230                 }
1231
1232                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1233                 udelay(40);
1234
1235                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1236                 udelay(40);
1237
1238                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1239                         u32 newbits3;
1240
1241                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1242                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1243                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1244                                             CLOCK_CTRL_TXCLK_DISABLE |
1245                                             CLOCK_CTRL_44MHZ_CORE);
1246                         } else {
1247                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1248                         }
1249
1250                         tw32_f(TG3PCI_CLOCK_CTRL,
1251                                          tp->pci_clock_ctrl | newbits3);
1252                         udelay(40);
1253                 }
1254         }
1255
1256         tg3_frob_aux_power(tp);
1257
1258         /* Workaround for unstable PLL clock */
1259         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1260             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1261                 u32 val = tr32(0x7d00);
1262
1263                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1264                 tw32(0x7d00, val);
1265                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1266                         tg3_halt_cpu(tp, RX_CPU_BASE);
1267         }
1268
1269         /* Finally, set the new power state. */
1270         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1271         udelay(100);    /* Delay after power state change */
1272
1273         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1274
1275         return 0;
1276 }
1277
1278 static void tg3_link_report(struct tg3 *tp)
1279 {
1280         if (!netif_carrier_ok(tp->dev)) {
1281                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1282         } else {
1283                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1284                        tp->dev->name,
1285                        (tp->link_config.active_speed == SPEED_1000 ?
1286                         1000 :
1287                         (tp->link_config.active_speed == SPEED_100 ?
1288                          100 : 10)),
1289                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1290                         "full" : "half"));
1291
1292                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1293                        "%s for RX.\n",
1294                        tp->dev->name,
1295                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1296                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1297         }
1298 }
1299
1300 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1301 {
1302         u32 new_tg3_flags = 0;
1303         u32 old_rx_mode = tp->rx_mode;
1304         u32 old_tx_mode = tp->tx_mode;
1305
1306         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1307
1308                 /* Convert 1000BaseX flow control bits to 1000BaseT
1309                  * bits before resolving flow control.
1310                  */
1311                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1312                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1313                                        ADVERTISE_PAUSE_ASYM);
1314                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1315
1316                         if (local_adv & ADVERTISE_1000XPAUSE)
1317                                 local_adv |= ADVERTISE_PAUSE_CAP;
1318                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1319                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1320                         if (remote_adv & LPA_1000XPAUSE)
1321                                 remote_adv |= LPA_PAUSE_CAP;
1322                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1323                                 remote_adv |= LPA_PAUSE_ASYM;
1324                 }
1325
1326                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1327                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1328                                 if (remote_adv & LPA_PAUSE_CAP)
1329                                         new_tg3_flags |=
1330                                                 (TG3_FLAG_RX_PAUSE |
1331                                                 TG3_FLAG_TX_PAUSE);
1332                                 else if (remote_adv & LPA_PAUSE_ASYM)
1333                                         new_tg3_flags |=
1334                                                 (TG3_FLAG_RX_PAUSE);
1335                         } else {
1336                                 if (remote_adv & LPA_PAUSE_CAP)
1337                                         new_tg3_flags |=
1338                                                 (TG3_FLAG_RX_PAUSE |
1339                                                 TG3_FLAG_TX_PAUSE);
1340                         }
1341                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1342                         if ((remote_adv & LPA_PAUSE_CAP) &&
1343                         (remote_adv & LPA_PAUSE_ASYM))
1344                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1345                 }
1346
1347                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1348                 tp->tg3_flags |= new_tg3_flags;
1349         } else {
1350                 new_tg3_flags = tp->tg3_flags;
1351         }
1352
1353         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1354                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1355         else
1356                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1357
1358         if (old_rx_mode != tp->rx_mode) {
1359                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1360         }
1361
1362         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1363                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1364         else
1365                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1366
1367         if (old_tx_mode != tp->tx_mode) {
1368                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1369         }
1370 }
1371
1372 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1373 {
1374         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1375         case MII_TG3_AUX_STAT_10HALF:
1376                 *speed = SPEED_10;
1377                 *duplex = DUPLEX_HALF;
1378                 break;
1379
1380         case MII_TG3_AUX_STAT_10FULL:
1381                 *speed = SPEED_10;
1382                 *duplex = DUPLEX_FULL;
1383                 break;
1384
1385         case MII_TG3_AUX_STAT_100HALF:
1386                 *speed = SPEED_100;
1387                 *duplex = DUPLEX_HALF;
1388                 break;
1389
1390         case MII_TG3_AUX_STAT_100FULL:
1391                 *speed = SPEED_100;
1392                 *duplex = DUPLEX_FULL;
1393                 break;
1394
1395         case MII_TG3_AUX_STAT_1000HALF:
1396                 *speed = SPEED_1000;
1397                 *duplex = DUPLEX_HALF;
1398                 break;
1399
1400         case MII_TG3_AUX_STAT_1000FULL:
1401                 *speed = SPEED_1000;
1402                 *duplex = DUPLEX_FULL;
1403                 break;
1404
1405         default:
1406                 *speed = SPEED_INVALID;
1407                 *duplex = DUPLEX_INVALID;
1408                 break;
1409         };
1410 }
1411
1412 static void tg3_phy_copper_begin(struct tg3 *tp)
1413 {
1414         u32 new_adv;
1415         int i;
1416
1417         if (tp->link_config.phy_is_low_power) {
1418                 /* Entering low power mode.  Disable gigabit and
1419                  * 100baseT advertisements.
1420                  */
1421                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1422
1423                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1424                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1425                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1426                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1427
1428                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1429         } else if (tp->link_config.speed == SPEED_INVALID) {
1430                 tp->link_config.advertising =
1431                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1432                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1433                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1434                          ADVERTISED_Autoneg | ADVERTISED_MII);
1435
1436                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1437                         tp->link_config.advertising &=
1438                                 ~(ADVERTISED_1000baseT_Half |
1439                                   ADVERTISED_1000baseT_Full);
1440
1441                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1442                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1443                         new_adv |= ADVERTISE_10HALF;
1444                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1445                         new_adv |= ADVERTISE_10FULL;
1446                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1447                         new_adv |= ADVERTISE_100HALF;
1448                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1449                         new_adv |= ADVERTISE_100FULL;
1450                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1451
1452                 if (tp->link_config.advertising &
1453                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1454                         new_adv = 0;
1455                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1456                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1457                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1458                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1459                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1460                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1461                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1462                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1463                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1464                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1465                 } else {
1466                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1467                 }
1468         } else {
1469                 /* Asking for a specific link mode. */
1470                 if (tp->link_config.speed == SPEED_1000) {
1471                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1472                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1473
1474                         if (tp->link_config.duplex == DUPLEX_FULL)
1475                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1476                         else
1477                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1478                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1479                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1480                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1481                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1482                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1483                 } else {
1484                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1485
1486                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1487                         if (tp->link_config.speed == SPEED_100) {
1488                                 if (tp->link_config.duplex == DUPLEX_FULL)
1489                                         new_adv |= ADVERTISE_100FULL;
1490                                 else
1491                                         new_adv |= ADVERTISE_100HALF;
1492                         } else {
1493                                 if (tp->link_config.duplex == DUPLEX_FULL)
1494                                         new_adv |= ADVERTISE_10FULL;
1495                                 else
1496                                         new_adv |= ADVERTISE_10HALF;
1497                         }
1498                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1499                 }
1500         }
1501
1502         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1503             tp->link_config.speed != SPEED_INVALID) {
1504                 u32 bmcr, orig_bmcr;
1505
1506                 tp->link_config.active_speed = tp->link_config.speed;
1507                 tp->link_config.active_duplex = tp->link_config.duplex;
1508
1509                 bmcr = 0;
1510                 switch (tp->link_config.speed) {
1511                 default:
1512                 case SPEED_10:
1513                         break;
1514
1515                 case SPEED_100:
1516                         bmcr |= BMCR_SPEED100;
1517                         break;
1518
1519                 case SPEED_1000:
1520                         bmcr |= TG3_BMCR_SPEED1000;
1521                         break;
1522                 };
1523
1524                 if (tp->link_config.duplex == DUPLEX_FULL)
1525                         bmcr |= BMCR_FULLDPLX;
1526
1527                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1528                     (bmcr != orig_bmcr)) {
1529                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1530                         for (i = 0; i < 1500; i++) {
1531                                 u32 tmp;
1532
1533                                 udelay(10);
1534                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1535                                     tg3_readphy(tp, MII_BMSR, &tmp))
1536                                         continue;
1537                                 if (!(tmp & BMSR_LSTATUS)) {
1538                                         udelay(40);
1539                                         break;
1540                                 }
1541                         }
1542                         tg3_writephy(tp, MII_BMCR, bmcr);
1543                         udelay(40);
1544                 }
1545         } else {
1546                 tg3_writephy(tp, MII_BMCR,
1547                              BMCR_ANENABLE | BMCR_ANRESTART);
1548         }
1549 }
1550
1551 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1552 {
1553         int err;
1554
1555         /* Turn off tap power management. */
1556         /* Set Extended packet length bit */
1557         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1558
1559         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1560         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1561
1562         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1563         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1564
1565         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1566         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1567
1568         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1569         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1570
1571         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1572         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1573
1574         udelay(40);
1575
1576         return err;
1577 }
1578
1579 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1580 {
1581         u32 adv_reg, all_mask;
1582
1583         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1584                 return 0;
1585
1586         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1587                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1588         if ((adv_reg & all_mask) != all_mask)
1589                 return 0;
1590         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1591                 u32 tg3_ctrl;
1592
1593                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1594                         return 0;
1595
1596                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1597                             MII_TG3_CTRL_ADV_1000_FULL);
1598                 if ((tg3_ctrl & all_mask) != all_mask)
1599                         return 0;
1600         }
1601         return 1;
1602 }
1603
1604 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1605 {
1606         int current_link_up;
1607         u32 bmsr, dummy;
1608         u16 current_speed;
1609         u8 current_duplex;
1610         int i, err;
1611
1612         tw32(MAC_EVENT, 0);
1613
1614         tw32_f(MAC_STATUS,
1615              (MAC_STATUS_SYNC_CHANGED |
1616               MAC_STATUS_CFG_CHANGED |
1617               MAC_STATUS_MI_COMPLETION |
1618               MAC_STATUS_LNKSTATE_CHANGED));
1619         udelay(40);
1620
1621         tp->mi_mode = MAC_MI_MODE_BASE;
1622         tw32_f(MAC_MI_MODE, tp->mi_mode);
1623         udelay(80);
1624
1625         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1626
1627         /* Some third-party PHYs need to be reset on link going
1628          * down.
1629          */
1630         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1631              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1632              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1633             netif_carrier_ok(tp->dev)) {
1634                 tg3_readphy(tp, MII_BMSR, &bmsr);
1635                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1636                     !(bmsr & BMSR_LSTATUS))
1637                         force_reset = 1;
1638         }
1639         if (force_reset)
1640                 tg3_phy_reset(tp);
1641
1642         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1643                 tg3_readphy(tp, MII_BMSR, &bmsr);
1644                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1645                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1646                         bmsr = 0;
1647
1648                 if (!(bmsr & BMSR_LSTATUS)) {
1649                         err = tg3_init_5401phy_dsp(tp);
1650                         if (err)
1651                                 return err;
1652
1653                         tg3_readphy(tp, MII_BMSR, &bmsr);
1654                         for (i = 0; i < 1000; i++) {
1655                                 udelay(10);
1656                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1657                                     (bmsr & BMSR_LSTATUS)) {
1658                                         udelay(40);
1659                                         break;
1660                                 }
1661                         }
1662
1663                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1664                             !(bmsr & BMSR_LSTATUS) &&
1665                             tp->link_config.active_speed == SPEED_1000) {
1666                                 err = tg3_phy_reset(tp);
1667                                 if (!err)
1668                                         err = tg3_init_5401phy_dsp(tp);
1669                                 if (err)
1670                                         return err;
1671                         }
1672                 }
1673         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1674                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1675                 /* 5701 {A0,B0} CRC bug workaround */
1676                 tg3_writephy(tp, 0x15, 0x0a75);
1677                 tg3_writephy(tp, 0x1c, 0x8c68);
1678                 tg3_writephy(tp, 0x1c, 0x8d68);
1679                 tg3_writephy(tp, 0x1c, 0x8c68);
1680         }
1681
1682         /* Clear pending interrupts... */
1683         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1684         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1685
1686         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1687                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1688         else
1689                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1690
1691         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1692             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1693                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1694                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1695                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1696                 else
1697                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1698         }
1699
1700         current_link_up = 0;
1701         current_speed = SPEED_INVALID;
1702         current_duplex = DUPLEX_INVALID;
1703
1704         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1705                 u32 val;
1706
1707                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1708                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1709                 if (!(val & (1 << 10))) {
1710                         val |= (1 << 10);
1711                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1712                         goto relink;
1713                 }
1714         }
1715
1716         bmsr = 0;
1717         for (i = 0; i < 100; i++) {
1718                 tg3_readphy(tp, MII_BMSR, &bmsr);
1719                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1720                     (bmsr & BMSR_LSTATUS))
1721                         break;
1722                 udelay(40);
1723         }
1724
1725         if (bmsr & BMSR_LSTATUS) {
1726                 u32 aux_stat, bmcr;
1727
1728                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1729                 for (i = 0; i < 2000; i++) {
1730                         udelay(10);
1731                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1732                             aux_stat)
1733                                 break;
1734                 }
1735
1736                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1737                                              &current_speed,
1738                                              &current_duplex);
1739
1740                 bmcr = 0;
1741                 for (i = 0; i < 200; i++) {
1742                         tg3_readphy(tp, MII_BMCR, &bmcr);
1743                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1744                                 continue;
1745                         if (bmcr && bmcr != 0x7fff)
1746                                 break;
1747                         udelay(10);
1748                 }
1749
1750                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1751                         if (bmcr & BMCR_ANENABLE) {
1752                                 current_link_up = 1;
1753
1754                                 /* Force autoneg restart if we are exiting
1755                                  * low power mode.
1756                                  */
1757                                 if (!tg3_copper_is_advertising_all(tp))
1758                                         current_link_up = 0;
1759                         } else {
1760                                 current_link_up = 0;
1761                         }
1762                 } else {
1763                         if (!(bmcr & BMCR_ANENABLE) &&
1764                             tp->link_config.speed == current_speed &&
1765                             tp->link_config.duplex == current_duplex) {
1766                                 current_link_up = 1;
1767                         } else {
1768                                 current_link_up = 0;
1769                         }
1770                 }
1771
1772                 tp->link_config.active_speed = current_speed;
1773                 tp->link_config.active_duplex = current_duplex;
1774         }
1775
1776         if (current_link_up == 1 &&
1777             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1778             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1779                 u32 local_adv, remote_adv;
1780
1781                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1782                         local_adv = 0;
1783                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1784
1785                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1786                         remote_adv = 0;
1787
1788                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1789
1790                 /* If we are not advertising full pause capability,
1791                  * something is wrong.  Bring the link down and reconfigure.
1792                  */
1793                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1794                         current_link_up = 0;
1795                 } else {
1796                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1797                 }
1798         }
1799 relink:
1800         if (current_link_up == 0) {
1801                 u32 tmp;
1802
1803                 tg3_phy_copper_begin(tp);
1804
1805                 tg3_readphy(tp, MII_BMSR, &tmp);
1806                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1807                     (tmp & BMSR_LSTATUS))
1808                         current_link_up = 1;
1809         }
1810
1811         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1812         if (current_link_up == 1) {
1813                 if (tp->link_config.active_speed == SPEED_100 ||
1814                     tp->link_config.active_speed == SPEED_10)
1815                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1816                 else
1817                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1818         } else
1819                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1820
1821         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1822         if (tp->link_config.active_duplex == DUPLEX_HALF)
1823                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1824
1825         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1826         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1827                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1828                     (current_link_up == 1 &&
1829                      tp->link_config.active_speed == SPEED_10))
1830                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1831         } else {
1832                 if (current_link_up == 1)
1833                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1834         }
1835
1836         /* ??? Without this setting Netgear GA302T PHY does not
1837          * ??? send/receive packets...
1838          */
1839         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1840             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1841                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1842                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1843                 udelay(80);
1844         }
1845
1846         tw32_f(MAC_MODE, tp->mac_mode);
1847         udelay(40);
1848
1849         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1850                 /* Polled via timer. */
1851                 tw32_f(MAC_EVENT, 0);
1852         } else {
1853                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1854         }
1855         udelay(40);
1856
1857         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1858             current_link_up == 1 &&
1859             tp->link_config.active_speed == SPEED_1000 &&
1860             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1861              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1862                 udelay(120);
1863                 tw32_f(MAC_STATUS,
1864                      (MAC_STATUS_SYNC_CHANGED |
1865                       MAC_STATUS_CFG_CHANGED));
1866                 udelay(40);
1867                 tg3_write_mem(tp,
1868                               NIC_SRAM_FIRMWARE_MBOX,
1869                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1870         }
1871
1872         if (current_link_up != netif_carrier_ok(tp->dev)) {
1873                 if (current_link_up)
1874                         netif_carrier_on(tp->dev);
1875                 else
1876                         netif_carrier_off(tp->dev);
1877                 tg3_link_report(tp);
1878         }
1879
1880         return 0;
1881 }
1882
1883 struct tg3_fiber_aneginfo {
1884         int state;
1885 #define ANEG_STATE_UNKNOWN              0
1886 #define ANEG_STATE_AN_ENABLE            1
1887 #define ANEG_STATE_RESTART_INIT         2
1888 #define ANEG_STATE_RESTART              3
1889 #define ANEG_STATE_DISABLE_LINK_OK      4
1890 #define ANEG_STATE_ABILITY_DETECT_INIT  5
1891 #define ANEG_STATE_ABILITY_DETECT       6
1892 #define ANEG_STATE_ACK_DETECT_INIT      7
1893 #define ANEG_STATE_ACK_DETECT           8
1894 #define ANEG_STATE_COMPLETE_ACK_INIT    9
1895 #define ANEG_STATE_COMPLETE_ACK         10
1896 #define ANEG_STATE_IDLE_DETECT_INIT     11
1897 #define ANEG_STATE_IDLE_DETECT          12
1898 #define ANEG_STATE_LINK_OK              13
1899 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
1900 #define ANEG_STATE_NEXT_PAGE_WAIT       15
1901
1902         u32 flags;
1903 #define MR_AN_ENABLE            0x00000001
1904 #define MR_RESTART_AN           0x00000002
1905 #define MR_AN_COMPLETE          0x00000004
1906 #define MR_PAGE_RX              0x00000008
1907 #define MR_NP_LOADED            0x00000010
1908 #define MR_TOGGLE_TX            0x00000020
1909 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
1910 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
1911 #define MR_LP_ADV_SYM_PAUSE     0x00000100
1912 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
1913 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1914 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1915 #define MR_LP_ADV_NEXT_PAGE     0x00001000
1916 #define MR_TOGGLE_RX            0x00002000
1917 #define MR_NP_RX                0x00004000
1918
1919 #define MR_LINK_OK              0x80000000
1920
1921         unsigned long link_time, cur_time;
1922
1923         u32 ability_match_cfg;
1924         int ability_match_count;
1925
1926         char ability_match, idle_match, ack_match;
1927
1928         u32 txconfig, rxconfig;
1929 #define ANEG_CFG_NP             0x00000080
1930 #define ANEG_CFG_ACK            0x00000040
1931 #define ANEG_CFG_RF2            0x00000020
1932 #define ANEG_CFG_RF1            0x00000010
1933 #define ANEG_CFG_PS2            0x00000001
1934 #define ANEG_CFG_PS1            0x00008000
1935 #define ANEG_CFG_HD             0x00004000
1936 #define ANEG_CFG_FD             0x00002000
1937 #define ANEG_CFG_INVAL          0x00001f06
1938
1939 };
1940 #define ANEG_OK         0
1941 #define ANEG_DONE       1
1942 #define ANEG_TIMER_ENAB 2
1943 #define ANEG_FAILED     -1
1944
1945 #define ANEG_STATE_SETTLE_TIME  10000
1946
1947 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1948                                    struct tg3_fiber_aneginfo *ap)
1949 {
1950         unsigned long delta;
1951         u32 rx_cfg_reg;
1952         int ret;
1953
1954         if (ap->state == ANEG_STATE_UNKNOWN) {
1955                 ap->rxconfig = 0;
1956                 ap->link_time = 0;
1957                 ap->cur_time = 0;
1958                 ap->ability_match_cfg = 0;
1959                 ap->ability_match_count = 0;
1960                 ap->ability_match = 0;
1961                 ap->idle_match = 0;
1962                 ap->ack_match = 0;
1963         }
1964         ap->cur_time++;
1965
1966         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1967                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1968
1969                 if (rx_cfg_reg != ap->ability_match_cfg) {
1970                         ap->ability_match_cfg = rx_cfg_reg;
1971                         ap->ability_match = 0;
1972                         ap->ability_match_count = 0;
1973                 } else {
1974                         if (++ap->ability_match_count > 1) {
1975                                 ap->ability_match = 1;
1976                                 ap->ability_match_cfg = rx_cfg_reg;
1977                         }
1978                 }
1979                 if (rx_cfg_reg & ANEG_CFG_ACK)
1980                         ap->ack_match = 1;
1981                 else
1982                         ap->ack_match = 0;
1983
1984                 ap->idle_match = 0;
1985         } else {
1986                 ap->idle_match = 1;
1987                 ap->ability_match_cfg = 0;
1988                 ap->ability_match_count = 0;
1989                 ap->ability_match = 0;
1990                 ap->ack_match = 0;
1991
1992                 rx_cfg_reg = 0;
1993         }
1994
1995         ap->rxconfig = rx_cfg_reg;
1996         ret = ANEG_OK;
1997
1998         switch(ap->state) {
1999         case ANEG_STATE_UNKNOWN:
2000                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2001                         ap->state = ANEG_STATE_AN_ENABLE;
2002
2003                 /* fallthru */
2004         case ANEG_STATE_AN_ENABLE:
2005                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2006                 if (ap->flags & MR_AN_ENABLE) {
2007                         ap->link_time = 0;
2008                         ap->cur_time = 0;
2009                         ap->ability_match_cfg = 0;
2010                         ap->ability_match_count = 0;
2011                         ap->ability_match = 0;
2012                         ap->idle_match = 0;
2013                         ap->ack_match = 0;
2014
2015                         ap->state = ANEG_STATE_RESTART_INIT;
2016                 } else {
2017                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2018                 }
2019                 break;
2020
2021         case ANEG_STATE_RESTART_INIT:
2022                 ap->link_time = ap->cur_time;
2023                 ap->flags &= ~(MR_NP_LOADED);
2024                 ap->txconfig = 0;
2025                 tw32(MAC_TX_AUTO_NEG, 0);
2026                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2027                 tw32_f(MAC_MODE, tp->mac_mode);
2028                 udelay(40);
2029
2030                 ret = ANEG_TIMER_ENAB;
2031                 ap->state = ANEG_STATE_RESTART;
2032
2033                 /* fallthru */
2034         case ANEG_STATE_RESTART:
2035                 delta = ap->cur_time - ap->link_time;
2036                 if (delta > ANEG_STATE_SETTLE_TIME) {
2037                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2038                 } else {
2039                         ret = ANEG_TIMER_ENAB;
2040                 }
2041                 break;
2042
2043         case ANEG_STATE_DISABLE_LINK_OK:
2044                 ret = ANEG_DONE;
2045                 break;
2046
2047         case ANEG_STATE_ABILITY_DETECT_INIT:
2048                 ap->flags &= ~(MR_TOGGLE_TX);
2049                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2050                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2051                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2052                 tw32_f(MAC_MODE, tp->mac_mode);
2053                 udelay(40);
2054
2055                 ap->state = ANEG_STATE_ABILITY_DETECT;
2056                 break;
2057
2058         case ANEG_STATE_ABILITY_DETECT:
2059                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2060                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2061                 }
2062                 break;
2063
2064         case ANEG_STATE_ACK_DETECT_INIT:
2065                 ap->txconfig |= ANEG_CFG_ACK;
2066                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2067                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2068                 tw32_f(MAC_MODE, tp->mac_mode);
2069                 udelay(40);
2070
2071                 ap->state = ANEG_STATE_ACK_DETECT;
2072
2073                 /* fallthru */
2074         case ANEG_STATE_ACK_DETECT:
2075                 if (ap->ack_match != 0) {
2076                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2077                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2078                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2079                         } else {
2080                                 ap->state = ANEG_STATE_AN_ENABLE;
2081                         }
2082                 } else if (ap->ability_match != 0 &&
2083                            ap->rxconfig == 0) {
2084                         ap->state = ANEG_STATE_AN_ENABLE;
2085                 }
2086                 break;
2087
2088         case ANEG_STATE_COMPLETE_ACK_INIT:
2089                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2090                         ret = ANEG_FAILED;
2091                         break;
2092                 }
2093                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2094                                MR_LP_ADV_HALF_DUPLEX |
2095                                MR_LP_ADV_SYM_PAUSE |
2096                                MR_LP_ADV_ASYM_PAUSE |
2097                                MR_LP_ADV_REMOTE_FAULT1 |
2098                                MR_LP_ADV_REMOTE_FAULT2 |
2099                                MR_LP_ADV_NEXT_PAGE |
2100                                MR_TOGGLE_RX |
2101                                MR_NP_RX);
2102                 if (ap->rxconfig & ANEG_CFG_FD)
2103                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2104                 if (ap->rxconfig & ANEG_CFG_HD)
2105                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2106                 if (ap->rxconfig & ANEG_CFG_PS1)
2107                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2108                 if (ap->rxconfig & ANEG_CFG_PS2)
2109                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2110                 if (ap->rxconfig & ANEG_CFG_RF1)
2111                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2112                 if (ap->rxconfig & ANEG_CFG_RF2)
2113                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2114                 if (ap->rxconfig & ANEG_CFG_NP)
2115                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2116
2117                 ap->link_time = ap->cur_time;
2118
2119                 ap->flags ^= (MR_TOGGLE_TX);
2120                 if (ap->rxconfig & 0x0008)
2121                         ap->flags |= MR_TOGGLE_RX;
2122                 if (ap->rxconfig & ANEG_CFG_NP)
2123                         ap->flags |= MR_NP_RX;
2124                 ap->flags |= MR_PAGE_RX;
2125
2126                 ap->state = ANEG_STATE_COMPLETE_ACK;
2127                 ret = ANEG_TIMER_ENAB;
2128                 break;
2129
2130         case ANEG_STATE_COMPLETE_ACK:
2131                 if (ap->ability_match != 0 &&
2132                     ap->rxconfig == 0) {
2133                         ap->state = ANEG_STATE_AN_ENABLE;
2134                         break;
2135                 }
2136                 delta = ap->cur_time - ap->link_time;
2137                 if (delta > ANEG_STATE_SETTLE_TIME) {
2138                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2139                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2140                         } else {
2141                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2142                                     !(ap->flags & MR_NP_RX)) {
2143                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2144                                 } else {
2145                                         ret = ANEG_FAILED;
2146                                 }
2147                         }
2148                 }
2149                 break;
2150
2151         case ANEG_STATE_IDLE_DETECT_INIT:
2152                 ap->link_time = ap->cur_time;
2153                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2154                 tw32_f(MAC_MODE, tp->mac_mode);
2155                 udelay(40);
2156
2157                 ap->state = ANEG_STATE_IDLE_DETECT;
2158                 ret = ANEG_TIMER_ENAB;
2159                 break;
2160
2161         case ANEG_STATE_IDLE_DETECT:
2162                 if (ap->ability_match != 0 &&
2163                     ap->rxconfig == 0) {
2164                         ap->state = ANEG_STATE_AN_ENABLE;
2165                         break;
2166                 }
2167                 delta = ap->cur_time - ap->link_time;
2168                 if (delta > ANEG_STATE_SETTLE_TIME) {
2169                         /* XXX another gem from the Broadcom driver :( */
2170                         ap->state = ANEG_STATE_LINK_OK;
2171                 }
2172                 break;
2173
2174         case ANEG_STATE_LINK_OK:
2175                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2176                 ret = ANEG_DONE;
2177                 break;
2178
2179         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2180                 /* ??? unimplemented */
2181                 break;
2182
2183         case ANEG_STATE_NEXT_PAGE_WAIT:
2184                 /* ??? unimplemented */
2185                 break;
2186
2187         default:
2188                 ret = ANEG_FAILED;
2189                 break;
2190         };
2191
2192         return ret;
2193 }
2194
2195 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2196 {
2197         int res = 0;
2198         struct tg3_fiber_aneginfo aninfo;
2199         int status = ANEG_FAILED;
2200         unsigned int tick;
2201         u32 tmp;
2202
2203         tw32_f(MAC_TX_AUTO_NEG, 0);
2204
2205         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2206         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2207         udelay(40);
2208
2209         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2210         udelay(40);
2211
2212         memset(&aninfo, 0, sizeof(aninfo));
2213         aninfo.flags |= MR_AN_ENABLE;
2214         aninfo.state = ANEG_STATE_UNKNOWN;
2215         aninfo.cur_time = 0;
2216         tick = 0;
2217         while (++tick < 195000) {
2218                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2219                 if (status == ANEG_DONE || status == ANEG_FAILED)
2220                         break;
2221
2222                 udelay(1);
2223         }
2224
2225         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2226         tw32_f(MAC_MODE, tp->mac_mode);
2227         udelay(40);
2228
2229         *flags = aninfo.flags;
2230
2231         if (status == ANEG_DONE &&
2232             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2233                              MR_LP_ADV_FULL_DUPLEX)))
2234                 res = 1;
2235
2236         return res;
2237 }
2238
2239 static void tg3_init_bcm8002(struct tg3 *tp)
2240 {
2241         u32 mac_status = tr32(MAC_STATUS);
2242         int i;
2243
2244         /* Reset when initting first time or we have a link. */
2245         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2246             !(mac_status & MAC_STATUS_PCS_SYNCED))
2247                 return;
2248
2249         /* Set PLL lock range. */
2250         tg3_writephy(tp, 0x16, 0x8007);
2251
2252         /* SW reset */
2253         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2254
2255         /* Wait for reset to complete. */
2256         /* XXX schedule_timeout() ... */
2257         for (i = 0; i < 500; i++)
2258                 udelay(10);
2259
2260         /* Config mode; select PMA/Ch 1 regs. */
2261         tg3_writephy(tp, 0x10, 0x8411);
2262
2263         /* Enable auto-lock and comdet, select txclk for tx. */
2264         tg3_writephy(tp, 0x11, 0x0a10);
2265
2266         tg3_writephy(tp, 0x18, 0x00a0);
2267         tg3_writephy(tp, 0x16, 0x41ff);
2268
2269         /* Assert and deassert POR. */
2270         tg3_writephy(tp, 0x13, 0x0400);
2271         udelay(40);
2272         tg3_writephy(tp, 0x13, 0x0000);
2273
2274         tg3_writephy(tp, 0x11, 0x0a50);
2275         udelay(40);
2276         tg3_writephy(tp, 0x11, 0x0a10);
2277
2278         /* Wait for signal to stabilize */
2279         /* XXX schedule_timeout() ... */
2280         for (i = 0; i < 15000; i++)
2281                 udelay(10);
2282
2283         /* Deselect the channel register so we can read the PHYID
2284          * later.
2285          */
2286         tg3_writephy(tp, 0x10, 0x8011);
2287 }
2288
2289 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2290 {
2291         u32 sg_dig_ctrl, sg_dig_status;
2292         u32 serdes_cfg, expected_sg_dig_ctrl;
2293         int workaround, port_a;
2294         int current_link_up;
2295
2296         serdes_cfg = 0;
2297         expected_sg_dig_ctrl = 0;
2298         workaround = 0;
2299         port_a = 1;
2300         current_link_up = 0;
2301
2302         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2303             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2304                 workaround = 1;
2305                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2306                         port_a = 0;
2307
2308                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2309                 /* preserve bits 20-23 for voltage regulator */
2310                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2311         }
2312
2313         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2314
2315         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2316                 if (sg_dig_ctrl & (1 << 31)) {
2317                         if (workaround) {
2318                                 u32 val = serdes_cfg;
2319
2320                                 if (port_a)
2321                                         val |= 0xc010000;
2322                                 else
2323                                         val |= 0x4010000;
2324                                 tw32_f(MAC_SERDES_CFG, val);
2325                         }
2326                         tw32_f(SG_DIG_CTRL, 0x01388400);
2327                 }
2328                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2329                         tg3_setup_flow_control(tp, 0, 0);
2330                         current_link_up = 1;
2331                 }
2332                 goto out;
2333         }
2334
2335         /* Want auto-negotiation.  */
2336         expected_sg_dig_ctrl = 0x81388400;
2337
2338         /* Pause capability */
2339         expected_sg_dig_ctrl |= (1 << 11);
2340
2341         /* Asymettric pause */
2342         expected_sg_dig_ctrl |= (1 << 12);
2343
2344         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2345                 if (workaround)
2346                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2347                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2348                 udelay(5);
2349                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2350
2351                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2352         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2353                                  MAC_STATUS_SIGNAL_DET)) {
2354                 int i;
2355
2356                 /* Giver time to negotiate (~200ms) */
2357                 for (i = 0; i < 40000; i++) {
2358                         sg_dig_status = tr32(SG_DIG_STATUS);
2359                         if (sg_dig_status & (0x3))
2360                                 break;
2361                         udelay(5);
2362                 }
2363                 mac_status = tr32(MAC_STATUS);
2364
2365                 if ((sg_dig_status & (1 << 1)) &&
2366                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2367                         u32 local_adv, remote_adv;
2368
2369                         local_adv = ADVERTISE_PAUSE_CAP;
2370                         remote_adv = 0;
2371                         if (sg_dig_status & (1 << 19))
2372                                 remote_adv |= LPA_PAUSE_CAP;
2373                         if (sg_dig_status & (1 << 20))
2374                                 remote_adv |= LPA_PAUSE_ASYM;
2375
2376                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2377                         current_link_up = 1;
2378                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2379                 } else if (!(sg_dig_status & (1 << 1))) {
2380                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2381                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2382                         else {
2383                                 if (workaround) {
2384                                         u32 val = serdes_cfg;
2385
2386                                         if (port_a)
2387                                                 val |= 0xc010000;
2388                                         else
2389                                                 val |= 0x4010000;
2390
2391                                         tw32_f(MAC_SERDES_CFG, val);
2392                                 }
2393
2394                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2395                                 udelay(40);
2396
2397                                 /* Link parallel detection - link is up */
2398                                 /* only if we have PCS_SYNC and not */
2399                                 /* receiving config code words */
2400                                 mac_status = tr32(MAC_STATUS);
2401                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2402                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2403                                         tg3_setup_flow_control(tp, 0, 0);
2404                                         current_link_up = 1;
2405                                 }
2406                         }
2407                 }
2408         }
2409
2410 out:
2411         return current_link_up;
2412 }
2413
2414 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2415 {
2416         int current_link_up = 0;
2417
2418         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2419                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2420                 goto out;
2421         }
2422
2423         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2424                 u32 flags;
2425                 int i;
2426
2427                 if (fiber_autoneg(tp, &flags)) {
2428                         u32 local_adv, remote_adv;
2429
2430                         local_adv = ADVERTISE_PAUSE_CAP;
2431                         remote_adv = 0;
2432                         if (flags & MR_LP_ADV_SYM_PAUSE)
2433                                 remote_adv |= LPA_PAUSE_CAP;
2434                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2435                                 remote_adv |= LPA_PAUSE_ASYM;
2436
2437                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2438
2439                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2440                         current_link_up = 1;
2441                 }
2442                 for (i = 0; i < 30; i++) {
2443                         udelay(20);
2444                         tw32_f(MAC_STATUS,
2445                                (MAC_STATUS_SYNC_CHANGED |
2446                                 MAC_STATUS_CFG_CHANGED));
2447                         udelay(40);
2448                         if ((tr32(MAC_STATUS) &
2449                              (MAC_STATUS_SYNC_CHANGED |
2450                               MAC_STATUS_CFG_CHANGED)) == 0)
2451                                 break;
2452                 }
2453
2454                 mac_status = tr32(MAC_STATUS);
2455                 if (current_link_up == 0 &&
2456                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2457                     !(mac_status & MAC_STATUS_RCVD_CFG))
2458                         current_link_up = 1;
2459         } else {
2460                 /* Forcing 1000FD link up. */
2461                 current_link_up = 1;
2462                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2463
2464                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2465                 udelay(40);
2466         }
2467
2468 out:
2469         return current_link_up;
2470 }
2471
2472 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2473 {
2474         u32 orig_pause_cfg;
2475         u16 orig_active_speed;
2476         u8 orig_active_duplex;
2477         u32 mac_status;
2478         int current_link_up;
2479         int i;
2480
2481         orig_pause_cfg =
2482                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2483                                   TG3_FLAG_TX_PAUSE));
2484         orig_active_speed = tp->link_config.active_speed;
2485         orig_active_duplex = tp->link_config.active_duplex;
2486
2487         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2488             netif_carrier_ok(tp->dev) &&
2489             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2490                 mac_status = tr32(MAC_STATUS);
2491                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2492                                MAC_STATUS_SIGNAL_DET |
2493                                MAC_STATUS_CFG_CHANGED |
2494                                MAC_STATUS_RCVD_CFG);
2495                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2496                                    MAC_STATUS_SIGNAL_DET)) {
2497                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2498                                             MAC_STATUS_CFG_CHANGED));
2499                         return 0;
2500                 }
2501         }
2502
2503         tw32_f(MAC_TX_AUTO_NEG, 0);
2504
2505         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2506         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2507         tw32_f(MAC_MODE, tp->mac_mode);
2508         udelay(40);
2509
2510         if (tp->phy_id == PHY_ID_BCM8002)
2511                 tg3_init_bcm8002(tp);
2512
2513         /* Enable link change event even when serdes polling.  */
2514         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2515         udelay(40);
2516
2517         current_link_up = 0;
2518         mac_status = tr32(MAC_STATUS);
2519
2520         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2521                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2522         else
2523                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2524
2525         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2526         tw32_f(MAC_MODE, tp->mac_mode);
2527         udelay(40);
2528
2529         tp->hw_status->status =
2530                 (SD_STATUS_UPDATED |
2531                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2532
2533         for (i = 0; i < 100; i++) {
2534                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2535                                     MAC_STATUS_CFG_CHANGED));
2536                 udelay(5);
2537                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2538                                          MAC_STATUS_CFG_CHANGED)) == 0)
2539                         break;
2540         }
2541
2542         mac_status = tr32(MAC_STATUS);
2543         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2544                 current_link_up = 0;
2545                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2546                         tw32_f(MAC_MODE, (tp->mac_mode |
2547                                           MAC_MODE_SEND_CONFIGS));
2548                         udelay(1);
2549                         tw32_f(MAC_MODE, tp->mac_mode);
2550                 }
2551         }
2552
2553         if (current_link_up == 1) {
2554                 tp->link_config.active_speed = SPEED_1000;
2555                 tp->link_config.active_duplex = DUPLEX_FULL;
2556                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2557                                     LED_CTRL_LNKLED_OVERRIDE |
2558                                     LED_CTRL_1000MBPS_ON));
2559         } else {
2560                 tp->link_config.active_speed = SPEED_INVALID;
2561                 tp->link_config.active_duplex = DUPLEX_INVALID;
2562                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2563                                     LED_CTRL_LNKLED_OVERRIDE |
2564                                     LED_CTRL_TRAFFIC_OVERRIDE));
2565         }
2566
2567         if (current_link_up != netif_carrier_ok(tp->dev)) {
2568                 if (current_link_up)
2569                         netif_carrier_on(tp->dev);
2570                 else
2571                         netif_carrier_off(tp->dev);
2572                 tg3_link_report(tp);
2573         } else {
2574                 u32 now_pause_cfg =
2575                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2576                                          TG3_FLAG_TX_PAUSE);
2577                 if (orig_pause_cfg != now_pause_cfg ||
2578                     orig_active_speed != tp->link_config.active_speed ||
2579                     orig_active_duplex != tp->link_config.active_duplex)
2580                         tg3_link_report(tp);
2581         }
2582
2583         return 0;
2584 }
2585
2586 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2587 {
2588         int current_link_up, err = 0;
2589         u32 bmsr, bmcr;
2590         u16 current_speed;
2591         u8 current_duplex;
2592
2593         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2594         tw32_f(MAC_MODE, tp->mac_mode);
2595         udelay(40);
2596
2597         tw32(MAC_EVENT, 0);
2598
2599         tw32_f(MAC_STATUS,
2600              (MAC_STATUS_SYNC_CHANGED |
2601               MAC_STATUS_CFG_CHANGED |
2602               MAC_STATUS_MI_COMPLETION |
2603               MAC_STATUS_LNKSTATE_CHANGED));
2604         udelay(40);
2605
2606         if (force_reset)
2607                 tg3_phy_reset(tp);
2608
2609         current_link_up = 0;
2610         current_speed = SPEED_INVALID;
2611         current_duplex = DUPLEX_INVALID;
2612
2613         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2614         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2615
2616         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2617
2618         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2619             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2620                 /* do nothing, just check for link up at the end */
2621         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2622                 u32 adv, new_adv;
2623
2624                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2625                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2626                                   ADVERTISE_1000XPAUSE |
2627                                   ADVERTISE_1000XPSE_ASYM |
2628                                   ADVERTISE_SLCT);
2629
2630                 /* Always advertise symmetric PAUSE just like copper */
2631                 new_adv |= ADVERTISE_1000XPAUSE;
2632
2633                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2634                         new_adv |= ADVERTISE_1000XHALF;
2635                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2636                         new_adv |= ADVERTISE_1000XFULL;
2637
2638                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2639                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2640                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2641                         tg3_writephy(tp, MII_BMCR, bmcr);
2642
2643                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2644                         tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2645                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2646
2647                         return err;
2648                 }
2649         } else {
2650                 u32 new_bmcr;
2651
2652                 bmcr &= ~BMCR_SPEED1000;
2653                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2654
2655                 if (tp->link_config.duplex == DUPLEX_FULL)
2656                         new_bmcr |= BMCR_FULLDPLX;
2657
2658                 if (new_bmcr != bmcr) {
2659                         /* BMCR_SPEED1000 is a reserved bit that needs
2660                          * to be set on write.
2661                          */
2662                         new_bmcr |= BMCR_SPEED1000;
2663
2664                         /* Force a linkdown */
2665                         if (netif_carrier_ok(tp->dev)) {
2666                                 u32 adv;
2667
2668                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2669                                 adv &= ~(ADVERTISE_1000XFULL |
2670                                          ADVERTISE_1000XHALF |
2671                                          ADVERTISE_SLCT);
2672                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2673                                 tg3_writephy(tp, MII_BMCR, bmcr |
2674                                                            BMCR_ANRESTART |
2675                                                            BMCR_ANENABLE);
2676                                 udelay(10);
2677                                 netif_carrier_off(tp->dev);
2678                         }
2679                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2680                         bmcr = new_bmcr;
2681                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2682                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2683                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2684                 }
2685         }
2686
2687         if (bmsr & BMSR_LSTATUS) {
2688                 current_speed = SPEED_1000;
2689                 current_link_up = 1;
2690                 if (bmcr & BMCR_FULLDPLX)
2691                         current_duplex = DUPLEX_FULL;
2692                 else
2693                         current_duplex = DUPLEX_HALF;
2694
2695                 if (bmcr & BMCR_ANENABLE) {
2696                         u32 local_adv, remote_adv, common;
2697
2698                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2699                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2700                         common = local_adv & remote_adv;
2701                         if (common & (ADVERTISE_1000XHALF |
2702                                       ADVERTISE_1000XFULL)) {
2703                                 if (common & ADVERTISE_1000XFULL)
2704                                         current_duplex = DUPLEX_FULL;
2705                                 else
2706                                         current_duplex = DUPLEX_HALF;
2707
2708                                 tg3_setup_flow_control(tp, local_adv,
2709                                                        remote_adv);
2710                         }
2711                         else
2712                                 current_link_up = 0;
2713                 }
2714         }
2715
2716         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2717         if (tp->link_config.active_duplex == DUPLEX_HALF)
2718                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2719
2720         tw32_f(MAC_MODE, tp->mac_mode);
2721         udelay(40);
2722
2723         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2724
2725         tp->link_config.active_speed = current_speed;
2726         tp->link_config.active_duplex = current_duplex;
2727
2728         if (current_link_up != netif_carrier_ok(tp->dev)) {
2729                 if (current_link_up)
2730                         netif_carrier_on(tp->dev);
2731                 else {
2732                         netif_carrier_off(tp->dev);
2733                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2734                 }
2735                 tg3_link_report(tp);
2736         }
2737         return err;
2738 }
2739
2740 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2741 {
2742         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2743                 /* Give autoneg time to complete. */
2744                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2745                 return;
2746         }
2747         if (!netif_carrier_ok(tp->dev) &&
2748             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2749                 u32 bmcr;
2750
2751                 tg3_readphy(tp, MII_BMCR, &bmcr);
2752                 if (bmcr & BMCR_ANENABLE) {
2753                         u32 phy1, phy2;
2754
2755                         /* Select shadow register 0x1f */
2756                         tg3_writephy(tp, 0x1c, 0x7c00);
2757                         tg3_readphy(tp, 0x1c, &phy1);
2758
2759                         /* Select expansion interrupt status register */
2760                         tg3_writephy(tp, 0x17, 0x0f01);
2761                         tg3_readphy(tp, 0x15, &phy2);
2762                         tg3_readphy(tp, 0x15, &phy2);
2763
2764                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2765                                 /* We have signal detect and not receiving
2766                                  * config code words, link is up by parallel
2767                                  * detection.
2768                                  */
2769
2770                                 bmcr &= ~BMCR_ANENABLE;
2771                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2772                                 tg3_writephy(tp, MII_BMCR, bmcr);
2773                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2774                         }
2775                 }
2776         }
2777         else if (netif_carrier_ok(tp->dev) &&
2778                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2779                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2780                 u32 phy2;
2781
2782                 /* Select expansion interrupt status register */
2783                 tg3_writephy(tp, 0x17, 0x0f01);
2784                 tg3_readphy(tp, 0x15, &phy2);
2785                 if (phy2 & 0x20) {
2786                         u32 bmcr;
2787
2788                         /* Config code words received, turn on autoneg. */
2789                         tg3_readphy(tp, MII_BMCR, &bmcr);
2790                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2791
2792                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2793
2794                 }
2795         }
2796 }
2797
2798 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2799 {
2800         int err;
2801
2802         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2803                 err = tg3_setup_fiber_phy(tp, force_reset);
2804         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2805                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2806         } else {
2807                 err = tg3_setup_copper_phy(tp, force_reset);
2808         }
2809
2810         if (tp->link_config.active_speed == SPEED_1000 &&
2811             tp->link_config.active_duplex == DUPLEX_HALF)
2812                 tw32(MAC_TX_LENGTHS,
2813                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2814                       (6 << TX_LENGTHS_IPG_SHIFT) |
2815                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2816         else
2817                 tw32(MAC_TX_LENGTHS,
2818                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2819                       (6 << TX_LENGTHS_IPG_SHIFT) |
2820                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2821
2822         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2823                 if (netif_carrier_ok(tp->dev)) {
2824                         tw32(HOSTCC_STAT_COAL_TICKS,
2825                              tp->coal.stats_block_coalesce_usecs);
2826                 } else {
2827                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2828                 }
2829         }
2830
2831         return err;
2832 }
2833
2834 /* Tigon3 never reports partial packet sends.  So we do not
2835  * need special logic to handle SKBs that have not had all
2836  * of their frags sent yet, like SunGEM does.
2837  */
2838 static void tg3_tx(struct tg3 *tp)
2839 {
2840         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2841         u32 sw_idx = tp->tx_cons;
2842
2843         while (sw_idx != hw_idx) {
2844                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2845                 struct sk_buff *skb = ri->skb;
2846                 int i;
2847
2848                 if (unlikely(skb == NULL))
2849                         BUG();
2850
2851                 pci_unmap_single(tp->pdev,
2852                                  pci_unmap_addr(ri, mapping),
2853                                  skb_headlen(skb),
2854                                  PCI_DMA_TODEVICE);
2855
2856                 ri->skb = NULL;
2857
2858                 sw_idx = NEXT_TX(sw_idx);
2859
2860                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2861                         if (unlikely(sw_idx == hw_idx))
2862                                 BUG();
2863
2864                         ri = &tp->tx_buffers[sw_idx];
2865                         if (unlikely(ri->skb != NULL))
2866                                 BUG();
2867
2868                         pci_unmap_page(tp->pdev,
2869                                        pci_unmap_addr(ri, mapping),
2870                                        skb_shinfo(skb)->frags[i].size,
2871                                        PCI_DMA_TODEVICE);
2872
2873                         sw_idx = NEXT_TX(sw_idx);
2874                 }
2875
2876                 dev_kfree_skb(skb);
2877         }
2878
2879         tp->tx_cons = sw_idx;
2880
2881         if (unlikely(netif_queue_stopped(tp->dev))) {
2882                 spin_lock(&tp->tx_lock);
2883                 if (netif_queue_stopped(tp->dev) &&
2884                     (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2885                         netif_wake_queue(tp->dev);
2886                 spin_unlock(&tp->tx_lock);
2887         }
2888 }
2889
2890 /* Returns size of skb allocated or < 0 on error.
2891  *
2892  * We only need to fill in the address because the other members
2893  * of the RX descriptor are invariant, see tg3_init_rings.
2894  *
2895  * Note the purposeful assymetry of cpu vs. chip accesses.  For
2896  * posting buffers we only dirty the first cache line of the RX
2897  * descriptor (containing the address).  Whereas for the RX status
2898  * buffers the cpu only reads the last cacheline of the RX descriptor
2899  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2900  */
2901 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2902                             int src_idx, u32 dest_idx_unmasked)
2903 {
2904         struct tg3_rx_buffer_desc *desc;
2905         struct ring_info *map, *src_map;
2906         struct sk_buff *skb;
2907         dma_addr_t mapping;
2908         int skb_size, dest_idx;
2909
2910         src_map = NULL;
2911         switch (opaque_key) {
2912         case RXD_OPAQUE_RING_STD:
2913                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2914                 desc = &tp->rx_std[dest_idx];
2915                 map = &tp->rx_std_buffers[dest_idx];
2916                 if (src_idx >= 0)
2917                         src_map = &tp->rx_std_buffers[src_idx];
2918                 skb_size = tp->rx_pkt_buf_sz;
2919                 break;
2920
2921         case RXD_OPAQUE_RING_JUMBO:
2922                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2923                 desc = &tp->rx_jumbo[dest_idx];
2924                 map = &tp->rx_jumbo_buffers[dest_idx];
2925                 if (src_idx >= 0)
2926                         src_map = &tp->rx_jumbo_buffers[src_idx];
2927                 skb_size = RX_JUMBO_PKT_BUF_SZ;
2928                 break;
2929
2930         default:
2931                 return -EINVAL;
2932         };
2933
2934         /* Do not overwrite any of the map or rp information
2935          * until we are sure we can commit to a new buffer.
2936          *
2937          * Callers depend upon this behavior and assume that
2938          * we leave everything unchanged if we fail.
2939          */
2940         skb = dev_alloc_skb(skb_size);
2941         if (skb == NULL)
2942                 return -ENOMEM;
2943
2944         skb->dev = tp->dev;
2945         skb_reserve(skb, tp->rx_offset);
2946
2947         mapping = pci_map_single(tp->pdev, skb->data,
2948                                  skb_size - tp->rx_offset,
2949                                  PCI_DMA_FROMDEVICE);
2950
2951         map->skb = skb;
2952         pci_unmap_addr_set(map, mapping, mapping);
2953
2954         if (src_map != NULL)
2955                 src_map->skb = NULL;
2956
2957         desc->addr_hi = ((u64)mapping >> 32);
2958         desc->addr_lo = ((u64)mapping & 0xffffffff);
2959
2960         return skb_size;
2961 }
2962
2963 /* We only need to move over in the address because the other
2964  * members of the RX descriptor are invariant.  See notes above
2965  * tg3_alloc_rx_skb for full details.
2966  */
2967 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2968                            int src_idx, u32 dest_idx_unmasked)
2969 {
2970         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2971         struct ring_info *src_map, *dest_map;
2972         int dest_idx;
2973
2974         switch (opaque_key) {
2975         case RXD_OPAQUE_RING_STD:
2976                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2977                 dest_desc = &tp->rx_std[dest_idx];
2978                 dest_map = &tp->rx_std_buffers[dest_idx];
2979                 src_desc = &tp->rx_std[src_idx];
2980                 src_map = &tp->rx_std_buffers[src_idx];
2981                 break;
2982
2983         case RXD_OPAQUE_RING_JUMBO:
2984                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2985                 dest_desc = &tp->rx_jumbo[dest_idx];
2986                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2987                 src_desc = &tp->rx_jumbo[src_idx];
2988                 src_map = &tp->rx_jumbo_buffers[src_idx];
2989                 break;
2990
2991         default:
2992                 return;
2993         };
2994
2995         dest_map->skb = src_map->skb;
2996         pci_unmap_addr_set(dest_map, mapping,
2997                            pci_unmap_addr(src_map, mapping));
2998         dest_desc->addr_hi = src_desc->addr_hi;
2999         dest_desc->addr_lo = src_desc->addr_lo;
3000
3001         src_map->skb = NULL;
3002 }
3003
3004 #if TG3_VLAN_TAG_USED
3005 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3006 {
3007         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3008 }
3009 #endif
3010
3011 /* The RX ring scheme is composed of multiple rings which post fresh
3012  * buffers to the chip, and one special ring the chip uses to report
3013  * status back to the host.
3014  *
3015  * The special ring reports the status of received packets to the
3016  * host.  The chip does not write into the original descriptor the
3017  * RX buffer was obtained from.  The chip simply takes the original
3018  * descriptor as provided by the host, updates the status and length
3019  * field, then writes this into the next status ring entry.
3020  *
3021  * Each ring the host uses to post buffers to the chip is described
3022  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3023  * it is first placed into the on-chip ram.  When the packet's length
3024  * is known, it walks down the TG3_BDINFO entries to select the ring.
3025  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3026  * which is within the range of the new packet's length is chosen.
3027  *
3028  * The "separate ring for rx status" scheme may sound queer, but it makes
3029  * sense from a cache coherency perspective.  If only the host writes
3030  * to the buffer post rings, and only the chip writes to the rx status
3031  * rings, then cache lines never move beyond shared-modified state.
3032  * If both the host and chip were to write into the same ring, cache line
3033  * eviction could occur since both entities want it in an exclusive state.
3034  */
3035 static int tg3_rx(struct tg3 *tp, int budget)
3036 {
3037         u32 work_mask;
3038         u32 sw_idx = tp->rx_rcb_ptr;
3039         u16 hw_idx;
3040         int received;
3041
3042         hw_idx = tp->hw_status->idx[0].rx_producer;
3043         /*
3044          * We need to order the read of hw_idx and the read of
3045          * the opaque cookie.
3046          */
3047         rmb();
3048         work_mask = 0;
3049         received = 0;
3050         while (sw_idx != hw_idx && budget > 0) {
3051                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3052                 unsigned int len;
3053                 struct sk_buff *skb;
3054                 dma_addr_t dma_addr;
3055                 u32 opaque_key, desc_idx, *post_ptr;
3056
3057                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3058                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3059                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3060                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3061                                                   mapping);
3062                         skb = tp->rx_std_buffers[desc_idx].skb;
3063                         post_ptr = &tp->rx_std_ptr;
3064                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3065                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3066                                                   mapping);
3067                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3068                         post_ptr = &tp->rx_jumbo_ptr;
3069                 }
3070                 else {
3071                         goto next_pkt_nopost;
3072                 }
3073
3074                 work_mask |= opaque_key;
3075
3076                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3077                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3078                 drop_it:
3079                         tg3_recycle_rx(tp, opaque_key,
3080                                        desc_idx, *post_ptr);
3081                 drop_it_no_recycle:
3082                         /* Other statistics kept track of by card. */
3083                         tp->net_stats.rx_dropped++;
3084                         goto next_pkt;
3085                 }
3086
3087                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3088
3089                 if (len > RX_COPY_THRESHOLD
3090                         && tp->rx_offset == 2
3091                         /* rx_offset != 2 iff this is a 5701 card running
3092                          * in PCI-X mode [see tg3_get_invariants()] */
3093                 ) {
3094                         int skb_size;
3095
3096                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3097                                                     desc_idx, *post_ptr);
3098                         if (skb_size < 0)
3099                                 goto drop_it;
3100
3101                         pci_unmap_single(tp->pdev, dma_addr,
3102                                          skb_size - tp->rx_offset,
3103                                          PCI_DMA_FROMDEVICE);
3104
3105                         skb_put(skb, len);
3106                 } else {
3107                         struct sk_buff *copy_skb;
3108
3109                         tg3_recycle_rx(tp, opaque_key,
3110                                        desc_idx, *post_ptr);
3111
3112                         copy_skb = dev_alloc_skb(len + 2);
3113                         if (copy_skb == NULL)
3114                                 goto drop_it_no_recycle;
3115
3116                         copy_skb->dev = tp->dev;
3117                         skb_reserve(copy_skb, 2);
3118                         skb_put(copy_skb, len);
3119                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3120                         memcpy(copy_skb->data, skb->data, len);
3121                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3122
3123                         /* We'll reuse the original ring buffer. */
3124                         skb = copy_skb;
3125                 }
3126
3127                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3128                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3129                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3130                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3131                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3132                 else
3133                         skb->ip_summed = CHECKSUM_NONE;
3134
3135                 skb->protocol = eth_type_trans(skb, tp->dev);
3136 #if TG3_VLAN_TAG_USED
3137                 if (tp->vlgrp != NULL &&
3138                     desc->type_flags & RXD_FLAG_VLAN) {
3139                         tg3_vlan_rx(tp, skb,
3140                                     desc->err_vlan & RXD_VLAN_MASK);
3141                 } else
3142 #endif
3143                         netif_receive_skb(skb);
3144
3145                 tp->dev->last_rx = jiffies;
3146                 received++;
3147                 budget--;
3148
3149 next_pkt:
3150                 (*post_ptr)++;
3151 next_pkt_nopost:
3152                 sw_idx++;
3153                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3154
3155                 /* Refresh hw_idx to see if there is new work */
3156                 if (sw_idx == hw_idx) {
3157                         hw_idx = tp->hw_status->idx[0].rx_producer;
3158                         rmb();
3159                 }
3160         }
3161
3162         /* ACK the status ring. */
3163         tp->rx_rcb_ptr = sw_idx;
3164         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3165
3166         /* Refill RX ring(s). */
3167         if (work_mask & RXD_OPAQUE_RING_STD) {
3168                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3169                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3170                              sw_idx);
3171         }
3172         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3173                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3174                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3175                              sw_idx);
3176         }
3177         mmiowb();
3178
3179         return received;
3180 }
3181
3182 static int tg3_poll(struct net_device *netdev, int *budget)
3183 {
3184         struct tg3 *tp = netdev_priv(netdev);
3185         struct tg3_hw_status *sblk = tp->hw_status;
3186         int done;
3187
3188         /* handle link change and other phy events */
3189         if (!(tp->tg3_flags &
3190               (TG3_FLAG_USE_LINKCHG_REG |
3191                TG3_FLAG_POLL_SERDES))) {
3192                 if (sblk->status & SD_STATUS_LINK_CHG) {
3193                         sblk->status = SD_STATUS_UPDATED |
3194                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3195                         spin_lock(&tp->lock);
3196                         tg3_setup_phy(tp, 0);
3197                         spin_unlock(&tp->lock);
3198                 }
3199         }
3200
3201         /* run TX completion thread */
3202         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3203                 tg3_tx(tp);
3204         }
3205
3206         /* run RX thread, within the bounds set by NAPI.
3207          * All RX "locking" is done by ensuring outside
3208          * code synchronizes with dev->poll()
3209          */
3210         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3211                 int orig_budget = *budget;
3212                 int work_done;
3213
3214                 if (orig_budget > netdev->quota)
3215                         orig_budget = netdev->quota;
3216
3217                 work_done = tg3_rx(tp, orig_budget);
3218
3219                 *budget -= work_done;
3220                 netdev->quota -= work_done;
3221         }
3222
3223         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
3224                 tp->last_tag = sblk->status_tag;
3225         rmb();
3226         sblk->status &= ~SD_STATUS_UPDATED;
3227
3228         /* if no more work, tell net stack and NIC we're done */
3229         done = !tg3_has_work(tp);
3230         if (done) {
3231                 spin_lock(&tp->lock);
3232                 netif_rx_complete(netdev);
3233                 tg3_restart_ints(tp);
3234                 spin_unlock(&tp->lock);
3235         }
3236
3237         return (done ? 0 : 1);
3238 }
3239
3240 static void tg3_irq_quiesce(struct tg3 *tp)
3241 {
3242         BUG_ON(tp->irq_sync);
3243
3244         tp->irq_sync = 1;
3245         smp_mb();
3246
3247         synchronize_irq(tp->pdev->irq);
3248 }
3249
3250 static inline int tg3_irq_sync(struct tg3 *tp)
3251 {
3252         return tp->irq_sync;
3253 }
3254
3255 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3256  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3257  * with as well.  Most of the time, this is not necessary except when
3258  * shutting down the device.
3259  */
3260 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3261 {
3262         if (irq_sync)
3263                 tg3_irq_quiesce(tp);
3264         spin_lock_bh(&tp->lock);
3265         spin_lock(&tp->tx_lock);
3266 }
3267
3268 static inline void tg3_full_unlock(struct tg3 *tp)
3269 {
3270         spin_unlock(&tp->tx_lock);
3271         spin_unlock_bh(&tp->lock);
3272 }
3273
3274 /* MSI ISR - No need to check for interrupt sharing and no need to
3275  * flush status block and interrupt mailbox. PCI ordering rules
3276  * guarantee that MSI will arrive after the status block.
3277  */
3278 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3279 {
3280         struct net_device *dev = dev_id;
3281         struct tg3 *tp = netdev_priv(dev);
3282
3283         prefetch(tp->hw_status);
3284         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3285         /*
3286          * Writing any value to intr-mbox-0 clears PCI INTA# and
3287          * chip-internal interrupt pending events.
3288          * Writing non-zero to intr-mbox-0 additional tells the
3289          * NIC to stop sending us irqs, engaging "in-intr-handler"
3290          * event coalescing.
3291          */
3292         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3293         if (likely(!tg3_irq_sync(tp)))
3294                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3295
3296         return IRQ_RETVAL(1);
3297 }
3298
3299 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3300 {
3301         struct net_device *dev = dev_id;
3302         struct tg3 *tp = netdev_priv(dev);
3303         struct tg3_hw_status *sblk = tp->hw_status;
3304         unsigned int handled = 1;
3305
3306         /* In INTx mode, it is possible for the interrupt to arrive at
3307          * the CPU before the status block posted prior to the interrupt.
3308          * Reading the PCI State register will confirm whether the
3309          * interrupt is ours and will flush the status block.
3310          */
3311         if ((sblk->status & SD_STATUS_UPDATED) ||
3312             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3313                 /*
3314                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3315                  * chip-internal interrupt pending events.
3316                  * Writing non-zero to intr-mbox-0 additional tells the
3317                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3318                  * event coalescing.
3319                  */
3320                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3321                              0x00000001);
3322                 if (tg3_irq_sync(tp))
3323                         goto out;
3324                 sblk->status &= ~SD_STATUS_UPDATED;
3325                 if (likely(tg3_has_work(tp))) {
3326                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3327                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3328                 } else {
3329                         /* No work, shared interrupt perhaps?  re-enable
3330                          * interrupts, and flush that PCI write
3331                          */
3332                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3333                                 0x00000000);
3334                 }
3335         } else {        /* shared interrupt */
3336                 handled = 0;
3337         }
3338 out:
3339         return IRQ_RETVAL(handled);
3340 }
3341
3342 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3343 {
3344         struct net_device *dev = dev_id;
3345         struct tg3 *tp = netdev_priv(dev);
3346         struct tg3_hw_status *sblk = tp->hw_status;
3347         unsigned int handled = 1;
3348
3349         /* In INTx mode, it is possible for the interrupt to arrive at
3350          * the CPU before the status block posted prior to the interrupt.
3351          * Reading the PCI State register will confirm whether the
3352          * interrupt is ours and will flush the status block.
3353          */
3354         if ((sblk->status & SD_STATUS_UPDATED) ||
3355             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3356                 /*
3357                  * writing any value to intr-mbox-0 clears PCI INTA# and
3358                  * chip-internal interrupt pending events.
3359                  * writing non-zero to intr-mbox-0 additional tells the
3360                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3361                  * event coalescing.
3362                  */
3363                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3364                              0x00000001);
3365                 tp->last_tag = sblk->status_tag;
3366                 rmb();
3367                 if (tg3_irq_sync(tp))
3368                         goto out;
3369                 sblk->status &= ~SD_STATUS_UPDATED;
3370                 if (likely(tg3_has_work(tp))) {
3371                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3372                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3373                 } else {
3374                         /* no work, shared interrupt perhaps?  re-enable
3375                          * interrupts, and flush that PCI write
3376                          */
3377                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3378                                        tp->last_tag << 24);
3379                 }
3380         } else {        /* shared interrupt */
3381                 handled = 0;
3382         }
3383 out:
3384         return IRQ_RETVAL(handled);
3385 }
3386
3387 /* ISR for interrupt test */
3388 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3389                 struct pt_regs *regs)
3390 {
3391         struct net_device *dev = dev_id;
3392         struct tg3 *tp = netdev_priv(dev);
3393         struct tg3_hw_status *sblk = tp->hw_status;
3394
3395         if (sblk->status & SD_STATUS_UPDATED) {
3396                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3397                              0x00000001);
3398                 return IRQ_RETVAL(1);
3399         }
3400         return IRQ_RETVAL(0);
3401 }
3402
3403 static int tg3_init_hw(struct tg3 *);
3404 static int tg3_halt(struct tg3 *, int, int);
3405
3406 #ifdef CONFIG_NET_POLL_CONTROLLER
3407 static void tg3_poll_controller(struct net_device *dev)
3408 {
3409         struct tg3 *tp = netdev_priv(dev);
3410
3411         tg3_interrupt(tp->pdev->irq, dev, NULL);
3412 }
3413 #endif
3414
3415 static void tg3_reset_task(void *_data)
3416 {
3417         struct tg3 *tp = _data;
3418         unsigned int restart_timer;
3419
3420         tg3_netif_stop(tp);
3421
3422         tg3_full_lock(tp, 1);
3423
3424         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3425         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3426
3427         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3428         tg3_init_hw(tp);
3429
3430         tg3_netif_start(tp);
3431
3432         tg3_full_unlock(tp);
3433
3434         if (restart_timer)
3435                 mod_timer(&tp->timer, jiffies + 1);
3436 }
3437
3438 static void tg3_tx_timeout(struct net_device *dev)
3439 {
3440         struct tg3 *tp = netdev_priv(dev);
3441
3442         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3443                dev->name);
3444
3445         schedule_work(&tp->reset_task);
3446 }
3447
3448 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3449
3450 static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3451                                        u32 guilty_entry, int guilty_len,
3452                                        u32 last_plus_one, u32 *start, u32 mss)
3453 {
3454         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3455         dma_addr_t new_addr;
3456         u32 entry = *start;
3457         int i;
3458
3459         if (!new_skb) {
3460                 dev_kfree_skb(skb);
3461                 return -1;
3462         }
3463
3464         /* New SKB is guaranteed to be linear. */
3465         entry = *start;
3466         new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3467                                   PCI_DMA_TODEVICE);
3468         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3469                     (skb->ip_summed == CHECKSUM_HW) ?
3470                     TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
3471         *start = NEXT_TX(entry);
3472
3473         /* Now clean up the sw ring entries. */
3474         i = 0;
3475         while (entry != last_plus_one) {
3476                 int len;
3477
3478                 if (i == 0)
3479                         len = skb_headlen(skb);
3480                 else
3481                         len = skb_shinfo(skb)->frags[i-1].size;
3482                 pci_unmap_single(tp->pdev,
3483                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3484                                  len, PCI_DMA_TODEVICE);
3485                 if (i == 0) {
3486                         tp->tx_buffers[entry].skb = new_skb;
3487                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3488                 } else {
3489                         tp->tx_buffers[entry].skb = NULL;
3490                 }
3491                 entry = NEXT_TX(entry);
3492                 i++;
3493         }
3494
3495         dev_kfree_skb(skb);
3496
3497         return 0;
3498 }
3499
3500 static void tg3_set_txd(struct tg3 *tp, int entry,
3501                         dma_addr_t mapping, int len, u32 flags,
3502                         u32 mss_and_is_end)
3503 {
3504         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3505         int is_end = (mss_and_is_end & 0x1);
3506         u32 mss = (mss_and_is_end >> 1);
3507         u32 vlan_tag = 0;
3508
3509         if (is_end)
3510                 flags |= TXD_FLAG_END;
3511         if (flags & TXD_FLAG_VLAN) {
3512                 vlan_tag = flags >> 16;
3513                 flags &= 0xffff;
3514         }
3515         vlan_tag |= (mss << TXD_MSS_SHIFT);
3516
3517         txd->addr_hi = ((u64) mapping >> 32);
3518         txd->addr_lo = ((u64) mapping & 0xffffffff);
3519         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3520         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3521 }
3522
3523 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3524 {
3525         u32 base = (u32) mapping & 0xffffffff;
3526
3527         return ((base > 0xffffdcc0) &&
3528                 (base + len + 8 < base));
3529 }
3530
3531 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3532 {
3533         struct tg3 *tp = netdev_priv(dev);
3534         dma_addr_t mapping;
3535         unsigned int i;
3536         u32 len, entry, base_flags, mss;
3537         int would_hit_hwbug;
3538
3539         len = skb_headlen(skb);
3540
3541         /* No BH disabling for tx_lock here.  We are running in BH disabled
3542          * context and TX reclaim runs via tp->poll inside of a software
3543          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3544          * no IRQ context deadlocks to worry about either.  Rejoice!
3545          */
3546         if (!spin_trylock(&tp->tx_lock))
3547                 return NETDEV_TX_LOCKED;
3548
3549         /* This is a hard error, log it. */
3550         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3551                 netif_stop_queue(dev);
3552                 spin_unlock(&tp->tx_lock);
3553                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3554                        dev->name);
3555                 return NETDEV_TX_BUSY;
3556         }
3557
3558         entry = tp->tx_prod;
3559         base_flags = 0;
3560         if (skb->ip_summed == CHECKSUM_HW)
3561                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3562 #if TG3_TSO_SUPPORT != 0
3563         mss = 0;
3564         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3565             (mss = skb_shinfo(skb)->tso_size) != 0) {
3566                 int tcp_opt_len, ip_tcp_len;
3567
3568                 if (skb_header_cloned(skb) &&
3569                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3570                         dev_kfree_skb(skb);
3571                         goto out_unlock;
3572                 }
3573
3574                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3575                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3576
3577                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3578                                TXD_FLAG_CPU_POST_DMA);
3579
3580                 skb->nh.iph->check = 0;
3581                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3582                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3583                         skb->h.th->check = 0;
3584                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3585                 }
3586                 else {
3587                         skb->h.th->check =
3588                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3589                                                    skb->nh.iph->daddr,
3590                                                    0, IPPROTO_TCP, 0);
3591                 }
3592
3593                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3594                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3595                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3596                                 int tsflags;
3597
3598                                 tsflags = ((skb->nh.iph->ihl - 5) +
3599                                            (tcp_opt_len >> 2));
3600                                 mss |= (tsflags << 11);
3601                         }
3602                 } else {
3603                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3604                                 int tsflags;
3605
3606                                 tsflags = ((skb->nh.iph->ihl - 5) +
3607                                            (tcp_opt_len >> 2));
3608                                 base_flags |= tsflags << 12;
3609                         }
3610                 }
3611         }
3612 #else
3613         mss = 0;
3614 #endif
3615 #if TG3_VLAN_TAG_USED
3616         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3617                 base_flags |= (TXD_FLAG_VLAN |
3618                                (vlan_tx_tag_get(skb) << 16));
3619 #endif
3620
3621         /* Queue skb data, a.k.a. the main skb fragment. */
3622         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3623
3624         tp->tx_buffers[entry].skb = skb;
3625         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3626
3627         would_hit_hwbug = 0;
3628
3629         if (tg3_4g_overflow_test(mapping, len))
3630                 would_hit_hwbug = entry + 1;
3631
3632         tg3_set_txd(tp, entry, mapping, len, base_flags,
3633                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3634
3635         entry = NEXT_TX(entry);
3636
3637         /* Now loop through additional data fragments, and queue them. */
3638         if (skb_shinfo(skb)->nr_frags > 0) {
3639                 unsigned int i, last;
3640
3641                 last = skb_shinfo(skb)->nr_frags - 1;
3642                 for (i = 0; i <= last; i++) {
3643                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3644
3645                         len = frag->size;
3646                         mapping = pci_map_page(tp->pdev,
3647                                                frag->page,
3648                                                frag->page_offset,
3649                                                len, PCI_DMA_TODEVICE);
3650
3651                         tp->tx_buffers[entry].skb = NULL;
3652                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3653
3654                         if (tg3_4g_overflow_test(mapping, len)) {
3655                                 /* Only one should match. */
3656                                 if (would_hit_hwbug)
3657                                         BUG();
3658                                 would_hit_hwbug = entry + 1;
3659                         }
3660
3661                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3662                                 tg3_set_txd(tp, entry, mapping, len,
3663                                             base_flags, (i == last)|(mss << 1));
3664                         else
3665                                 tg3_set_txd(tp, entry, mapping, len,
3666                                             base_flags, (i == last));
3667
3668                         entry = NEXT_TX(entry);
3669                 }
3670         }
3671
3672         if (would_hit_hwbug) {
3673                 u32 last_plus_one = entry;
3674                 u32 start;
3675                 unsigned int len = 0;
3676
3677                 would_hit_hwbug -= 1;
3678                 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3679                 entry &= (TG3_TX_RING_SIZE - 1);
3680                 start = entry;
3681                 i = 0;
3682                 while (entry != last_plus_one) {
3683                         if (i == 0)
3684                                 len = skb_headlen(skb);
3685                         else
3686                                 len = skb_shinfo(skb)->frags[i-1].size;
3687
3688                         if (entry == would_hit_hwbug)
3689                                 break;
3690
3691                         i++;
3692                         entry = NEXT_TX(entry);
3693
3694                 }
3695
3696                 /* If the workaround fails due to memory/mapping
3697                  * failure, silently drop this packet.
3698                  */
3699                 if (tigon3_4gb_hwbug_workaround(tp, skb,
3700                                                 entry, len,
3701                                                 last_plus_one,
3702                                                 &start, mss))
3703                         goto out_unlock;
3704
3705                 entry = start;
3706         }
3707
3708         /* Packets are ready, update Tx producer idx local and on card. */
3709         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3710
3711         tp->tx_prod = entry;
3712         if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
3713                 netif_stop_queue(dev);
3714                 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
3715                         netif_wake_queue(tp->dev);
3716         }
3717
3718 out_unlock:
3719         mmiowb();
3720         spin_unlock(&tp->tx_lock);
3721
3722         dev->trans_start = jiffies;
3723
3724         return NETDEV_TX_OK;
3725 }
3726
3727 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3728                                int new_mtu)
3729 {
3730         dev->mtu = new_mtu;
3731
3732         if (new_mtu > ETH_DATA_LEN) {
3733                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
3734                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
3735                         ethtool_op_set_tso(dev, 0);
3736                 }
3737                 else
3738                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
3739         } else {
3740                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
3741                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
3742                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
3743         }
3744 }
3745
3746 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3747 {
3748         struct tg3 *tp = netdev_priv(dev);
3749
3750         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3751                 return -EINVAL;
3752
3753         if (!netif_running(dev)) {
3754                 /* We'll just catch it later when the
3755                  * device is up'd.
3756                  */
3757                 tg3_set_mtu(dev, tp, new_mtu);
3758                 return 0;
3759         }
3760
3761         tg3_netif_stop(tp);
3762
3763         tg3_full_lock(tp, 1);
3764
3765         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3766
3767         tg3_set_mtu(dev, tp, new_mtu);
3768
3769         tg3_init_hw(tp);
3770
3771         tg3_netif_start(tp);
3772
3773         tg3_full_unlock(tp);
3774
3775         return 0;
3776 }
3777
3778 /* Free up pending packets in all rx/tx rings.
3779  *
3780  * The chip has been shut down and the driver detached from
3781  * the networking, so no interrupts or new tx packets will
3782  * end up in the driver.  tp->{tx,}lock is not held and we are not
3783  * in an interrupt context and thus may sleep.
3784  */
3785 static void tg3_free_rings(struct tg3 *tp)
3786 {
3787         struct ring_info *rxp;
3788         int i;
3789
3790         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3791                 rxp = &tp->rx_std_buffers[i];
3792
3793                 if (rxp->skb == NULL)
3794                         continue;
3795                 pci_unmap_single(tp->pdev,
3796                                  pci_unmap_addr(rxp, mapping),
3797                                  tp->rx_pkt_buf_sz - tp->rx_offset,
3798                                  PCI_DMA_FROMDEVICE);
3799                 dev_kfree_skb_any(rxp->skb);
3800                 rxp->skb = NULL;
3801         }
3802
3803         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3804                 rxp = &tp->rx_jumbo_buffers[i];
3805
3806                 if (rxp->skb == NULL)
3807                         continue;
3808                 pci_unmap_single(tp->pdev,
3809                                  pci_unmap_addr(rxp, mapping),
3810                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3811                                  PCI_DMA_FROMDEVICE);
3812                 dev_kfree_skb_any(rxp->skb);
3813                 rxp->skb = NULL;
3814         }
3815
3816         for (i = 0; i < TG3_TX_RING_SIZE; ) {
3817                 struct tx_ring_info *txp;
3818                 struct sk_buff *skb;
3819                 int j;
3820
3821                 txp = &tp->tx_buffers[i];
3822                 skb = txp->skb;
3823
3824                 if (skb == NULL) {
3825                         i++;
3826                         continue;
3827                 }
3828
3829                 pci_unmap_single(tp->pdev,
3830                                  pci_unmap_addr(txp, mapping),
3831                                  skb_headlen(skb),
3832                                  PCI_DMA_TODEVICE);
3833                 txp->skb = NULL;
3834
3835                 i++;
3836
3837                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3838                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3839                         pci_unmap_page(tp->pdev,
3840                                        pci_unmap_addr(txp, mapping),
3841                                        skb_shinfo(skb)->frags[j].size,
3842                                        PCI_DMA_TODEVICE);
3843                         i++;
3844                 }
3845
3846                 dev_kfree_skb_any(skb);
3847         }
3848 }
3849
3850 /* Initialize tx/rx rings for packet processing.
3851  *
3852  * The chip has been shut down and the driver detached from
3853  * the networking, so no interrupts or new tx packets will
3854  * end up in the driver.  tp->{tx,}lock are held and thus
3855  * we may not sleep.
3856  */
3857 static void tg3_init_rings(struct tg3 *tp)
3858 {
3859         u32 i;
3860
3861         /* Free up all the SKBs. */
3862         tg3_free_rings(tp);
3863
3864         /* Zero out all descriptors. */
3865         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3866         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3867         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3868         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3869
3870         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
3871         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) &&
3872             (tp->dev->mtu > ETH_DATA_LEN))
3873                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
3874
3875         /* Initialize invariants of the rings, we only set this
3876          * stuff once.  This works because the card does not
3877          * write into the rx buffer posting rings.
3878          */
3879         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3880                 struct tg3_rx_buffer_desc *rxd;
3881
3882                 rxd = &tp->rx_std[i];
3883                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
3884                         << RXD_LEN_SHIFT;
3885                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3886                 rxd->opaque = (RXD_OPAQUE_RING_STD |
3887                                (i << RXD_OPAQUE_INDEX_SHIFT));
3888         }
3889
3890         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3891                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3892                         struct tg3_rx_buffer_desc *rxd;
3893
3894                         rxd = &tp->rx_jumbo[i];
3895                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3896                                 << RXD_LEN_SHIFT;
3897                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3898                                 RXD_FLAG_JUMBO;
3899                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3900                                (i << RXD_OPAQUE_INDEX_SHIFT));
3901                 }
3902         }
3903
3904         /* Now allocate fresh SKBs for each rx ring. */
3905         for (i = 0; i < tp->rx_pending; i++) {
3906                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3907                                      -1, i) < 0)
3908                         break;
3909         }
3910
3911         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3912                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3913                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3914                                              -1, i) < 0)
3915                                 break;
3916                 }
3917         }
3918 }
3919
3920 /*
3921  * Must not be invoked with interrupt sources disabled and
3922  * the hardware shutdown down.
3923  */
3924 static void tg3_free_consistent(struct tg3 *tp)
3925 {
3926         if (tp->rx_std_buffers) {
3927                 kfree(tp->rx_std_buffers);
3928                 tp->rx_std_buffers = NULL;
3929         }
3930         if (tp->rx_std) {
3931                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3932                                     tp->rx_std, tp->rx_std_mapping);
3933                 tp->rx_std = NULL;
3934         }
3935         if (tp->rx_jumbo) {
3936                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3937                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
3938                 tp->rx_jumbo = NULL;
3939         }
3940         if (tp->rx_rcb) {
3941                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3942                                     tp->rx_rcb, tp->rx_rcb_mapping);
3943                 tp->rx_rcb = NULL;
3944         }
3945         if (tp->tx_ring) {
3946                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3947                         tp->tx_ring, tp->tx_desc_mapping);
3948                 tp->tx_ring = NULL;
3949         }
3950         if (tp->hw_status) {
3951                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3952                                     tp->hw_status, tp->status_mapping);
3953                 tp->hw_status = NULL;
3954         }
3955         if (tp->hw_stats) {
3956                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3957                                     tp->hw_stats, tp->stats_mapping);
3958                 tp->hw_stats = NULL;
3959         }
3960 }
3961
3962 /*
3963  * Must not be invoked with interrupt sources disabled and
3964  * the hardware shutdown down.  Can sleep.
3965  */
3966 static int tg3_alloc_consistent(struct tg3 *tp)
3967 {
3968         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3969                                       (TG3_RX_RING_SIZE +
3970                                        TG3_RX_JUMBO_RING_SIZE)) +
3971                                      (sizeof(struct tx_ring_info) *
3972                                       TG3_TX_RING_SIZE),
3973                                      GFP_KERNEL);
3974         if (!tp->rx_std_buffers)
3975                 return -ENOMEM;
3976
3977         memset(tp->rx_std_buffers, 0,
3978                (sizeof(struct ring_info) *
3979                 (TG3_RX_RING_SIZE +
3980                  TG3_RX_JUMBO_RING_SIZE)) +
3981                (sizeof(struct tx_ring_info) *
3982                 TG3_TX_RING_SIZE));
3983
3984         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3985         tp->tx_buffers = (struct tx_ring_info *)
3986                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3987
3988         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3989                                           &tp->rx_std_mapping);
3990         if (!tp->rx_std)
3991                 goto err_out;
3992
3993         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3994                                             &tp->rx_jumbo_mapping);
3995
3996         if (!tp->rx_jumbo)
3997                 goto err_out;
3998
3999         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4000                                           &tp->rx_rcb_mapping);
4001         if (!tp->rx_rcb)
4002                 goto err_out;
4003
4004         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4005                                            &tp->tx_desc_mapping);
4006         if (!tp->tx_ring)
4007                 goto err_out;
4008
4009         tp->hw_status = pci_alloc_consistent(tp->pdev,
4010                                              TG3_HW_STATUS_SIZE,
4011                                              &tp->status_mapping);
4012         if (!tp->hw_status)
4013                 goto err_out;
4014
4015         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4016                                             sizeof(struct tg3_hw_stats),
4017                                             &tp->stats_mapping);
4018         if (!tp->hw_stats)
4019                 goto err_out;
4020
4021         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4022         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4023
4024         return 0;
4025
4026 err_out:
4027         tg3_free_consistent(tp);
4028         return -ENOMEM;
4029 }
4030
4031 #define MAX_WAIT_CNT 1000
4032
4033 /* To stop a block, clear the enable bit and poll till it
4034  * clears.  tp->lock is held.
4035  */
4036 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4037 {
4038         unsigned int i;
4039         u32 val;
4040
4041         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4042                 switch (ofs) {
4043                 case RCVLSC_MODE:
4044                 case DMAC_MODE:
4045                 case MBFREE_MODE:
4046                 case BUFMGR_MODE:
4047                 case MEMARB_MODE:
4048                         /* We can't enable/disable these bits of the
4049                          * 5705/5750, just say success.
4050                          */
4051                         return 0;
4052
4053                 default:
4054                         break;
4055                 };
4056         }
4057
4058         val = tr32(ofs);
4059         val &= ~enable_bit;
4060         tw32_f(ofs, val);
4061
4062         for (i = 0; i < MAX_WAIT_CNT; i++) {
4063                 udelay(100);
4064                 val = tr32(ofs);
4065                 if ((val & enable_bit) == 0)
4066                         break;
4067         }
4068
4069         if (i == MAX_WAIT_CNT && !silent) {
4070                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4071                        "ofs=%lx enable_bit=%x\n",
4072                        ofs, enable_bit);
4073                 return -ENODEV;
4074         }
4075
4076         return 0;
4077 }
4078
4079 /* tp->lock is held. */
4080 static int tg3_abort_hw(struct tg3 *tp, int silent)
4081 {
4082         int i, err;
4083
4084         tg3_disable_ints(tp);
4085
4086         tp->rx_mode &= ~RX_MODE_ENABLE;
4087         tw32_f(MAC_RX_MODE, tp->rx_mode);
4088         udelay(10);
4089
4090         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4091         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4092         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4093         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4094         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4095         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4096
4097         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4098         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4099         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4100         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4101         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4102         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4103         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4104
4105         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4106         tw32_f(MAC_MODE, tp->mac_mode);
4107         udelay(40);
4108
4109         tp->tx_mode &= ~TX_MODE_ENABLE;
4110         tw32_f(MAC_TX_MODE, tp->tx_mode);
4111
4112         for (i = 0; i < MAX_WAIT_CNT; i++) {
4113                 udelay(100);
4114                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4115                         break;
4116         }
4117         if (i >= MAX_WAIT_CNT) {
4118                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4119                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4120                        tp->dev->name, tr32(MAC_TX_MODE));
4121                 err |= -ENODEV;
4122         }
4123
4124         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4125         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4126         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4127
4128         tw32(FTQ_RESET, 0xffffffff);
4129         tw32(FTQ_RESET, 0x00000000);
4130
4131         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4132         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4133
4134         if (tp->hw_status)
4135                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4136         if (tp->hw_stats)
4137                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4138
4139         return err;
4140 }
4141
4142 /* tp->lock is held. */
4143 static int tg3_nvram_lock(struct tg3 *tp)
4144 {
4145         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4146                 int i;
4147
4148                 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4149                 for (i = 0; i < 8000; i++) {
4150                         if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4151                                 break;
4152                         udelay(20);
4153                 }
4154                 if (i == 8000)
4155                         return -ENODEV;
4156         }
4157         return 0;
4158 }
4159
4160 /* tp->lock is held. */
4161 static void tg3_nvram_unlock(struct tg3 *tp)
4162 {
4163         if (tp->tg3_flags & TG3_FLAG_NVRAM)
4164                 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4165 }
4166
4167 /* tp->lock is held. */
4168 static void tg3_enable_nvram_access(struct tg3 *tp)
4169 {
4170         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4171             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4172                 u32 nvaccess = tr32(NVRAM_ACCESS);
4173
4174                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4175         }
4176 }
4177
4178 /* tp->lock is held. */
4179 static void tg3_disable_nvram_access(struct tg3 *tp)
4180 {
4181         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4182             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4183                 u32 nvaccess = tr32(NVRAM_ACCESS);
4184
4185                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4186         }
4187 }
4188
4189 /* tp->lock is held. */
4190 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4191 {
4192         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4193                 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4194                               NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4195
4196         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4197                 switch (kind) {
4198                 case RESET_KIND_INIT:
4199                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4200                                       DRV_STATE_START);
4201                         break;
4202
4203                 case RESET_KIND_SHUTDOWN:
4204                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4205                                       DRV_STATE_UNLOAD);
4206                         break;
4207
4208                 case RESET_KIND_SUSPEND:
4209                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4210                                       DRV_STATE_SUSPEND);
4211                         break;
4212
4213                 default:
4214                         break;
4215                 };
4216         }
4217 }
4218
4219 /* tp->lock is held. */
4220 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4221 {
4222         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4223                 switch (kind) {
4224                 case RESET_KIND_INIT:
4225                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4226                                       DRV_STATE_START_DONE);
4227                         break;
4228
4229                 case RESET_KIND_SHUTDOWN:
4230                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4231                                       DRV_STATE_UNLOAD_DONE);
4232                         break;
4233
4234                 default:
4235                         break;
4236                 };
4237         }
4238 }
4239
4240 /* tp->lock is held. */
4241 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4242 {
4243         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4244                 switch (kind) {
4245                 case RESET_KIND_INIT:
4246                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4247                                       DRV_STATE_START);
4248                         break;
4249
4250                 case RESET_KIND_SHUTDOWN:
4251                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4252                                       DRV_STATE_UNLOAD);
4253                         break;
4254
4255                 case RESET_KIND_SUSPEND:
4256                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4257                                       DRV_STATE_SUSPEND);
4258                         break;
4259
4260                 default:
4261                         break;
4262                 };
4263         }
4264 }
4265
4266 static void tg3_stop_fw(struct tg3 *);
4267
4268 /* tp->lock is held. */
4269 static int tg3_chip_reset(struct tg3 *tp)
4270 {
4271         u32 val;
4272         void (*write_op)(struct tg3 *, u32, u32);
4273         int i;
4274
4275         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4276                 tg3_nvram_lock(tp);
4277
4278         /*
4279          * We must avoid the readl() that normally takes place.
4280          * It locks machines, causes machine checks, and other
4281          * fun things.  So, temporarily disable the 5701
4282          * hardware workaround, while we do the reset.
4283          */
4284         write_op = tp->write32;
4285         if (write_op == tg3_write_flush_reg32)
4286                 tp->write32 = tg3_write32;
4287
4288         /* do the reset */
4289         val = GRC_MISC_CFG_CORECLK_RESET;
4290
4291         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4292                 if (tr32(0x7e2c) == 0x60) {
4293                         tw32(0x7e2c, 0x20);
4294                 }
4295                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4296                         tw32(GRC_MISC_CFG, (1 << 29));
4297                         val |= (1 << 29);
4298                 }
4299         }
4300
4301         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4302                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4303         tw32(GRC_MISC_CFG, val);
4304
4305         /* restore 5701 hardware bug workaround write method */
4306         tp->write32 = write_op;
4307
4308         /* Unfortunately, we have to delay before the PCI read back.
4309          * Some 575X chips even will not respond to a PCI cfg access
4310          * when the reset command is given to the chip.
4311          *
4312          * How do these hardware designers expect things to work
4313          * properly if the PCI write is posted for a long period
4314          * of time?  It is always necessary to have some method by
4315          * which a register read back can occur to push the write
4316          * out which does the reset.
4317          *
4318          * For most tg3 variants the trick below was working.
4319          * Ho hum...
4320          */
4321         udelay(120);
4322
4323         /* Flush PCI posted writes.  The normal MMIO registers
4324          * are inaccessible at this time so this is the only
4325          * way to make this reliably (actually, this is no longer
4326          * the case, see above).  I tried to use indirect
4327          * register read/write but this upset some 5701 variants.
4328          */
4329         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4330
4331         udelay(120);
4332
4333         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4334                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4335                         int i;
4336                         u32 cfg_val;
4337
4338                         /* Wait for link training to complete.  */
4339                         for (i = 0; i < 5000; i++)
4340                                 udelay(100);
4341
4342                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4343                         pci_write_config_dword(tp->pdev, 0xc4,
4344                                                cfg_val | (1 << 15));
4345                 }
4346                 /* Set PCIE max payload size and clear error status.  */
4347                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4348         }
4349
4350         /* Re-enable indirect register accesses. */
4351         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4352                                tp->misc_host_ctrl);
4353
4354         /* Set MAX PCI retry to zero. */
4355         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4356         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4357             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4358                 val |= PCISTATE_RETRY_SAME_DMA;
4359         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4360
4361         pci_restore_state(tp->pdev);
4362
4363         /* Make sure PCI-X relaxed ordering bit is clear. */
4364         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4365         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4366         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4367
4368         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
4369                 u32 val;
4370
4371                 /* Chip reset on 5780 will reset MSI enable bit,
4372                  * so need to restore it.
4373                  */
4374                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4375                         u16 ctrl;
4376
4377                         pci_read_config_word(tp->pdev,
4378                                              tp->msi_cap + PCI_MSI_FLAGS,
4379                                              &ctrl);
4380                         pci_write_config_word(tp->pdev,
4381                                               tp->msi_cap + PCI_MSI_FLAGS,
4382                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4383                         val = tr32(MSGINT_MODE);
4384                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4385                 }
4386
4387                 val = tr32(MEMARB_MODE);
4388                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4389
4390         } else
4391                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4392
4393         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4394                 tg3_stop_fw(tp);
4395                 tw32(0x5000, 0x400);
4396         }
4397
4398         tw32(GRC_MODE, tp->grc_mode);
4399
4400         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4401                 u32 val = tr32(0xc4);
4402
4403                 tw32(0xc4, val | (1 << 15));
4404         }
4405
4406         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4407             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4408                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4409                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4410                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4411                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4412         }
4413
4414         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4415                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4416                 tw32_f(MAC_MODE, tp->mac_mode);
4417         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4418                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4419                 tw32_f(MAC_MODE, tp->mac_mode);
4420         } else
4421                 tw32_f(MAC_MODE, 0);
4422         udelay(40);
4423
4424         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4425                 /* Wait for firmware initialization to complete. */
4426                 for (i = 0; i < 100000; i++) {
4427                         tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4428                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4429                                 break;
4430                         udelay(10);
4431                 }
4432                 if (i >= 100000) {
4433                         printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4434                                "firmware will not restart magic=%08x\n",
4435                                tp->dev->name, val);
4436                         return -ENODEV;
4437                 }
4438         }
4439
4440         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4441             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4442                 u32 val = tr32(0x7c00);
4443
4444                 tw32(0x7c00, val | (1 << 25));
4445         }
4446
4447         /* Reprobe ASF enable state.  */
4448         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4449         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4450         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4451         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4452                 u32 nic_cfg;
4453
4454                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4455                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4456                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4457                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4458                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4459                 }
4460         }
4461
4462         return 0;
4463 }
4464
4465 /* tp->lock is held. */
4466 static void tg3_stop_fw(struct tg3 *tp)
4467 {
4468         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4469                 u32 val;
4470                 int i;
4471
4472                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4473                 val = tr32(GRC_RX_CPU_EVENT);
4474                 val |= (1 << 14);
4475                 tw32(GRC_RX_CPU_EVENT, val);
4476
4477                 /* Wait for RX cpu to ACK the event.  */
4478                 for (i = 0; i < 100; i++) {
4479                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4480                                 break;
4481                         udelay(1);
4482                 }
4483         }
4484 }
4485
4486 /* tp->lock is held. */
4487 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4488 {
4489         int err;
4490
4491         tg3_stop_fw(tp);
4492
4493         tg3_write_sig_pre_reset(tp, kind);
4494
4495         tg3_abort_hw(tp, silent);
4496         err = tg3_chip_reset(tp);
4497
4498         tg3_write_sig_legacy(tp, kind);
4499         tg3_write_sig_post_reset(tp, kind);
4500
4501         if (err)
4502                 return err;
4503
4504         return 0;
4505 }
4506
4507 #define TG3_FW_RELEASE_MAJOR    0x0
4508 #define TG3_FW_RELASE_MINOR     0x0
4509 #define TG3_FW_RELEASE_FIX      0x0
4510 #define TG3_FW_START_ADDR       0x08000000
4511 #define TG3_FW_TEXT_ADDR        0x08000000
4512 #define TG3_FW_TEXT_LEN         0x9c0
4513 #define TG3_FW_RODATA_ADDR      0x080009c0
4514 #define TG3_FW_RODATA_LEN       0x60
4515 #define TG3_FW_DATA_ADDR        0x08000a40
4516 #define TG3_FW_DATA_LEN         0x20
4517 #define TG3_FW_SBSS_ADDR        0x08000a60
4518 #define TG3_FW_SBSS_LEN         0xc
4519 #define TG3_FW_BSS_ADDR         0x08000a70
4520 #define TG3_FW_BSS_LEN          0x10
4521
4522 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4523         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4524         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4525         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4526         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4527         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4528         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4529         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4530         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4531         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4532         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4533         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4534         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4535         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4536         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4537         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4538         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4539         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4540         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4541         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4542         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4543         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4544         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4545         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4546         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4547         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4548         0, 0, 0, 0, 0, 0,
4549         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4550         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4551         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4552         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4553         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4554         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4555         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4556         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4557         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4558         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4559         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4560         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4561         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4562         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4563         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4564         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4565         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4566         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4567         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4568         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4569         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4570         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4571         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4572         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4573         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4574         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4575         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4576         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4577         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4578         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4579         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4580         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4581         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4582         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4583         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4584         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4585         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4586         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4587         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4588         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4589         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4590         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4591         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4592         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4593         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4594         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4595         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4596         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4597         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4598         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4599         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4600         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4601         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4602         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4603         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4604         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4605         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4606         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4607         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4608         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4609         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4610         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4611         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4612         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4613         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4614 };
4615
4616 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4617         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4618         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4619         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4620         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4621         0x00000000
4622 };
4623
4624 #if 0 /* All zeros, don't eat up space with it. */
4625 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4626         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4627         0x00000000, 0x00000000, 0x00000000, 0x00000000
4628 };
4629 #endif
4630
4631 #define RX_CPU_SCRATCH_BASE     0x30000
4632 #define RX_CPU_SCRATCH_SIZE     0x04000
4633 #define TX_CPU_SCRATCH_BASE     0x34000
4634 #define TX_CPU_SCRATCH_SIZE     0x04000
4635
4636 /* tp->lock is held. */
4637 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4638 {
4639         int i;
4640
4641         if (offset == TX_CPU_BASE &&
4642             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4643                 BUG();
4644
4645         if (offset == RX_CPU_BASE) {
4646                 for (i = 0; i < 10000; i++) {
4647                         tw32(offset + CPU_STATE, 0xffffffff);
4648                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4649                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4650                                 break;
4651                 }
4652
4653                 tw32(offset + CPU_STATE, 0xffffffff);
4654                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
4655                 udelay(10);
4656         } else {
4657                 for (i = 0; i < 10000; i++) {
4658                         tw32(offset + CPU_STATE, 0xffffffff);
4659                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4660                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4661                                 break;
4662                 }
4663         }
4664
4665         if (i >= 10000) {
4666                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4667                        "and %s CPU\n",
4668                        tp->dev->name,
4669                        (offset == RX_CPU_BASE ? "RX" : "TX"));
4670                 return -ENODEV;
4671         }
4672         return 0;
4673 }
4674
4675 struct fw_info {
4676         unsigned int text_base;
4677         unsigned int text_len;
4678         u32 *text_data;
4679         unsigned int rodata_base;
4680         unsigned int rodata_len;
4681         u32 *rodata_data;
4682         unsigned int data_base;
4683         unsigned int data_len;
4684         u32 *data_data;
4685 };
4686
4687 /* tp->lock is held. */
4688 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4689                                  int cpu_scratch_size, struct fw_info *info)
4690 {
4691         int err, i;
4692         void (*write_op)(struct tg3 *, u32, u32);
4693
4694         if (cpu_base == TX_CPU_BASE &&
4695             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4696                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4697                        "TX cpu firmware on %s which is 5705.\n",
4698                        tp->dev->name);
4699                 return -EINVAL;
4700         }
4701
4702         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4703                 write_op = tg3_write_mem;
4704         else
4705                 write_op = tg3_write_indirect_reg32;
4706
4707         /* It is possible that bootcode is still loading at this point.
4708          * Get the nvram lock first before halting the cpu.
4709          */
4710         tg3_nvram_lock(tp);
4711         err = tg3_halt_cpu(tp, cpu_base);
4712         tg3_nvram_unlock(tp);
4713         if (err)
4714                 goto out;
4715
4716         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4717                 write_op(tp, cpu_scratch_base + i, 0);
4718         tw32(cpu_base + CPU_STATE, 0xffffffff);
4719         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4720         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4721                 write_op(tp, (cpu_scratch_base +
4722                               (info->text_base & 0xffff) +
4723                               (i * sizeof(u32))),
4724                          (info->text_data ?
4725                           info->text_data[i] : 0));
4726         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4727                 write_op(tp, (cpu_scratch_base +
4728                               (info->rodata_base & 0xffff) +
4729                               (i * sizeof(u32))),
4730                          (info->rodata_data ?
4731                           info->rodata_data[i] : 0));
4732         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4733                 write_op(tp, (cpu_scratch_base +
4734                               (info->data_base & 0xffff) +
4735                               (i * sizeof(u32))),
4736                          (info->data_data ?
4737                           info->data_data[i] : 0));
4738
4739         err = 0;
4740
4741 out:
4742         return err;
4743 }
4744
4745 /* tp->lock is held. */
4746 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4747 {
4748         struct fw_info info;
4749         int err, i;
4750
4751         info.text_base = TG3_FW_TEXT_ADDR;
4752         info.text_len = TG3_FW_TEXT_LEN;
4753         info.text_data = &tg3FwText[0];
4754         info.rodata_base = TG3_FW_RODATA_ADDR;
4755         info.rodata_len = TG3_FW_RODATA_LEN;
4756         info.rodata_data = &tg3FwRodata[0];
4757         info.data_base = TG3_FW_DATA_ADDR;
4758         info.data_len = TG3_FW_DATA_LEN;
4759         info.data_data = NULL;
4760
4761         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4762                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4763                                     &info);
4764         if (err)
4765                 return err;
4766
4767         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4768                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4769                                     &info);
4770         if (err)
4771                 return err;
4772
4773         /* Now startup only the RX cpu. */
4774         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4775         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4776
4777         for (i = 0; i < 5; i++) {
4778                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4779                         break;
4780                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4781                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
4782                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4783                 udelay(1000);
4784         }
4785         if (i >= 5) {
4786                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4787                        "to set RX CPU PC, is %08x should be %08x\n",
4788                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4789                        TG3_FW_TEXT_ADDR);
4790                 return -ENODEV;
4791         }
4792         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4793         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
4794
4795         return 0;
4796 }
4797
4798 #if TG3_TSO_SUPPORT != 0
4799
4800 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
4801 #define TG3_TSO_FW_RELASE_MINOR         0x6
4802 #define TG3_TSO_FW_RELEASE_FIX          0x0
4803 #define TG3_TSO_FW_START_ADDR           0x08000000
4804 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
4805 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
4806 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
4807 #define TG3_TSO_FW_RODATA_LEN           0x60
4808 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
4809 #define TG3_TSO_FW_DATA_LEN             0x30
4810 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
4811 #define TG3_TSO_FW_SBSS_LEN             0x2c
4812 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
4813 #define TG3_TSO_FW_BSS_LEN              0x894
4814
4815 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4816         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4817         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4818         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4819         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4820         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4821         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4822         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4823         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4824         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4825         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4826         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4827         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4828         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4829         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4830         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4831         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4832         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4833         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4834         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4835         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4836         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4837         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4838         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4839         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4840         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4841         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4842         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4843         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4844         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4845         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4846         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4847         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4848         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4849         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4850         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4851         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4852         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4853         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4854         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4855         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4856         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4857         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4858         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4859         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4860         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4861         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4862         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4863         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4864         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4865         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4866         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4867         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4868         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4869         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4870         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4871         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4872         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4873         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4874         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4875         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4876         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4877         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4878         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4879         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4880         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4881         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4882         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4883         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4884         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4885         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4886         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4887         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4888         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4889         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4890         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4891         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4892         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4893         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4894         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4895         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4896         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4897         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4898         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4899         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4900         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4901         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4902         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4903         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4904         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4905         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4906         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4907         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4908         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4909         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4910         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4911         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4912         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4913         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4914         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4915         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4916         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4917         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4918         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4919         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4920         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4921         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4922         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4923         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4924         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4925         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4926         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4927         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4928         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4929         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4930         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4931         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4932         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4933         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4934         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4935         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4936         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4937         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4938         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4939         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4940         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4941         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4942         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4943         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4944         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4945         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4946         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4947         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4948         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4949         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4950         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4951         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4952         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4953         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4954         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4955         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4956         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4957         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4958         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4959         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4960         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4961         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4962         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4963         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4964         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4965         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4966         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4967         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4968         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4969         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4970         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4971         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4972         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4973         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4974         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4975         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4976         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4977         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4978         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4979         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4980         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4981         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4982         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4983         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4984         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4985         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4986         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4987         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4988         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4989         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4990         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4991         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4992         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4993         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4994         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4995         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4996         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4997         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4998         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4999         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5000         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5001         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5002         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5003         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5004         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5005         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5006         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5007         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5008         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5009         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5010         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5011         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5012         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5013         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5014         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5015         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5016         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5017         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5018         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5019         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5020         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5021         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5022         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5023         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5024         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5025         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5026         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5027         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5028         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5029         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5030         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5031         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5032         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5033         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5034         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5035         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5036         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5037         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5038         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5039         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5040         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5041         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5042         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5043         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5044         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5045         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5046         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5047         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5048         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5049         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5050         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5051         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5052         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5053         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5054         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5055         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5056         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5057         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5058         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5059         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5060         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5061         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5062         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5063         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5064         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5065         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5066         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5067         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5068         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5069         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5070         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5071         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5072         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5073         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5074         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5075         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5076         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5077         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5078         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5079         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5080         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5081         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5082         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5083         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5084         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5085         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5086         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5087         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5088         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5089         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5090         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5091         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5092         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5093         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5094         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5095         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5096         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5097         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5098         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5099         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5100 };
5101
5102 static u32 tg3TsoFwRodata[] = {
5103         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5104         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5105         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5106         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5107         0x00000000,
5108 };
5109
5110 static u32 tg3TsoFwData[] = {
5111         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5112         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5113         0x00000000,
5114 };
5115
5116 /* 5705 needs a special version of the TSO firmware.  */
5117 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5118 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5119 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5120 #define TG3_TSO5_FW_START_ADDR          0x00010000
5121 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5122 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5123 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5124 #define TG3_TSO5_FW_RODATA_LEN          0x50
5125 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5126 #define TG3_TSO5_FW_DATA_LEN            0x20
5127 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5128 #define TG3_TSO5_FW_SBSS_LEN            0x28
5129 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5130 #define TG3_TSO5_FW_BSS_LEN             0x88
5131
5132 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5133         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5134         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5135         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5136         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5137         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5138         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5139         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5140         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5141         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5142         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5143         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5144         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5145         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5146         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5147         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5148         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5149         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5150         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5151         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5152         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5153         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5154         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5155         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5156         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5157         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5158         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5159         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5160         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5161         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5162         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5163         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5164         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5165         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5166         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5167         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5168         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5169         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5170         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5171         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5172         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5173         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5174         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5175         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5176         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5177         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5178         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5179         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5180         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5181         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5182         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5183         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5184         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5185         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5186         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5187         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5188         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5189         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5190         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5191         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5192         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5193         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5194         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5195         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5196         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5197         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5198         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5199         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5200         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5201         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5202         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5203         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5204         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5205         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5206         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5207         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5208         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5209         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5210         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5211         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5212         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5213         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5214         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5215         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5216         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5217         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5218         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5219         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5220         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5221         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5222         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5223         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5224         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5225         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5226         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5227         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5228         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5229         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5230         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5231         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5232         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5233         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5234         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5235         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5236         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5237         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5238         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5239         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5240         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5241         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5242         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5243         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5244         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5245         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5246         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5247         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5248         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5249         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5250         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5251         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5252         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5253         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5254         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5255         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5256         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5257         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5258         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5259         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5260         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5261         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5262         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5263         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5264         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5265         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5266         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5267         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5268         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5269         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5270         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5271         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5272         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5273         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5274         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5275         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5276         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5277         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5278         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5279         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5280         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5281         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5282         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5283         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5284         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5285         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5286         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5287         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5288         0x00000000, 0x00000000, 0x00000000,
5289 };
5290
5291 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5292         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5293         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5294         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5295         0x00000000, 0x00000000, 0x00000000,
5296 };
5297
5298 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5299         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5300         0x00000000, 0x00000000, 0x00000000,
5301 };
5302
5303 /* tp->lock is held. */
5304 static int tg3_load_tso_firmware(struct tg3 *tp)
5305 {
5306         struct fw_info info;
5307         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5308         int err, i;
5309
5310         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5311                 return 0;
5312
5313         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5314                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5315                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5316                 info.text_data = &tg3Tso5FwText[0];
5317                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5318                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5319                 info.rodata_data = &tg3Tso5FwRodata[0];
5320                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5321                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5322                 info.data_data = &tg3Tso5FwData[0];
5323                 cpu_base = RX_CPU_BASE;
5324                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5325                 cpu_scratch_size = (info.text_len +
5326                                     info.rodata_len +
5327                                     info.data_len +
5328                                     TG3_TSO5_FW_SBSS_LEN +
5329                                     TG3_TSO5_FW_BSS_LEN);
5330         } else {
5331                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5332                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5333                 info.text_data = &tg3TsoFwText[0];
5334                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5335                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5336                 info.rodata_data = &tg3TsoFwRodata[0];
5337                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5338                 info.data_len = TG3_TSO_FW_DATA_LEN;
5339                 info.data_data = &tg3TsoFwData[0];
5340                 cpu_base = TX_CPU_BASE;
5341                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5342                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5343         }
5344
5345         err = tg3_load_firmware_cpu(tp, cpu_base,
5346                                     cpu_scratch_base, cpu_scratch_size,
5347                                     &info);
5348         if (err)
5349                 return err;
5350
5351         /* Now startup the cpu. */
5352         tw32(cpu_base + CPU_STATE, 0xffffffff);
5353         tw32_f(cpu_base + CPU_PC,    info.text_base);
5354
5355         for (i = 0; i < 5; i++) {
5356                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5357                         break;
5358                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5359                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5360                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5361                 udelay(1000);
5362         }
5363         if (i >= 5) {
5364                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5365                        "to set CPU PC, is %08x should be %08x\n",
5366                        tp->dev->name, tr32(cpu_base + CPU_PC),
5367                        info.text_base);
5368                 return -ENODEV;
5369         }
5370         tw32(cpu_base + CPU_STATE, 0xffffffff);
5371         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5372         return 0;
5373 }
5374
5375 #endif /* TG3_TSO_SUPPORT != 0 */
5376
5377 /* tp->lock is held. */
5378 static void __tg3_set_mac_addr(struct tg3 *tp)
5379 {
5380         u32 addr_high, addr_low;
5381         int i;
5382
5383         addr_high = ((tp->dev->dev_addr[0] << 8) |
5384                      tp->dev->dev_addr[1]);
5385         addr_low = ((tp->dev->dev_addr[2] << 24) |
5386                     (tp->dev->dev_addr[3] << 16) |
5387                     (tp->dev->dev_addr[4] <<  8) |
5388                     (tp->dev->dev_addr[5] <<  0));
5389         for (i = 0; i < 4; i++) {
5390                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5391                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5392         }
5393
5394         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5395             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5396                 for (i = 0; i < 12; i++) {
5397                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5398                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5399                 }
5400         }
5401
5402         addr_high = (tp->dev->dev_addr[0] +
5403                      tp->dev->dev_addr[1] +
5404                      tp->dev->dev_addr[2] +
5405                      tp->dev->dev_addr[3] +
5406                      tp->dev->dev_addr[4] +
5407                      tp->dev->dev_addr[5]) &
5408                 TX_BACKOFF_SEED_MASK;
5409         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5410 }
5411
5412 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5413 {
5414         struct tg3 *tp = netdev_priv(dev);
5415         struct sockaddr *addr = p;
5416
5417         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5418
5419         spin_lock_bh(&tp->lock);
5420         __tg3_set_mac_addr(tp);
5421         spin_unlock_bh(&tp->lock);
5422
5423         return 0;
5424 }
5425
5426 /* tp->lock is held. */
5427 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5428                            dma_addr_t mapping, u32 maxlen_flags,
5429                            u32 nic_addr)
5430 {
5431         tg3_write_mem(tp,
5432                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5433                       ((u64) mapping >> 32));
5434         tg3_write_mem(tp,
5435                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5436                       ((u64) mapping & 0xffffffff));
5437         tg3_write_mem(tp,
5438                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5439                        maxlen_flags);
5440
5441         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5442                 tg3_write_mem(tp,
5443                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5444                               nic_addr);
5445 }
5446
5447 static void __tg3_set_rx_mode(struct net_device *);
5448 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5449 {
5450         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5451         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5452         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5453         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5454         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5455                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5456                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5457         }
5458         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5459         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5460         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5461                 u32 val = ec->stats_block_coalesce_usecs;
5462
5463                 if (!netif_carrier_ok(tp->dev))
5464                         val = 0;
5465
5466                 tw32(HOSTCC_STAT_COAL_TICKS, val);
5467         }
5468 }
5469
5470 /* tp->lock is held. */
5471 static int tg3_reset_hw(struct tg3 *tp)
5472 {
5473         u32 val, rdmac_mode;
5474         int i, err, limit;
5475
5476         tg3_disable_ints(tp);
5477
5478         tg3_stop_fw(tp);
5479
5480         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5481
5482         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5483                 tg3_abort_hw(tp, 1);
5484         }
5485
5486         err = tg3_chip_reset(tp);
5487         if (err)
5488                 return err;
5489
5490         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5491
5492         /* This works around an issue with Athlon chipsets on
5493          * B3 tigon3 silicon.  This bit has no effect on any
5494          * other revision.  But do not set this on PCI Express
5495          * chips.
5496          */
5497         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5498                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5499         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5500
5501         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5502             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5503                 val = tr32(TG3PCI_PCISTATE);
5504                 val |= PCISTATE_RETRY_SAME_DMA;
5505                 tw32(TG3PCI_PCISTATE, val);
5506         }
5507
5508         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5509                 /* Enable some hw fixes.  */
5510                 val = tr32(TG3PCI_MSI_DATA);
5511                 val |= (1 << 26) | (1 << 28) | (1 << 29);
5512                 tw32(TG3PCI_MSI_DATA, val);
5513         }
5514
5515         /* Descriptor ring init may make accesses to the
5516          * NIC SRAM area to setup the TX descriptors, so we
5517          * can only do this after the hardware has been
5518          * successfully reset.
5519          */
5520         tg3_init_rings(tp);
5521
5522         /* This value is determined during the probe time DMA
5523          * engine test, tg3_test_dma.
5524          */
5525         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5526
5527         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5528                           GRC_MODE_4X_NIC_SEND_RINGS |
5529                           GRC_MODE_NO_TX_PHDR_CSUM |
5530                           GRC_MODE_NO_RX_PHDR_CSUM);
5531         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5532         if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5533                 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5534         if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5535                 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5536
5537         tw32(GRC_MODE,
5538              tp->grc_mode |
5539              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5540
5541         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
5542         val = tr32(GRC_MISC_CFG);
5543         val &= ~0xff;
5544         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5545         tw32(GRC_MISC_CFG, val);
5546
5547         /* Initialize MBUF/DESC pool. */
5548         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5549                 /* Do nothing.  */
5550         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5551                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5552                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5553                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5554                 else
5555                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5556                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5557                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5558         }
5559 #if TG3_TSO_SUPPORT != 0
5560         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5561                 int fw_len;
5562
5563                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5564                           TG3_TSO5_FW_RODATA_LEN +
5565                           TG3_TSO5_FW_DATA_LEN +
5566                           TG3_TSO5_FW_SBSS_LEN +
5567                           TG3_TSO5_FW_BSS_LEN);
5568                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5569                 tw32(BUFMGR_MB_POOL_ADDR,
5570                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5571                 tw32(BUFMGR_MB_POOL_SIZE,
5572                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5573         }
5574 #endif
5575
5576         if (tp->dev->mtu <= ETH_DATA_LEN) {
5577                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5578                      tp->bufmgr_config.mbuf_read_dma_low_water);
5579                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5580                      tp->bufmgr_config.mbuf_mac_rx_low_water);
5581                 tw32(BUFMGR_MB_HIGH_WATER,
5582                      tp->bufmgr_config.mbuf_high_water);
5583         } else {
5584                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5585                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5586                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5587                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5588                 tw32(BUFMGR_MB_HIGH_WATER,
5589                      tp->bufmgr_config.mbuf_high_water_jumbo);
5590         }
5591         tw32(BUFMGR_DMA_LOW_WATER,
5592              tp->bufmgr_config.dma_low_water);
5593         tw32(BUFMGR_DMA_HIGH_WATER,
5594              tp->bufmgr_config.dma_high_water);
5595
5596         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5597         for (i = 0; i < 2000; i++) {
5598                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5599                         break;
5600                 udelay(10);
5601         }
5602         if (i >= 2000) {
5603                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5604                        tp->dev->name);
5605                 return -ENODEV;
5606         }
5607
5608         /* Setup replenish threshold. */
5609         tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5610
5611         /* Initialize TG3_BDINFO's at:
5612          *  RCVDBDI_STD_BD:     standard eth size rx ring
5613          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
5614          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
5615          *
5616          * like so:
5617          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
5618          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
5619          *                              ring attribute flags
5620          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
5621          *
5622          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5623          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5624          *
5625          * The size of each ring is fixed in the firmware, but the location is
5626          * configurable.
5627          */
5628         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5629              ((u64) tp->rx_std_mapping >> 32));
5630         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5631              ((u64) tp->rx_std_mapping & 0xffffffff));
5632         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5633              NIC_SRAM_RX_BUFFER_DESC);
5634
5635         /* Don't even try to program the JUMBO/MINI buffer descriptor
5636          * configs on 5705.
5637          */
5638         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5639                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5640                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5641         } else {
5642                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5643                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5644
5645                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5646                      BDINFO_FLAGS_DISABLED);
5647
5648                 /* Setup replenish threshold. */
5649                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5650
5651                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5652                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5653                              ((u64) tp->rx_jumbo_mapping >> 32));
5654                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5655                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5656                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5657                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5658                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5659                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5660                 } else {
5661                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5662                              BDINFO_FLAGS_DISABLED);
5663                 }
5664
5665         }
5666
5667         /* There is only one send ring on 5705/5750, no need to explicitly
5668          * disable the others.
5669          */
5670         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5671                 /* Clear out send RCB ring in SRAM. */
5672                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5673                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5674                                       BDINFO_FLAGS_DISABLED);
5675         }
5676
5677         tp->tx_prod = 0;
5678         tp->tx_cons = 0;
5679         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5680         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5681
5682         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5683                        tp->tx_desc_mapping,
5684                        (TG3_TX_RING_SIZE <<
5685                         BDINFO_FLAGS_MAXLEN_SHIFT),
5686                        NIC_SRAM_TX_BUFFER_DESC);
5687
5688         /* There is only one receive return ring on 5705/5750, no need
5689          * to explicitly disable the others.
5690          */
5691         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5692                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5693                      i += TG3_BDINFO_SIZE) {
5694                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5695                                       BDINFO_FLAGS_DISABLED);
5696                 }
5697         }
5698
5699         tp->rx_rcb_ptr = 0;
5700         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5701
5702         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5703                        tp->rx_rcb_mapping,
5704                        (TG3_RX_RCB_RING_SIZE(tp) <<
5705                         BDINFO_FLAGS_MAXLEN_SHIFT),
5706                        0);
5707
5708         tp->rx_std_ptr = tp->rx_pending;
5709         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5710                      tp->rx_std_ptr);
5711
5712         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
5713                                                 tp->rx_jumbo_pending : 0;
5714         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5715                      tp->rx_jumbo_ptr);
5716
5717         /* Initialize MAC address and backoff seed. */
5718         __tg3_set_mac_addr(tp);
5719
5720         /* MTU + ethernet header + FCS + optional VLAN tag */
5721         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5722
5723         /* The slot time is changed by tg3_setup_phy if we
5724          * run at gigabit with half duplex.
5725          */
5726         tw32(MAC_TX_LENGTHS,
5727              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5728              (6 << TX_LENGTHS_IPG_SHIFT) |
5729              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5730
5731         /* Receive rules. */
5732         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5733         tw32(RCVLPC_CONFIG, 0x0181);
5734
5735         /* Calculate RDMAC_MODE setting early, we need it to determine
5736          * the RCVLPC_STATE_ENABLE mask.
5737          */
5738         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5739                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5740                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5741                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5742                       RDMAC_MODE_LNGREAD_ENAB);
5743         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5744                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
5745
5746         /* If statement applies to 5705 and 5750 PCI devices only */
5747         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5748              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5749             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
5750                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5751                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5752                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5753                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5754                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5755                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5756                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5757                 }
5758         }
5759
5760         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5761                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5762
5763 #if TG3_TSO_SUPPORT != 0
5764         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5765                 rdmac_mode |= (1 << 27);
5766 #endif
5767
5768         /* Receive/send statistics. */
5769         if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5770             (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5771                 val = tr32(RCVLPC_STATS_ENABLE);
5772                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5773                 tw32(RCVLPC_STATS_ENABLE, val);
5774         } else {
5775                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5776         }
5777         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5778         tw32(SNDDATAI_STATSENAB, 0xffffff);
5779         tw32(SNDDATAI_STATSCTRL,
5780              (SNDDATAI_SCTRL_ENABLE |
5781               SNDDATAI_SCTRL_FASTUPD));
5782
5783         /* Setup host coalescing engine. */
5784         tw32(HOSTCC_MODE, 0);
5785         for (i = 0; i < 2000; i++) {
5786                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5787                         break;
5788                 udelay(10);
5789         }
5790
5791         __tg3_set_coalesce(tp, &tp->coal);
5792
5793         /* set status block DMA address */
5794         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5795              ((u64) tp->status_mapping >> 32));
5796         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5797              ((u64) tp->status_mapping & 0xffffffff));
5798
5799         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5800                 /* Status/statistics block address.  See tg3_timer,
5801                  * the tg3_periodic_fetch_stats call there, and
5802                  * tg3_get_stats to see how this works for 5705/5750 chips.
5803                  */
5804                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5805                      ((u64) tp->stats_mapping >> 32));
5806                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5807                      ((u64) tp->stats_mapping & 0xffffffff));
5808                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5809                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5810         }
5811
5812         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5813
5814         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5815         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5816         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5817                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5818
5819         /* Clear statistics/status block in chip, and status block in ram. */
5820         for (i = NIC_SRAM_STATS_BLK;
5821              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5822              i += sizeof(u32)) {
5823                 tg3_write_mem(tp, i, 0);
5824                 udelay(40);
5825         }
5826         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5827
5828         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5829                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5830         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5831         udelay(40);
5832
5833         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5834          * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5835          * register to preserve the GPIO settings for LOMs. The GPIOs,
5836          * whether used as inputs or outputs, are set by boot code after
5837          * reset.
5838          */
5839         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5840                 u32 gpio_mask;
5841
5842                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5843                             GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
5844
5845                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5846                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5847                                      GRC_LCLCTRL_GPIO_OUTPUT3;
5848
5849                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5850
5851                 /* GPIO1 must be driven high for eeprom write protect */
5852                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5853                                        GRC_LCLCTRL_GPIO_OUTPUT1);
5854         }
5855         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5856         udelay(100);
5857
5858         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5859         tp->last_tag = 0;
5860
5861         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5862                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5863                 udelay(40);
5864         }
5865
5866         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5867                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5868                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5869                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5870                WDMAC_MODE_LNGREAD_ENAB);
5871
5872         /* If statement applies to 5705 and 5750 PCI devices only */
5873         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5874              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5875             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
5876                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5877                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5878                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5879                         /* nothing */
5880                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5881                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5882                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5883                         val |= WDMAC_MODE_RX_ACCEL;
5884                 }
5885         }
5886
5887         tw32_f(WDMAC_MODE, val);
5888         udelay(40);
5889
5890         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5891                 val = tr32(TG3PCI_X_CAPS);
5892                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5893                         val &= ~PCIX_CAPS_BURST_MASK;
5894                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5895                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5896                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5897                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5898                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5899                                 val |= (tp->split_mode_max_reqs <<
5900                                         PCIX_CAPS_SPLIT_SHIFT);
5901                 }
5902                 tw32(TG3PCI_X_CAPS, val);
5903         }
5904
5905         tw32_f(RDMAC_MODE, rdmac_mode);
5906         udelay(40);
5907
5908         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5909         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5910                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5911         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5912         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5913         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5914         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5915         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5916 #if TG3_TSO_SUPPORT != 0
5917         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5918                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5919 #endif
5920         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5921         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5922
5923         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5924                 err = tg3_load_5701_a0_firmware_fix(tp);
5925                 if (err)
5926                         return err;
5927         }
5928
5929 #if TG3_TSO_SUPPORT != 0
5930         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5931                 err = tg3_load_tso_firmware(tp);
5932                 if (err)
5933                         return err;
5934         }
5935 #endif
5936
5937         tp->tx_mode = TX_MODE_ENABLE;
5938         tw32_f(MAC_TX_MODE, tp->tx_mode);
5939         udelay(100);
5940
5941         tp->rx_mode = RX_MODE_ENABLE;
5942         tw32_f(MAC_RX_MODE, tp->rx_mode);
5943         udelay(10);
5944
5945         if (tp->link_config.phy_is_low_power) {
5946                 tp->link_config.phy_is_low_power = 0;
5947                 tp->link_config.speed = tp->link_config.orig_speed;
5948                 tp->link_config.duplex = tp->link_config.orig_duplex;
5949                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5950         }
5951
5952         tp->mi_mode = MAC_MI_MODE_BASE;
5953         tw32_f(MAC_MI_MODE, tp->mi_mode);
5954         udelay(80);
5955
5956         tw32(MAC_LED_CTRL, tp->led_ctrl);
5957
5958         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5959         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
5960                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5961                 udelay(10);
5962         }
5963         tw32_f(MAC_RX_MODE, tp->rx_mode);
5964         udelay(10);
5965
5966         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5967                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5968                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5969                         /* Set drive transmission level to 1.2V  */
5970                         /* only if the signal pre-emphasis bit is not set  */
5971                         val = tr32(MAC_SERDES_CFG);
5972                         val &= 0xfffff000;
5973                         val |= 0x880;
5974                         tw32(MAC_SERDES_CFG, val);
5975                 }
5976                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5977                         tw32(MAC_SERDES_CFG, 0x616000);
5978         }
5979
5980         /* Prevent chip from dropping frames when flow control
5981          * is enabled.
5982          */
5983         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5984
5985         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5986             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5987                 /* Use hardware link auto-negotiation */
5988                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5989         }
5990
5991         err = tg3_setup_phy(tp, 1);
5992         if (err)
5993                 return err;
5994
5995         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5996                 u32 tmp;
5997
5998                 /* Clear CRC stats. */
5999                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6000                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
6001                         tg3_readphy(tp, 0x14, &tmp);
6002                 }
6003         }
6004
6005         __tg3_set_rx_mode(tp->dev);
6006
6007         /* Initialize receive rules. */
6008         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6009         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6010         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6011         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6012
6013         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6014             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780))
6015                 limit = 8;
6016         else
6017                 limit = 16;
6018         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6019                 limit -= 4;
6020         switch (limit) {
6021         case 16:
6022                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6023         case 15:
6024                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6025         case 14:
6026                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6027         case 13:
6028                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6029         case 12:
6030                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6031         case 11:
6032                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6033         case 10:
6034                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6035         case 9:
6036                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6037         case 8:
6038                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6039         case 7:
6040                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6041         case 6:
6042                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6043         case 5:
6044                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6045         case 4:
6046                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6047         case 3:
6048                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6049         case 2:
6050         case 1:
6051
6052         default:
6053                 break;
6054         };
6055
6056         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6057
6058         return 0;
6059 }
6060
6061 /* Called at device open time to get the chip ready for
6062  * packet processing.  Invoked with tp->lock held.
6063  */
6064 static int tg3_init_hw(struct tg3 *tp)
6065 {
6066         int err;
6067
6068         /* Force the chip into D0. */
6069         err = tg3_set_power_state(tp, 0);
6070         if (err)
6071                 goto out;
6072
6073         tg3_switch_clocks(tp);
6074
6075         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6076
6077         err = tg3_reset_hw(tp);
6078
6079 out:
6080         return err;
6081 }
6082
6083 #define TG3_STAT_ADD32(PSTAT, REG) \
6084 do {    u32 __val = tr32(REG); \
6085         (PSTAT)->low += __val; \
6086         if ((PSTAT)->low < __val) \
6087                 (PSTAT)->high += 1; \
6088 } while (0)
6089
6090 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6091 {
6092         struct tg3_hw_stats *sp = tp->hw_stats;
6093
6094         if (!netif_carrier_ok(tp->dev))
6095                 return;
6096
6097         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6098         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6099         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6100         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6101         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6102         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6103         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6104         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6105         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6106         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6107         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6108         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6109         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6110
6111         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6112         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6113         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6114         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6115         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6116         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6117         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6118         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6119         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6120         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6121         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6122         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6123         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6124         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6125 }
6126
6127 static void tg3_timer(unsigned long __opaque)
6128 {
6129         struct tg3 *tp = (struct tg3 *) __opaque;
6130
6131         spin_lock(&tp->lock);
6132
6133         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6134                 /* All of this garbage is because when using non-tagged
6135                  * IRQ status the mailbox/status_block protocol the chip
6136                  * uses with the cpu is race prone.
6137                  */
6138                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6139                         tw32(GRC_LOCAL_CTRL,
6140                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6141                 } else {
6142                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6143                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6144                 }
6145
6146                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6147                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6148                         spin_unlock(&tp->lock);
6149                         schedule_work(&tp->reset_task);
6150                         return;
6151                 }
6152         }
6153
6154         /* This part only runs once per second. */
6155         if (!--tp->timer_counter) {
6156                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6157                         tg3_periodic_fetch_stats(tp);
6158
6159                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6160                         u32 mac_stat;
6161                         int phy_event;
6162
6163                         mac_stat = tr32(MAC_STATUS);
6164
6165                         phy_event = 0;
6166                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6167                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6168                                         phy_event = 1;
6169                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6170                                 phy_event = 1;
6171
6172                         if (phy_event)
6173                                 tg3_setup_phy(tp, 0);
6174                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6175                         u32 mac_stat = tr32(MAC_STATUS);
6176                         int need_setup = 0;
6177
6178                         if (netif_carrier_ok(tp->dev) &&
6179                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6180                                 need_setup = 1;
6181                         }
6182                         if (! netif_carrier_ok(tp->dev) &&
6183                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6184                                          MAC_STATUS_SIGNAL_DET))) {
6185                                 need_setup = 1;
6186                         }
6187                         if (need_setup) {
6188                                 tw32_f(MAC_MODE,
6189                                      (tp->mac_mode &
6190                                       ~MAC_MODE_PORT_MODE_MASK));
6191                                 udelay(40);
6192                                 tw32_f(MAC_MODE, tp->mac_mode);
6193                                 udelay(40);
6194                                 tg3_setup_phy(tp, 0);
6195                         }
6196                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6197                         tg3_serdes_parallel_detect(tp);
6198
6199                 tp->timer_counter = tp->timer_multiplier;
6200         }
6201
6202         /* Heartbeat is only sent once every 120 seconds.  */
6203         if (!--tp->asf_counter) {
6204                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6205                         u32 val;
6206
6207                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
6208                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6209                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
6210                         val = tr32(GRC_RX_CPU_EVENT);
6211                         val |= (1 << 14);
6212                         tw32(GRC_RX_CPU_EVENT, val);
6213                 }
6214                 tp->asf_counter = tp->asf_multiplier;
6215         }
6216
6217         spin_unlock(&tp->lock);
6218
6219         tp->timer.expires = jiffies + tp->timer_offset;
6220         add_timer(&tp->timer);
6221 }
6222
6223 static int tg3_test_interrupt(struct tg3 *tp)
6224 {
6225         struct net_device *dev = tp->dev;
6226         int err, i;
6227         u32 int_mbox = 0;
6228
6229         if (!netif_running(dev))
6230                 return -ENODEV;
6231
6232         tg3_disable_ints(tp);
6233
6234         free_irq(tp->pdev->irq, dev);
6235
6236         err = request_irq(tp->pdev->irq, tg3_test_isr,
6237                           SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6238         if (err)
6239                 return err;
6240
6241         tg3_enable_ints(tp);
6242
6243         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6244                HOSTCC_MODE_NOW);
6245
6246         for (i = 0; i < 5; i++) {
6247                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6248                                         TG3_64BIT_REG_LOW);
6249                 if (int_mbox != 0)
6250                         break;
6251                 msleep(10);
6252         }
6253
6254         tg3_disable_ints(tp);
6255
6256         free_irq(tp->pdev->irq, dev);
6257
6258         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6259                 err = request_irq(tp->pdev->irq, tg3_msi,
6260                                   SA_SAMPLE_RANDOM, dev->name, dev);
6261         else {
6262                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6263                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6264                         fn = tg3_interrupt_tagged;
6265                 err = request_irq(tp->pdev->irq, fn,
6266                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6267         }
6268
6269         if (err)
6270                 return err;
6271
6272         if (int_mbox != 0)
6273                 return 0;
6274
6275         return -EIO;
6276 }
6277
6278 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6279  * successfully restored
6280  */
6281 static int tg3_test_msi(struct tg3 *tp)
6282 {
6283         struct net_device *dev = tp->dev;
6284         int err;
6285         u16 pci_cmd;
6286
6287         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6288                 return 0;
6289
6290         /* Turn off SERR reporting in case MSI terminates with Master
6291          * Abort.
6292          */
6293         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6294         pci_write_config_word(tp->pdev, PCI_COMMAND,
6295                               pci_cmd & ~PCI_COMMAND_SERR);
6296
6297         err = tg3_test_interrupt(tp);
6298
6299         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6300
6301         if (!err)
6302                 return 0;
6303
6304         /* other failures */
6305         if (err != -EIO)
6306                 return err;
6307
6308         /* MSI test failed, go back to INTx mode */
6309         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6310                "switching to INTx mode. Please report this failure to "
6311                "the PCI maintainer and include system chipset information.\n",
6312                        tp->dev->name);
6313
6314         free_irq(tp->pdev->irq, dev);
6315         pci_disable_msi(tp->pdev);
6316
6317         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6318
6319         {
6320                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6321                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6322                         fn = tg3_interrupt_tagged;
6323
6324                 err = request_irq(tp->pdev->irq, fn,
6325                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6326         }
6327         if (err)
6328                 return err;
6329
6330         /* Need to reset the chip because the MSI cycle may have terminated
6331          * with Master Abort.
6332          */
6333         tg3_full_lock(tp, 1);
6334
6335         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6336         err = tg3_init_hw(tp);
6337
6338         tg3_full_unlock(tp);
6339
6340         if (err)
6341                 free_irq(tp->pdev->irq, dev);
6342
6343         return err;
6344 }
6345
6346 static int tg3_open(struct net_device *dev)
6347 {
6348         struct tg3 *tp = netdev_priv(dev);
6349         int err;
6350
6351         tg3_full_lock(tp, 0);
6352
6353         tg3_disable_ints(tp);
6354         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6355
6356         tg3_full_unlock(tp);
6357
6358         /* The placement of this call is tied
6359          * to the setup and use of Host TX descriptors.
6360          */
6361         err = tg3_alloc_consistent(tp);
6362         if (err)
6363                 return err;
6364
6365         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6366             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6367             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
6368                 /* All MSI supporting chips should support tagged
6369                  * status.  Assert that this is the case.
6370                  */
6371                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6372                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6373                                "Not using MSI.\n", tp->dev->name);
6374                 } else if (pci_enable_msi(tp->pdev) == 0) {
6375                         u32 msi_mode;
6376
6377                         msi_mode = tr32(MSGINT_MODE);
6378                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6379                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6380                 }
6381         }
6382         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6383                 err = request_irq(tp->pdev->irq, tg3_msi,
6384                                   SA_SAMPLE_RANDOM, dev->name, dev);
6385         else {
6386                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6387                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6388                         fn = tg3_interrupt_tagged;
6389
6390                 err = request_irq(tp->pdev->irq, fn,
6391                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6392         }
6393
6394         if (err) {
6395                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6396                         pci_disable_msi(tp->pdev);
6397                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6398                 }
6399                 tg3_free_consistent(tp);
6400                 return err;
6401         }
6402
6403         tg3_full_lock(tp, 0);
6404
6405         err = tg3_init_hw(tp);
6406         if (err) {
6407                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6408                 tg3_free_rings(tp);
6409         } else {
6410                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6411                         tp->timer_offset = HZ;
6412                 else
6413                         tp->timer_offset = HZ / 10;
6414
6415                 BUG_ON(tp->timer_offset > HZ);
6416                 tp->timer_counter = tp->timer_multiplier =
6417                         (HZ / tp->timer_offset);
6418                 tp->asf_counter = tp->asf_multiplier =
6419                         ((HZ / tp->timer_offset) * 120);
6420
6421                 init_timer(&tp->timer);
6422                 tp->timer.expires = jiffies + tp->timer_offset;
6423                 tp->timer.data = (unsigned long) tp;
6424                 tp->timer.function = tg3_timer;
6425         }
6426
6427         tg3_full_unlock(tp);
6428
6429         if (err) {
6430                 free_irq(tp->pdev->irq, dev);
6431                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6432                         pci_disable_msi(tp->pdev);
6433                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6434                 }
6435                 tg3_free_consistent(tp);
6436                 return err;
6437         }
6438
6439         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6440                 err = tg3_test_msi(tp);
6441
6442                 if (err) {
6443                         tg3_full_lock(tp, 0);
6444
6445                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6446                                 pci_disable_msi(tp->pdev);
6447                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6448                         }
6449                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6450                         tg3_free_rings(tp);
6451                         tg3_free_consistent(tp);
6452
6453                         tg3_full_unlock(tp);
6454
6455                         return err;
6456                 }
6457         }
6458
6459         tg3_full_lock(tp, 0);
6460
6461         add_timer(&tp->timer);
6462         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6463         tg3_enable_ints(tp);
6464
6465         tg3_full_unlock(tp);
6466
6467         netif_start_queue(dev);
6468
6469         return 0;
6470 }
6471
6472 #if 0
6473 /*static*/ void tg3_dump_state(struct tg3 *tp)
6474 {
6475         u32 val32, val32_2, val32_3, val32_4, val32_5;
6476         u16 val16;
6477         int i;
6478
6479         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6480         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6481         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6482                val16, val32);
6483
6484         /* MAC block */
6485         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6486                tr32(MAC_MODE), tr32(MAC_STATUS));
6487         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6488                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6489         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6490                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6491         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6492                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6493
6494         /* Send data initiator control block */
6495         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6496                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6497         printk("       SNDDATAI_STATSCTRL[%08x]\n",
6498                tr32(SNDDATAI_STATSCTRL));
6499
6500         /* Send data completion control block */
6501         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6502
6503         /* Send BD ring selector block */
6504         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6505                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6506
6507         /* Send BD initiator control block */
6508         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6509                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6510
6511         /* Send BD completion control block */
6512         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6513
6514         /* Receive list placement control block */
6515         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6516                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6517         printk("       RCVLPC_STATSCTRL[%08x]\n",
6518                tr32(RCVLPC_STATSCTRL));
6519
6520         /* Receive data and receive BD initiator control block */
6521         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6522                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6523
6524         /* Receive data completion control block */
6525         printk("DEBUG: RCVDCC_MODE[%08x]\n",
6526                tr32(RCVDCC_MODE));
6527
6528         /* Receive BD initiator control block */
6529         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6530                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6531
6532         /* Receive BD completion control block */
6533         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6534                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6535
6536         /* Receive list selector control block */
6537         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6538                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6539
6540         /* Mbuf cluster free block */
6541         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6542                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6543
6544         /* Host coalescing control block */
6545         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6546                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6547         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6548                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6549                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6550         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6551                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6552                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6553         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6554                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6555         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6556                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6557
6558         /* Memory arbiter control block */
6559         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6560                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6561
6562         /* Buffer manager control block */
6563         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6564                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6565         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6566                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6567         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6568                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6569                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6570                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6571
6572         /* Read DMA control block */
6573         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6574                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6575
6576         /* Write DMA control block */
6577         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6578                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6579
6580         /* DMA completion block */
6581         printk("DEBUG: DMAC_MODE[%08x]\n",
6582                tr32(DMAC_MODE));
6583
6584         /* GRC block */
6585         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6586                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6587         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6588                tr32(GRC_LOCAL_CTRL));
6589
6590         /* TG3_BDINFOs */
6591         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6592                tr32(RCVDBDI_JUMBO_BD + 0x0),
6593                tr32(RCVDBDI_JUMBO_BD + 0x4),
6594                tr32(RCVDBDI_JUMBO_BD + 0x8),
6595                tr32(RCVDBDI_JUMBO_BD + 0xc));
6596         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6597                tr32(RCVDBDI_STD_BD + 0x0),
6598                tr32(RCVDBDI_STD_BD + 0x4),
6599                tr32(RCVDBDI_STD_BD + 0x8),
6600                tr32(RCVDBDI_STD_BD + 0xc));
6601         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6602                tr32(RCVDBDI_MINI_BD + 0x0),
6603                tr32(RCVDBDI_MINI_BD + 0x4),
6604                tr32(RCVDBDI_MINI_BD + 0x8),
6605                tr32(RCVDBDI_MINI_BD + 0xc));
6606
6607         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6608         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6609         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6610         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6611         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6612                val32, val32_2, val32_3, val32_4);
6613
6614         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6615         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6616         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6617         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6618         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6619                val32, val32_2, val32_3, val32_4);
6620
6621         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6622         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6623         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6624         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6625         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6626         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6627                val32, val32_2, val32_3, val32_4, val32_5);
6628
6629         /* SW status block */
6630         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6631                tp->hw_status->status,
6632                tp->hw_status->status_tag,
6633                tp->hw_status->rx_jumbo_consumer,
6634                tp->hw_status->rx_consumer,
6635                tp->hw_status->rx_mini_consumer,
6636                tp->hw_status->idx[0].rx_producer,
6637                tp->hw_status->idx[0].tx_consumer);
6638
6639         /* SW statistics block */
6640         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6641                ((u32 *)tp->hw_stats)[0],
6642                ((u32 *)tp->hw_stats)[1],
6643                ((u32 *)tp->hw_stats)[2],
6644                ((u32 *)tp->hw_stats)[3]);
6645
6646         /* Mailboxes */
6647         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6648                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6649                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6650                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6651                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6652
6653         /* NIC side send descriptors. */
6654         for (i = 0; i < 6; i++) {
6655                 unsigned long txd;
6656
6657                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6658                         + (i * sizeof(struct tg3_tx_buffer_desc));
6659                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6660                        i,
6661                        readl(txd + 0x0), readl(txd + 0x4),
6662                        readl(txd + 0x8), readl(txd + 0xc));
6663         }
6664
6665         /* NIC side RX descriptors. */
6666         for (i = 0; i < 6; i++) {
6667                 unsigned long rxd;
6668
6669                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6670                         + (i * sizeof(struct tg3_rx_buffer_desc));
6671                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6672                        i,
6673                        readl(rxd + 0x0), readl(rxd + 0x4),
6674                        readl(rxd + 0x8), readl(rxd + 0xc));
6675                 rxd += (4 * sizeof(u32));
6676                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6677                        i,
6678                        readl(rxd + 0x0), readl(rxd + 0x4),
6679                        readl(rxd + 0x8), readl(rxd + 0xc));
6680         }
6681
6682         for (i = 0; i < 6; i++) {
6683                 unsigned long rxd;
6684
6685                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6686                         + (i * sizeof(struct tg3_rx_buffer_desc));
6687                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6688                        i,
6689                        readl(rxd + 0x0), readl(rxd + 0x4),
6690                        readl(rxd + 0x8), readl(rxd + 0xc));
6691                 rxd += (4 * sizeof(u32));
6692                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6693                        i,
6694                        readl(rxd + 0x0), readl(rxd + 0x4),
6695                        readl(rxd + 0x8), readl(rxd + 0xc));
6696         }
6697 }
6698 #endif
6699
6700 static struct net_device_stats *tg3_get_stats(struct net_device *);
6701 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6702
6703 static int tg3_close(struct net_device *dev)
6704 {
6705         struct tg3 *tp = netdev_priv(dev);
6706
6707         netif_stop_queue(dev);
6708
6709         del_timer_sync(&tp->timer);
6710
6711         tg3_full_lock(tp, 1);
6712 #if 0
6713         tg3_dump_state(tp);
6714 #endif
6715
6716         tg3_disable_ints(tp);
6717
6718         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6719         tg3_free_rings(tp);
6720         tp->tg3_flags &=
6721                 ~(TG3_FLAG_INIT_COMPLETE |
6722                   TG3_FLAG_GOT_SERDES_FLOWCTL);
6723         netif_carrier_off(tp->dev);
6724
6725         tg3_full_unlock(tp);
6726
6727         free_irq(tp->pdev->irq, dev);
6728         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6729                 pci_disable_msi(tp->pdev);
6730                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6731         }
6732
6733         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6734                sizeof(tp->net_stats_prev));
6735         memcpy(&tp->estats_prev, tg3_get_estats(tp),
6736                sizeof(tp->estats_prev));
6737
6738         tg3_free_consistent(tp);
6739
6740         return 0;
6741 }
6742
6743 static inline unsigned long get_stat64(tg3_stat64_t *val)
6744 {
6745         unsigned long ret;
6746
6747 #if (BITS_PER_LONG == 32)
6748         ret = val->low;
6749 #else
6750         ret = ((u64)val->high << 32) | ((u64)val->low);
6751 #endif
6752         return ret;
6753 }
6754
6755 static unsigned long calc_crc_errors(struct tg3 *tp)
6756 {
6757         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6758
6759         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6760             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6761              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6762                 u32 val;
6763
6764                 spin_lock_bh(&tp->lock);
6765                 if (!tg3_readphy(tp, 0x1e, &val)) {
6766                         tg3_writephy(tp, 0x1e, val | 0x8000);
6767                         tg3_readphy(tp, 0x14, &val);
6768                 } else
6769                         val = 0;
6770                 spin_unlock_bh(&tp->lock);
6771
6772                 tp->phy_crc_errors += val;
6773
6774                 return tp->phy_crc_errors;
6775         }
6776
6777         return get_stat64(&hw_stats->rx_fcs_errors);
6778 }
6779
6780 #define ESTAT_ADD(member) \
6781         estats->member =        old_estats->member + \
6782                                 get_stat64(&hw_stats->member)
6783
6784 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6785 {
6786         struct tg3_ethtool_stats *estats = &tp->estats;
6787         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6788         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6789
6790         if (!hw_stats)
6791                 return old_estats;
6792
6793         ESTAT_ADD(rx_octets);
6794         ESTAT_ADD(rx_fragments);
6795         ESTAT_ADD(rx_ucast_packets);
6796         ESTAT_ADD(rx_mcast_packets);
6797         ESTAT_ADD(rx_bcast_packets);
6798         ESTAT_ADD(rx_fcs_errors);
6799         ESTAT_ADD(rx_align_errors);
6800         ESTAT_ADD(rx_xon_pause_rcvd);
6801         ESTAT_ADD(rx_xoff_pause_rcvd);
6802         ESTAT_ADD(rx_mac_ctrl_rcvd);
6803         ESTAT_ADD(rx_xoff_entered);
6804         ESTAT_ADD(rx_frame_too_long_errors);
6805         ESTAT_ADD(rx_jabbers);
6806         ESTAT_ADD(rx_undersize_packets);
6807         ESTAT_ADD(rx_in_length_errors);
6808         ESTAT_ADD(rx_out_length_errors);
6809         ESTAT_ADD(rx_64_or_less_octet_packets);
6810         ESTAT_ADD(rx_65_to_127_octet_packets);
6811         ESTAT_ADD(rx_128_to_255_octet_packets);
6812         ESTAT_ADD(rx_256_to_511_octet_packets);
6813         ESTAT_ADD(rx_512_to_1023_octet_packets);
6814         ESTAT_ADD(rx_1024_to_1522_octet_packets);
6815         ESTAT_ADD(rx_1523_to_2047_octet_packets);
6816         ESTAT_ADD(rx_2048_to_4095_octet_packets);
6817         ESTAT_ADD(rx_4096_to_8191_octet_packets);
6818         ESTAT_ADD(rx_8192_to_9022_octet_packets);
6819
6820         ESTAT_ADD(tx_octets);
6821         ESTAT_ADD(tx_collisions);
6822         ESTAT_ADD(tx_xon_sent);
6823         ESTAT_ADD(tx_xoff_sent);
6824         ESTAT_ADD(tx_flow_control);
6825         ESTAT_ADD(tx_mac_errors);
6826         ESTAT_ADD(tx_single_collisions);
6827         ESTAT_ADD(tx_mult_collisions);
6828         ESTAT_ADD(tx_deferred);
6829         ESTAT_ADD(tx_excessive_collisions);
6830         ESTAT_ADD(tx_late_collisions);
6831         ESTAT_ADD(tx_collide_2times);
6832         ESTAT_ADD(tx_collide_3times);
6833         ESTAT_ADD(tx_collide_4times);
6834         ESTAT_ADD(tx_collide_5times);
6835         ESTAT_ADD(tx_collide_6times);
6836         ESTAT_ADD(tx_collide_7times);
6837         ESTAT_ADD(tx_collide_8times);
6838         ESTAT_ADD(tx_collide_9times);
6839         ESTAT_ADD(tx_collide_10times);
6840         ESTAT_ADD(tx_collide_11times);
6841         ESTAT_ADD(tx_collide_12times);
6842         ESTAT_ADD(tx_collide_13times);
6843         ESTAT_ADD(tx_collide_14times);
6844         ESTAT_ADD(tx_collide_15times);
6845         ESTAT_ADD(tx_ucast_packets);
6846         ESTAT_ADD(tx_mcast_packets);
6847         ESTAT_ADD(tx_bcast_packets);
6848         ESTAT_ADD(tx_carrier_sense_errors);
6849         ESTAT_ADD(tx_discards);
6850         ESTAT_ADD(tx_errors);
6851
6852         ESTAT_ADD(dma_writeq_full);
6853         ESTAT_ADD(dma_write_prioq_full);
6854         ESTAT_ADD(rxbds_empty);
6855         ESTAT_ADD(rx_discards);
6856         ESTAT_ADD(rx_errors);
6857         ESTAT_ADD(rx_threshold_hit);
6858
6859         ESTAT_ADD(dma_readq_full);
6860         ESTAT_ADD(dma_read_prioq_full);
6861         ESTAT_ADD(tx_comp_queue_full);
6862
6863         ESTAT_ADD(ring_set_send_prod_index);
6864         ESTAT_ADD(ring_status_update);
6865         ESTAT_ADD(nic_irqs);
6866         ESTAT_ADD(nic_avoided_irqs);
6867         ESTAT_ADD(nic_tx_threshold_hit);
6868
6869         return estats;
6870 }
6871
6872 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6873 {
6874         struct tg3 *tp = netdev_priv(dev);
6875         struct net_device_stats *stats = &tp->net_stats;
6876         struct net_device_stats *old_stats = &tp->net_stats_prev;
6877         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6878
6879         if (!hw_stats)
6880                 return old_stats;
6881
6882         stats->rx_packets = old_stats->rx_packets +
6883                 get_stat64(&hw_stats->rx_ucast_packets) +
6884                 get_stat64(&hw_stats->rx_mcast_packets) +
6885                 get_stat64(&hw_stats->rx_bcast_packets);
6886
6887         stats->tx_packets = old_stats->tx_packets +
6888                 get_stat64(&hw_stats->tx_ucast_packets) +
6889                 get_stat64(&hw_stats->tx_mcast_packets) +
6890                 get_stat64(&hw_stats->tx_bcast_packets);
6891
6892         stats->rx_bytes = old_stats->rx_bytes +
6893                 get_stat64(&hw_stats->rx_octets);
6894         stats->tx_bytes = old_stats->tx_bytes +
6895                 get_stat64(&hw_stats->tx_octets);
6896
6897         stats->rx_errors = old_stats->rx_errors +
6898                 get_stat64(&hw_stats->rx_errors) +
6899                 get_stat64(&hw_stats->rx_discards);
6900         stats->tx_errors = old_stats->tx_errors +
6901                 get_stat64(&hw_stats->tx_errors) +
6902                 get_stat64(&hw_stats->tx_mac_errors) +
6903                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6904                 get_stat64(&hw_stats->tx_discards);
6905
6906         stats->multicast = old_stats->multicast +
6907                 get_stat64(&hw_stats->rx_mcast_packets);
6908         stats->collisions = old_stats->collisions +
6909                 get_stat64(&hw_stats->tx_collisions);
6910
6911         stats->rx_length_errors = old_stats->rx_length_errors +
6912                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6913                 get_stat64(&hw_stats->rx_undersize_packets);
6914
6915         stats->rx_over_errors = old_stats->rx_over_errors +
6916                 get_stat64(&hw_stats->rxbds_empty);
6917         stats->rx_frame_errors = old_stats->rx_frame_errors +
6918                 get_stat64(&hw_stats->rx_align_errors);
6919         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6920                 get_stat64(&hw_stats->tx_discards);
6921         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6922                 get_stat64(&hw_stats->tx_carrier_sense_errors);
6923
6924         stats->rx_crc_errors = old_stats->rx_crc_errors +
6925                 calc_crc_errors(tp);
6926
6927         return stats;
6928 }
6929
6930 static inline u32 calc_crc(unsigned char *buf, int len)
6931 {
6932         u32 reg;
6933         u32 tmp;
6934         int j, k;
6935
6936         reg = 0xffffffff;
6937
6938         for (j = 0; j < len; j++) {
6939                 reg ^= buf[j];
6940
6941                 for (k = 0; k < 8; k++) {
6942                         tmp = reg & 0x01;
6943
6944                         reg >>= 1;
6945
6946                         if (tmp) {
6947                                 reg ^= 0xedb88320;
6948                         }
6949                 }
6950         }
6951
6952         return ~reg;
6953 }
6954
6955 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6956 {
6957         /* accept or reject all multicast frames */
6958         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6959         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6960         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6961         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6962 }
6963
6964 static void __tg3_set_rx_mode(struct net_device *dev)
6965 {
6966         struct tg3 *tp = netdev_priv(dev);
6967         u32 rx_mode;
6968
6969         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6970                                   RX_MODE_KEEP_VLAN_TAG);
6971
6972         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6973          * flag clear.
6974          */
6975 #if TG3_VLAN_TAG_USED
6976         if (!tp->vlgrp &&
6977             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6978                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6979 #else
6980         /* By definition, VLAN is disabled always in this
6981          * case.
6982          */
6983         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6984                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6985 #endif
6986
6987         if (dev->flags & IFF_PROMISC) {
6988                 /* Promiscuous mode. */
6989                 rx_mode |= RX_MODE_PROMISC;
6990         } else if (dev->flags & IFF_ALLMULTI) {
6991                 /* Accept all multicast. */
6992                 tg3_set_multi (tp, 1);
6993         } else if (dev->mc_count < 1) {
6994                 /* Reject all multicast. */
6995                 tg3_set_multi (tp, 0);
6996         } else {
6997                 /* Accept one or more multicast(s). */
6998                 struct dev_mc_list *mclist;
6999                 unsigned int i;
7000                 u32 mc_filter[4] = { 0, };
7001                 u32 regidx;
7002                 u32 bit;
7003                 u32 crc;
7004
7005                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7006                      i++, mclist = mclist->next) {
7007
7008                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7009                         bit = ~crc & 0x7f;
7010                         regidx = (bit & 0x60) >> 5;
7011                         bit &= 0x1f;
7012                         mc_filter[regidx] |= (1 << bit);
7013                 }
7014
7015                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7016                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7017                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7018                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7019         }
7020
7021         if (rx_mode != tp->rx_mode) {
7022                 tp->rx_mode = rx_mode;
7023                 tw32_f(MAC_RX_MODE, rx_mode);
7024                 udelay(10);
7025         }
7026 }
7027
7028 static void tg3_set_rx_mode(struct net_device *dev)
7029 {
7030         struct tg3 *tp = netdev_priv(dev);
7031
7032         tg3_full_lock(tp, 0);
7033         __tg3_set_rx_mode(dev);
7034         tg3_full_unlock(tp);
7035 }
7036
7037 #define TG3_REGDUMP_LEN         (32 * 1024)
7038
7039 static int tg3_get_regs_len(struct net_device *dev)
7040 {
7041         return TG3_REGDUMP_LEN;
7042 }
7043
7044 static void tg3_get_regs(struct net_device *dev,
7045                 struct ethtool_regs *regs, void *_p)
7046 {
7047         u32 *p = _p;
7048         struct tg3 *tp = netdev_priv(dev);
7049         u8 *orig_p = _p;
7050         int i;
7051
7052         regs->version = 0;
7053
7054         memset(p, 0, TG3_REGDUMP_LEN);
7055
7056         tg3_full_lock(tp, 0);
7057
7058 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7059 #define GET_REG32_LOOP(base,len)                \
7060 do {    p = (u32 *)(orig_p + (base));           \
7061         for (i = 0; i < len; i += 4)            \
7062                 __GET_REG32((base) + i);        \
7063 } while (0)
7064 #define GET_REG32_1(reg)                        \
7065 do {    p = (u32 *)(orig_p + (reg));            \
7066         __GET_REG32((reg));                     \
7067 } while (0)
7068
7069         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7070         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7071         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7072         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7073         GET_REG32_1(SNDDATAC_MODE);
7074         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7075         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7076         GET_REG32_1(SNDBDC_MODE);
7077         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7078         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7079         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7080         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7081         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7082         GET_REG32_1(RCVDCC_MODE);
7083         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7084         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7085         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7086         GET_REG32_1(MBFREE_MODE);
7087         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7088         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7089         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7090         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7091         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7092         GET_REG32_LOOP(RX_CPU_BASE, 0x280);
7093         GET_REG32_LOOP(TX_CPU_BASE, 0x280);
7094         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7095         GET_REG32_LOOP(FTQ_RESET, 0x120);
7096         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7097         GET_REG32_1(DMAC_MODE);
7098         GET_REG32_LOOP(GRC_MODE, 0x4c);
7099         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7100                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7101
7102 #undef __GET_REG32
7103 #undef GET_REG32_LOOP
7104 #undef GET_REG32_1
7105
7106         tg3_full_unlock(tp);
7107 }
7108
7109 static int tg3_get_eeprom_len(struct net_device *dev)
7110 {
7111         struct tg3 *tp = netdev_priv(dev);
7112
7113         return tp->nvram_size;
7114 }
7115
7116 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7117
7118 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7119 {
7120         struct tg3 *tp = netdev_priv(dev);
7121         int ret;
7122         u8  *pd;
7123         u32 i, offset, len, val, b_offset, b_count;
7124
7125         offset = eeprom->offset;
7126         len = eeprom->len;
7127         eeprom->len = 0;
7128
7129         eeprom->magic = TG3_EEPROM_MAGIC;
7130
7131         if (offset & 3) {
7132                 /* adjustments to start on required 4 byte boundary */
7133                 b_offset = offset & 3;
7134                 b_count = 4 - b_offset;
7135                 if (b_count > len) {
7136                         /* i.e. offset=1 len=2 */
7137                         b_count = len;
7138                 }
7139                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7140                 if (ret)
7141                         return ret;
7142                 val = cpu_to_le32(val);
7143                 memcpy(data, ((char*)&val) + b_offset, b_count);
7144                 len -= b_count;
7145                 offset += b_count;
7146                 eeprom->len += b_count;
7147         }
7148
7149         /* read bytes upto the last 4 byte boundary */
7150         pd = &data[eeprom->len];
7151         for (i = 0; i < (len - (len & 3)); i += 4) {
7152                 ret = tg3_nvram_read(tp, offset + i, &val);
7153                 if (ret) {
7154                         eeprom->len += i;
7155                         return ret;
7156                 }
7157                 val = cpu_to_le32(val);
7158                 memcpy(pd + i, &val, 4);
7159         }
7160         eeprom->len += i;
7161
7162         if (len & 3) {
7163                 /* read last bytes not ending on 4 byte boundary */
7164                 pd = &data[eeprom->len];
7165                 b_count = len & 3;
7166                 b_offset = offset + len - b_count;
7167                 ret = tg3_nvram_read(tp, b_offset, &val);
7168                 if (ret)
7169                         return ret;
7170                 val = cpu_to_le32(val);
7171                 memcpy(pd, ((char*)&val), b_count);
7172                 eeprom->len += b_count;
7173         }
7174         return 0;
7175 }
7176
7177 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7178
7179 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7180 {
7181         struct tg3 *tp = netdev_priv(dev);
7182         int ret;
7183         u32 offset, len, b_offset, odd_len, start, end;
7184         u8 *buf;
7185
7186         if (eeprom->magic != TG3_EEPROM_MAGIC)
7187                 return -EINVAL;
7188
7189         offset = eeprom->offset;
7190         len = eeprom->len;
7191
7192         if ((b_offset = (offset & 3))) {
7193                 /* adjustments to start on required 4 byte boundary */
7194                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7195                 if (ret)
7196                         return ret;
7197                 start = cpu_to_le32(start);
7198                 len += b_offset;
7199                 offset &= ~3;
7200                 if (len < 4)
7201                         len = 4;
7202         }
7203
7204         odd_len = 0;
7205         if (len & 3) {
7206                 /* adjustments to end on required 4 byte boundary */
7207                 odd_len = 1;
7208                 len = (len + 3) & ~3;
7209                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7210                 if (ret)
7211                         return ret;
7212                 end = cpu_to_le32(end);
7213         }
7214
7215         buf = data;
7216         if (b_offset || odd_len) {
7217                 buf = kmalloc(len, GFP_KERNEL);
7218                 if (buf == 0)
7219                         return -ENOMEM;
7220                 if (b_offset)
7221                         memcpy(buf, &start, 4);
7222                 if (odd_len)
7223                         memcpy(buf+len-4, &end, 4);
7224                 memcpy(buf + b_offset, data, eeprom->len);
7225         }
7226
7227         ret = tg3_nvram_write_block(tp, offset, len, buf);
7228
7229         if (buf != data)
7230                 kfree(buf);
7231
7232         return ret;
7233 }
7234
7235 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7236 {
7237         struct tg3 *tp = netdev_priv(dev);
7238
7239         cmd->supported = (SUPPORTED_Autoneg);
7240
7241         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7242                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7243                                    SUPPORTED_1000baseT_Full);
7244
7245         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
7246                 cmd->supported |= (SUPPORTED_100baseT_Half |
7247                                   SUPPORTED_100baseT_Full |
7248                                   SUPPORTED_10baseT_Half |
7249                                   SUPPORTED_10baseT_Full |
7250                                   SUPPORTED_MII);
7251         else
7252                 cmd->supported |= SUPPORTED_FIBRE;
7253
7254         cmd->advertising = tp->link_config.advertising;
7255         if (netif_running(dev)) {
7256                 cmd->speed = tp->link_config.active_speed;
7257                 cmd->duplex = tp->link_config.active_duplex;
7258         }
7259         cmd->port = 0;
7260         cmd->phy_address = PHY_ADDR;
7261         cmd->transceiver = 0;
7262         cmd->autoneg = tp->link_config.autoneg;
7263         cmd->maxtxpkt = 0;
7264         cmd->maxrxpkt = 0;
7265         return 0;
7266 }
7267
7268 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7269 {
7270         struct tg3 *tp = netdev_priv(dev);
7271
7272         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7273                 /* These are the only valid advertisement bits allowed.  */
7274                 if (cmd->autoneg == AUTONEG_ENABLE &&
7275                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7276                                           ADVERTISED_1000baseT_Full |
7277                                           ADVERTISED_Autoneg |
7278                                           ADVERTISED_FIBRE)))
7279                         return -EINVAL;
7280         }
7281
7282         tg3_full_lock(tp, 0);
7283
7284         tp->link_config.autoneg = cmd->autoneg;
7285         if (cmd->autoneg == AUTONEG_ENABLE) {
7286                 tp->link_config.advertising = cmd->advertising;
7287                 tp->link_config.speed = SPEED_INVALID;
7288                 tp->link_config.duplex = DUPLEX_INVALID;
7289         } else {
7290                 tp->link_config.advertising = 0;
7291                 tp->link_config.speed = cmd->speed;
7292                 tp->link_config.duplex = cmd->duplex;
7293         }
7294
7295         if (netif_running(dev))
7296                 tg3_setup_phy(tp, 1);
7297
7298         tg3_full_unlock(tp);
7299
7300         return 0;
7301 }
7302
7303 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7304 {
7305         struct tg3 *tp = netdev_priv(dev);
7306
7307         strcpy(info->driver, DRV_MODULE_NAME);
7308         strcpy(info->version, DRV_MODULE_VERSION);
7309         strcpy(info->bus_info, pci_name(tp->pdev));
7310 }
7311
7312 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7313 {
7314         struct tg3 *tp = netdev_priv(dev);
7315
7316         wol->supported = WAKE_MAGIC;
7317         wol->wolopts = 0;
7318         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7319                 wol->wolopts = WAKE_MAGIC;
7320         memset(&wol->sopass, 0, sizeof(wol->sopass));
7321 }
7322
7323 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7324 {
7325         struct tg3 *tp = netdev_priv(dev);
7326
7327         if (wol->wolopts & ~WAKE_MAGIC)
7328                 return -EINVAL;
7329         if ((wol->wolopts & WAKE_MAGIC) &&
7330             tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7331             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7332                 return -EINVAL;
7333
7334         spin_lock_bh(&tp->lock);
7335         if (wol->wolopts & WAKE_MAGIC)
7336                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7337         else
7338                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7339         spin_unlock_bh(&tp->lock);
7340
7341         return 0;
7342 }
7343
7344 static u32 tg3_get_msglevel(struct net_device *dev)
7345 {
7346         struct tg3 *tp = netdev_priv(dev);
7347         return tp->msg_enable;
7348 }
7349
7350 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7351 {
7352         struct tg3 *tp = netdev_priv(dev);
7353         tp->msg_enable = value;
7354 }
7355
7356 #if TG3_TSO_SUPPORT != 0
7357 static int tg3_set_tso(struct net_device *dev, u32 value)
7358 {
7359         struct tg3 *tp = netdev_priv(dev);
7360
7361         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7362                 if (value)
7363                         return -EINVAL;
7364                 return 0;
7365         }
7366         return ethtool_op_set_tso(dev, value);
7367 }
7368 #endif
7369
7370 static int tg3_nway_reset(struct net_device *dev)
7371 {
7372         struct tg3 *tp = netdev_priv(dev);
7373         u32 bmcr;
7374         int r;
7375
7376         if (!netif_running(dev))
7377                 return -EAGAIN;
7378
7379         spin_lock_bh(&tp->lock);
7380         r = -EINVAL;
7381         tg3_readphy(tp, MII_BMCR, &bmcr);
7382         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7383             (bmcr & BMCR_ANENABLE)) {
7384                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
7385                 r = 0;
7386         }
7387         spin_unlock_bh(&tp->lock);
7388
7389         return r;
7390 }
7391
7392 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7393 {
7394         struct tg3 *tp = netdev_priv(dev);
7395
7396         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7397         ering->rx_mini_max_pending = 0;
7398         ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7399
7400         ering->rx_pending = tp->rx_pending;
7401         ering->rx_mini_pending = 0;
7402         ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7403         ering->tx_pending = tp->tx_pending;
7404 }
7405
7406 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7407 {
7408         struct tg3 *tp = netdev_priv(dev);
7409         int irq_sync = 0;
7410
7411         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7412             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7413             (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7414                 return -EINVAL;
7415
7416         if (netif_running(dev)) {
7417                 tg3_netif_stop(tp);
7418                 irq_sync = 1;
7419         }
7420
7421         tg3_full_lock(tp, irq_sync);
7422
7423         tp->rx_pending = ering->rx_pending;
7424
7425         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7426             tp->rx_pending > 63)
7427                 tp->rx_pending = 63;
7428         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7429         tp->tx_pending = ering->tx_pending;
7430
7431         if (netif_running(dev)) {
7432                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7433                 tg3_init_hw(tp);
7434                 tg3_netif_start(tp);
7435         }
7436
7437         tg3_full_unlock(tp);
7438
7439         return 0;
7440 }
7441
7442 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7443 {
7444         struct tg3 *tp = netdev_priv(dev);
7445
7446         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7447         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7448         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7449 }
7450
7451 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7452 {
7453         struct tg3 *tp = netdev_priv(dev);
7454         int irq_sync = 0;
7455
7456         if (netif_running(dev)) {
7457                 tg3_netif_stop(tp);
7458                 irq_sync = 1;
7459         }
7460
7461         tg3_full_lock(tp, irq_sync);
7462
7463         if (epause->autoneg)
7464                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7465         else
7466                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7467         if (epause->rx_pause)
7468                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7469         else
7470                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7471         if (epause->tx_pause)
7472                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7473         else
7474                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7475
7476         if (netif_running(dev)) {
7477                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7478                 tg3_init_hw(tp);
7479                 tg3_netif_start(tp);
7480         }
7481
7482         tg3_full_unlock(tp);
7483
7484         return 0;
7485 }
7486
7487 static u32 tg3_get_rx_csum(struct net_device *dev)
7488 {
7489         struct tg3 *tp = netdev_priv(dev);
7490         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7491 }
7492
7493 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7494 {
7495         struct tg3 *tp = netdev_priv(dev);
7496
7497         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7498                 if (data != 0)
7499                         return -EINVAL;
7500                 return 0;
7501         }
7502
7503         spin_lock_bh(&tp->lock);
7504         if (data)
7505                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7506         else
7507                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7508         spin_unlock_bh(&tp->lock);
7509
7510         return 0;
7511 }
7512
7513 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7514 {
7515         struct tg3 *tp = netdev_priv(dev);
7516
7517         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7518                 if (data != 0)
7519                         return -EINVAL;
7520                 return 0;
7521         }
7522
7523         if (data)
7524                 dev->features |= NETIF_F_IP_CSUM;
7525         else
7526                 dev->features &= ~NETIF_F_IP_CSUM;
7527
7528         return 0;
7529 }
7530
7531 static int tg3_get_stats_count (struct net_device *dev)
7532 {
7533         return TG3_NUM_STATS;
7534 }
7535
7536 static int tg3_get_test_count (struct net_device *dev)
7537 {
7538         return TG3_NUM_TEST;
7539 }
7540
7541 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7542 {
7543         switch (stringset) {
7544         case ETH_SS_STATS:
7545                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7546                 break;
7547         case ETH_SS_TEST:
7548                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7549                 break;
7550         default:
7551                 WARN_ON(1);     /* we need a WARN() */
7552                 break;
7553         }
7554 }
7555
7556 static int tg3_phys_id(struct net_device *dev, u32 data)
7557 {
7558         struct tg3 *tp = netdev_priv(dev);
7559         int i;
7560
7561         if (!netif_running(tp->dev))
7562                 return -EAGAIN;
7563
7564         if (data == 0)
7565                 data = 2;
7566
7567         for (i = 0; i < (data * 2); i++) {
7568                 if ((i % 2) == 0)
7569                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7570                                            LED_CTRL_1000MBPS_ON |
7571                                            LED_CTRL_100MBPS_ON |
7572                                            LED_CTRL_10MBPS_ON |
7573                                            LED_CTRL_TRAFFIC_OVERRIDE |
7574                                            LED_CTRL_TRAFFIC_BLINK |
7575                                            LED_CTRL_TRAFFIC_LED);
7576
7577                 else
7578                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7579                                            LED_CTRL_TRAFFIC_OVERRIDE);
7580
7581                 if (msleep_interruptible(500))
7582                         break;
7583         }
7584         tw32(MAC_LED_CTRL, tp->led_ctrl);
7585         return 0;
7586 }
7587
7588 static void tg3_get_ethtool_stats (struct net_device *dev,
7589                                    struct ethtool_stats *estats, u64 *tmp_stats)
7590 {
7591         struct tg3 *tp = netdev_priv(dev);
7592         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7593 }
7594
7595 #define NVRAM_TEST_SIZE 0x100
7596
7597 static int tg3_test_nvram(struct tg3 *tp)
7598 {
7599         u32 *buf, csum;
7600         int i, j, err = 0;
7601
7602         buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7603         if (buf == NULL)
7604                 return -ENOMEM;
7605
7606         for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7607                 u32 val;
7608
7609                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7610                         break;
7611                 buf[j] = cpu_to_le32(val);
7612         }
7613         if (i < NVRAM_TEST_SIZE)
7614                 goto out;
7615
7616         err = -EIO;
7617         if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7618                 goto out;
7619
7620         /* Bootstrap checksum at offset 0x10 */
7621         csum = calc_crc((unsigned char *) buf, 0x10);
7622         if(csum != cpu_to_le32(buf[0x10/4]))
7623                 goto out;
7624
7625         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7626         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7627         if (csum != cpu_to_le32(buf[0xfc/4]))
7628                  goto out;
7629
7630         err = 0;
7631
7632 out:
7633         kfree(buf);
7634         return err;
7635 }
7636
7637 #define TG3_SERDES_TIMEOUT_SEC  2
7638 #define TG3_COPPER_TIMEOUT_SEC  6
7639
7640 static int tg3_test_link(struct tg3 *tp)
7641 {
7642         int i, max;
7643
7644         if (!netif_running(tp->dev))
7645                 return -ENODEV;
7646
7647         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
7648                 max = TG3_SERDES_TIMEOUT_SEC;
7649         else
7650                 max = TG3_COPPER_TIMEOUT_SEC;
7651
7652         for (i = 0; i < max; i++) {
7653                 if (netif_carrier_ok(tp->dev))
7654                         return 0;
7655
7656                 if (msleep_interruptible(1000))
7657                         break;
7658         }
7659
7660         return -EIO;
7661 }
7662
7663 /* Only test the commonly used registers */
7664 static int tg3_test_registers(struct tg3 *tp)
7665 {
7666         int i, is_5705;
7667         u32 offset, read_mask, write_mask, val, save_val, read_val;
7668         static struct {
7669                 u16 offset;
7670                 u16 flags;
7671 #define TG3_FL_5705     0x1
7672 #define TG3_FL_NOT_5705 0x2
7673 #define TG3_FL_NOT_5788 0x4
7674                 u32 read_mask;
7675                 u32 write_mask;
7676         } reg_tbl[] = {
7677                 /* MAC Control Registers */
7678                 { MAC_MODE, TG3_FL_NOT_5705,
7679                         0x00000000, 0x00ef6f8c },
7680                 { MAC_MODE, TG3_FL_5705,
7681                         0x00000000, 0x01ef6b8c },
7682                 { MAC_STATUS, TG3_FL_NOT_5705,
7683                         0x03800107, 0x00000000 },
7684                 { MAC_STATUS, TG3_FL_5705,
7685                         0x03800100, 0x00000000 },
7686                 { MAC_ADDR_0_HIGH, 0x0000,
7687                         0x00000000, 0x0000ffff },
7688                 { MAC_ADDR_0_LOW, 0x0000,
7689                         0x00000000, 0xffffffff },
7690                 { MAC_RX_MTU_SIZE, 0x0000,
7691                         0x00000000, 0x0000ffff },
7692                 { MAC_TX_MODE, 0x0000,
7693                         0x00000000, 0x00000070 },
7694                 { MAC_TX_LENGTHS, 0x0000,
7695                         0x00000000, 0x00003fff },
7696                 { MAC_RX_MODE, TG3_FL_NOT_5705,
7697                         0x00000000, 0x000007fc },
7698                 { MAC_RX_MODE, TG3_FL_5705,
7699                         0x00000000, 0x000007dc },
7700                 { MAC_HASH_REG_0, 0x0000,
7701                         0x00000000, 0xffffffff },
7702                 { MAC_HASH_REG_1, 0x0000,
7703                         0x00000000, 0xffffffff },
7704                 { MAC_HASH_REG_2, 0x0000,
7705                         0x00000000, 0xffffffff },
7706                 { MAC_HASH_REG_3, 0x0000,
7707                         0x00000000, 0xffffffff },
7708
7709                 /* Receive Data and Receive BD Initiator Control Registers. */
7710                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7711                         0x00000000, 0xffffffff },
7712                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7713                         0x00000000, 0xffffffff },
7714                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7715                         0x00000000, 0x00000003 },
7716                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7717                         0x00000000, 0xffffffff },
7718                 { RCVDBDI_STD_BD+0, 0x0000,
7719                         0x00000000, 0xffffffff },
7720                 { RCVDBDI_STD_BD+4, 0x0000,
7721                         0x00000000, 0xffffffff },
7722                 { RCVDBDI_STD_BD+8, 0x0000,
7723                         0x00000000, 0xffff0002 },
7724                 { RCVDBDI_STD_BD+0xc, 0x0000,
7725                         0x00000000, 0xffffffff },
7726
7727                 /* Receive BD Initiator Control Registers. */
7728                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7729                         0x00000000, 0xffffffff },
7730                 { RCVBDI_STD_THRESH, TG3_FL_5705,
7731                         0x00000000, 0x000003ff },
7732                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7733                         0x00000000, 0xffffffff },
7734
7735                 /* Host Coalescing Control Registers. */
7736                 { HOSTCC_MODE, TG3_FL_NOT_5705,
7737                         0x00000000, 0x00000004 },
7738                 { HOSTCC_MODE, TG3_FL_5705,
7739                         0x00000000, 0x000000f6 },
7740                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7741                         0x00000000, 0xffffffff },
7742                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7743                         0x00000000, 0x000003ff },
7744                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7745                         0x00000000, 0xffffffff },
7746                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7747                         0x00000000, 0x000003ff },
7748                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7749                         0x00000000, 0xffffffff },
7750                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7751                         0x00000000, 0x000000ff },
7752                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7753                         0x00000000, 0xffffffff },
7754                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7755                         0x00000000, 0x000000ff },
7756                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7757                         0x00000000, 0xffffffff },
7758                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7759                         0x00000000, 0xffffffff },
7760                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7761                         0x00000000, 0xffffffff },
7762                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7763                         0x00000000, 0x000000ff },
7764                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7765                         0x00000000, 0xffffffff },
7766                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7767                         0x00000000, 0x000000ff },
7768                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7769                         0x00000000, 0xffffffff },
7770                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7771                         0x00000000, 0xffffffff },
7772                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7773                         0x00000000, 0xffffffff },
7774                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7775                         0x00000000, 0xffffffff },
7776                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7777                         0x00000000, 0xffffffff },
7778                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7779                         0xffffffff, 0x00000000 },
7780                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7781                         0xffffffff, 0x00000000 },
7782
7783                 /* Buffer Manager Control Registers. */
7784                 { BUFMGR_MB_POOL_ADDR, 0x0000,
7785                         0x00000000, 0x007fff80 },
7786                 { BUFMGR_MB_POOL_SIZE, 0x0000,
7787                         0x00000000, 0x007fffff },
7788                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7789                         0x00000000, 0x0000003f },
7790                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7791                         0x00000000, 0x000001ff },
7792                 { BUFMGR_MB_HIGH_WATER, 0x0000,
7793                         0x00000000, 0x000001ff },
7794                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7795                         0xffffffff, 0x00000000 },
7796                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7797                         0xffffffff, 0x00000000 },
7798
7799                 /* Mailbox Registers */
7800                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7801                         0x00000000, 0x000001ff },
7802                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7803                         0x00000000, 0x000001ff },
7804                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7805                         0x00000000, 0x000007ff },
7806                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7807                         0x00000000, 0x000001ff },
7808
7809                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7810         };
7811
7812         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7813                 is_5705 = 1;
7814         else
7815                 is_5705 = 0;
7816
7817         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7818                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7819                         continue;
7820
7821                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7822                         continue;
7823
7824                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7825                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
7826                         continue;
7827
7828                 offset = (u32) reg_tbl[i].offset;
7829                 read_mask = reg_tbl[i].read_mask;
7830                 write_mask = reg_tbl[i].write_mask;
7831
7832                 /* Save the original register content */
7833                 save_val = tr32(offset);
7834
7835                 /* Determine the read-only value. */
7836                 read_val = save_val & read_mask;
7837
7838                 /* Write zero to the register, then make sure the read-only bits
7839                  * are not changed and the read/write bits are all zeros.
7840                  */
7841                 tw32(offset, 0);
7842
7843                 val = tr32(offset);
7844
7845                 /* Test the read-only and read/write bits. */
7846                 if (((val & read_mask) != read_val) || (val & write_mask))
7847                         goto out;
7848
7849                 /* Write ones to all the bits defined by RdMask and WrMask, then
7850                  * make sure the read-only bits are not changed and the
7851                  * read/write bits are all ones.
7852                  */
7853                 tw32(offset, read_mask | write_mask);
7854
7855                 val = tr32(offset);
7856
7857                 /* Test the read-only bits. */
7858                 if ((val & read_mask) != read_val)
7859                         goto out;
7860
7861                 /* Test the read/write bits. */
7862                 if ((val & write_mask) != write_mask)
7863                         goto out;
7864
7865                 tw32(offset, save_val);
7866         }
7867
7868         return 0;
7869
7870 out:
7871         printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7872         tw32(offset, save_val);
7873         return -EIO;
7874 }
7875
7876 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7877 {
7878         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7879         int i;
7880         u32 j;
7881
7882         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7883                 for (j = 0; j < len; j += 4) {
7884                         u32 val;
7885
7886                         tg3_write_mem(tp, offset + j, test_pattern[i]);
7887                         tg3_read_mem(tp, offset + j, &val);
7888                         if (val != test_pattern[i])
7889                                 return -EIO;
7890                 }
7891         }
7892         return 0;
7893 }
7894
7895 static int tg3_test_memory(struct tg3 *tp)
7896 {
7897         static struct mem_entry {
7898                 u32 offset;
7899                 u32 len;
7900         } mem_tbl_570x[] = {
7901                 { 0x00000000, 0x01000},
7902                 { 0x00002000, 0x1c000},
7903                 { 0xffffffff, 0x00000}
7904         }, mem_tbl_5705[] = {
7905                 { 0x00000100, 0x0000c},
7906                 { 0x00000200, 0x00008},
7907                 { 0x00000b50, 0x00400},
7908                 { 0x00004000, 0x00800},
7909                 { 0x00006000, 0x01000},
7910                 { 0x00008000, 0x02000},
7911                 { 0x00010000, 0x0e000},
7912                 { 0xffffffff, 0x00000}
7913         };
7914         struct mem_entry *mem_tbl;
7915         int err = 0;
7916         int i;
7917
7918         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7919                 mem_tbl = mem_tbl_5705;
7920         else
7921                 mem_tbl = mem_tbl_570x;
7922
7923         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
7924                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
7925                     mem_tbl[i].len)) != 0)
7926                         break;
7927         }
7928
7929         return err;
7930 }
7931
7932 #define TG3_MAC_LOOPBACK        0
7933 #define TG3_PHY_LOOPBACK        1
7934
7935 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
7936 {
7937         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
7938         u32 desc_idx;
7939         struct sk_buff *skb, *rx_skb;
7940         u8 *tx_data;
7941         dma_addr_t map;
7942         int num_pkts, tx_len, rx_len, i, err;
7943         struct tg3_rx_buffer_desc *desc;
7944
7945         if (loopback_mode == TG3_MAC_LOOPBACK) {
7946                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7947                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
7948                            MAC_MODE_PORT_MODE_GMII;
7949                 tw32(MAC_MODE, mac_mode);
7950         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
7951                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7952                            MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
7953                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
7954                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
7955                 tw32(MAC_MODE, mac_mode);
7956
7957                 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
7958                                            BMCR_SPEED1000);
7959         }
7960         else
7961                 return -EINVAL;
7962
7963         err = -EIO;
7964
7965         tx_len = 1514;
7966         skb = dev_alloc_skb(tx_len);
7967         tx_data = skb_put(skb, tx_len);
7968         memcpy(tx_data, tp->dev->dev_addr, 6);
7969         memset(tx_data + 6, 0x0, 8);
7970
7971         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
7972
7973         for (i = 14; i < tx_len; i++)
7974                 tx_data[i] = (u8) (i & 0xff);
7975
7976         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
7977
7978         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7979              HOSTCC_MODE_NOW);
7980
7981         udelay(10);
7982
7983         rx_start_idx = tp->hw_status->idx[0].rx_producer;
7984
7985         num_pkts = 0;
7986
7987         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
7988
7989         tp->tx_prod++;
7990         num_pkts++;
7991
7992         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
7993                      tp->tx_prod);
7994         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
7995
7996         udelay(10);
7997
7998         for (i = 0; i < 10; i++) {
7999                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8000                        HOSTCC_MODE_NOW);
8001
8002                 udelay(10);
8003
8004                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8005                 rx_idx = tp->hw_status->idx[0].rx_producer;
8006                 if ((tx_idx == tp->tx_prod) &&
8007                     (rx_idx == (rx_start_idx + num_pkts)))
8008                         break;
8009         }
8010
8011         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8012         dev_kfree_skb(skb);
8013
8014         if (tx_idx != tp->tx_prod)
8015                 goto out;
8016
8017         if (rx_idx != rx_start_idx + num_pkts)
8018                 goto out;
8019
8020         desc = &tp->rx_rcb[rx_start_idx];
8021         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8022         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8023         if (opaque_key != RXD_OPAQUE_RING_STD)
8024                 goto out;
8025
8026         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8027             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8028                 goto out;
8029
8030         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8031         if (rx_len != tx_len)
8032                 goto out;
8033
8034         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8035
8036         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8037         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8038
8039         for (i = 14; i < tx_len; i++) {
8040                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8041                         goto out;
8042         }
8043         err = 0;
8044
8045         /* tg3_free_rings will unmap and free the rx_skb */
8046 out:
8047         return err;
8048 }
8049
8050 #define TG3_MAC_LOOPBACK_FAILED         1
8051 #define TG3_PHY_LOOPBACK_FAILED         2
8052 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8053                                          TG3_PHY_LOOPBACK_FAILED)
8054
8055 static int tg3_test_loopback(struct tg3 *tp)
8056 {
8057         int err = 0;
8058
8059         if (!netif_running(tp->dev))
8060                 return TG3_LOOPBACK_FAILED;
8061
8062         tg3_reset_hw(tp);
8063
8064         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8065                 err |= TG3_MAC_LOOPBACK_FAILED;
8066         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8067                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8068                         err |= TG3_PHY_LOOPBACK_FAILED;
8069         }
8070
8071         return err;
8072 }
8073
8074 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8075                           u64 *data)
8076 {
8077         struct tg3 *tp = netdev_priv(dev);
8078
8079         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8080
8081         if (tg3_test_nvram(tp) != 0) {
8082                 etest->flags |= ETH_TEST_FL_FAILED;
8083                 data[0] = 1;
8084         }
8085         if (tg3_test_link(tp) != 0) {
8086                 etest->flags |= ETH_TEST_FL_FAILED;
8087                 data[1] = 1;
8088         }
8089         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8090                 int irq_sync = 0;
8091
8092                 if (netif_running(dev)) {
8093                         tg3_netif_stop(tp);
8094                         irq_sync = 1;
8095                 }
8096
8097                 tg3_full_lock(tp, irq_sync);
8098
8099                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8100                 tg3_nvram_lock(tp);
8101                 tg3_halt_cpu(tp, RX_CPU_BASE);
8102                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8103                         tg3_halt_cpu(tp, TX_CPU_BASE);
8104                 tg3_nvram_unlock(tp);
8105
8106                 if (tg3_test_registers(tp) != 0) {
8107                         etest->flags |= ETH_TEST_FL_FAILED;
8108                         data[2] = 1;
8109                 }
8110                 if (tg3_test_memory(tp) != 0) {
8111                         etest->flags |= ETH_TEST_FL_FAILED;
8112                         data[3] = 1;
8113                 }
8114                 if ((data[4] = tg3_test_loopback(tp)) != 0)
8115                         etest->flags |= ETH_TEST_FL_FAILED;
8116
8117                 tg3_full_unlock(tp);
8118
8119                 if (tg3_test_interrupt(tp) != 0) {
8120                         etest->flags |= ETH_TEST_FL_FAILED;
8121                         data[5] = 1;
8122                 }
8123
8124                 tg3_full_lock(tp, 0);
8125
8126                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8127                 if (netif_running(dev)) {
8128                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8129                         tg3_init_hw(tp);
8130                         tg3_netif_start(tp);
8131                 }
8132
8133                 tg3_full_unlock(tp);
8134         }
8135 }
8136
8137 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8138 {
8139         struct mii_ioctl_data *data = if_mii(ifr);
8140         struct tg3 *tp = netdev_priv(dev);
8141         int err;
8142
8143         switch(cmd) {
8144         case SIOCGMIIPHY:
8145                 data->phy_id = PHY_ADDR;
8146
8147                 /* fallthru */
8148         case SIOCGMIIREG: {
8149                 u32 mii_regval;
8150
8151                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8152                         break;                  /* We have no PHY */
8153
8154                 spin_lock_bh(&tp->lock);
8155                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
8156                 spin_unlock_bh(&tp->lock);
8157
8158                 data->val_out = mii_regval;
8159
8160                 return err;
8161         }
8162
8163         case SIOCSMIIREG:
8164                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8165                         break;                  /* We have no PHY */
8166
8167                 if (!capable(CAP_NET_ADMIN))
8168                         return -EPERM;
8169
8170                 spin_lock_bh(&tp->lock);
8171                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
8172                 spin_unlock_bh(&tp->lock);
8173
8174                 return err;
8175
8176         default:
8177                 /* do nothing */
8178                 break;
8179         }
8180         return -EOPNOTSUPP;
8181 }
8182
8183 #if TG3_VLAN_TAG_USED
8184 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8185 {
8186         struct tg3 *tp = netdev_priv(dev);
8187
8188         tg3_full_lock(tp, 0);
8189
8190         tp->vlgrp = grp;
8191
8192         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8193         __tg3_set_rx_mode(dev);
8194
8195         tg3_full_unlock(tp);
8196 }
8197
8198 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8199 {
8200         struct tg3 *tp = netdev_priv(dev);
8201
8202         tg3_full_lock(tp, 0);
8203         if (tp->vlgrp)
8204                 tp->vlgrp->vlan_devices[vid] = NULL;
8205         tg3_full_unlock(tp);
8206 }
8207 #endif
8208
8209 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8210 {
8211         struct tg3 *tp = netdev_priv(dev);
8212
8213         memcpy(ec, &tp->coal, sizeof(*ec));
8214         return 0;
8215 }
8216
8217 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8218 {
8219         struct tg3 *tp = netdev_priv(dev);
8220         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8221         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8222
8223         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8224                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8225                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8226                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8227                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8228         }
8229
8230         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8231             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8232             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8233             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8234             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8235             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8236             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8237             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8238             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8239             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8240                 return -EINVAL;
8241
8242         /* No rx interrupts will be generated if both are zero */
8243         if ((ec->rx_coalesce_usecs == 0) &&
8244             (ec->rx_max_coalesced_frames == 0))
8245                 return -EINVAL;
8246
8247         /* No tx interrupts will be generated if both are zero */
8248         if ((ec->tx_coalesce_usecs == 0) &&
8249             (ec->tx_max_coalesced_frames == 0))
8250                 return -EINVAL;
8251
8252         /* Only copy relevant parameters, ignore all others. */
8253         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8254         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8255         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8256         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8257         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8258         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8259         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8260         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8261         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8262
8263         if (netif_running(dev)) {
8264                 tg3_full_lock(tp, 0);
8265                 __tg3_set_coalesce(tp, &tp->coal);
8266                 tg3_full_unlock(tp);
8267         }
8268         return 0;
8269 }
8270
8271 static struct ethtool_ops tg3_ethtool_ops = {
8272         .get_settings           = tg3_get_settings,
8273         .set_settings           = tg3_set_settings,
8274         .get_drvinfo            = tg3_get_drvinfo,
8275         .get_regs_len           = tg3_get_regs_len,
8276         .get_regs               = tg3_get_regs,
8277         .get_wol                = tg3_get_wol,
8278         .set_wol                = tg3_set_wol,
8279         .get_msglevel           = tg3_get_msglevel,
8280         .set_msglevel           = tg3_set_msglevel,
8281         .nway_reset             = tg3_nway_reset,
8282         .get_link               = ethtool_op_get_link,
8283         .get_eeprom_len         = tg3_get_eeprom_len,
8284         .get_eeprom             = tg3_get_eeprom,
8285         .set_eeprom             = tg3_set_eeprom,
8286         .get_ringparam          = tg3_get_ringparam,
8287         .set_ringparam          = tg3_set_ringparam,
8288         .get_pauseparam         = tg3_get_pauseparam,
8289         .set_pauseparam         = tg3_set_pauseparam,
8290         .get_rx_csum            = tg3_get_rx_csum,
8291         .set_rx_csum            = tg3_set_rx_csum,
8292         .get_tx_csum            = ethtool_op_get_tx_csum,
8293         .set_tx_csum            = tg3_set_tx_csum,
8294         .get_sg                 = ethtool_op_get_sg,
8295         .set_sg                 = ethtool_op_set_sg,
8296 #if TG3_TSO_SUPPORT != 0
8297         .get_tso                = ethtool_op_get_tso,
8298         .set_tso                = tg3_set_tso,
8299 #endif
8300         .self_test_count        = tg3_get_test_count,
8301         .self_test              = tg3_self_test,
8302         .get_strings            = tg3_get_strings,
8303         .phys_id                = tg3_phys_id,
8304         .get_stats_count        = tg3_get_stats_count,
8305         .get_ethtool_stats      = tg3_get_ethtool_stats,
8306         .get_coalesce           = tg3_get_coalesce,
8307         .set_coalesce           = tg3_set_coalesce,
8308 };
8309
8310 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8311 {
8312         u32 cursize, val;
8313
8314         tp->nvram_size = EEPROM_CHIP_SIZE;
8315
8316         if (tg3_nvram_read(tp, 0, &val) != 0)
8317                 return;
8318
8319         if (swab32(val) != TG3_EEPROM_MAGIC)
8320                 return;
8321
8322         /*
8323          * Size the chip by reading offsets at increasing powers of two.
8324          * When we encounter our validation signature, we know the addressing
8325          * has wrapped around, and thus have our chip size.
8326          */
8327         cursize = 0x800;
8328
8329         while (cursize < tp->nvram_size) {
8330                 if (tg3_nvram_read(tp, cursize, &val) != 0)
8331                         return;
8332
8333                 if (swab32(val) == TG3_EEPROM_MAGIC)
8334                         break;
8335
8336                 cursize <<= 1;
8337         }
8338
8339         tp->nvram_size = cursize;
8340 }
8341
8342 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8343 {
8344         u32 val;
8345
8346         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8347                 if (val != 0) {
8348                         tp->nvram_size = (val >> 16) * 1024;
8349                         return;
8350                 }
8351         }
8352         tp->nvram_size = 0x20000;
8353 }
8354
8355 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8356 {
8357         u32 nvcfg1;
8358
8359         nvcfg1 = tr32(NVRAM_CFG1);
8360         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8361                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8362         }
8363         else {
8364                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8365                 tw32(NVRAM_CFG1, nvcfg1);
8366         }
8367
8368         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
8369             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)) {
8370                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8371                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8372                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8373                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8374                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8375                                 break;
8376                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8377                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8378                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8379                                 break;
8380                         case FLASH_VENDOR_ATMEL_EEPROM:
8381                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8382                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8383                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8384                                 break;
8385                         case FLASH_VENDOR_ST:
8386                                 tp->nvram_jedecnum = JEDEC_ST;
8387                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8388                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8389                                 break;
8390                         case FLASH_VENDOR_SAIFUN:
8391                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
8392                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8393                                 break;
8394                         case FLASH_VENDOR_SST_SMALL:
8395                         case FLASH_VENDOR_SST_LARGE:
8396                                 tp->nvram_jedecnum = JEDEC_SST;
8397                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8398                                 break;
8399                 }
8400         }
8401         else {
8402                 tp->nvram_jedecnum = JEDEC_ATMEL;
8403                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8404                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8405         }
8406 }
8407
8408 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8409 {
8410         u32 nvcfg1;
8411
8412         nvcfg1 = tr32(NVRAM_CFG1);
8413
8414         /* NVRAM protection for TPM */
8415         if (nvcfg1 & (1 << 27))
8416                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8417
8418         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8419                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8420                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8421                         tp->nvram_jedecnum = JEDEC_ATMEL;
8422                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8423                         break;
8424                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8425                         tp->nvram_jedecnum = JEDEC_ATMEL;
8426                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8427                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8428                         break;
8429                 case FLASH_5752VENDOR_ST_M45PE10:
8430                 case FLASH_5752VENDOR_ST_M45PE20:
8431                 case FLASH_5752VENDOR_ST_M45PE40:
8432                         tp->nvram_jedecnum = JEDEC_ST;
8433                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8434                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8435                         break;
8436         }
8437
8438         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8439                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8440                         case FLASH_5752PAGE_SIZE_256:
8441                                 tp->nvram_pagesize = 256;
8442                                 break;
8443                         case FLASH_5752PAGE_SIZE_512:
8444                                 tp->nvram_pagesize = 512;
8445                                 break;
8446                         case FLASH_5752PAGE_SIZE_1K:
8447                                 tp->nvram_pagesize = 1024;
8448                                 break;
8449                         case FLASH_5752PAGE_SIZE_2K:
8450                                 tp->nvram_pagesize = 2048;
8451                                 break;
8452                         case FLASH_5752PAGE_SIZE_4K:
8453                                 tp->nvram_pagesize = 4096;
8454                                 break;
8455                         case FLASH_5752PAGE_SIZE_264:
8456                                 tp->nvram_pagesize = 264;
8457                                 break;
8458                 }
8459         }
8460         else {
8461                 /* For eeprom, set pagesize to maximum eeprom size */
8462                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8463
8464                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8465                 tw32(NVRAM_CFG1, nvcfg1);
8466         }
8467 }
8468
8469 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
8470 static void __devinit tg3_nvram_init(struct tg3 *tp)
8471 {
8472         int j;
8473
8474         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8475                 return;
8476
8477         tw32_f(GRC_EEPROM_ADDR,
8478              (EEPROM_ADDR_FSM_RESET |
8479               (EEPROM_DEFAULT_CLOCK_PERIOD <<
8480                EEPROM_ADDR_CLKPERD_SHIFT)));
8481
8482         /* XXX schedule_timeout() ... */
8483         for (j = 0; j < 100; j++)
8484                 udelay(10);
8485
8486         /* Enable seeprom accesses. */
8487         tw32_f(GRC_LOCAL_CTRL,
8488              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8489         udelay(100);
8490
8491         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8492             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8493                 tp->tg3_flags |= TG3_FLAG_NVRAM;
8494
8495                 tg3_enable_nvram_access(tp);
8496
8497                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8498                         tg3_get_5752_nvram_info(tp);
8499                 else
8500                         tg3_get_nvram_info(tp);
8501
8502                 tg3_get_nvram_size(tp);
8503
8504                 tg3_disable_nvram_access(tp);
8505
8506         } else {
8507                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8508
8509                 tg3_get_eeprom_size(tp);
8510         }
8511 }
8512
8513 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8514                                         u32 offset, u32 *val)
8515 {
8516         u32 tmp;
8517         int i;
8518
8519         if (offset > EEPROM_ADDR_ADDR_MASK ||
8520             (offset % 4) != 0)
8521                 return -EINVAL;
8522
8523         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8524                                         EEPROM_ADDR_DEVID_MASK |
8525                                         EEPROM_ADDR_READ);
8526         tw32(GRC_EEPROM_ADDR,
8527              tmp |
8528              (0 << EEPROM_ADDR_DEVID_SHIFT) |
8529              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8530               EEPROM_ADDR_ADDR_MASK) |
8531              EEPROM_ADDR_READ | EEPROM_ADDR_START);
8532
8533         for (i = 0; i < 10000; i++) {
8534                 tmp = tr32(GRC_EEPROM_ADDR);
8535
8536                 if (tmp & EEPROM_ADDR_COMPLETE)
8537                         break;
8538                 udelay(100);
8539         }
8540         if (!(tmp & EEPROM_ADDR_COMPLETE))
8541                 return -EBUSY;
8542
8543         *val = tr32(GRC_EEPROM_DATA);
8544         return 0;
8545 }
8546
8547 #define NVRAM_CMD_TIMEOUT 10000
8548
8549 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8550 {
8551         int i;
8552
8553         tw32(NVRAM_CMD, nvram_cmd);
8554         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8555                 udelay(10);
8556                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8557                         udelay(10);
8558                         break;
8559                 }
8560         }
8561         if (i == NVRAM_CMD_TIMEOUT) {
8562                 return -EBUSY;
8563         }
8564         return 0;
8565 }
8566
8567 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8568 {
8569         int ret;
8570
8571         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8572                 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8573                 return -EINVAL;
8574         }
8575
8576         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8577                 return tg3_nvram_read_using_eeprom(tp, offset, val);
8578
8579         if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8580                 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8581                 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8582
8583                 offset = ((offset / tp->nvram_pagesize) <<
8584                           ATMEL_AT45DB0X1B_PAGE_POS) +
8585                         (offset % tp->nvram_pagesize);
8586         }
8587
8588         if (offset > NVRAM_ADDR_MSK)
8589                 return -EINVAL;
8590
8591         tg3_nvram_lock(tp);
8592
8593         tg3_enable_nvram_access(tp);
8594
8595         tw32(NVRAM_ADDR, offset);
8596         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8597                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8598
8599         if (ret == 0)
8600                 *val = swab32(tr32(NVRAM_RDDATA));
8601
8602         tg3_nvram_unlock(tp);
8603
8604         tg3_disable_nvram_access(tp);
8605
8606         return ret;
8607 }
8608
8609 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8610                                     u32 offset, u32 len, u8 *buf)
8611 {
8612         int i, j, rc = 0;
8613         u32 val;
8614
8615         for (i = 0; i < len; i += 4) {
8616                 u32 addr, data;
8617
8618                 addr = offset + i;
8619
8620                 memcpy(&data, buf + i, 4);
8621
8622                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8623
8624                 val = tr32(GRC_EEPROM_ADDR);
8625                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8626
8627                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8628                         EEPROM_ADDR_READ);
8629                 tw32(GRC_EEPROM_ADDR, val |
8630                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
8631                         (addr & EEPROM_ADDR_ADDR_MASK) |
8632                         EEPROM_ADDR_START |
8633                         EEPROM_ADDR_WRITE);
8634
8635                 for (j = 0; j < 10000; j++) {
8636                         val = tr32(GRC_EEPROM_ADDR);
8637
8638                         if (val & EEPROM_ADDR_COMPLETE)
8639                                 break;
8640                         udelay(100);
8641                 }
8642                 if (!(val & EEPROM_ADDR_COMPLETE)) {
8643                         rc = -EBUSY;
8644                         break;
8645                 }
8646         }
8647
8648         return rc;
8649 }
8650
8651 /* offset and length are dword aligned */
8652 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8653                 u8 *buf)
8654 {
8655         int ret = 0;
8656         u32 pagesize = tp->nvram_pagesize;
8657         u32 pagemask = pagesize - 1;
8658         u32 nvram_cmd;
8659         u8 *tmp;
8660
8661         tmp = kmalloc(pagesize, GFP_KERNEL);
8662         if (tmp == NULL)
8663                 return -ENOMEM;
8664
8665         while (len) {
8666                 int j;
8667                 u32 phy_addr, page_off, size;
8668
8669                 phy_addr = offset & ~pagemask;
8670
8671                 for (j = 0; j < pagesize; j += 4) {
8672                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
8673                                                 (u32 *) (tmp + j))))
8674                                 break;
8675                 }
8676                 if (ret)
8677                         break;
8678
8679                 page_off = offset & pagemask;
8680                 size = pagesize;
8681                 if (len < size)
8682                         size = len;
8683
8684                 len -= size;
8685
8686                 memcpy(tmp + page_off, buf, size);
8687
8688                 offset = offset + (pagesize - page_off);
8689
8690                 tg3_enable_nvram_access(tp);
8691
8692                 /*
8693                  * Before we can erase the flash page, we need
8694                  * to issue a special "write enable" command.
8695                  */
8696                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8697
8698                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8699                         break;
8700
8701                 /* Erase the target page */
8702                 tw32(NVRAM_ADDR, phy_addr);
8703
8704                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8705                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8706
8707                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8708                         break;
8709
8710                 /* Issue another write enable to start the write. */
8711                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8712
8713                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8714                         break;
8715
8716                 for (j = 0; j < pagesize; j += 4) {
8717                         u32 data;
8718
8719                         data = *((u32 *) (tmp + j));
8720                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
8721
8722                         tw32(NVRAM_ADDR, phy_addr + j);
8723
8724                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8725                                 NVRAM_CMD_WR;
8726
8727                         if (j == 0)
8728                                 nvram_cmd |= NVRAM_CMD_FIRST;
8729                         else if (j == (pagesize - 4))
8730                                 nvram_cmd |= NVRAM_CMD_LAST;
8731
8732                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8733                                 break;
8734                 }
8735                 if (ret)
8736                         break;
8737         }
8738
8739         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8740         tg3_nvram_exec_cmd(tp, nvram_cmd);
8741
8742         kfree(tmp);
8743
8744         return ret;
8745 }
8746
8747 /* offset and length are dword aligned */
8748 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8749                 u8 *buf)
8750 {
8751         int i, ret = 0;
8752
8753         for (i = 0; i < len; i += 4, offset += 4) {
8754                 u32 data, page_off, phy_addr, nvram_cmd;
8755
8756                 memcpy(&data, buf + i, 4);
8757                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8758
8759                 page_off = offset % tp->nvram_pagesize;
8760
8761                 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8762                         (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8763
8764                         phy_addr = ((offset / tp->nvram_pagesize) <<
8765                                     ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8766                 }
8767                 else {
8768                         phy_addr = offset;
8769                 }
8770
8771                 tw32(NVRAM_ADDR, phy_addr);
8772
8773                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8774
8775                 if ((page_off == 0) || (i == 0))
8776                         nvram_cmd |= NVRAM_CMD_FIRST;
8777                 else if (page_off == (tp->nvram_pagesize - 4))
8778                         nvram_cmd |= NVRAM_CMD_LAST;
8779
8780                 if (i == (len - 4))
8781                         nvram_cmd |= NVRAM_CMD_LAST;
8782
8783                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
8784                     (tp->nvram_jedecnum == JEDEC_ST) &&
8785                     (nvram_cmd & NVRAM_CMD_FIRST)) {
8786
8787                         if ((ret = tg3_nvram_exec_cmd(tp,
8788                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8789                                 NVRAM_CMD_DONE)))
8790
8791                                 break;
8792                 }
8793                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8794                         /* We always do complete word writes to eeprom. */
8795                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8796                 }
8797
8798                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8799                         break;
8800         }
8801         return ret;
8802 }
8803
8804 /* offset and length are dword aligned */
8805 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8806 {
8807         int ret;
8808
8809         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8810                 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8811                 return -EINVAL;
8812         }
8813
8814         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8815                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8816                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
8817                 udelay(40);
8818         }
8819
8820         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8821                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8822         }
8823         else {
8824                 u32 grc_mode;
8825
8826                 tg3_nvram_lock(tp);
8827
8828                 tg3_enable_nvram_access(tp);
8829                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8830                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
8831                         tw32(NVRAM_WRITE1, 0x406);
8832
8833                 grc_mode = tr32(GRC_MODE);
8834                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8835
8836                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8837                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8838
8839                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
8840                                 buf);
8841                 }
8842                 else {
8843                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8844                                 buf);
8845                 }
8846
8847                 grc_mode = tr32(GRC_MODE);
8848                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8849
8850                 tg3_disable_nvram_access(tp);
8851                 tg3_nvram_unlock(tp);
8852         }
8853
8854         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8855                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8856                 udelay(40);
8857         }
8858
8859         return ret;
8860 }
8861
8862 struct subsys_tbl_ent {
8863         u16 subsys_vendor, subsys_devid;
8864         u32 phy_id;
8865 };
8866
8867 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8868         /* Broadcom boards. */
8869         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8870         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8871         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8872         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
8873         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8874         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8875         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
8876         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8877         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8878         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8879         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8880
8881         /* 3com boards. */
8882         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8883         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8884         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
8885         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8886         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8887
8888         /* DELL boards. */
8889         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8890         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8891         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8892         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8893
8894         /* Compaq boards. */
8895         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8896         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8897         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
8898         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
8899         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
8900
8901         /* IBM boards. */
8902         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
8903 };
8904
8905 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
8906 {
8907         int i;
8908
8909         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
8910                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
8911                      tp->pdev->subsystem_vendor) &&
8912                     (subsys_id_to_phy_id[i].subsys_devid ==
8913                      tp->pdev->subsystem_device))
8914                         return &subsys_id_to_phy_id[i];
8915         }
8916         return NULL;
8917 }
8918
8919 /* Since this function may be called in D3-hot power state during
8920  * tg3_init_one(), only config cycles are allowed.
8921  */
8922 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
8923 {
8924         u32 val;
8925
8926         /* Make sure register accesses (indirect or otherwise)
8927          * will function correctly.
8928          */
8929         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8930                                tp->misc_host_ctrl);
8931
8932         tp->phy_id = PHY_ID_INVALID;
8933         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8934
8935         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8936         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8937                 u32 nic_cfg, led_cfg;
8938                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
8939                 int eeprom_phy_serdes = 0;
8940
8941                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8942                 tp->nic_sram_data_cfg = nic_cfg;
8943
8944                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
8945                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
8946                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8947                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8948                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
8949                     (ver > 0) && (ver < 0x100))
8950                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
8951
8952                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
8953                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
8954                         eeprom_phy_serdes = 1;
8955
8956                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
8957                 if (nic_phy_id != 0) {
8958                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
8959                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
8960
8961                         eeprom_phy_id  = (id1 >> 16) << 10;
8962                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
8963                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
8964                 } else
8965                         eeprom_phy_id = 0;
8966
8967                 tp->phy_id = eeprom_phy_id;
8968                 if (eeprom_phy_serdes) {
8969                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8970                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
8971                         else
8972                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8973                 }
8974
8975                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8976                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
8977                                     SHASTA_EXT_LED_MODE_MASK);
8978                 else
8979                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
8980
8981                 switch (led_cfg) {
8982                 default:
8983                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
8984                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8985                         break;
8986
8987                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
8988                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8989                         break;
8990
8991                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
8992                         tp->led_ctrl = LED_CTRL_MODE_MAC;
8993
8994                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
8995                          * read on some older 5700/5701 bootcode.
8996                          */
8997                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
8998                             ASIC_REV_5700 ||
8999                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
9000                             ASIC_REV_5701)
9001                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9002
9003                         break;
9004
9005                 case SHASTA_EXT_LED_SHARED:
9006                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
9007                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9008                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9009                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9010                                                  LED_CTRL_MODE_PHY_2);
9011                         break;
9012
9013                 case SHASTA_EXT_LED_MAC:
9014                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9015                         break;
9016
9017                 case SHASTA_EXT_LED_COMBO:
9018                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
9019                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9020                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9021                                                  LED_CTRL_MODE_PHY_2);
9022                         break;
9023
9024                 };
9025
9026                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9027                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9028                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9029                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9030
9031                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9032                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9033                     (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
9034                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9035
9036                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9037                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
9038                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9039                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9040                 }
9041                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9042                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9043
9044                 if (cfg2 & (1 << 17))
9045                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9046
9047                 /* serdes signal pre-emphasis in register 0x590 set by */
9048                 /* bootcode if bit 18 is set */
9049                 if (cfg2 & (1 << 18))
9050                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9051         }
9052 }
9053
9054 static int __devinit tg3_phy_probe(struct tg3 *tp)
9055 {
9056         u32 hw_phy_id_1, hw_phy_id_2;
9057         u32 hw_phy_id, hw_phy_id_masked;
9058         int err;
9059
9060         /* Reading the PHY ID register can conflict with ASF
9061          * firwmare access to the PHY hardware.
9062          */
9063         err = 0;
9064         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9065                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9066         } else {
9067                 /* Now read the physical PHY_ID from the chip and verify
9068                  * that it is sane.  If it doesn't look good, we fall back
9069                  * to either the hard-coded table based PHY_ID and failing
9070                  * that the value found in the eeprom area.
9071                  */
9072                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9073                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9074
9075                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
9076                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9077                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
9078
9079                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9080         }
9081
9082         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9083                 tp->phy_id = hw_phy_id;
9084                 if (hw_phy_id_masked == PHY_ID_BCM8002)
9085                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9086                 else
9087                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
9088         } else {
9089                 if (tp->phy_id != PHY_ID_INVALID) {
9090                         /* Do nothing, phy ID already set up in
9091                          * tg3_get_eeprom_hw_cfg().
9092                          */
9093                 } else {
9094                         struct subsys_tbl_ent *p;
9095
9096                         /* No eeprom signature?  Try the hardcoded
9097                          * subsys device table.
9098                          */
9099                         p = lookup_by_subsys(tp);
9100                         if (!p)
9101                                 return -ENODEV;
9102
9103                         tp->phy_id = p->phy_id;
9104                         if (!tp->phy_id ||
9105                             tp->phy_id == PHY_ID_BCM8002)
9106                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9107                 }
9108         }
9109
9110         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
9111             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9112                 u32 bmsr, adv_reg, tg3_ctrl;
9113
9114                 tg3_readphy(tp, MII_BMSR, &bmsr);
9115                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9116                     (bmsr & BMSR_LSTATUS))
9117                         goto skip_phy_reset;
9118
9119                 err = tg3_phy_reset(tp);
9120                 if (err)
9121                         return err;
9122
9123                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9124                            ADVERTISE_100HALF | ADVERTISE_100FULL |
9125                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9126                 tg3_ctrl = 0;
9127                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9128                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9129                                     MII_TG3_CTRL_ADV_1000_FULL);
9130                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9131                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9132                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9133                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
9134                 }
9135
9136                 if (!tg3_copper_is_advertising_all(tp)) {
9137                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9138
9139                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9140                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9141
9142                         tg3_writephy(tp, MII_BMCR,
9143                                      BMCR_ANENABLE | BMCR_ANRESTART);
9144                 }
9145                 tg3_phy_set_wirespeed(tp);
9146
9147                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9148                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9149                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9150         }
9151
9152 skip_phy_reset:
9153         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9154                 err = tg3_init_5401phy_dsp(tp);
9155                 if (err)
9156                         return err;
9157         }
9158
9159         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9160                 err = tg3_init_5401phy_dsp(tp);
9161         }
9162
9163         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9164                 tp->link_config.advertising =
9165                         (ADVERTISED_1000baseT_Half |
9166                          ADVERTISED_1000baseT_Full |
9167                          ADVERTISED_Autoneg |
9168                          ADVERTISED_FIBRE);
9169         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9170                 tp->link_config.advertising &=
9171                         ~(ADVERTISED_1000baseT_Half |
9172                           ADVERTISED_1000baseT_Full);
9173
9174         return err;
9175 }
9176
9177 static void __devinit tg3_read_partno(struct tg3 *tp)
9178 {
9179         unsigned char vpd_data[256];
9180         int i;
9181
9182         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9183                 /* Sun decided not to put the necessary bits in the
9184                  * NVRAM of their onboard tg3 parts :(
9185                  */
9186                 strcpy(tp->board_part_number, "Sun 570X");
9187                 return;
9188         }
9189
9190         for (i = 0; i < 256; i += 4) {
9191                 u32 tmp;
9192
9193                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9194                         goto out_not_found;
9195
9196                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
9197                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
9198                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9199                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9200         }
9201
9202         /* Now parse and find the part number. */
9203         for (i = 0; i < 256; ) {
9204                 unsigned char val = vpd_data[i];
9205                 int block_end;
9206
9207                 if (val == 0x82 || val == 0x91) {
9208                         i = (i + 3 +
9209                              (vpd_data[i + 1] +
9210                               (vpd_data[i + 2] << 8)));
9211                         continue;
9212                 }
9213
9214                 if (val != 0x90)
9215                         goto out_not_found;
9216
9217                 block_end = (i + 3 +
9218                              (vpd_data[i + 1] +
9219                               (vpd_data[i + 2] << 8)));
9220                 i += 3;
9221                 while (i < block_end) {
9222                         if (vpd_data[i + 0] == 'P' &&
9223                             vpd_data[i + 1] == 'N') {
9224                                 int partno_len = vpd_data[i + 2];
9225
9226                                 if (partno_len > 24)
9227                                         goto out_not_found;
9228
9229                                 memcpy(tp->board_part_number,
9230                                        &vpd_data[i + 3],
9231                                        partno_len);
9232
9233                                 /* Success. */
9234                                 return;
9235                         }
9236                 }
9237
9238                 /* Part number not found. */
9239                 goto out_not_found;
9240         }
9241
9242 out_not_found:
9243         strcpy(tp->board_part_number, "none");
9244 }
9245
9246 #ifdef CONFIG_SPARC64
9247 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9248 {
9249         struct pci_dev *pdev = tp->pdev;
9250         struct pcidev_cookie *pcp = pdev->sysdata;
9251
9252         if (pcp != NULL) {
9253                 int node = pcp->prom_node;
9254                 u32 venid;
9255                 int err;
9256
9257                 err = prom_getproperty(node, "subsystem-vendor-id",
9258                                        (char *) &venid, sizeof(venid));
9259                 if (err == 0 || err == -1)
9260                         return 0;
9261                 if (venid == PCI_VENDOR_ID_SUN)
9262                         return 1;
9263         }
9264         return 0;
9265 }
9266 #endif
9267
9268 static int __devinit tg3_get_invariants(struct tg3 *tp)
9269 {
9270         static struct pci_device_id write_reorder_chipsets[] = {
9271                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9272                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
9273                 { },
9274         };
9275         u32 misc_ctrl_reg;
9276         u32 cacheline_sz_reg;
9277         u32 pci_state_reg, grc_misc_cfg;
9278         u32 val;
9279         u16 pci_cmd;
9280         int err;
9281
9282 #ifdef CONFIG_SPARC64
9283         if (tg3_is_sun_570X(tp))
9284                 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
9285 #endif
9286
9287         /* If we have an AMD 762 chipset, write
9288          * reordering to the mailbox registers done by the host
9289          * controller can cause major troubles.  We read back from
9290          * every mailbox register write to force the writes to be
9291          * posted to the chip in order.
9292          */
9293         if (pci_dev_present(write_reorder_chipsets))
9294                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
9295
9296         /* Force memory write invalidate off.  If we leave it on,
9297          * then on 5700_BX chips we have to enable a workaround.
9298          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
9299          * to match the cacheline size.  The Broadcom driver have this
9300          * workaround but turns MWI off all the times so never uses
9301          * it.  This seems to suggest that the workaround is insufficient.
9302          */
9303         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9304         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
9305         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9306
9307         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
9308          * has the register indirect write enable bit set before
9309          * we try to access any of the MMIO registers.  It is also
9310          * critical that the PCI-X hw workaround situation is decided
9311          * before that as well.
9312          */
9313         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9314                               &misc_ctrl_reg);
9315
9316         tp->pci_chip_rev_id = (misc_ctrl_reg >>
9317                                MISC_HOST_CTRL_CHIPREV_SHIFT);
9318
9319         /* Wrong chip ID in 5752 A0. This code can be removed later
9320          * as A0 is not in production.
9321          */
9322         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
9323                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
9324
9325         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
9326          * we need to disable memory and use config. cycles
9327          * only to access all registers. The 5702/03 chips
9328          * can mistakenly decode the special cycles from the
9329          * ICH chipsets as memory write cycles, causing corruption
9330          * of register and memory space. Only certain ICH bridges
9331          * will drive special cycles with non-zero data during the
9332          * address phase which can fall within the 5703's address
9333          * range. This is not an ICH bug as the PCI spec allows
9334          * non-zero address during special cycles. However, only
9335          * these ICH bridges are known to drive non-zero addresses
9336          * during special cycles.
9337          *
9338          * Since special cycles do not cross PCI bridges, we only
9339          * enable this workaround if the 5703 is on the secondary
9340          * bus of these ICH bridges.
9341          */
9342         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
9343             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
9344                 static struct tg3_dev_id {
9345                         u32     vendor;
9346                         u32     device;
9347                         u32     rev;
9348                 } ich_chipsets[] = {
9349                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
9350                           PCI_ANY_ID },
9351                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
9352                           PCI_ANY_ID },
9353                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
9354                           0xa },
9355                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
9356                           PCI_ANY_ID },
9357                         { },
9358                 };
9359                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
9360                 struct pci_dev *bridge = NULL;
9361
9362                 while (pci_id->vendor != 0) {
9363                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
9364                                                 bridge);
9365                         if (!bridge) {
9366                                 pci_id++;
9367                                 continue;
9368                         }
9369                         if (pci_id->rev != PCI_ANY_ID) {
9370                                 u8 rev;
9371
9372                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
9373                                                      &rev);
9374                                 if (rev > pci_id->rev)
9375                                         continue;
9376                         }
9377                         if (bridge->subordinate &&
9378                             (bridge->subordinate->number ==
9379                              tp->pdev->bus->number)) {
9380
9381                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
9382                                 pci_dev_put(bridge);
9383                                 break;
9384                         }
9385                 }
9386         }
9387
9388         /* Find msi capability. */
9389         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9390                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
9391
9392         /* Initialize misc host control in PCI block. */
9393         tp->misc_host_ctrl |= (misc_ctrl_reg &
9394                                MISC_HOST_CTRL_CHIPREV);
9395         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9396                                tp->misc_host_ctrl);
9397
9398         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9399                               &cacheline_sz_reg);
9400
9401         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
9402         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
9403         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
9404         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
9405
9406         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
9407             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
9408             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9409                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
9410
9411         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
9412             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
9413                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
9414
9415         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9416                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
9417
9418         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
9419             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
9420             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
9421                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
9422
9423         if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
9424                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
9425
9426         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9427             tp->pci_lat_timer < 64) {
9428                 tp->pci_lat_timer = 64;
9429
9430                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
9431                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
9432                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
9433                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
9434
9435                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9436                                        cacheline_sz_reg);
9437         }
9438
9439         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9440                               &pci_state_reg);
9441
9442         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
9443                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
9444
9445                 /* If this is a 5700 BX chipset, and we are in PCI-X
9446                  * mode, enable register write workaround.
9447                  *
9448                  * The workaround is to use indirect register accesses
9449                  * for all chip writes not to mailbox registers.
9450                  */
9451                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
9452                         u32 pm_reg;
9453                         u16 pci_cmd;
9454
9455                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9456
9457                         /* The chip can have it's power management PCI config
9458                          * space registers clobbered due to this bug.
9459                          * So explicitly force the chip into D0 here.
9460                          */
9461                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9462                                               &pm_reg);
9463                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
9464                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9465                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9466                                                pm_reg);
9467
9468                         /* Also, force SERR#/PERR# in PCI command. */
9469                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9470                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
9471                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9472                 }
9473         }
9474
9475         /* 5700 BX chips need to have their TX producer index mailboxes
9476          * written twice to workaround a bug.
9477          */
9478         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9479                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9480
9481         /* Back to back register writes can cause problems on this chip,
9482          * the workaround is to read back all reg writes except those to
9483          * mailbox regs.  See tg3_write_indirect_reg32().
9484          *
9485          * PCI Express 5750_A0 rev chips need this workaround too.
9486          */
9487         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9488             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
9489              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
9490                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
9491
9492         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
9493                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
9494         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
9495                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
9496
9497         /* Chip-specific fixup from Broadcom driver */
9498         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
9499             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
9500                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
9501                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
9502         }
9503
9504         /* Default fast path register access methods */
9505         tp->read32 = tg3_read32;
9506         tp->write32 = tg3_write32;
9507         tp->read32_mbox = tg3_read32;
9508         tp->write32_mbox = tg3_write32;
9509         tp->write32_tx_mbox = tg3_write32;
9510         tp->write32_rx_mbox = tg3_write32;
9511
9512         /* Various workaround register access methods */
9513         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
9514                 tp->write32 = tg3_write_indirect_reg32;
9515         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
9516                 tp->write32 = tg3_write_flush_reg32;
9517
9518         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
9519             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
9520                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9521                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
9522                         tp->write32_rx_mbox = tg3_write_flush_reg32;
9523         }
9524
9525         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
9526                 tp->read32 = tg3_read_indirect_reg32;
9527                 tp->write32 = tg3_write_indirect_reg32;
9528                 tp->read32_mbox = tg3_read_indirect_mbox;
9529                 tp->write32_mbox = tg3_write_indirect_mbox;
9530                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
9531                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
9532
9533                 iounmap(tp->regs);
9534                 tp->regs = 0;
9535
9536                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9537                 pci_cmd &= ~PCI_COMMAND_MEMORY;
9538                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9539         }
9540
9541         /* Get eeprom hw config before calling tg3_set_power_state().
9542          * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
9543          * determined before calling tg3_set_power_state() so that
9544          * we know whether or not to switch out of Vaux power.
9545          * When the flag is set, it means that GPIO1 is used for eeprom
9546          * write protect and also implies that it is a LOM where GPIOs
9547          * are not used to switch power.
9548          */
9549         tg3_get_eeprom_hw_cfg(tp);
9550
9551         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
9552          * GPIO1 driven high will bring 5700's external PHY out of reset.
9553          * It is also used as eeprom write protect on LOMs.
9554          */
9555         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
9556         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9557             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
9558                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9559                                        GRC_LCLCTRL_GPIO_OUTPUT1);
9560         /* Unused GPIO3 must be driven as output on 5752 because there
9561          * are no pull-up resistors on unused GPIO pins.
9562          */
9563         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9564                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
9565
9566         /* Force the chip into D0. */
9567         err = tg3_set_power_state(tp, 0);
9568         if (err) {
9569                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
9570                        pci_name(tp->pdev));
9571                 return err;
9572         }
9573
9574         /* 5700 B0 chips do not support checksumming correctly due
9575          * to hardware bugs.
9576          */
9577         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9578                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9579
9580         /* Pseudo-header checksum is done by hardware logic and not
9581          * the offload processers, so make the chip do the pseudo-
9582          * header checksums on receive.  For transmit it is more
9583          * convenient to do the pseudo-header checksum in software
9584          * as Linux does that on transmit for us in all cases.
9585          */
9586         tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9587         tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9588
9589         /* Derive initial jumbo mode from MTU assigned in
9590          * ether_setup() via the alloc_etherdev() call
9591          */
9592         if (tp->dev->mtu > ETH_DATA_LEN &&
9593             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780)
9594                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
9595
9596         /* Determine WakeOnLan speed to use. */
9597         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9598             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9599             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9600             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9601                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9602         } else {
9603                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9604         }
9605
9606         /* A few boards don't want Ethernet@WireSpeed phy feature */
9607         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9608             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9609              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
9610              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
9611             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9612                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9613
9614         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9615             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9616                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9617         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9618                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9619
9620         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9621                 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9622
9623         tp->coalesce_mode = 0;
9624         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9625             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9626                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9627
9628         /* Initialize MAC MI mode, polling disabled. */
9629         tw32_f(MAC_MI_MODE, tp->mi_mode);
9630         udelay(80);
9631
9632         /* Initialize data/descriptor byte/word swapping. */
9633         val = tr32(GRC_MODE);
9634         val &= GRC_MODE_HOST_STACKUP;
9635         tw32(GRC_MODE, val | tp->grc_mode);
9636
9637         tg3_switch_clocks(tp);
9638
9639         /* Clear this out for sanity. */
9640         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9641
9642         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9643                               &pci_state_reg);
9644         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9645             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9646                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9647
9648                 if (chiprevid == CHIPREV_ID_5701_A0 ||
9649                     chiprevid == CHIPREV_ID_5701_B0 ||
9650                     chiprevid == CHIPREV_ID_5701_B2 ||
9651                     chiprevid == CHIPREV_ID_5701_B5) {
9652                         void __iomem *sram_base;
9653
9654                         /* Write some dummy words into the SRAM status block
9655                          * area, see if it reads back correctly.  If the return
9656                          * value is bad, force enable the PCIX workaround.
9657                          */
9658                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9659
9660                         writel(0x00000000, sram_base);
9661                         writel(0x00000000, sram_base + 4);
9662                         writel(0xffffffff, sram_base + 4);
9663                         if (readl(sram_base) != 0x00000000)
9664                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9665                 }
9666         }
9667
9668         udelay(50);
9669         tg3_nvram_init(tp);
9670
9671         grc_misc_cfg = tr32(GRC_MISC_CFG);
9672         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9673
9674         /* Broadcom's driver says that CIOBE multisplit has a bug */
9675 #if 0
9676         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9677             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9678                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9679                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9680         }
9681 #endif
9682         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9683             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9684              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9685                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9686
9687         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9688             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9689                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9690         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9691                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9692                                       HOSTCC_MODE_CLRTICK_TXBD);
9693
9694                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9695                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9696                                        tp->misc_host_ctrl);
9697         }
9698
9699         /* these are limited to 10/100 only */
9700         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9701              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9702             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9703              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9704              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9705               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9706               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9707             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9708              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9709               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9710                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9711
9712         err = tg3_phy_probe(tp);
9713         if (err) {
9714                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9715                        pci_name(tp->pdev), err);
9716                 /* ... but do not return immediately ... */
9717         }
9718
9719         tg3_read_partno(tp);
9720
9721         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9722                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9723         } else {
9724                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9725                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9726                 else
9727                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9728         }
9729
9730         /* 5700 {AX,BX} chips have a broken status block link
9731          * change bit implementation, so we must use the
9732          * status register in those cases.
9733          */
9734         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9735                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9736         else
9737                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9738
9739         /* The led_ctrl is set during tg3_phy_probe, here we might
9740          * have to force the link status polling mechanism based
9741          * upon subsystem IDs.
9742          */
9743         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9744             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9745                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9746                                   TG3_FLAG_USE_LINKCHG_REG);
9747         }
9748
9749         /* For all SERDES we poll the MAC status register. */
9750         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9751                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9752         else
9753                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9754
9755         /* It seems all chips can get confused if TX buffers
9756          * straddle the 4GB address boundary in some cases.
9757          */
9758         tp->dev->hard_start_xmit = tg3_start_xmit;
9759
9760         tp->rx_offset = 2;
9761         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9762             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9763                 tp->rx_offset = 0;
9764
9765         /* By default, disable wake-on-lan.  User can change this
9766          * using ETHTOOL_SWOL.
9767          */
9768         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9769
9770         return err;
9771 }
9772
9773 #ifdef CONFIG_SPARC64
9774 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9775 {
9776         struct net_device *dev = tp->dev;
9777         struct pci_dev *pdev = tp->pdev;
9778         struct pcidev_cookie *pcp = pdev->sysdata;
9779
9780         if (pcp != NULL) {
9781                 int node = pcp->prom_node;
9782
9783                 if (prom_getproplen(node, "local-mac-address") == 6) {
9784                         prom_getproperty(node, "local-mac-address",
9785                                          dev->dev_addr, 6);
9786                         return 0;
9787                 }
9788         }
9789         return -ENODEV;
9790 }
9791
9792 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9793 {
9794         struct net_device *dev = tp->dev;
9795
9796         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
9797         return 0;
9798 }
9799 #endif
9800
9801 static int __devinit tg3_get_device_address(struct tg3 *tp)
9802 {
9803         struct net_device *dev = tp->dev;
9804         u32 hi, lo, mac_offset;
9805
9806 #ifdef CONFIG_SPARC64
9807         if (!tg3_get_macaddr_sparc(tp))
9808                 return 0;
9809 #endif
9810
9811         mac_offset = 0x7c;
9812         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9813              !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
9814             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
9815                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9816                         mac_offset = 0xcc;
9817                 if (tg3_nvram_lock(tp))
9818                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9819                 else
9820                         tg3_nvram_unlock(tp);
9821         }
9822
9823         /* First try to get it from MAC address mailbox. */
9824         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9825         if ((hi >> 16) == 0x484b) {
9826                 dev->dev_addr[0] = (hi >>  8) & 0xff;
9827                 dev->dev_addr[1] = (hi >>  0) & 0xff;
9828
9829                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9830                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9831                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9832                 dev->dev_addr[4] = (lo >>  8) & 0xff;
9833                 dev->dev_addr[5] = (lo >>  0) & 0xff;
9834         }
9835         /* Next, try NVRAM. */
9836         else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9837                  !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9838                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9839                 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9840                 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9841                 dev->dev_addr[2] = ((lo >>  0) & 0xff);
9842                 dev->dev_addr[3] = ((lo >>  8) & 0xff);
9843                 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9844                 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9845         }
9846         /* Finally just fetch it out of the MAC control regs. */
9847         else {
9848                 hi = tr32(MAC_ADDR_0_HIGH);
9849                 lo = tr32(MAC_ADDR_0_LOW);
9850
9851                 dev->dev_addr[5] = lo & 0xff;
9852                 dev->dev_addr[4] = (lo >> 8) & 0xff;
9853                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9854                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9855                 dev->dev_addr[1] = hi & 0xff;
9856                 dev->dev_addr[0] = (hi >> 8) & 0xff;
9857         }
9858
9859         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9860 #ifdef CONFIG_SPARC64
9861                 if (!tg3_get_default_macaddr_sparc(tp))
9862                         return 0;
9863 #endif
9864                 return -EINVAL;
9865         }
9866         return 0;
9867 }
9868
9869 #define BOUNDARY_SINGLE_CACHELINE       1
9870 #define BOUNDARY_MULTI_CACHELINE        2
9871
9872 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9873 {
9874         int cacheline_size;
9875         u8 byte;
9876         int goal;
9877
9878         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9879         if (byte == 0)
9880                 cacheline_size = 1024;
9881         else
9882                 cacheline_size = (int) byte * 4;
9883
9884         /* On 5703 and later chips, the boundary bits have no
9885          * effect.
9886          */
9887         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9888             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9889             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9890                 goto out;
9891
9892 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9893         goal = BOUNDARY_MULTI_CACHELINE;
9894 #else
9895 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9896         goal = BOUNDARY_SINGLE_CACHELINE;
9897 #else
9898         goal = 0;
9899 #endif
9900 #endif
9901
9902         if (!goal)
9903                 goto out;
9904
9905         /* PCI controllers on most RISC systems tend to disconnect
9906          * when a device tries to burst across a cache-line boundary.
9907          * Therefore, letting tg3 do so just wastes PCI bandwidth.
9908          *
9909          * Unfortunately, for PCI-E there are only limited
9910          * write-side controls for this, and thus for reads
9911          * we will still get the disconnects.  We'll also waste
9912          * these PCI cycles for both read and write for chips
9913          * other than 5700 and 5701 which do not implement the
9914          * boundary bits.
9915          */
9916         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
9917             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
9918                 switch (cacheline_size) {
9919                 case 16:
9920                 case 32:
9921                 case 64:
9922                 case 128:
9923                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9924                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
9925                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
9926                         } else {
9927                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9928                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9929                         }
9930                         break;
9931
9932                 case 256:
9933                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
9934                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
9935                         break;
9936
9937                 default:
9938                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9939                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9940                         break;
9941                 };
9942         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9943                 switch (cacheline_size) {
9944                 case 16:
9945                 case 32:
9946                 case 64:
9947                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9948                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9949                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
9950                                 break;
9951                         }
9952                         /* fallthrough */
9953                 case 128:
9954                 default:
9955                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9956                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
9957                         break;
9958                 };
9959         } else {
9960                 switch (cacheline_size) {
9961                 case 16:
9962                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9963                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
9964                                         DMA_RWCTRL_WRITE_BNDRY_16);
9965                                 break;
9966                         }
9967                         /* fallthrough */
9968                 case 32:
9969                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9970                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
9971                                         DMA_RWCTRL_WRITE_BNDRY_32);
9972                                 break;
9973                         }
9974                         /* fallthrough */
9975                 case 64:
9976                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9977                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
9978                                         DMA_RWCTRL_WRITE_BNDRY_64);
9979                                 break;
9980                         }
9981                         /* fallthrough */
9982                 case 128:
9983                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9984                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
9985                                         DMA_RWCTRL_WRITE_BNDRY_128);
9986                                 break;
9987                         }
9988                         /* fallthrough */
9989                 case 256:
9990                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
9991                                 DMA_RWCTRL_WRITE_BNDRY_256);
9992                         break;
9993                 case 512:
9994                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
9995                                 DMA_RWCTRL_WRITE_BNDRY_512);
9996                         break;
9997                 case 1024:
9998                 default:
9999                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10000                                 DMA_RWCTRL_WRITE_BNDRY_1024);
10001                         break;
10002                 };
10003         }
10004
10005 out:
10006         return val;
10007 }
10008
10009 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10010 {
10011         struct tg3_internal_buffer_desc test_desc;
10012         u32 sram_dma_descs;
10013         int i, ret;
10014
10015         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10016
10017         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10018         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10019         tw32(RDMAC_STATUS, 0);
10020         tw32(WDMAC_STATUS, 0);
10021
10022         tw32(BUFMGR_MODE, 0);
10023         tw32(FTQ_RESET, 0);
10024
10025         test_desc.addr_hi = ((u64) buf_dma) >> 32;
10026         test_desc.addr_lo = buf_dma & 0xffffffff;
10027         test_desc.nic_mbuf = 0x00002100;
10028         test_desc.len = size;
10029
10030         /*
10031          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10032          * the *second* time the tg3 driver was getting loaded after an
10033          * initial scan.
10034          *
10035          * Broadcom tells me:
10036          *   ...the DMA engine is connected to the GRC block and a DMA
10037          *   reset may affect the GRC block in some unpredictable way...
10038          *   The behavior of resets to individual blocks has not been tested.
10039          *
10040          * Broadcom noted the GRC reset will also reset all sub-components.
10041          */
10042         if (to_device) {
10043                 test_desc.cqid_sqid = (13 << 8) | 2;
10044
10045                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10046                 udelay(40);
10047         } else {
10048                 test_desc.cqid_sqid = (16 << 8) | 7;
10049
10050                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10051                 udelay(40);
10052         }
10053         test_desc.flags = 0x00000005;
10054
10055         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10056                 u32 val;
10057
10058                 val = *(((u32 *)&test_desc) + i);
10059                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10060                                        sram_dma_descs + (i * sizeof(u32)));
10061                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10062         }
10063         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10064
10065         if (to_device) {
10066                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10067         } else {
10068                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10069         }
10070
10071         ret = -ENODEV;
10072         for (i = 0; i < 40; i++) {
10073                 u32 val;
10074
10075                 if (to_device)
10076                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10077                 else
10078                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10079                 if ((val & 0xffff) == sram_dma_descs) {
10080                         ret = 0;
10081                         break;
10082                 }
10083
10084                 udelay(100);
10085         }
10086
10087         return ret;
10088 }
10089
10090 #define TEST_BUFFER_SIZE        0x2000
10091
10092 static int __devinit tg3_test_dma(struct tg3 *tp)
10093 {
10094         dma_addr_t buf_dma;
10095         u32 *buf, saved_dma_rwctrl;
10096         int ret;
10097
10098         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10099         if (!buf) {
10100                 ret = -ENOMEM;
10101                 goto out_nofree;
10102         }
10103
10104         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10105                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10106
10107         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
10108
10109         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10110                 /* DMA read watermark not used on PCIE */
10111                 tp->dma_rwctrl |= 0x00180000;
10112         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
10113                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10114                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
10115                         tp->dma_rwctrl |= 0x003f0000;
10116                 else
10117                         tp->dma_rwctrl |= 0x003f000f;
10118         } else {
10119                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10120                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10121                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10122
10123                         if (ccval == 0x6 || ccval == 0x7)
10124                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10125
10126                         /* Set bit 23 to enable PCIX hw bug fix */
10127                         tp->dma_rwctrl |= 0x009f0000;
10128                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10129                         /* 5780 always in PCIX mode */
10130                         tp->dma_rwctrl |= 0x00144000;
10131                 } else {
10132                         tp->dma_rwctrl |= 0x001b000f;
10133                 }
10134         }
10135
10136         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10137             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10138                 tp->dma_rwctrl &= 0xfffffff0;
10139
10140         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10141             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10142                 /* Remove this if it causes problems for some boards. */
10143                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10144
10145                 /* On 5700/5701 chips, we need to set this bit.
10146                  * Otherwise the chip will issue cacheline transactions
10147                  * to streamable DMA memory with not all the byte
10148                  * enables turned on.  This is an error on several
10149                  * RISC PCI controllers, in particular sparc64.
10150                  *
10151                  * On 5703/5704 chips, this bit has been reassigned
10152                  * a different meaning.  In particular, it is used
10153                  * on those chips to enable a PCI-X workaround.
10154                  */
10155                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10156         }
10157
10158         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10159
10160 #if 0
10161         /* Unneeded, already done by tg3_get_invariants.  */
10162         tg3_switch_clocks(tp);
10163 #endif
10164
10165         ret = 0;
10166         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10167             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10168                 goto out;
10169
10170         /* It is best to perform DMA test with maximum write burst size
10171          * to expose the 5700/5701 write DMA bug.
10172          */
10173         saved_dma_rwctrl = tp->dma_rwctrl;
10174         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10175         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10176
10177         while (1) {
10178                 u32 *p = buf, i;
10179
10180                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10181                         p[i] = i;
10182
10183                 /* Send the buffer to the chip. */
10184                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10185                 if (ret) {
10186                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10187                         break;
10188                 }
10189
10190 #if 0
10191                 /* validate data reached card RAM correctly. */
10192                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10193                         u32 val;
10194                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
10195                         if (le32_to_cpu(val) != p[i]) {
10196                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
10197                                 /* ret = -ENODEV here? */
10198                         }
10199                         p[i] = 0;
10200                 }
10201 #endif
10202                 /* Now read it back. */
10203                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
10204                 if (ret) {
10205                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
10206
10207                         break;
10208                 }
10209
10210                 /* Verify it. */
10211                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10212                         if (p[i] == i)
10213                                 continue;
10214
10215                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10216                             DMA_RWCTRL_WRITE_BNDRY_16) {
10217                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10218                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10219                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10220                                 break;
10221                         } else {
10222                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
10223                                 ret = -ENODEV;
10224                                 goto out;
10225                         }
10226                 }
10227
10228                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
10229                         /* Success. */
10230                         ret = 0;
10231                         break;
10232                 }
10233         }
10234         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10235             DMA_RWCTRL_WRITE_BNDRY_16) {
10236                 static struct pci_device_id dma_wait_state_chipsets[] = {
10237                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
10238                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
10239                         { },
10240                 };
10241
10242                 /* DMA test passed without adjusting DMA boundary,
10243                  * now look for chipsets that are known to expose the
10244                  * DMA bug without failing the test.
10245                  */
10246                 if (pci_dev_present(dma_wait_state_chipsets)) {
10247                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10248                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10249                 }
10250                 else
10251                         /* Safe to use the calculated DMA boundary. */
10252                         tp->dma_rwctrl = saved_dma_rwctrl;
10253
10254                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10255         }
10256
10257 out:
10258         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
10259 out_nofree:
10260         return ret;
10261 }
10262
10263 static void __devinit tg3_init_link_config(struct tg3 *tp)
10264 {
10265         tp->link_config.advertising =
10266                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10267                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10268                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
10269                  ADVERTISED_Autoneg | ADVERTISED_MII);
10270         tp->link_config.speed = SPEED_INVALID;
10271         tp->link_config.duplex = DUPLEX_INVALID;
10272         tp->link_config.autoneg = AUTONEG_ENABLE;
10273         netif_carrier_off(tp->dev);
10274         tp->link_config.active_speed = SPEED_INVALID;
10275         tp->link_config.active_duplex = DUPLEX_INVALID;
10276         tp->link_config.phy_is_low_power = 0;
10277         tp->link_config.orig_speed = SPEED_INVALID;
10278         tp->link_config.orig_duplex = DUPLEX_INVALID;
10279         tp->link_config.orig_autoneg = AUTONEG_INVALID;
10280 }
10281
10282 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
10283 {
10284         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10285                 tp->bufmgr_config.mbuf_read_dma_low_water =
10286                         DEFAULT_MB_RDMA_LOW_WATER_5705;
10287                 tp->bufmgr_config.mbuf_mac_rx_low_water =
10288                         DEFAULT_MB_MACRX_LOW_WATER_5705;
10289                 tp->bufmgr_config.mbuf_high_water =
10290                         DEFAULT_MB_HIGH_WATER_5705;
10291
10292                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10293                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
10294                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10295                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
10296                 tp->bufmgr_config.mbuf_high_water_jumbo =
10297                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
10298         } else {
10299                 tp->bufmgr_config.mbuf_read_dma_low_water =
10300                         DEFAULT_MB_RDMA_LOW_WATER;
10301                 tp->bufmgr_config.mbuf_mac_rx_low_water =
10302                         DEFAULT_MB_MACRX_LOW_WATER;
10303                 tp->bufmgr_config.mbuf_high_water =
10304                         DEFAULT_MB_HIGH_WATER;
10305
10306                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10307                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
10308                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10309                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
10310                 tp->bufmgr_config.mbuf_high_water_jumbo =
10311                         DEFAULT_MB_HIGH_WATER_JUMBO;
10312         }
10313
10314         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
10315         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
10316 }
10317
10318 static char * __devinit tg3_phy_string(struct tg3 *tp)
10319 {
10320         switch (tp->phy_id & PHY_ID_MASK) {
10321         case PHY_ID_BCM5400:    return "5400";
10322         case PHY_ID_BCM5401:    return "5401";
10323         case PHY_ID_BCM5411:    return "5411";
10324         case PHY_ID_BCM5701:    return "5701";
10325         case PHY_ID_BCM5703:    return "5703";
10326         case PHY_ID_BCM5704:    return "5704";
10327         case PHY_ID_BCM5705:    return "5705";
10328         case PHY_ID_BCM5750:    return "5750";
10329         case PHY_ID_BCM5752:    return "5752";
10330         case PHY_ID_BCM5780:    return "5780";
10331         case PHY_ID_BCM8002:    return "8002/serdes";
10332         case 0:                 return "serdes";
10333         default:                return "unknown";
10334         };
10335 }
10336
10337 static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
10338 {
10339         struct pci_dev *peer;
10340         unsigned int func, devnr = tp->pdev->devfn & ~7;
10341
10342         for (func = 0; func < 8; func++) {
10343                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
10344                 if (peer && peer != tp->pdev)
10345                         break;
10346                 pci_dev_put(peer);
10347         }
10348         if (!peer || peer == tp->pdev)
10349                 BUG();
10350
10351         /*
10352          * We don't need to keep the refcount elevated; there's no way
10353          * to remove one half of this device without removing the other
10354          */
10355         pci_dev_put(peer);
10356
10357         return peer;
10358 }
10359
10360 static void __devinit tg3_init_coal(struct tg3 *tp)
10361 {
10362         struct ethtool_coalesce *ec = &tp->coal;
10363
10364         memset(ec, 0, sizeof(*ec));
10365         ec->cmd = ETHTOOL_GCOALESCE;
10366         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
10367         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
10368         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
10369         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
10370         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
10371         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
10372         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
10373         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
10374         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
10375
10376         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
10377                                  HOSTCC_MODE_CLRTICK_TXBD)) {
10378                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
10379                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
10380                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
10381                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
10382         }
10383
10384         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10385                 ec->rx_coalesce_usecs_irq = 0;
10386                 ec->tx_coalesce_usecs_irq = 0;
10387                 ec->stats_block_coalesce_usecs = 0;
10388         }
10389 }
10390
10391 static int __devinit tg3_init_one(struct pci_dev *pdev,
10392                                   const struct pci_device_id *ent)
10393 {
10394         static int tg3_version_printed = 0;
10395         unsigned long tg3reg_base, tg3reg_len;
10396         struct net_device *dev;
10397         struct tg3 *tp;
10398         int i, err, pci_using_dac, pm_cap;
10399
10400         if (tg3_version_printed++ == 0)
10401                 printk(KERN_INFO "%s", version);
10402
10403         err = pci_enable_device(pdev);
10404         if (err) {
10405                 printk(KERN_ERR PFX "Cannot enable PCI device, "
10406                        "aborting.\n");
10407                 return err;
10408         }
10409
10410         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10411                 printk(KERN_ERR PFX "Cannot find proper PCI device "
10412                        "base address, aborting.\n");
10413                 err = -ENODEV;
10414                 goto err_out_disable_pdev;
10415         }
10416
10417         err = pci_request_regions(pdev, DRV_MODULE_NAME);
10418         if (err) {
10419                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
10420                        "aborting.\n");
10421                 goto err_out_disable_pdev;
10422         }
10423
10424         pci_set_master(pdev);
10425
10426         /* Find power-management capability. */
10427         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10428         if (pm_cap == 0) {
10429                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
10430                        "aborting.\n");
10431                 err = -EIO;
10432                 goto err_out_free_res;
10433         }
10434
10435         /* Configure DMA attributes. */
10436         err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
10437         if (!err) {
10438                 pci_using_dac = 1;
10439                 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
10440                 if (err < 0) {
10441                         printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
10442                                "for consistent allocations\n");
10443                         goto err_out_free_res;
10444                 }
10445         } else {
10446                 err = pci_set_dma_mask(pdev, 0xffffffffULL);
10447                 if (err) {
10448                         printk(KERN_ERR PFX "No usable DMA configuration, "
10449                                "aborting.\n");
10450                         goto err_out_free_res;
10451                 }
10452                 pci_using_dac = 0;
10453         }
10454
10455         tg3reg_base = pci_resource_start(pdev, 0);
10456         tg3reg_len = pci_resource_len(pdev, 0);
10457
10458         dev = alloc_etherdev(sizeof(*tp));
10459         if (!dev) {
10460                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
10461                 err = -ENOMEM;
10462                 goto err_out_free_res;
10463         }
10464
10465         SET_MODULE_OWNER(dev);
10466         SET_NETDEV_DEV(dev, &pdev->dev);
10467
10468         if (pci_using_dac)
10469                 dev->features |= NETIF_F_HIGHDMA;
10470         dev->features |= NETIF_F_LLTX;
10471 #if TG3_VLAN_TAG_USED
10472         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
10473         dev->vlan_rx_register = tg3_vlan_rx_register;
10474         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
10475 #endif
10476
10477         tp = netdev_priv(dev);
10478         tp->pdev = pdev;
10479         tp->dev = dev;
10480         tp->pm_cap = pm_cap;
10481         tp->mac_mode = TG3_DEF_MAC_MODE;
10482         tp->rx_mode = TG3_DEF_RX_MODE;
10483         tp->tx_mode = TG3_DEF_TX_MODE;
10484         tp->mi_mode = MAC_MI_MODE_BASE;
10485         if (tg3_debug > 0)
10486                 tp->msg_enable = tg3_debug;
10487         else
10488                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
10489
10490         /* The word/byte swap controls here control register access byte
10491          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
10492          * setting below.
10493          */
10494         tp->misc_host_ctrl =
10495                 MISC_HOST_CTRL_MASK_PCI_INT |
10496                 MISC_HOST_CTRL_WORD_SWAP |
10497                 MISC_HOST_CTRL_INDIR_ACCESS |
10498                 MISC_HOST_CTRL_PCISTATE_RW;
10499
10500         /* The NONFRM (non-frame) byte/word swap controls take effect
10501          * on descriptor entries, anything which isn't packet data.
10502          *
10503          * The StrongARM chips on the board (one for tx, one for rx)
10504          * are running in big-endian mode.
10505          */
10506         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
10507                         GRC_MODE_WSWAP_NONFRM_DATA);
10508 #ifdef __BIG_ENDIAN
10509         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
10510 #endif
10511         spin_lock_init(&tp->lock);
10512         spin_lock_init(&tp->tx_lock);
10513         spin_lock_init(&tp->indirect_lock);
10514         INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
10515
10516         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
10517         if (tp->regs == 0UL) {
10518                 printk(KERN_ERR PFX "Cannot map device registers, "
10519                        "aborting.\n");
10520                 err = -ENOMEM;
10521                 goto err_out_free_dev;
10522         }
10523
10524         tg3_init_link_config(tp);
10525
10526         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
10527         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
10528         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
10529
10530         dev->open = tg3_open;
10531         dev->stop = tg3_close;
10532         dev->get_stats = tg3_get_stats;
10533         dev->set_multicast_list = tg3_set_rx_mode;
10534         dev->set_mac_address = tg3_set_mac_addr;
10535         dev->do_ioctl = tg3_ioctl;
10536         dev->tx_timeout = tg3_tx_timeout;
10537         dev->poll = tg3_poll;
10538         dev->ethtool_ops = &tg3_ethtool_ops;
10539         dev->weight = 64;
10540         dev->watchdog_timeo = TG3_TX_TIMEOUT;
10541         dev->change_mtu = tg3_change_mtu;
10542         dev->irq = pdev->irq;
10543 #ifdef CONFIG_NET_POLL_CONTROLLER
10544         dev->poll_controller = tg3_poll_controller;
10545 #endif
10546
10547         err = tg3_get_invariants(tp);
10548         if (err) {
10549                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
10550                        "aborting.\n");
10551                 goto err_out_iounmap;
10552         }
10553
10554         tg3_init_bufmgr_config(tp);
10555
10556 #if TG3_TSO_SUPPORT != 0
10557         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
10558                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10559         }
10560         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10561             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10562             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
10563             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
10564                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
10565         } else {
10566                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10567         }
10568
10569         /* TSO is off by default, user can enable using ethtool.  */
10570 #if 0
10571         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
10572                 dev->features |= NETIF_F_TSO;
10573 #endif
10574
10575 #endif
10576
10577         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
10578             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
10579             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
10580                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
10581                 tp->rx_pending = 63;
10582         }
10583
10584         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10585                 tp->pdev_peer = tg3_find_5704_peer(tp);
10586
10587         err = tg3_get_device_address(tp);
10588         if (err) {
10589                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10590                        "aborting.\n");
10591                 goto err_out_iounmap;
10592         }
10593
10594         /*
10595          * Reset chip in case UNDI or EFI driver did not shutdown
10596          * DMA self test will enable WDMAC and we'll see (spurious)
10597          * pending DMA on the PCI bus at that point.
10598          */
10599         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10600             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10601                 pci_save_state(tp->pdev);
10602                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
10603                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10604         }
10605
10606         err = tg3_test_dma(tp);
10607         if (err) {
10608                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10609                 goto err_out_iounmap;
10610         }
10611
10612         /* Tigon3 can do ipv4 only... and some chips have buggy
10613          * checksumming.
10614          */
10615         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10616                 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10617                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10618         } else
10619                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10620
10621         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10622                 dev->features &= ~NETIF_F_HIGHDMA;
10623
10624         /* flow control autonegotiation is default behavior */
10625         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10626
10627         tg3_init_coal(tp);
10628
10629         /* Now that we have fully setup the chip, save away a snapshot
10630          * of the PCI config space.  We need to restore this after
10631          * GRC_MISC_CFG core clock resets and some resume events.
10632          */
10633         pci_save_state(tp->pdev);
10634
10635         err = register_netdev(dev);
10636         if (err) {
10637                 printk(KERN_ERR PFX "Cannot register net device, "
10638                        "aborting.\n");
10639                 goto err_out_iounmap;
10640         }
10641
10642         pci_set_drvdata(pdev, dev);
10643
10644         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
10645                dev->name,
10646                tp->board_part_number,
10647                tp->pci_chip_rev_id,
10648                tg3_phy_string(tp),
10649                ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
10650                ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
10651                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
10652                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
10653                ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
10654                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10655
10656         for (i = 0; i < 6; i++)
10657                 printk("%2.2x%c", dev->dev_addr[i],
10658                        i == 5 ? '\n' : ':');
10659
10660         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10661                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10662                "TSOcap[%d] \n",
10663                dev->name,
10664                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10665                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10666                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10667                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10668                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10669                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10670                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
10671         printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10672                dev->name, tp->dma_rwctrl);
10673
10674         return 0;
10675
10676 err_out_iounmap:
10677         if (tp->regs) {
10678                 iounmap(tp->regs);
10679                 tp->regs = 0;
10680         }
10681
10682 err_out_free_dev:
10683         free_netdev(dev);
10684
10685 err_out_free_res:
10686         pci_release_regions(pdev);
10687
10688 err_out_disable_pdev:
10689         pci_disable_device(pdev);
10690         pci_set_drvdata(pdev, NULL);
10691         return err;
10692 }
10693
10694 static void __devexit tg3_remove_one(struct pci_dev *pdev)
10695 {
10696         struct net_device *dev = pci_get_drvdata(pdev);
10697
10698         if (dev) {
10699                 struct tg3 *tp = netdev_priv(dev);
10700
10701                 unregister_netdev(dev);
10702                 if (tp->regs) {
10703                         iounmap(tp->regs);
10704                         tp->regs = 0;
10705                 }
10706                 free_netdev(dev);
10707                 pci_release_regions(pdev);
10708                 pci_disable_device(pdev);
10709                 pci_set_drvdata(pdev, NULL);
10710         }
10711 }
10712
10713 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10714 {
10715         struct net_device *dev = pci_get_drvdata(pdev);
10716         struct tg3 *tp = netdev_priv(dev);
10717         int err;
10718
10719         if (!netif_running(dev))
10720                 return 0;
10721
10722         tg3_netif_stop(tp);
10723
10724         del_timer_sync(&tp->timer);
10725
10726         tg3_full_lock(tp, 1);
10727         tg3_disable_ints(tp);
10728         tg3_full_unlock(tp);
10729
10730         netif_device_detach(dev);
10731
10732         tg3_full_lock(tp, 0);
10733         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10734         tg3_full_unlock(tp);
10735
10736         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10737         if (err) {
10738                 tg3_full_lock(tp, 0);
10739
10740                 tg3_init_hw(tp);
10741
10742                 tp->timer.expires = jiffies + tp->timer_offset;
10743                 add_timer(&tp->timer);
10744
10745                 netif_device_attach(dev);
10746                 tg3_netif_start(tp);
10747
10748                 tg3_full_unlock(tp);
10749         }
10750
10751         return err;
10752 }
10753
10754 static int tg3_resume(struct pci_dev *pdev)
10755 {
10756         struct net_device *dev = pci_get_drvdata(pdev);
10757         struct tg3 *tp = netdev_priv(dev);
10758         int err;
10759
10760         if (!netif_running(dev))
10761                 return 0;
10762
10763         pci_restore_state(tp->pdev);
10764
10765         err = tg3_set_power_state(tp, 0);
10766         if (err)
10767                 return err;
10768
10769         netif_device_attach(dev);
10770
10771         tg3_full_lock(tp, 0);
10772
10773         tg3_init_hw(tp);
10774
10775         tp->timer.expires = jiffies + tp->timer_offset;
10776         add_timer(&tp->timer);
10777
10778         tg3_netif_start(tp);
10779
10780         tg3_full_unlock(tp);
10781
10782         return 0;
10783 }
10784
10785 static struct pci_driver tg3_driver = {
10786         .name           = DRV_MODULE_NAME,
10787         .id_table       = tg3_pci_tbl,
10788         .probe          = tg3_init_one,
10789         .remove         = __devexit_p(tg3_remove_one),
10790         .suspend        = tg3_suspend,
10791         .resume         = tg3_resume
10792 };
10793
10794 static int __init tg3_init(void)
10795 {
10796         return pci_module_init(&tg3_driver);
10797 }
10798
10799 static void __exit tg3_cleanup(void)
10800 {
10801         pci_unregister_driver(&tg3_driver);
10802 }
10803
10804 module_init(tg3_init);
10805 module_exit(tg3_cleanup);