2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
10 * Copyright (C) 2000-2003 Broadcom Corporation.
13 #include <linux/config.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/compiler.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/pci.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/ethtool.h>
29 #include <linux/mii.h>
30 #include <linux/if_vlan.h>
32 #include <linux/tcp.h>
33 #include <linux/workqueue.h>
35 #include <net/checksum.h>
37 #include <asm/system.h>
39 #include <asm/byteorder.h>
40 #include <asm/uaccess.h>
43 #include <asm/idprom.h>
44 #include <asm/oplib.h>
48 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49 #define TG3_VLAN_TAG_USED 1
51 #define TG3_VLAN_TAG_USED 0
55 #define TG3_TSO_SUPPORT 1
57 #define TG3_TSO_SUPPORT 0
62 #define DRV_MODULE_NAME "tg3"
63 #define PFX DRV_MODULE_NAME ": "
64 #define DRV_MODULE_VERSION "3.25"
65 #define DRV_MODULE_RELDATE "March 24, 2005"
67 #define TG3_DEF_MAC_MODE 0
68 #define TG3_DEF_RX_MODE 0
69 #define TG3_DEF_TX_MODE 0
70 #define TG3_DEF_MSG_ENABLE \
80 /* length of time before we decide the hardware is borked,
81 * and dev->tx_timeout() should be called to fix the problem
83 #define TG3_TX_TIMEOUT (5 * HZ)
85 /* hardware minimum and maximum for a single frame's data payload */
86 #define TG3_MIN_MTU 60
87 #define TG3_MAX_MTU(tp) \
88 (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
90 /* These numbers seem to be hard coded in the NIC firmware somehow.
91 * You can't change the ring sizes, but you can change where you place
92 * them in the NIC onboard memory.
94 #define TG3_RX_RING_SIZE 512
95 #define TG3_DEF_RX_RING_PENDING 200
96 #define TG3_RX_JUMBO_RING_SIZE 256
97 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
99 /* Do not place this n-ring entries value into the tp struct itself,
100 * we really want to expose these constants to GCC so that modulo et
101 * al. operations are done with shifts and masks instead of with
102 * hw multiply/modulo instructions. Another solution would be to
103 * replace things like '% foo' with '& (foo - 1)'.
105 #define TG3_RX_RCB_RING_SIZE(tp) \
106 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
108 #define TG3_TX_RING_SIZE 512
109 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
111 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
113 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
114 TG3_RX_JUMBO_RING_SIZE)
115 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
116 TG3_RX_RCB_RING_SIZE(tp))
117 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
119 #define TX_RING_GAP(TP) \
120 (TG3_TX_RING_SIZE - (TP)->tx_pending)
121 #define TX_BUFFS_AVAIL(TP) \
122 (((TP)->tx_cons <= (TP)->tx_prod) ? \
123 (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod : \
124 (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
125 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
128 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130 /* minimum number of free TX descriptors required to wake up TX process */
131 #define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
133 /* number of ETHTOOL_GSTATS u64's */
134 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
136 static char version[] __devinitdata =
137 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
139 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
140 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
141 MODULE_LICENSE("GPL");
142 MODULE_VERSION(DRV_MODULE_VERSION);
144 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
145 module_param(tg3_debug, int, 0);
146 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
148 static struct pci_device_id tg3_pci_tbl[] = {
149 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
151 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
153 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
155 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
157 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
159 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
161 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
163 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
165 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
167 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
169 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
171 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
173 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
175 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
177 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
179 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
181 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
183 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
185 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
187 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
189 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
191 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
193 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
195 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
197 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
199 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
201 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
203 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
205 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
207 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
209 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
211 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
213 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
215 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
217 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
219 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
221 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
223 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
225 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
227 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
229 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
234 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
237 const char string[ETH_GSTRING_LEN];
238 } ethtool_stats_keys[TG3_NUM_STATS] = {
241 { "rx_ucast_packets" },
242 { "rx_mcast_packets" },
243 { "rx_bcast_packets" },
245 { "rx_align_errors" },
246 { "rx_xon_pause_rcvd" },
247 { "rx_xoff_pause_rcvd" },
248 { "rx_mac_ctrl_rcvd" },
249 { "rx_xoff_entered" },
250 { "rx_frame_too_long_errors" },
252 { "rx_undersize_packets" },
253 { "rx_in_length_errors" },
254 { "rx_out_length_errors" },
255 { "rx_64_or_less_octet_packets" },
256 { "rx_65_to_127_octet_packets" },
257 { "rx_128_to_255_octet_packets" },
258 { "rx_256_to_511_octet_packets" },
259 { "rx_512_to_1023_octet_packets" },
260 { "rx_1024_to_1522_octet_packets" },
261 { "rx_1523_to_2047_octet_packets" },
262 { "rx_2048_to_4095_octet_packets" },
263 { "rx_4096_to_8191_octet_packets" },
264 { "rx_8192_to_9022_octet_packets" },
271 { "tx_flow_control" },
273 { "tx_single_collisions" },
274 { "tx_mult_collisions" },
276 { "tx_excessive_collisions" },
277 { "tx_late_collisions" },
278 { "tx_collide_2times" },
279 { "tx_collide_3times" },
280 { "tx_collide_4times" },
281 { "tx_collide_5times" },
282 { "tx_collide_6times" },
283 { "tx_collide_7times" },
284 { "tx_collide_8times" },
285 { "tx_collide_9times" },
286 { "tx_collide_10times" },
287 { "tx_collide_11times" },
288 { "tx_collide_12times" },
289 { "tx_collide_13times" },
290 { "tx_collide_14times" },
291 { "tx_collide_15times" },
292 { "tx_ucast_packets" },
293 { "tx_mcast_packets" },
294 { "tx_bcast_packets" },
295 { "tx_carrier_sense_errors" },
299 { "dma_writeq_full" },
300 { "dma_write_prioq_full" },
304 { "rx_threshold_hit" },
306 { "dma_readq_full" },
307 { "dma_read_prioq_full" },
308 { "tx_comp_queue_full" },
310 { "ring_set_send_prod_index" },
311 { "ring_status_update" },
313 { "nic_avoided_irqs" },
314 { "nic_tx_threshold_hit" }
317 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
319 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
322 spin_lock_irqsave(&tp->indirect_lock, flags);
323 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
324 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
325 spin_unlock_irqrestore(&tp->indirect_lock, flags);
327 writel(val, tp->regs + off);
328 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
329 readl(tp->regs + off);
333 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
335 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
338 spin_lock_irqsave(&tp->indirect_lock, flags);
339 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
340 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
341 spin_unlock_irqrestore(&tp->indirect_lock, flags);
343 void __iomem *dest = tp->regs + off;
345 readl(dest); /* always flush PCI write */
349 static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val)
351 void __iomem *mbox = tp->regs + off;
353 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
357 static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
359 void __iomem *mbox = tp->regs + off;
361 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
363 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
367 #define tw32_mailbox(reg, val) writel(((val) & 0xffffffff), tp->regs + (reg))
368 #define tw32_rx_mbox(reg, val) _tw32_rx_mbox(tp, reg, val)
369 #define tw32_tx_mbox(reg, val) _tw32_tx_mbox(tp, reg, val)
371 #define tw32(reg,val) tg3_write_indirect_reg32(tp,(reg),(val))
372 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
373 #define tw16(reg,val) writew(((val) & 0xffff), tp->regs + (reg))
374 #define tw8(reg,val) writeb(((val) & 0xff), tp->regs + (reg))
375 #define tr32(reg) readl(tp->regs + (reg))
376 #define tr16(reg) readw(tp->regs + (reg))
377 #define tr8(reg) readb(tp->regs + (reg))
379 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
385 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
387 /* Always leave this as zero. */
388 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
389 spin_unlock_irqrestore(&tp->indirect_lock, flags);
392 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
396 spin_lock_irqsave(&tp->indirect_lock, flags);
397 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
398 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
400 /* Always leave this as zero. */
401 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
402 spin_unlock_irqrestore(&tp->indirect_lock, flags);
405 static void tg3_disable_ints(struct tg3 *tp)
407 tw32(TG3PCI_MISC_HOST_CTRL,
408 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
409 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
410 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
413 static inline void tg3_cond_int(struct tg3 *tp)
415 if (tp->hw_status->status & SD_STATUS_UPDATED)
416 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
419 static void tg3_enable_ints(struct tg3 *tp)
421 tw32(TG3PCI_MISC_HOST_CTRL,
422 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
423 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000);
424 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
430 * similar to tg3_enable_ints, but it can return without flushing the
431 * PIO write which reenables interrupts
433 static void tg3_restart_ints(struct tg3 *tp)
435 tw32(TG3PCI_MISC_HOST_CTRL,
436 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
437 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000);
443 static inline void tg3_netif_stop(struct tg3 *tp)
445 netif_poll_disable(tp->dev);
446 netif_tx_disable(tp->dev);
449 static inline void tg3_netif_start(struct tg3 *tp)
451 netif_wake_queue(tp->dev);
452 /* NOTE: unconditional netif_wake_queue is only appropriate
453 * so long as all callers are assured to have free tx slots
454 * (such as after tg3_init_hw)
456 netif_poll_enable(tp->dev);
460 static void tg3_switch_clocks(struct tg3 *tp)
462 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
465 orig_clock_ctrl = clock_ctrl;
466 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
467 CLOCK_CTRL_CLKRUN_OENABLE |
469 tp->pci_clock_ctrl = clock_ctrl;
471 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
472 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
473 tw32_f(TG3PCI_CLOCK_CTRL,
474 clock_ctrl | CLOCK_CTRL_625_CORE);
477 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
478 tw32_f(TG3PCI_CLOCK_CTRL,
480 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
482 tw32_f(TG3PCI_CLOCK_CTRL,
483 clock_ctrl | (CLOCK_CTRL_ALTCLK));
486 tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
490 #define PHY_BUSY_LOOPS 5000
492 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
498 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
500 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
506 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
507 MI_COM_PHY_ADDR_MASK);
508 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
509 MI_COM_REG_ADDR_MASK);
510 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
512 tw32_f(MAC_MI_COM, frame_val);
514 loops = PHY_BUSY_LOOPS;
517 frame_val = tr32(MAC_MI_COM);
519 if ((frame_val & MI_COM_BUSY) == 0) {
521 frame_val = tr32(MAC_MI_COM);
529 *val = frame_val & MI_COM_DATA_MASK;
533 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
534 tw32_f(MAC_MI_MODE, tp->mi_mode);
541 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
547 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
549 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
553 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
554 MI_COM_PHY_ADDR_MASK);
555 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
556 MI_COM_REG_ADDR_MASK);
557 frame_val |= (val & MI_COM_DATA_MASK);
558 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
560 tw32_f(MAC_MI_COM, frame_val);
562 loops = PHY_BUSY_LOOPS;
565 frame_val = tr32(MAC_MI_COM);
566 if ((frame_val & MI_COM_BUSY) == 0) {
568 frame_val = tr32(MAC_MI_COM);
578 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
579 tw32_f(MAC_MI_MODE, tp->mi_mode);
586 static void tg3_phy_set_wirespeed(struct tg3 *tp)
590 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
593 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
594 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
595 tg3_writephy(tp, MII_TG3_AUX_CTRL,
596 (val | (1 << 15) | (1 << 4)));
599 static int tg3_bmcr_reset(struct tg3 *tp)
604 /* OK, reset it, and poll the BMCR_RESET bit until it
605 * clears or we time out.
607 phy_control = BMCR_RESET;
608 err = tg3_writephy(tp, MII_BMCR, phy_control);
614 err = tg3_readphy(tp, MII_BMCR, &phy_control);
618 if ((phy_control & BMCR_RESET) == 0) {
630 static int tg3_wait_macro_done(struct tg3 *tp)
637 if (!tg3_readphy(tp, 0x16, &tmp32)) {
638 if ((tmp32 & 0x1000) == 0)
648 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
650 static const u32 test_pat[4][6] = {
651 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
652 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
653 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
654 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
658 for (chan = 0; chan < 4; chan++) {
661 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
662 (chan * 0x2000) | 0x0200);
663 tg3_writephy(tp, 0x16, 0x0002);
665 for (i = 0; i < 6; i++)
666 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
669 tg3_writephy(tp, 0x16, 0x0202);
670 if (tg3_wait_macro_done(tp)) {
675 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
676 (chan * 0x2000) | 0x0200);
677 tg3_writephy(tp, 0x16, 0x0082);
678 if (tg3_wait_macro_done(tp)) {
683 tg3_writephy(tp, 0x16, 0x0802);
684 if (tg3_wait_macro_done(tp)) {
689 for (i = 0; i < 6; i += 2) {
692 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
693 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
694 tg3_wait_macro_done(tp)) {
700 if (low != test_pat[chan][i] ||
701 high != test_pat[chan][i+1]) {
702 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
703 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
704 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
714 static int tg3_phy_reset_chanpat(struct tg3 *tp)
718 for (chan = 0; chan < 4; chan++) {
721 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
722 (chan * 0x2000) | 0x0200);
723 tg3_writephy(tp, 0x16, 0x0002);
724 for (i = 0; i < 6; i++)
725 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
726 tg3_writephy(tp, 0x16, 0x0202);
727 if (tg3_wait_macro_done(tp))
734 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
736 u32 reg32, phy9_orig;
737 int retries, do_phy_reset, err;
743 err = tg3_bmcr_reset(tp);
749 /* Disable transmitter and interrupt. */
750 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
754 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
756 /* Set full-duplex, 1000 mbps. */
757 tg3_writephy(tp, MII_BMCR,
758 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
760 /* Set to master mode. */
761 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
764 tg3_writephy(tp, MII_TG3_CTRL,
765 (MII_TG3_CTRL_AS_MASTER |
766 MII_TG3_CTRL_ENABLE_AS_MASTER));
768 /* Enable SM_DSP_CLOCK and 6dB. */
769 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
771 /* Block the PHY control access. */
772 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
773 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
775 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
780 err = tg3_phy_reset_chanpat(tp);
784 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
785 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
787 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
788 tg3_writephy(tp, 0x16, 0x0000);
790 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
791 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
792 /* Set Extended packet length bit for jumbo frames */
793 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
796 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
799 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
801 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
803 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
810 /* This will reset the tigon3 PHY if there is no valid
811 * link unless the FORCE argument is non-zero.
813 static int tg3_phy_reset(struct tg3 *tp)
818 err = tg3_readphy(tp, MII_BMSR, &phy_status);
819 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
824 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
825 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
826 err = tg3_phy_reset_5703_4_5(tp);
832 err = tg3_bmcr_reset(tp);
837 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
838 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
839 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
840 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
841 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
843 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
845 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
846 tg3_writephy(tp, 0x1c, 0x8d68);
847 tg3_writephy(tp, 0x1c, 0x8d68);
849 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
850 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
852 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
853 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
854 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
857 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
859 /* Set Extended packet length bit (bit 14) on all chips that */
860 /* support jumbo frames */
861 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
862 /* Cannot do read-modify-write on 5401 */
863 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
864 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
867 /* Set bit 14 with read-modify-write to preserve other bits */
868 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
869 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
870 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
873 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
874 * jumbo frames transmission.
876 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
879 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
880 tg3_writephy(tp, MII_TG3_EXT_CTRL,
881 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
884 tg3_phy_set_wirespeed(tp);
888 static void tg3_frob_aux_power(struct tg3 *tp)
890 struct tg3 *tp_peer = tp;
892 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
896 tp_peer = pci_get_drvdata(tp->pdev_peer);
902 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
903 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
906 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
907 (GRC_LCLCTRL_GPIO_OE0 |
908 GRC_LCLCTRL_GPIO_OE1 |
909 GRC_LCLCTRL_GPIO_OE2 |
910 GRC_LCLCTRL_GPIO_OUTPUT0 |
911 GRC_LCLCTRL_GPIO_OUTPUT1));
918 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
921 /* On 5753 and variants, GPIO2 cannot be used. */
922 no_gpio2 = tp->nic_sram_data_cfg &
923 NIC_SRAM_DATA_CFG_NO_GPIO2;
925 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
926 GRC_LCLCTRL_GPIO_OE1 |
927 GRC_LCLCTRL_GPIO_OE2 |
928 GRC_LCLCTRL_GPIO_OUTPUT1 |
929 GRC_LCLCTRL_GPIO_OUTPUT2;
931 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
932 GRC_LCLCTRL_GPIO_OUTPUT2);
934 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
938 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
940 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
945 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
946 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
952 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
953 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
955 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
958 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
959 (GRC_LCLCTRL_GPIO_OE1 |
960 GRC_LCLCTRL_GPIO_OUTPUT1));
963 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
964 (GRC_LCLCTRL_GPIO_OE1));
967 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
968 (GRC_LCLCTRL_GPIO_OE1 |
969 GRC_LCLCTRL_GPIO_OUTPUT1));
975 static int tg3_setup_phy(struct tg3 *, int);
977 #define RESET_KIND_SHUTDOWN 0
978 #define RESET_KIND_INIT 1
979 #define RESET_KIND_SUSPEND 2
981 static void tg3_write_sig_post_reset(struct tg3 *, int);
982 static int tg3_halt_cpu(struct tg3 *, u32);
984 static int tg3_set_power_state(struct tg3 *tp, int state)
987 u16 power_control, power_caps;
990 /* Make sure register accesses (indirect or otherwise)
991 * will function correctly.
993 pci_write_config_dword(tp->pdev,
994 TG3PCI_MISC_HOST_CTRL,
997 pci_read_config_word(tp->pdev,
1000 power_control |= PCI_PM_CTRL_PME_STATUS;
1001 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1005 pci_write_config_word(tp->pdev,
1008 udelay(100); /* Delay after power state change */
1010 /* Switch out of Vaux if it is not a LOM */
1011 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1012 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1031 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1033 tp->dev->name, state);
1037 power_control |= PCI_PM_CTRL_PME_ENABLE;
1039 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1040 tw32(TG3PCI_MISC_HOST_CTRL,
1041 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1043 if (tp->link_config.phy_is_low_power == 0) {
1044 tp->link_config.phy_is_low_power = 1;
1045 tp->link_config.orig_speed = tp->link_config.speed;
1046 tp->link_config.orig_duplex = tp->link_config.duplex;
1047 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1050 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1051 tp->link_config.speed = SPEED_10;
1052 tp->link_config.duplex = DUPLEX_HALF;
1053 tp->link_config.autoneg = AUTONEG_ENABLE;
1054 tg3_setup_phy(tp, 0);
1057 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1059 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1062 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1063 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1066 mac_mode = MAC_MODE_PORT_MODE_MII;
1068 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1069 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1070 mac_mode |= MAC_MODE_LINK_POLARITY;
1072 mac_mode = MAC_MODE_PORT_MODE_TBI;
1075 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1076 tw32(MAC_LED_CTRL, tp->led_ctrl);
1078 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1079 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1080 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1082 tw32_f(MAC_MODE, mac_mode);
1085 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1089 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1090 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1091 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1094 base_val = tp->pci_clock_ctrl;
1095 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1096 CLOCK_CTRL_TXCLK_DISABLE);
1098 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1100 CLOCK_CTRL_PWRDOWN_PLL133);
1102 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1103 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1104 u32 newbits1, newbits2;
1106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1107 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1108 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1109 CLOCK_CTRL_TXCLK_DISABLE |
1111 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1112 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1113 newbits1 = CLOCK_CTRL_625_CORE;
1114 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1116 newbits1 = CLOCK_CTRL_ALTCLK;
1117 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1120 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1123 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1126 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1131 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1132 CLOCK_CTRL_TXCLK_DISABLE |
1133 CLOCK_CTRL_44MHZ_CORE);
1135 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1138 tw32_f(TG3PCI_CLOCK_CTRL,
1139 tp->pci_clock_ctrl | newbits3);
1144 tg3_frob_aux_power(tp);
1146 /* Workaround for unstable PLL clock */
1147 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1148 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1149 u32 val = tr32(0x7d00);
1151 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1153 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1154 tg3_halt_cpu(tp, RX_CPU_BASE);
1157 /* Finally, set the new power state. */
1158 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1159 udelay(100); /* Delay after power state change */
1161 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1166 static void tg3_link_report(struct tg3 *tp)
1168 if (!netif_carrier_ok(tp->dev)) {
1169 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1171 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1173 (tp->link_config.active_speed == SPEED_1000 ?
1175 (tp->link_config.active_speed == SPEED_100 ?
1177 (tp->link_config.active_duplex == DUPLEX_FULL ?
1180 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1183 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1184 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1188 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1190 u32 new_tg3_flags = 0;
1191 u32 old_rx_mode = tp->rx_mode;
1192 u32 old_tx_mode = tp->tx_mode;
1194 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1195 if (local_adv & ADVERTISE_PAUSE_CAP) {
1196 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1197 if (remote_adv & LPA_PAUSE_CAP)
1199 (TG3_FLAG_RX_PAUSE |
1201 else if (remote_adv & LPA_PAUSE_ASYM)
1203 (TG3_FLAG_RX_PAUSE);
1205 if (remote_adv & LPA_PAUSE_CAP)
1207 (TG3_FLAG_RX_PAUSE |
1210 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1211 if ((remote_adv & LPA_PAUSE_CAP) &&
1212 (remote_adv & LPA_PAUSE_ASYM))
1213 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1216 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1217 tp->tg3_flags |= new_tg3_flags;
1219 new_tg3_flags = tp->tg3_flags;
1222 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1223 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1225 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1227 if (old_rx_mode != tp->rx_mode) {
1228 tw32_f(MAC_RX_MODE, tp->rx_mode);
1231 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1232 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1234 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1236 if (old_tx_mode != tp->tx_mode) {
1237 tw32_f(MAC_TX_MODE, tp->tx_mode);
1241 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1243 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1244 case MII_TG3_AUX_STAT_10HALF:
1246 *duplex = DUPLEX_HALF;
1249 case MII_TG3_AUX_STAT_10FULL:
1251 *duplex = DUPLEX_FULL;
1254 case MII_TG3_AUX_STAT_100HALF:
1256 *duplex = DUPLEX_HALF;
1259 case MII_TG3_AUX_STAT_100FULL:
1261 *duplex = DUPLEX_FULL;
1264 case MII_TG3_AUX_STAT_1000HALF:
1265 *speed = SPEED_1000;
1266 *duplex = DUPLEX_HALF;
1269 case MII_TG3_AUX_STAT_1000FULL:
1270 *speed = SPEED_1000;
1271 *duplex = DUPLEX_FULL;
1275 *speed = SPEED_INVALID;
1276 *duplex = DUPLEX_INVALID;
1281 static void tg3_phy_copper_begin(struct tg3 *tp)
1286 if (tp->link_config.phy_is_low_power) {
1287 /* Entering low power mode. Disable gigabit and
1288 * 100baseT advertisements.
1290 tg3_writephy(tp, MII_TG3_CTRL, 0);
1292 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1293 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1294 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1295 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1297 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1298 } else if (tp->link_config.speed == SPEED_INVALID) {
1299 tp->link_config.advertising =
1300 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1301 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1302 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1303 ADVERTISED_Autoneg | ADVERTISED_MII);
1305 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1306 tp->link_config.advertising &=
1307 ~(ADVERTISED_1000baseT_Half |
1308 ADVERTISED_1000baseT_Full);
1310 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1311 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1312 new_adv |= ADVERTISE_10HALF;
1313 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1314 new_adv |= ADVERTISE_10FULL;
1315 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1316 new_adv |= ADVERTISE_100HALF;
1317 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1318 new_adv |= ADVERTISE_100FULL;
1319 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1321 if (tp->link_config.advertising &
1322 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1324 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1325 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1326 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1327 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1328 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1329 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1330 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1331 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1332 MII_TG3_CTRL_ENABLE_AS_MASTER);
1333 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1335 tg3_writephy(tp, MII_TG3_CTRL, 0);
1338 /* Asking for a specific link mode. */
1339 if (tp->link_config.speed == SPEED_1000) {
1340 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1341 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1343 if (tp->link_config.duplex == DUPLEX_FULL)
1344 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1346 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1347 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1348 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1349 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1350 MII_TG3_CTRL_ENABLE_AS_MASTER);
1351 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1353 tg3_writephy(tp, MII_TG3_CTRL, 0);
1355 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1356 if (tp->link_config.speed == SPEED_100) {
1357 if (tp->link_config.duplex == DUPLEX_FULL)
1358 new_adv |= ADVERTISE_100FULL;
1360 new_adv |= ADVERTISE_100HALF;
1362 if (tp->link_config.duplex == DUPLEX_FULL)
1363 new_adv |= ADVERTISE_10FULL;
1365 new_adv |= ADVERTISE_10HALF;
1367 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1371 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1372 tp->link_config.speed != SPEED_INVALID) {
1373 u32 bmcr, orig_bmcr;
1375 tp->link_config.active_speed = tp->link_config.speed;
1376 tp->link_config.active_duplex = tp->link_config.duplex;
1379 switch (tp->link_config.speed) {
1385 bmcr |= BMCR_SPEED100;
1389 bmcr |= TG3_BMCR_SPEED1000;
1393 if (tp->link_config.duplex == DUPLEX_FULL)
1394 bmcr |= BMCR_FULLDPLX;
1396 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1397 (bmcr != orig_bmcr)) {
1398 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1399 for (i = 0; i < 1500; i++) {
1403 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1404 tg3_readphy(tp, MII_BMSR, &tmp))
1406 if (!(tmp & BMSR_LSTATUS)) {
1411 tg3_writephy(tp, MII_BMCR, bmcr);
1415 tg3_writephy(tp, MII_BMCR,
1416 BMCR_ANENABLE | BMCR_ANRESTART);
1420 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1424 /* Turn off tap power management. */
1425 /* Set Extended packet length bit */
1426 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1428 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1429 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1431 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1432 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1434 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1435 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1437 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1438 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1440 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1441 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1448 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1450 u32 adv_reg, all_mask;
1452 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1455 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1456 ADVERTISE_100HALF | ADVERTISE_100FULL);
1457 if ((adv_reg & all_mask) != all_mask)
1459 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1462 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1465 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1466 MII_TG3_CTRL_ADV_1000_FULL);
1467 if ((tg3_ctrl & all_mask) != all_mask)
1473 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1475 int current_link_up;
1484 (MAC_STATUS_SYNC_CHANGED |
1485 MAC_STATUS_CFG_CHANGED |
1486 MAC_STATUS_MI_COMPLETION |
1487 MAC_STATUS_LNKSTATE_CHANGED));
1490 tp->mi_mode = MAC_MI_MODE_BASE;
1491 tw32_f(MAC_MI_MODE, tp->mi_mode);
1494 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1496 /* Some third-party PHYs need to be reset on link going
1499 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1500 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1501 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1502 netif_carrier_ok(tp->dev)) {
1503 tg3_readphy(tp, MII_BMSR, &bmsr);
1504 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1505 !(bmsr & BMSR_LSTATUS))
1511 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1512 tg3_readphy(tp, MII_BMSR, &bmsr);
1513 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1514 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1517 if (!(bmsr & BMSR_LSTATUS)) {
1518 err = tg3_init_5401phy_dsp(tp);
1522 tg3_readphy(tp, MII_BMSR, &bmsr);
1523 for (i = 0; i < 1000; i++) {
1525 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1526 (bmsr & BMSR_LSTATUS)) {
1532 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1533 !(bmsr & BMSR_LSTATUS) &&
1534 tp->link_config.active_speed == SPEED_1000) {
1535 err = tg3_phy_reset(tp);
1537 err = tg3_init_5401phy_dsp(tp);
1542 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1543 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1544 /* 5701 {A0,B0} CRC bug workaround */
1545 tg3_writephy(tp, 0x15, 0x0a75);
1546 tg3_writephy(tp, 0x1c, 0x8c68);
1547 tg3_writephy(tp, 0x1c, 0x8d68);
1548 tg3_writephy(tp, 0x1c, 0x8c68);
1551 /* Clear pending interrupts... */
1552 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1553 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1555 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1556 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1558 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1561 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1562 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1563 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1564 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1566 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1569 current_link_up = 0;
1570 current_speed = SPEED_INVALID;
1571 current_duplex = DUPLEX_INVALID;
1573 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1576 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1577 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1578 if (!(val & (1 << 10))) {
1580 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1586 for (i = 0; i < 100; i++) {
1587 tg3_readphy(tp, MII_BMSR, &bmsr);
1588 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1589 (bmsr & BMSR_LSTATUS))
1594 if (bmsr & BMSR_LSTATUS) {
1597 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1598 for (i = 0; i < 2000; i++) {
1600 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1605 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1610 for (i = 0; i < 200; i++) {
1611 tg3_readphy(tp, MII_BMCR, &bmcr);
1612 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1614 if (bmcr && bmcr != 0x7fff)
1619 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1620 if (bmcr & BMCR_ANENABLE) {
1621 current_link_up = 1;
1623 /* Force autoneg restart if we are exiting
1626 if (!tg3_copper_is_advertising_all(tp))
1627 current_link_up = 0;
1629 current_link_up = 0;
1632 if (!(bmcr & BMCR_ANENABLE) &&
1633 tp->link_config.speed == current_speed &&
1634 tp->link_config.duplex == current_duplex) {
1635 current_link_up = 1;
1637 current_link_up = 0;
1641 tp->link_config.active_speed = current_speed;
1642 tp->link_config.active_duplex = current_duplex;
1645 if (current_link_up == 1 &&
1646 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1647 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1648 u32 local_adv, remote_adv;
1650 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1652 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1654 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1657 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1659 /* If we are not advertising full pause capability,
1660 * something is wrong. Bring the link down and reconfigure.
1662 if (local_adv != ADVERTISE_PAUSE_CAP) {
1663 current_link_up = 0;
1665 tg3_setup_flow_control(tp, local_adv, remote_adv);
1669 if (current_link_up == 0) {
1672 tg3_phy_copper_begin(tp);
1674 tg3_readphy(tp, MII_BMSR, &tmp);
1675 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1676 (tmp & BMSR_LSTATUS))
1677 current_link_up = 1;
1680 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1681 if (current_link_up == 1) {
1682 if (tp->link_config.active_speed == SPEED_100 ||
1683 tp->link_config.active_speed == SPEED_10)
1684 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1686 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1688 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1690 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1691 if (tp->link_config.active_duplex == DUPLEX_HALF)
1692 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1694 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1695 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1696 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1697 (current_link_up == 1 &&
1698 tp->link_config.active_speed == SPEED_10))
1699 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1701 if (current_link_up == 1)
1702 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1705 /* ??? Without this setting Netgear GA302T PHY does not
1706 * ??? send/receive packets...
1708 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1709 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1710 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1711 tw32_f(MAC_MI_MODE, tp->mi_mode);
1715 tw32_f(MAC_MODE, tp->mac_mode);
1718 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1719 /* Polled via timer. */
1720 tw32_f(MAC_EVENT, 0);
1722 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1726 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1727 current_link_up == 1 &&
1728 tp->link_config.active_speed == SPEED_1000 &&
1729 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1730 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1733 (MAC_STATUS_SYNC_CHANGED |
1734 MAC_STATUS_CFG_CHANGED));
1737 NIC_SRAM_FIRMWARE_MBOX,
1738 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1741 if (current_link_up != netif_carrier_ok(tp->dev)) {
1742 if (current_link_up)
1743 netif_carrier_on(tp->dev);
1745 netif_carrier_off(tp->dev);
1746 tg3_link_report(tp);
1752 struct tg3_fiber_aneginfo {
1754 #define ANEG_STATE_UNKNOWN 0
1755 #define ANEG_STATE_AN_ENABLE 1
1756 #define ANEG_STATE_RESTART_INIT 2
1757 #define ANEG_STATE_RESTART 3
1758 #define ANEG_STATE_DISABLE_LINK_OK 4
1759 #define ANEG_STATE_ABILITY_DETECT_INIT 5
1760 #define ANEG_STATE_ABILITY_DETECT 6
1761 #define ANEG_STATE_ACK_DETECT_INIT 7
1762 #define ANEG_STATE_ACK_DETECT 8
1763 #define ANEG_STATE_COMPLETE_ACK_INIT 9
1764 #define ANEG_STATE_COMPLETE_ACK 10
1765 #define ANEG_STATE_IDLE_DETECT_INIT 11
1766 #define ANEG_STATE_IDLE_DETECT 12
1767 #define ANEG_STATE_LINK_OK 13
1768 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1769 #define ANEG_STATE_NEXT_PAGE_WAIT 15
1772 #define MR_AN_ENABLE 0x00000001
1773 #define MR_RESTART_AN 0x00000002
1774 #define MR_AN_COMPLETE 0x00000004
1775 #define MR_PAGE_RX 0x00000008
1776 #define MR_NP_LOADED 0x00000010
1777 #define MR_TOGGLE_TX 0x00000020
1778 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
1779 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
1780 #define MR_LP_ADV_SYM_PAUSE 0x00000100
1781 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
1782 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1783 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1784 #define MR_LP_ADV_NEXT_PAGE 0x00001000
1785 #define MR_TOGGLE_RX 0x00002000
1786 #define MR_NP_RX 0x00004000
1788 #define MR_LINK_OK 0x80000000
1790 unsigned long link_time, cur_time;
1792 u32 ability_match_cfg;
1793 int ability_match_count;
1795 char ability_match, idle_match, ack_match;
1797 u32 txconfig, rxconfig;
1798 #define ANEG_CFG_NP 0x00000080
1799 #define ANEG_CFG_ACK 0x00000040
1800 #define ANEG_CFG_RF2 0x00000020
1801 #define ANEG_CFG_RF1 0x00000010
1802 #define ANEG_CFG_PS2 0x00000001
1803 #define ANEG_CFG_PS1 0x00008000
1804 #define ANEG_CFG_HD 0x00004000
1805 #define ANEG_CFG_FD 0x00002000
1806 #define ANEG_CFG_INVAL 0x00001f06
1811 #define ANEG_TIMER_ENAB 2
1812 #define ANEG_FAILED -1
1814 #define ANEG_STATE_SETTLE_TIME 10000
1816 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1817 struct tg3_fiber_aneginfo *ap)
1819 unsigned long delta;
1823 if (ap->state == ANEG_STATE_UNKNOWN) {
1827 ap->ability_match_cfg = 0;
1828 ap->ability_match_count = 0;
1829 ap->ability_match = 0;
1835 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1836 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1838 if (rx_cfg_reg != ap->ability_match_cfg) {
1839 ap->ability_match_cfg = rx_cfg_reg;
1840 ap->ability_match = 0;
1841 ap->ability_match_count = 0;
1843 if (++ap->ability_match_count > 1) {
1844 ap->ability_match = 1;
1845 ap->ability_match_cfg = rx_cfg_reg;
1848 if (rx_cfg_reg & ANEG_CFG_ACK)
1856 ap->ability_match_cfg = 0;
1857 ap->ability_match_count = 0;
1858 ap->ability_match = 0;
1864 ap->rxconfig = rx_cfg_reg;
1868 case ANEG_STATE_UNKNOWN:
1869 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1870 ap->state = ANEG_STATE_AN_ENABLE;
1873 case ANEG_STATE_AN_ENABLE:
1874 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1875 if (ap->flags & MR_AN_ENABLE) {
1878 ap->ability_match_cfg = 0;
1879 ap->ability_match_count = 0;
1880 ap->ability_match = 0;
1884 ap->state = ANEG_STATE_RESTART_INIT;
1886 ap->state = ANEG_STATE_DISABLE_LINK_OK;
1890 case ANEG_STATE_RESTART_INIT:
1891 ap->link_time = ap->cur_time;
1892 ap->flags &= ~(MR_NP_LOADED);
1894 tw32(MAC_TX_AUTO_NEG, 0);
1895 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1896 tw32_f(MAC_MODE, tp->mac_mode);
1899 ret = ANEG_TIMER_ENAB;
1900 ap->state = ANEG_STATE_RESTART;
1903 case ANEG_STATE_RESTART:
1904 delta = ap->cur_time - ap->link_time;
1905 if (delta > ANEG_STATE_SETTLE_TIME) {
1906 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1908 ret = ANEG_TIMER_ENAB;
1912 case ANEG_STATE_DISABLE_LINK_OK:
1916 case ANEG_STATE_ABILITY_DETECT_INIT:
1917 ap->flags &= ~(MR_TOGGLE_TX);
1918 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1919 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1920 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1921 tw32_f(MAC_MODE, tp->mac_mode);
1924 ap->state = ANEG_STATE_ABILITY_DETECT;
1927 case ANEG_STATE_ABILITY_DETECT:
1928 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1929 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1933 case ANEG_STATE_ACK_DETECT_INIT:
1934 ap->txconfig |= ANEG_CFG_ACK;
1935 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1936 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1937 tw32_f(MAC_MODE, tp->mac_mode);
1940 ap->state = ANEG_STATE_ACK_DETECT;
1943 case ANEG_STATE_ACK_DETECT:
1944 if (ap->ack_match != 0) {
1945 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1946 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1947 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1949 ap->state = ANEG_STATE_AN_ENABLE;
1951 } else if (ap->ability_match != 0 &&
1952 ap->rxconfig == 0) {
1953 ap->state = ANEG_STATE_AN_ENABLE;
1957 case ANEG_STATE_COMPLETE_ACK_INIT:
1958 if (ap->rxconfig & ANEG_CFG_INVAL) {
1962 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1963 MR_LP_ADV_HALF_DUPLEX |
1964 MR_LP_ADV_SYM_PAUSE |
1965 MR_LP_ADV_ASYM_PAUSE |
1966 MR_LP_ADV_REMOTE_FAULT1 |
1967 MR_LP_ADV_REMOTE_FAULT2 |
1968 MR_LP_ADV_NEXT_PAGE |
1971 if (ap->rxconfig & ANEG_CFG_FD)
1972 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1973 if (ap->rxconfig & ANEG_CFG_HD)
1974 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1975 if (ap->rxconfig & ANEG_CFG_PS1)
1976 ap->flags |= MR_LP_ADV_SYM_PAUSE;
1977 if (ap->rxconfig & ANEG_CFG_PS2)
1978 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1979 if (ap->rxconfig & ANEG_CFG_RF1)
1980 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1981 if (ap->rxconfig & ANEG_CFG_RF2)
1982 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1983 if (ap->rxconfig & ANEG_CFG_NP)
1984 ap->flags |= MR_LP_ADV_NEXT_PAGE;
1986 ap->link_time = ap->cur_time;
1988 ap->flags ^= (MR_TOGGLE_TX);
1989 if (ap->rxconfig & 0x0008)
1990 ap->flags |= MR_TOGGLE_RX;
1991 if (ap->rxconfig & ANEG_CFG_NP)
1992 ap->flags |= MR_NP_RX;
1993 ap->flags |= MR_PAGE_RX;
1995 ap->state = ANEG_STATE_COMPLETE_ACK;
1996 ret = ANEG_TIMER_ENAB;
1999 case ANEG_STATE_COMPLETE_ACK:
2000 if (ap->ability_match != 0 &&
2001 ap->rxconfig == 0) {
2002 ap->state = ANEG_STATE_AN_ENABLE;
2005 delta = ap->cur_time - ap->link_time;
2006 if (delta > ANEG_STATE_SETTLE_TIME) {
2007 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2008 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2010 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2011 !(ap->flags & MR_NP_RX)) {
2012 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2020 case ANEG_STATE_IDLE_DETECT_INIT:
2021 ap->link_time = ap->cur_time;
2022 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2023 tw32_f(MAC_MODE, tp->mac_mode);
2026 ap->state = ANEG_STATE_IDLE_DETECT;
2027 ret = ANEG_TIMER_ENAB;
2030 case ANEG_STATE_IDLE_DETECT:
2031 if (ap->ability_match != 0 &&
2032 ap->rxconfig == 0) {
2033 ap->state = ANEG_STATE_AN_ENABLE;
2036 delta = ap->cur_time - ap->link_time;
2037 if (delta > ANEG_STATE_SETTLE_TIME) {
2038 /* XXX another gem from the Broadcom driver :( */
2039 ap->state = ANEG_STATE_LINK_OK;
2043 case ANEG_STATE_LINK_OK:
2044 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2048 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2049 /* ??? unimplemented */
2052 case ANEG_STATE_NEXT_PAGE_WAIT:
2053 /* ??? unimplemented */
2064 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2067 struct tg3_fiber_aneginfo aninfo;
2068 int status = ANEG_FAILED;
2072 tw32_f(MAC_TX_AUTO_NEG, 0);
2074 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2075 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2078 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2081 memset(&aninfo, 0, sizeof(aninfo));
2082 aninfo.flags |= MR_AN_ENABLE;
2083 aninfo.state = ANEG_STATE_UNKNOWN;
2084 aninfo.cur_time = 0;
2086 while (++tick < 195000) {
2087 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2088 if (status == ANEG_DONE || status == ANEG_FAILED)
2094 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2095 tw32_f(MAC_MODE, tp->mac_mode);
2098 *flags = aninfo.flags;
2100 if (status == ANEG_DONE &&
2101 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2102 MR_LP_ADV_FULL_DUPLEX)))
2108 static void tg3_init_bcm8002(struct tg3 *tp)
2110 u32 mac_status = tr32(MAC_STATUS);
2113 /* Reset when initting first time or we have a link. */
2114 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2115 !(mac_status & MAC_STATUS_PCS_SYNCED))
2118 /* Set PLL lock range. */
2119 tg3_writephy(tp, 0x16, 0x8007);
2122 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2124 /* Wait for reset to complete. */
2125 /* XXX schedule_timeout() ... */
2126 for (i = 0; i < 500; i++)
2129 /* Config mode; select PMA/Ch 1 regs. */
2130 tg3_writephy(tp, 0x10, 0x8411);
2132 /* Enable auto-lock and comdet, select txclk for tx. */
2133 tg3_writephy(tp, 0x11, 0x0a10);
2135 tg3_writephy(tp, 0x18, 0x00a0);
2136 tg3_writephy(tp, 0x16, 0x41ff);
2138 /* Assert and deassert POR. */
2139 tg3_writephy(tp, 0x13, 0x0400);
2141 tg3_writephy(tp, 0x13, 0x0000);
2143 tg3_writephy(tp, 0x11, 0x0a50);
2145 tg3_writephy(tp, 0x11, 0x0a10);
2147 /* Wait for signal to stabilize */
2148 /* XXX schedule_timeout() ... */
2149 for (i = 0; i < 15000; i++)
2152 /* Deselect the channel register so we can read the PHYID
2155 tg3_writephy(tp, 0x10, 0x8011);
2158 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2160 u32 sg_dig_ctrl, sg_dig_status;
2161 u32 serdes_cfg, expected_sg_dig_ctrl;
2162 int workaround, port_a;
2163 int current_link_up;
2166 expected_sg_dig_ctrl = 0;
2169 current_link_up = 0;
2171 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2172 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2174 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2177 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2178 /* preserve bits 20-23 for voltage regulator */
2179 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2182 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2184 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2185 if (sg_dig_ctrl & (1 << 31)) {
2187 u32 val = serdes_cfg;
2193 tw32_f(MAC_SERDES_CFG, val);
2195 tw32_f(SG_DIG_CTRL, 0x01388400);
2197 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2198 tg3_setup_flow_control(tp, 0, 0);
2199 current_link_up = 1;
2204 /* Want auto-negotiation. */
2205 expected_sg_dig_ctrl = 0x81388400;
2207 /* Pause capability */
2208 expected_sg_dig_ctrl |= (1 << 11);
2210 /* Asymettric pause */
2211 expected_sg_dig_ctrl |= (1 << 12);
2213 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2215 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2216 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2218 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2220 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2221 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2222 MAC_STATUS_SIGNAL_DET)) {
2225 /* Giver time to negotiate (~200ms) */
2226 for (i = 0; i < 40000; i++) {
2227 sg_dig_status = tr32(SG_DIG_STATUS);
2228 if (sg_dig_status & (0x3))
2232 mac_status = tr32(MAC_STATUS);
2234 if ((sg_dig_status & (1 << 1)) &&
2235 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2236 u32 local_adv, remote_adv;
2238 local_adv = ADVERTISE_PAUSE_CAP;
2240 if (sg_dig_status & (1 << 19))
2241 remote_adv |= LPA_PAUSE_CAP;
2242 if (sg_dig_status & (1 << 20))
2243 remote_adv |= LPA_PAUSE_ASYM;
2245 tg3_setup_flow_control(tp, local_adv, remote_adv);
2246 current_link_up = 1;
2247 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2248 } else if (!(sg_dig_status & (1 << 1))) {
2249 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2250 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2253 u32 val = serdes_cfg;
2260 tw32_f(MAC_SERDES_CFG, val);
2263 tw32_f(SG_DIG_CTRL, 0x01388400);
2266 /* Link parallel detection - link is up */
2267 /* only if we have PCS_SYNC and not */
2268 /* receiving config code words */
2269 mac_status = tr32(MAC_STATUS);
2270 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2271 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2272 tg3_setup_flow_control(tp, 0, 0);
2273 current_link_up = 1;
2280 return current_link_up;
2283 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2285 int current_link_up = 0;
2287 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2288 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2292 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2296 if (fiber_autoneg(tp, &flags)) {
2297 u32 local_adv, remote_adv;
2299 local_adv = ADVERTISE_PAUSE_CAP;
2301 if (flags & MR_LP_ADV_SYM_PAUSE)
2302 remote_adv |= LPA_PAUSE_CAP;
2303 if (flags & MR_LP_ADV_ASYM_PAUSE)
2304 remote_adv |= LPA_PAUSE_ASYM;
2306 tg3_setup_flow_control(tp, local_adv, remote_adv);
2308 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2309 current_link_up = 1;
2311 for (i = 0; i < 30; i++) {
2314 (MAC_STATUS_SYNC_CHANGED |
2315 MAC_STATUS_CFG_CHANGED));
2317 if ((tr32(MAC_STATUS) &
2318 (MAC_STATUS_SYNC_CHANGED |
2319 MAC_STATUS_CFG_CHANGED)) == 0)
2323 mac_status = tr32(MAC_STATUS);
2324 if (current_link_up == 0 &&
2325 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2326 !(mac_status & MAC_STATUS_RCVD_CFG))
2327 current_link_up = 1;
2329 /* Forcing 1000FD link up. */
2330 current_link_up = 1;
2331 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2333 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2338 return current_link_up;
2341 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2344 u16 orig_active_speed;
2345 u8 orig_active_duplex;
2347 int current_link_up;
2351 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2352 TG3_FLAG_TX_PAUSE));
2353 orig_active_speed = tp->link_config.active_speed;
2354 orig_active_duplex = tp->link_config.active_duplex;
2356 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2357 netif_carrier_ok(tp->dev) &&
2358 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2359 mac_status = tr32(MAC_STATUS);
2360 mac_status &= (MAC_STATUS_PCS_SYNCED |
2361 MAC_STATUS_SIGNAL_DET |
2362 MAC_STATUS_CFG_CHANGED |
2363 MAC_STATUS_RCVD_CFG);
2364 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2365 MAC_STATUS_SIGNAL_DET)) {
2366 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2367 MAC_STATUS_CFG_CHANGED));
2372 tw32_f(MAC_TX_AUTO_NEG, 0);
2374 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2375 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2376 tw32_f(MAC_MODE, tp->mac_mode);
2379 if (tp->phy_id == PHY_ID_BCM8002)
2380 tg3_init_bcm8002(tp);
2382 /* Enable link change event even when serdes polling. */
2383 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2386 current_link_up = 0;
2387 mac_status = tr32(MAC_STATUS);
2389 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2390 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2392 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2394 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2395 tw32_f(MAC_MODE, tp->mac_mode);
2398 tp->hw_status->status =
2399 (SD_STATUS_UPDATED |
2400 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2402 for (i = 0; i < 100; i++) {
2403 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2404 MAC_STATUS_CFG_CHANGED));
2406 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2407 MAC_STATUS_CFG_CHANGED)) == 0)
2411 mac_status = tr32(MAC_STATUS);
2412 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2413 current_link_up = 0;
2414 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2415 tw32_f(MAC_MODE, (tp->mac_mode |
2416 MAC_MODE_SEND_CONFIGS));
2418 tw32_f(MAC_MODE, tp->mac_mode);
2422 if (current_link_up == 1) {
2423 tp->link_config.active_speed = SPEED_1000;
2424 tp->link_config.active_duplex = DUPLEX_FULL;
2425 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2426 LED_CTRL_LNKLED_OVERRIDE |
2427 LED_CTRL_1000MBPS_ON));
2429 tp->link_config.active_speed = SPEED_INVALID;
2430 tp->link_config.active_duplex = DUPLEX_INVALID;
2431 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2432 LED_CTRL_LNKLED_OVERRIDE |
2433 LED_CTRL_TRAFFIC_OVERRIDE));
2436 if (current_link_up != netif_carrier_ok(tp->dev)) {
2437 if (current_link_up)
2438 netif_carrier_on(tp->dev);
2440 netif_carrier_off(tp->dev);
2441 tg3_link_report(tp);
2444 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2446 if (orig_pause_cfg != now_pause_cfg ||
2447 orig_active_speed != tp->link_config.active_speed ||
2448 orig_active_duplex != tp->link_config.active_duplex)
2449 tg3_link_report(tp);
2455 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2459 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2460 err = tg3_setup_fiber_phy(tp, force_reset);
2462 err = tg3_setup_copper_phy(tp, force_reset);
2465 if (tp->link_config.active_speed == SPEED_1000 &&
2466 tp->link_config.active_duplex == DUPLEX_HALF)
2467 tw32(MAC_TX_LENGTHS,
2468 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2469 (6 << TX_LENGTHS_IPG_SHIFT) |
2470 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2472 tw32(MAC_TX_LENGTHS,
2473 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2474 (6 << TX_LENGTHS_IPG_SHIFT) |
2475 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2477 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2478 if (netif_carrier_ok(tp->dev)) {
2479 tw32(HOSTCC_STAT_COAL_TICKS,
2480 DEFAULT_STAT_COAL_TICKS);
2482 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2489 /* Tigon3 never reports partial packet sends. So we do not
2490 * need special logic to handle SKBs that have not had all
2491 * of their frags sent yet, like SunGEM does.
2493 static void tg3_tx(struct tg3 *tp)
2495 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2496 u32 sw_idx = tp->tx_cons;
2498 while (sw_idx != hw_idx) {
2499 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2500 struct sk_buff *skb = ri->skb;
2503 if (unlikely(skb == NULL))
2506 pci_unmap_single(tp->pdev,
2507 pci_unmap_addr(ri, mapping),
2513 sw_idx = NEXT_TX(sw_idx);
2515 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2516 if (unlikely(sw_idx == hw_idx))
2519 ri = &tp->tx_buffers[sw_idx];
2520 if (unlikely(ri->skb != NULL))
2523 pci_unmap_page(tp->pdev,
2524 pci_unmap_addr(ri, mapping),
2525 skb_shinfo(skb)->frags[i].size,
2528 sw_idx = NEXT_TX(sw_idx);
2531 dev_kfree_skb_irq(skb);
2534 tp->tx_cons = sw_idx;
2536 if (netif_queue_stopped(tp->dev) &&
2537 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2538 netif_wake_queue(tp->dev);
2541 /* Returns size of skb allocated or < 0 on error.
2543 * We only need to fill in the address because the other members
2544 * of the RX descriptor are invariant, see tg3_init_rings.
2546 * Note the purposeful assymetry of cpu vs. chip accesses. For
2547 * posting buffers we only dirty the first cache line of the RX
2548 * descriptor (containing the address). Whereas for the RX status
2549 * buffers the cpu only reads the last cacheline of the RX descriptor
2550 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2552 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2553 int src_idx, u32 dest_idx_unmasked)
2555 struct tg3_rx_buffer_desc *desc;
2556 struct ring_info *map, *src_map;
2557 struct sk_buff *skb;
2559 int skb_size, dest_idx;
2562 switch (opaque_key) {
2563 case RXD_OPAQUE_RING_STD:
2564 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2565 desc = &tp->rx_std[dest_idx];
2566 map = &tp->rx_std_buffers[dest_idx];
2568 src_map = &tp->rx_std_buffers[src_idx];
2569 skb_size = RX_PKT_BUF_SZ;
2572 case RXD_OPAQUE_RING_JUMBO:
2573 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2574 desc = &tp->rx_jumbo[dest_idx];
2575 map = &tp->rx_jumbo_buffers[dest_idx];
2577 src_map = &tp->rx_jumbo_buffers[src_idx];
2578 skb_size = RX_JUMBO_PKT_BUF_SZ;
2585 /* Do not overwrite any of the map or rp information
2586 * until we are sure we can commit to a new buffer.
2588 * Callers depend upon this behavior and assume that
2589 * we leave everything unchanged if we fail.
2591 skb = dev_alloc_skb(skb_size);
2596 skb_reserve(skb, tp->rx_offset);
2598 mapping = pci_map_single(tp->pdev, skb->data,
2599 skb_size - tp->rx_offset,
2600 PCI_DMA_FROMDEVICE);
2603 pci_unmap_addr_set(map, mapping, mapping);
2605 if (src_map != NULL)
2606 src_map->skb = NULL;
2608 desc->addr_hi = ((u64)mapping >> 32);
2609 desc->addr_lo = ((u64)mapping & 0xffffffff);
2614 /* We only need to move over in the address because the other
2615 * members of the RX descriptor are invariant. See notes above
2616 * tg3_alloc_rx_skb for full details.
2618 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2619 int src_idx, u32 dest_idx_unmasked)
2621 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2622 struct ring_info *src_map, *dest_map;
2625 switch (opaque_key) {
2626 case RXD_OPAQUE_RING_STD:
2627 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2628 dest_desc = &tp->rx_std[dest_idx];
2629 dest_map = &tp->rx_std_buffers[dest_idx];
2630 src_desc = &tp->rx_std[src_idx];
2631 src_map = &tp->rx_std_buffers[src_idx];
2634 case RXD_OPAQUE_RING_JUMBO:
2635 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2636 dest_desc = &tp->rx_jumbo[dest_idx];
2637 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2638 src_desc = &tp->rx_jumbo[src_idx];
2639 src_map = &tp->rx_jumbo_buffers[src_idx];
2646 dest_map->skb = src_map->skb;
2647 pci_unmap_addr_set(dest_map, mapping,
2648 pci_unmap_addr(src_map, mapping));
2649 dest_desc->addr_hi = src_desc->addr_hi;
2650 dest_desc->addr_lo = src_desc->addr_lo;
2652 src_map->skb = NULL;
2655 #if TG3_VLAN_TAG_USED
2656 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
2658 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
2662 /* The RX ring scheme is composed of multiple rings which post fresh
2663 * buffers to the chip, and one special ring the chip uses to report
2664 * status back to the host.
2666 * The special ring reports the status of received packets to the
2667 * host. The chip does not write into the original descriptor the
2668 * RX buffer was obtained from. The chip simply takes the original
2669 * descriptor as provided by the host, updates the status and length
2670 * field, then writes this into the next status ring entry.
2672 * Each ring the host uses to post buffers to the chip is described
2673 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
2674 * it is first placed into the on-chip ram. When the packet's length
2675 * is known, it walks down the TG3_BDINFO entries to select the ring.
2676 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2677 * which is within the range of the new packet's length is chosen.
2679 * The "separate ring for rx status" scheme may sound queer, but it makes
2680 * sense from a cache coherency perspective. If only the host writes
2681 * to the buffer post rings, and only the chip writes to the rx status
2682 * rings, then cache lines never move beyond shared-modified state.
2683 * If both the host and chip were to write into the same ring, cache line
2684 * eviction could occur since both entities want it in an exclusive state.
2686 static int tg3_rx(struct tg3 *tp, int budget)
2689 u32 rx_rcb_ptr = tp->rx_rcb_ptr;
2693 hw_idx = tp->hw_status->idx[0].rx_producer;
2695 * We need to order the read of hw_idx and the read of
2696 * the opaque cookie.
2699 sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
2702 while (sw_idx != hw_idx && budget > 0) {
2703 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
2705 struct sk_buff *skb;
2706 dma_addr_t dma_addr;
2707 u32 opaque_key, desc_idx, *post_ptr;
2709 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
2710 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
2711 if (opaque_key == RXD_OPAQUE_RING_STD) {
2712 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
2714 skb = tp->rx_std_buffers[desc_idx].skb;
2715 post_ptr = &tp->rx_std_ptr;
2716 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
2717 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
2719 skb = tp->rx_jumbo_buffers[desc_idx].skb;
2720 post_ptr = &tp->rx_jumbo_ptr;
2723 goto next_pkt_nopost;
2726 work_mask |= opaque_key;
2728 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
2729 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
2731 tg3_recycle_rx(tp, opaque_key,
2732 desc_idx, *post_ptr);
2734 /* Other statistics kept track of by card. */
2735 tp->net_stats.rx_dropped++;
2739 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
2741 if (len > RX_COPY_THRESHOLD
2742 && tp->rx_offset == 2
2743 /* rx_offset != 2 iff this is a 5701 card running
2744 * in PCI-X mode [see tg3_get_invariants()] */
2748 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
2749 desc_idx, *post_ptr);
2753 pci_unmap_single(tp->pdev, dma_addr,
2754 skb_size - tp->rx_offset,
2755 PCI_DMA_FROMDEVICE);
2759 struct sk_buff *copy_skb;
2761 tg3_recycle_rx(tp, opaque_key,
2762 desc_idx, *post_ptr);
2764 copy_skb = dev_alloc_skb(len + 2);
2765 if (copy_skb == NULL)
2766 goto drop_it_no_recycle;
2768 copy_skb->dev = tp->dev;
2769 skb_reserve(copy_skb, 2);
2770 skb_put(copy_skb, len);
2771 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2772 memcpy(copy_skb->data, skb->data, len);
2773 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2775 /* We'll reuse the original ring buffer. */
2779 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
2780 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
2781 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
2782 >> RXD_TCPCSUM_SHIFT) == 0xffff))
2783 skb->ip_summed = CHECKSUM_UNNECESSARY;
2785 skb->ip_summed = CHECKSUM_NONE;
2787 skb->protocol = eth_type_trans(skb, tp->dev);
2788 #if TG3_VLAN_TAG_USED
2789 if (tp->vlgrp != NULL &&
2790 desc->type_flags & RXD_FLAG_VLAN) {
2791 tg3_vlan_rx(tp, skb,
2792 desc->err_vlan & RXD_VLAN_MASK);
2795 netif_receive_skb(skb);
2797 tp->dev->last_rx = jiffies;
2805 sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
2808 /* ACK the status ring. */
2809 tp->rx_rcb_ptr = rx_rcb_ptr;
2810 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW,
2811 (rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp)));
2813 /* Refill RX ring(s). */
2814 if (work_mask & RXD_OPAQUE_RING_STD) {
2815 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
2816 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2819 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2820 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
2821 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
2829 static int tg3_poll(struct net_device *netdev, int *budget)
2831 struct tg3 *tp = netdev_priv(netdev);
2832 struct tg3_hw_status *sblk = tp->hw_status;
2833 unsigned long flags;
2836 spin_lock_irqsave(&tp->lock, flags);
2838 /* handle link change and other phy events */
2839 if (!(tp->tg3_flags &
2840 (TG3_FLAG_USE_LINKCHG_REG |
2841 TG3_FLAG_POLL_SERDES))) {
2842 if (sblk->status & SD_STATUS_LINK_CHG) {
2843 sblk->status = SD_STATUS_UPDATED |
2844 (sblk->status & ~SD_STATUS_LINK_CHG);
2845 tg3_setup_phy(tp, 0);
2849 /* run TX completion thread */
2850 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
2851 spin_lock(&tp->tx_lock);
2853 spin_unlock(&tp->tx_lock);
2856 spin_unlock_irqrestore(&tp->lock, flags);
2858 /* run RX thread, within the bounds set by NAPI.
2859 * All RX "locking" is done by ensuring outside
2860 * code synchronizes with dev->poll()
2863 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
2864 int orig_budget = *budget;
2867 if (orig_budget > netdev->quota)
2868 orig_budget = netdev->quota;
2870 work_done = tg3_rx(tp, orig_budget);
2872 *budget -= work_done;
2873 netdev->quota -= work_done;
2875 if (work_done >= orig_budget)
2879 /* if no more work, tell net stack and NIC we're done */
2881 spin_lock_irqsave(&tp->lock, flags);
2882 __netif_rx_complete(netdev);
2883 tg3_restart_ints(tp);
2884 spin_unlock_irqrestore(&tp->lock, flags);
2887 return (done ? 0 : 1);
2890 static inline unsigned int tg3_has_work(struct net_device *dev, struct tg3 *tp)
2892 struct tg3_hw_status *sblk = tp->hw_status;
2893 unsigned int work_exists = 0;
2895 /* check for phy events */
2896 if (!(tp->tg3_flags &
2897 (TG3_FLAG_USE_LINKCHG_REG |
2898 TG3_FLAG_POLL_SERDES))) {
2899 if (sblk->status & SD_STATUS_LINK_CHG)
2902 /* check for RX/TX work to do */
2903 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
2904 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
2910 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2912 struct net_device *dev = dev_id;
2913 struct tg3 *tp = netdev_priv(dev);
2914 struct tg3_hw_status *sblk = tp->hw_status;
2915 unsigned long flags;
2916 unsigned int handled = 1;
2918 spin_lock_irqsave(&tp->lock, flags);
2920 /* In INTx mode, it is possible for the interrupt to arrive at
2921 * the CPU before the status block posted prior to the interrupt.
2922 * Reading the PCI State register will confirm whether the
2923 * interrupt is ours and will flush the status block.
2925 if ((sblk->status & SD_STATUS_UPDATED) ||
2926 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
2928 * writing any value to intr-mbox-0 clears PCI INTA# and
2929 * chip-internal interrupt pending events.
2930 * writing non-zero to intr-mbox-0 additional tells the
2931 * NIC to stop sending us irqs, engaging "in-intr-handler"
2934 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2937 * Flush PCI write. This also guarantees that our
2938 * status block has been flushed to host memory.
2940 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
2941 sblk->status &= ~SD_STATUS_UPDATED;
2943 if (likely(tg3_has_work(dev, tp)))
2944 netif_rx_schedule(dev); /* schedule NAPI poll */
2946 /* no work, shared interrupt perhaps? re-enable
2947 * interrupts, and flush that PCI write
2949 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2951 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
2953 } else { /* shared interrupt */
2957 spin_unlock_irqrestore(&tp->lock, flags);
2959 return IRQ_RETVAL(handled);
2962 static int tg3_init_hw(struct tg3 *);
2963 static int tg3_halt(struct tg3 *);
2965 #ifdef CONFIG_NET_POLL_CONTROLLER
2966 static void tg3_poll_controller(struct net_device *dev)
2968 tg3_interrupt(dev->irq, dev, NULL);
2972 static void tg3_reset_task(void *_data)
2974 struct tg3 *tp = _data;
2975 unsigned int restart_timer;
2979 spin_lock_irq(&tp->lock);
2980 spin_lock(&tp->tx_lock);
2982 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
2983 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
2988 tg3_netif_start(tp);
2990 spin_unlock(&tp->tx_lock);
2991 spin_unlock_irq(&tp->lock);
2994 mod_timer(&tp->timer, jiffies + 1);
2997 static void tg3_tx_timeout(struct net_device *dev)
2999 struct tg3 *tp = netdev_priv(dev);
3001 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3004 schedule_work(&tp->reset_task);
3007 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3009 static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3010 u32 guilty_entry, int guilty_len,
3011 u32 last_plus_one, u32 *start, u32 mss)
3013 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3014 dma_addr_t new_addr;
3023 /* New SKB is guaranteed to be linear. */
3025 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3027 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3028 (skb->ip_summed == CHECKSUM_HW) ?
3029 TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
3030 *start = NEXT_TX(entry);
3032 /* Now clean up the sw ring entries. */
3034 while (entry != last_plus_one) {
3038 len = skb_headlen(skb);
3040 len = skb_shinfo(skb)->frags[i-1].size;
3041 pci_unmap_single(tp->pdev,
3042 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3043 len, PCI_DMA_TODEVICE);
3045 tp->tx_buffers[entry].skb = new_skb;
3046 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3048 tp->tx_buffers[entry].skb = NULL;
3050 entry = NEXT_TX(entry);
3059 static void tg3_set_txd(struct tg3 *tp, int entry,
3060 dma_addr_t mapping, int len, u32 flags,
3063 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3064 int is_end = (mss_and_is_end & 0x1);
3065 u32 mss = (mss_and_is_end >> 1);
3069 flags |= TXD_FLAG_END;
3070 if (flags & TXD_FLAG_VLAN) {
3071 vlan_tag = flags >> 16;
3074 vlan_tag |= (mss << TXD_MSS_SHIFT);
3076 txd->addr_hi = ((u64) mapping >> 32);
3077 txd->addr_lo = ((u64) mapping & 0xffffffff);
3078 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3079 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3082 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3084 u32 base = (u32) mapping & 0xffffffff;
3086 return ((base > 0xffffdcc0) &&
3087 (base + len + 8 < base));
3090 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3092 struct tg3 *tp = netdev_priv(dev);
3095 u32 len, entry, base_flags, mss;
3096 int would_hit_hwbug;
3097 unsigned long flags;
3099 len = skb_headlen(skb);
3101 /* No BH disabling for tx_lock here. We are running in BH disabled
3102 * context and TX reclaim runs via tp->poll inside of a software
3103 * interrupt. Rejoice!
3105 * Actually, things are not so simple. If we are to take a hw
3106 * IRQ here, we can deadlock, consider:
3115 * spin on tp->tx_lock
3117 * So we really do need to disable interrupts when taking
3120 local_irq_save(flags);
3121 if (!spin_trylock(&tp->tx_lock)) {
3122 local_irq_restore(flags);
3123 return NETDEV_TX_LOCKED;
3126 /* This is a hard error, log it. */
3127 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3128 netif_stop_queue(dev);
3129 spin_unlock_irqrestore(&tp->tx_lock, flags);
3130 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3132 return NETDEV_TX_BUSY;
3135 entry = tp->tx_prod;
3137 if (skb->ip_summed == CHECKSUM_HW)
3138 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3139 #if TG3_TSO_SUPPORT != 0
3141 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3142 (mss = skb_shinfo(skb)->tso_size) != 0) {
3143 int tcp_opt_len, ip_tcp_len;
3145 if (skb_header_cloned(skb) &&
3146 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3151 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3152 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3154 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3155 TXD_FLAG_CPU_POST_DMA);
3157 skb->nh.iph->check = 0;
3158 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3159 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3160 skb->h.th->check = 0;
3161 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3165 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3170 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3171 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3172 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3175 tsflags = ((skb->nh.iph->ihl - 5) +
3176 (tcp_opt_len >> 2));
3177 mss |= (tsflags << 11);
3180 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3183 tsflags = ((skb->nh.iph->ihl - 5) +
3184 (tcp_opt_len >> 2));
3185 base_flags |= tsflags << 12;
3192 #if TG3_VLAN_TAG_USED
3193 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3194 base_flags |= (TXD_FLAG_VLAN |
3195 (vlan_tx_tag_get(skb) << 16));
3198 /* Queue skb data, a.k.a. the main skb fragment. */
3199 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3201 tp->tx_buffers[entry].skb = skb;
3202 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3204 would_hit_hwbug = 0;
3206 if (tg3_4g_overflow_test(mapping, len))
3207 would_hit_hwbug = entry + 1;
3209 tg3_set_txd(tp, entry, mapping, len, base_flags,
3210 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3212 entry = NEXT_TX(entry);
3214 /* Now loop through additional data fragments, and queue them. */
3215 if (skb_shinfo(skb)->nr_frags > 0) {
3216 unsigned int i, last;
3218 last = skb_shinfo(skb)->nr_frags - 1;
3219 for (i = 0; i <= last; i++) {
3220 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3223 mapping = pci_map_page(tp->pdev,
3226 len, PCI_DMA_TODEVICE);
3228 tp->tx_buffers[entry].skb = NULL;
3229 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3231 if (tg3_4g_overflow_test(mapping, len)) {
3232 /* Only one should match. */
3233 if (would_hit_hwbug)
3235 would_hit_hwbug = entry + 1;
3238 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3239 tg3_set_txd(tp, entry, mapping, len,
3240 base_flags, (i == last)|(mss << 1));
3242 tg3_set_txd(tp, entry, mapping, len,
3243 base_flags, (i == last));
3245 entry = NEXT_TX(entry);
3249 if (would_hit_hwbug) {
3250 u32 last_plus_one = entry;
3252 unsigned int len = 0;
3254 would_hit_hwbug -= 1;
3255 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3256 entry &= (TG3_TX_RING_SIZE - 1);
3259 while (entry != last_plus_one) {
3261 len = skb_headlen(skb);
3263 len = skb_shinfo(skb)->frags[i-1].size;
3265 if (entry == would_hit_hwbug)
3269 entry = NEXT_TX(entry);
3273 /* If the workaround fails due to memory/mapping
3274 * failure, silently drop this packet.
3276 if (tigon3_4gb_hwbug_workaround(tp, skb,
3285 /* Packets are ready, update Tx producer idx local and on card. */
3286 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3288 tp->tx_prod = entry;
3289 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
3290 netif_stop_queue(dev);
3294 spin_unlock_irqrestore(&tp->tx_lock, flags);
3296 dev->trans_start = jiffies;
3298 return NETDEV_TX_OK;
3301 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3306 if (new_mtu > ETH_DATA_LEN)
3307 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
3309 tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE;
3312 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3314 struct tg3 *tp = netdev_priv(dev);
3316 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3319 if (!netif_running(dev)) {
3320 /* We'll just catch it later when the
3323 tg3_set_mtu(dev, tp, new_mtu);
3328 spin_lock_irq(&tp->lock);
3329 spin_lock(&tp->tx_lock);
3333 tg3_set_mtu(dev, tp, new_mtu);
3337 tg3_netif_start(tp);
3339 spin_unlock(&tp->tx_lock);
3340 spin_unlock_irq(&tp->lock);
3345 /* Free up pending packets in all rx/tx rings.
3347 * The chip has been shut down and the driver detached from
3348 * the networking, so no interrupts or new tx packets will
3349 * end up in the driver. tp->{tx,}lock is not held and we are not
3350 * in an interrupt context and thus may sleep.
3352 static void tg3_free_rings(struct tg3 *tp)
3354 struct ring_info *rxp;
3357 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3358 rxp = &tp->rx_std_buffers[i];
3360 if (rxp->skb == NULL)
3362 pci_unmap_single(tp->pdev,
3363 pci_unmap_addr(rxp, mapping),
3364 RX_PKT_BUF_SZ - tp->rx_offset,
3365 PCI_DMA_FROMDEVICE);
3366 dev_kfree_skb_any(rxp->skb);
3370 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3371 rxp = &tp->rx_jumbo_buffers[i];
3373 if (rxp->skb == NULL)
3375 pci_unmap_single(tp->pdev,
3376 pci_unmap_addr(rxp, mapping),
3377 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3378 PCI_DMA_FROMDEVICE);
3379 dev_kfree_skb_any(rxp->skb);
3383 for (i = 0; i < TG3_TX_RING_SIZE; ) {
3384 struct tx_ring_info *txp;
3385 struct sk_buff *skb;
3388 txp = &tp->tx_buffers[i];
3396 pci_unmap_single(tp->pdev,
3397 pci_unmap_addr(txp, mapping),
3404 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3405 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3406 pci_unmap_page(tp->pdev,
3407 pci_unmap_addr(txp, mapping),
3408 skb_shinfo(skb)->frags[j].size,
3413 dev_kfree_skb_any(skb);
3417 /* Initialize tx/rx rings for packet processing.
3419 * The chip has been shut down and the driver detached from
3420 * the networking, so no interrupts or new tx packets will
3421 * end up in the driver. tp->{tx,}lock are held and thus
3424 static void tg3_init_rings(struct tg3 *tp)
3428 /* Free up all the SKBs. */
3431 /* Zero out all descriptors. */
3432 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3433 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3434 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3435 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3437 /* Initialize invariants of the rings, we only set this
3438 * stuff once. This works because the card does not
3439 * write into the rx buffer posting rings.
3441 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3442 struct tg3_rx_buffer_desc *rxd;
3444 rxd = &tp->rx_std[i];
3445 rxd->idx_len = (RX_PKT_BUF_SZ - tp->rx_offset - 64)
3447 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3448 rxd->opaque = (RXD_OPAQUE_RING_STD |
3449 (i << RXD_OPAQUE_INDEX_SHIFT));
3452 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3453 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3454 struct tg3_rx_buffer_desc *rxd;
3456 rxd = &tp->rx_jumbo[i];
3457 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3459 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3461 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3462 (i << RXD_OPAQUE_INDEX_SHIFT));
3466 /* Now allocate fresh SKBs for each rx ring. */
3467 for (i = 0; i < tp->rx_pending; i++) {
3468 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3473 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3474 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3475 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3483 * Must not be invoked with interrupt sources disabled and
3484 * the hardware shutdown down.
3486 static void tg3_free_consistent(struct tg3 *tp)
3488 if (tp->rx_std_buffers) {
3489 kfree(tp->rx_std_buffers);
3490 tp->rx_std_buffers = NULL;
3493 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3494 tp->rx_std, tp->rx_std_mapping);
3498 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3499 tp->rx_jumbo, tp->rx_jumbo_mapping);
3500 tp->rx_jumbo = NULL;
3503 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3504 tp->rx_rcb, tp->rx_rcb_mapping);
3508 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3509 tp->tx_ring, tp->tx_desc_mapping);
3512 if (tp->hw_status) {
3513 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3514 tp->hw_status, tp->status_mapping);
3515 tp->hw_status = NULL;
3518 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3519 tp->hw_stats, tp->stats_mapping);
3520 tp->hw_stats = NULL;
3525 * Must not be invoked with interrupt sources disabled and
3526 * the hardware shutdown down. Can sleep.
3528 static int tg3_alloc_consistent(struct tg3 *tp)
3530 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3532 TG3_RX_JUMBO_RING_SIZE)) +
3533 (sizeof(struct tx_ring_info) *
3536 if (!tp->rx_std_buffers)
3539 memset(tp->rx_std_buffers, 0,
3540 (sizeof(struct ring_info) *
3542 TG3_RX_JUMBO_RING_SIZE)) +
3543 (sizeof(struct tx_ring_info) *
3546 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3547 tp->tx_buffers = (struct tx_ring_info *)
3548 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3550 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3551 &tp->rx_std_mapping);
3555 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3556 &tp->rx_jumbo_mapping);
3561 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3562 &tp->rx_rcb_mapping);
3566 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
3567 &tp->tx_desc_mapping);
3571 tp->hw_status = pci_alloc_consistent(tp->pdev,
3573 &tp->status_mapping);
3577 tp->hw_stats = pci_alloc_consistent(tp->pdev,
3578 sizeof(struct tg3_hw_stats),
3579 &tp->stats_mapping);
3583 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3584 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3589 tg3_free_consistent(tp);
3593 #define MAX_WAIT_CNT 1000
3595 /* To stop a block, clear the enable bit and poll till it
3596 * clears. tp->lock is held.
3598 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit)
3603 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
3610 /* We can't enable/disable these bits of the
3611 * 5705/5750, just say success.
3624 for (i = 0; i < MAX_WAIT_CNT; i++) {
3627 if ((val & enable_bit) == 0)
3631 if (i == MAX_WAIT_CNT) {
3632 printk(KERN_ERR PFX "tg3_stop_block timed out, "
3633 "ofs=%lx enable_bit=%x\n",
3641 /* tp->lock is held. */
3642 static int tg3_abort_hw(struct tg3 *tp)
3646 tg3_disable_ints(tp);
3648 tp->rx_mode &= ~RX_MODE_ENABLE;
3649 tw32_f(MAC_RX_MODE, tp->rx_mode);
3652 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE);
3653 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE);
3654 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE);
3655 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE);
3656 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE);
3657 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE);
3659 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE);
3660 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE);
3661 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
3662 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE);
3663 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
3664 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE);
3665 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE);
3669 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
3670 tw32_f(MAC_MODE, tp->mac_mode);
3673 tp->tx_mode &= ~TX_MODE_ENABLE;
3674 tw32_f(MAC_TX_MODE, tp->tx_mode);
3676 for (i = 0; i < MAX_WAIT_CNT; i++) {
3678 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
3681 if (i >= MAX_WAIT_CNT) {
3682 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
3683 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3684 tp->dev->name, tr32(MAC_TX_MODE));
3688 err = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
3689 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE);
3690 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
3692 tw32(FTQ_RESET, 0xffffffff);
3693 tw32(FTQ_RESET, 0x00000000);
3695 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
3696 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
3701 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3703 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3709 /* tp->lock is held. */
3710 static int tg3_nvram_lock(struct tg3 *tp)
3712 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
3715 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3716 for (i = 0; i < 8000; i++) {
3717 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3727 /* tp->lock is held. */
3728 static void tg3_nvram_unlock(struct tg3 *tp)
3730 if (tp->tg3_flags & TG3_FLAG_NVRAM)
3731 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3734 /* tp->lock is held. */
3735 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
3737 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3738 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
3739 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
3741 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3743 case RESET_KIND_INIT:
3744 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3748 case RESET_KIND_SHUTDOWN:
3749 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3753 case RESET_KIND_SUSPEND:
3754 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3764 /* tp->lock is held. */
3765 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
3767 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3769 case RESET_KIND_INIT:
3770 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3771 DRV_STATE_START_DONE);
3774 case RESET_KIND_SHUTDOWN:
3775 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3776 DRV_STATE_UNLOAD_DONE);
3785 /* tp->lock is held. */
3786 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
3788 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3790 case RESET_KIND_INIT:
3791 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3795 case RESET_KIND_SHUTDOWN:
3796 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3800 case RESET_KIND_SUSPEND:
3801 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3811 static void tg3_stop_fw(struct tg3 *);
3813 /* tp->lock is held. */
3814 static int tg3_chip_reset(struct tg3 *tp)
3820 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3824 * We must avoid the readl() that normally takes place.
3825 * It locks machines, causes machine checks, and other
3826 * fun things. So, temporarily disable the 5701
3827 * hardware workaround, while we do the reset.
3829 flags_save = tp->tg3_flags;
3830 tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
3833 val = GRC_MISC_CFG_CORECLK_RESET;
3835 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3836 if (tr32(0x7e2c) == 0x60) {
3839 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3840 tw32(GRC_MISC_CFG, (1 << 29));
3845 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
3846 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
3847 tw32(GRC_MISC_CFG, val);
3849 /* restore 5701 hardware bug workaround flag */
3850 tp->tg3_flags = flags_save;
3852 /* Unfortunately, we have to delay before the PCI read back.
3853 * Some 575X chips even will not respond to a PCI cfg access
3854 * when the reset command is given to the chip.
3856 * How do these hardware designers expect things to work
3857 * properly if the PCI write is posted for a long period
3858 * of time? It is always necessary to have some method by
3859 * which a register read back can occur to push the write
3860 * out which does the reset.
3862 * For most tg3 variants the trick below was working.
3867 /* Flush PCI posted writes. The normal MMIO registers
3868 * are inaccessible at this time so this is the only
3869 * way to make this reliably (actually, this is no longer
3870 * the case, see above). I tried to use indirect
3871 * register read/write but this upset some 5701 variants.
3873 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
3877 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3878 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
3882 /* Wait for link training to complete. */
3883 for (i = 0; i < 5000; i++)
3886 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
3887 pci_write_config_dword(tp->pdev, 0xc4,
3888 cfg_val | (1 << 15));
3890 /* Set PCIE max payload size and clear error status. */
3891 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
3894 /* Re-enable indirect register accesses. */
3895 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
3896 tp->misc_host_ctrl);
3898 /* Set MAX PCI retry to zero. */
3899 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
3900 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
3901 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
3902 val |= PCISTATE_RETRY_SAME_DMA;
3903 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
3905 pci_restore_state(tp->pdev);
3907 /* Make sure PCI-X relaxed ordering bit is clear. */
3908 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
3909 val &= ~PCIX_CAPS_RELAXED_ORDERING;
3910 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
3912 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
3914 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
3916 tw32(0x5000, 0x400);
3919 tw32(GRC_MODE, tp->grc_mode);
3921 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
3922 u32 val = tr32(0xc4);
3924 tw32(0xc4, val | (1 << 15));
3927 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
3928 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3929 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
3930 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
3931 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
3932 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
3935 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3936 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
3937 tw32_f(MAC_MODE, tp->mac_mode);
3939 tw32_f(MAC_MODE, 0);
3942 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
3943 /* Wait for firmware initialization to complete. */
3944 for (i = 0; i < 100000; i++) {
3945 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
3946 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3951 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
3952 "firmware will not restart magic=%08x\n",
3953 tp->dev->name, val);
3958 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
3959 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3960 u32 val = tr32(0x7c00);
3962 tw32(0x7c00, val | (1 << 25));
3965 /* Reprobe ASF enable state. */
3966 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
3967 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
3968 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
3969 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
3972 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
3973 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
3974 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
3975 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
3976 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
3983 /* tp->lock is held. */
3984 static void tg3_stop_fw(struct tg3 *tp)
3986 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3990 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
3991 val = tr32(GRC_RX_CPU_EVENT);
3993 tw32(GRC_RX_CPU_EVENT, val);
3995 /* Wait for RX cpu to ACK the event. */
3996 for (i = 0; i < 100; i++) {
3997 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4004 /* tp->lock is held. */
4005 static int tg3_halt(struct tg3 *tp)
4011 tg3_write_sig_pre_reset(tp, RESET_KIND_SHUTDOWN);
4014 err = tg3_chip_reset(tp);
4016 tg3_write_sig_legacy(tp, RESET_KIND_SHUTDOWN);
4017 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4025 #define TG3_FW_RELEASE_MAJOR 0x0
4026 #define TG3_FW_RELASE_MINOR 0x0
4027 #define TG3_FW_RELEASE_FIX 0x0
4028 #define TG3_FW_START_ADDR 0x08000000
4029 #define TG3_FW_TEXT_ADDR 0x08000000
4030 #define TG3_FW_TEXT_LEN 0x9c0
4031 #define TG3_FW_RODATA_ADDR 0x080009c0
4032 #define TG3_FW_RODATA_LEN 0x60
4033 #define TG3_FW_DATA_ADDR 0x08000a40
4034 #define TG3_FW_DATA_LEN 0x20
4035 #define TG3_FW_SBSS_ADDR 0x08000a60
4036 #define TG3_FW_SBSS_LEN 0xc
4037 #define TG3_FW_BSS_ADDR 0x08000a70
4038 #define TG3_FW_BSS_LEN 0x10
4040 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4041 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4042 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4043 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4044 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4045 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4046 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4047 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4048 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4049 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4050 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4051 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4052 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4053 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4054 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4055 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4056 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4057 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4058 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4059 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4060 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4061 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4062 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4063 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4064 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4065 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4067 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4068 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4069 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4070 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4071 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4072 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4073 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4074 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4075 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4076 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4077 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4078 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4079 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4080 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4081 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4082 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4083 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4084 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4085 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4086 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4087 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4088 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4089 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4090 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4091 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4092 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4093 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4094 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4095 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4096 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4097 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4098 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4099 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4100 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4101 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4102 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4103 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4104 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4105 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4106 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4107 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4108 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4109 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4110 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4111 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4112 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4113 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4114 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4115 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4116 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4117 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4118 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4119 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4120 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4121 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4122 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4123 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4124 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4125 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4126 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4127 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4128 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4129 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4130 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4131 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4134 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4135 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4136 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4137 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4138 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4142 #if 0 /* All zeros, don't eat up space with it. */
4143 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4144 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4145 0x00000000, 0x00000000, 0x00000000, 0x00000000
4149 #define RX_CPU_SCRATCH_BASE 0x30000
4150 #define RX_CPU_SCRATCH_SIZE 0x04000
4151 #define TX_CPU_SCRATCH_BASE 0x34000
4152 #define TX_CPU_SCRATCH_SIZE 0x04000
4154 /* tp->lock is held. */
4155 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4159 if (offset == TX_CPU_BASE &&
4160 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4163 if (offset == RX_CPU_BASE) {
4164 for (i = 0; i < 10000; i++) {
4165 tw32(offset + CPU_STATE, 0xffffffff);
4166 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4167 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4171 tw32(offset + CPU_STATE, 0xffffffff);
4172 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4175 for (i = 0; i < 10000; i++) {
4176 tw32(offset + CPU_STATE, 0xffffffff);
4177 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4178 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4184 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4187 (offset == RX_CPU_BASE ? "RX" : "TX"));
4194 unsigned int text_base;
4195 unsigned int text_len;
4197 unsigned int rodata_base;
4198 unsigned int rodata_len;
4200 unsigned int data_base;
4201 unsigned int data_len;
4205 /* tp->lock is held. */
4206 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4207 int cpu_scratch_size, struct fw_info *info)
4210 u32 orig_tg3_flags = tp->tg3_flags;
4211 void (*write_op)(struct tg3 *, u32, u32);
4213 if (cpu_base == TX_CPU_BASE &&
4214 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4215 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4216 "TX cpu firmware on %s which is 5705.\n",
4221 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4222 write_op = tg3_write_mem;
4224 write_op = tg3_write_indirect_reg32;
4226 /* Force use of PCI config space for indirect register
4229 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
4231 err = tg3_halt_cpu(tp, cpu_base);
4235 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4236 write_op(tp, cpu_scratch_base + i, 0);
4237 tw32(cpu_base + CPU_STATE, 0xffffffff);
4238 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4239 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4240 write_op(tp, (cpu_scratch_base +
4241 (info->text_base & 0xffff) +
4244 info->text_data[i] : 0));
4245 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4246 write_op(tp, (cpu_scratch_base +
4247 (info->rodata_base & 0xffff) +
4249 (info->rodata_data ?
4250 info->rodata_data[i] : 0));
4251 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4252 write_op(tp, (cpu_scratch_base +
4253 (info->data_base & 0xffff) +
4256 info->data_data[i] : 0));
4261 tp->tg3_flags = orig_tg3_flags;
4265 /* tp->lock is held. */
4266 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4268 struct fw_info info;
4271 info.text_base = TG3_FW_TEXT_ADDR;
4272 info.text_len = TG3_FW_TEXT_LEN;
4273 info.text_data = &tg3FwText[0];
4274 info.rodata_base = TG3_FW_RODATA_ADDR;
4275 info.rodata_len = TG3_FW_RODATA_LEN;
4276 info.rodata_data = &tg3FwRodata[0];
4277 info.data_base = TG3_FW_DATA_ADDR;
4278 info.data_len = TG3_FW_DATA_LEN;
4279 info.data_data = NULL;
4281 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4282 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4287 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4288 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4293 /* Now startup only the RX cpu. */
4294 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4295 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4297 for (i = 0; i < 5; i++) {
4298 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4300 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4301 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
4302 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4306 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4307 "to set RX CPU PC, is %08x should be %08x\n",
4308 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4312 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4313 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
4318 #if TG3_TSO_SUPPORT != 0
4320 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
4321 #define TG3_TSO_FW_RELASE_MINOR 0x6
4322 #define TG3_TSO_FW_RELEASE_FIX 0x0
4323 #define TG3_TSO_FW_START_ADDR 0x08000000
4324 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
4325 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
4326 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4327 #define TG3_TSO_FW_RODATA_LEN 0x60
4328 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
4329 #define TG3_TSO_FW_DATA_LEN 0x30
4330 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4331 #define TG3_TSO_FW_SBSS_LEN 0x2c
4332 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
4333 #define TG3_TSO_FW_BSS_LEN 0x894
4335 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4336 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4337 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4338 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4339 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4340 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4341 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4342 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4343 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4344 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4345 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4346 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4347 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4348 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4349 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4350 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4351 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4352 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4353 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4354 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4355 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4356 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4357 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4358 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4359 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4360 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4361 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4362 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4363 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4364 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4365 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4366 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4367 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4368 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4369 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4370 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4371 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4372 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4373 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4374 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4375 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4376 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4377 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4378 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4379 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4380 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4381 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4382 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4383 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4384 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4385 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4386 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4387 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4388 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4389 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4390 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4391 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4392 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4393 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4394 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4395 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4396 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4397 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4398 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4399 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4400 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4401 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4402 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4403 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4404 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4405 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4406 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4407 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4408 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4409 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4410 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4411 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4412 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4413 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4414 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4415 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4416 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4417 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4418 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4419 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4420 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4421 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4422 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4423 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4424 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4425 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4426 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4427 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4428 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4429 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4430 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4431 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4432 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4433 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4434 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4435 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4436 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4437 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4438 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4439 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4440 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4441 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4442 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4443 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4444 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4445 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4446 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4447 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4448 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4449 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4450 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4451 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4452 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4453 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4454 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4455 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4456 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4457 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4458 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4459 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4460 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4461 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4462 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4463 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4464 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4465 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4466 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4467 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4468 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4469 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4470 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4471 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4472 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4473 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4474 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4475 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4476 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4477 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4478 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4479 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4480 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4481 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4482 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4483 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4484 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4485 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4486 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4487 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4488 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4489 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4490 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4491 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4492 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4493 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4494 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4495 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4496 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4497 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4498 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4499 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4500 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4501 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4502 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4503 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4504 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4505 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4506 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4507 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4508 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4509 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4510 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4511 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4512 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4513 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4514 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4515 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4516 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4517 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4518 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4519 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4520 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4521 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4522 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4523 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4524 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4525 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4526 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4527 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4528 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4529 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4530 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4531 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4532 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4533 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4534 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4535 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4536 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4537 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4538 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4539 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4540 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4541 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4542 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4543 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4544 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4545 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4546 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4547 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4548 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4549 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4550 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4551 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4552 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4553 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4554 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4555 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4556 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4557 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4558 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4559 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4560 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4561 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4562 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4563 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4564 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4565 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4566 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4567 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4568 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4569 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4570 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4571 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4572 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4573 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4574 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4575 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4576 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4577 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4578 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4579 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4580 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4581 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4582 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4583 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4584 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4585 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4586 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4587 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4588 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4589 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4590 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4591 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4592 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4593 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4594 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4595 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4596 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4597 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4598 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4599 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4600 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4601 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4602 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4603 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4604 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4605 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4606 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4607 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4608 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4609 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4610 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4611 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4612 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4613 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4614 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4615 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4616 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4617 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4618 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4619 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4622 static u32 tg3TsoFwRodata[] = {
4623 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4624 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4625 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4626 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4630 static u32 tg3TsoFwData[] = {
4631 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4632 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4636 /* 5705 needs a special version of the TSO firmware. */
4637 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
4638 #define TG3_TSO5_FW_RELASE_MINOR 0x2
4639 #define TG3_TSO5_FW_RELEASE_FIX 0x0
4640 #define TG3_TSO5_FW_START_ADDR 0x00010000
4641 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
4642 #define TG3_TSO5_FW_TEXT_LEN 0xe90
4643 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
4644 #define TG3_TSO5_FW_RODATA_LEN 0x50
4645 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
4646 #define TG3_TSO5_FW_DATA_LEN 0x20
4647 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
4648 #define TG3_TSO5_FW_SBSS_LEN 0x28
4649 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
4650 #define TG3_TSO5_FW_BSS_LEN 0x88
4652 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
4653 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4654 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4655 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4656 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4657 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4658 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4659 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4660 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4661 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4662 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4663 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4664 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4665 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4666 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4667 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4668 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4669 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4670 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4671 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4672 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4673 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4674 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4675 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4676 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4677 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4678 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4679 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4680 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4681 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4682 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4683 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4684 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4685 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4686 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4687 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4688 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4689 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4690 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4691 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4692 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4693 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4694 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4695 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4696 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4697 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4698 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4699 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4700 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4701 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4702 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4703 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4704 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4705 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4706 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4707 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4708 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4709 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4710 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4711 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4712 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4713 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4714 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4715 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4716 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4717 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4718 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4719 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4720 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4721 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4722 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4723 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4724 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4725 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4726 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4727 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4728 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4729 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4730 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4731 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4732 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4733 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4734 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4735 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4736 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4737 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4738 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4739 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4740 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4741 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4742 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4743 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4744 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4745 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4746 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4747 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4748 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4749 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4750 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4751 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4752 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4753 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4754 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4755 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4756 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4757 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4758 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4759 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4760 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4761 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4762 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4763 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4764 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4765 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4766 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4767 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4768 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4769 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4770 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4771 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4772 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4773 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4774 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4775 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4776 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4777 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4778 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4779 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4780 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4781 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4782 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4783 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4784 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4785 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4786 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4787 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4788 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4789 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4790 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4791 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4792 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4793 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4794 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4795 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4796 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4797 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4798 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4799 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4800 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4801 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4802 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
4803 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
4804 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4805 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
4806 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
4807 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4808 0x00000000, 0x00000000, 0x00000000,
4811 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
4812 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4813 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
4814 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4815 0x00000000, 0x00000000, 0x00000000,
4818 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
4819 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
4820 0x00000000, 0x00000000, 0x00000000,
4823 /* tp->lock is held. */
4824 static int tg3_load_tso_firmware(struct tg3 *tp)
4826 struct fw_info info;
4827 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
4830 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4833 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4834 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
4835 info.text_len = TG3_TSO5_FW_TEXT_LEN;
4836 info.text_data = &tg3Tso5FwText[0];
4837 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
4838 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
4839 info.rodata_data = &tg3Tso5FwRodata[0];
4840 info.data_base = TG3_TSO5_FW_DATA_ADDR;
4841 info.data_len = TG3_TSO5_FW_DATA_LEN;
4842 info.data_data = &tg3Tso5FwData[0];
4843 cpu_base = RX_CPU_BASE;
4844 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
4845 cpu_scratch_size = (info.text_len +
4848 TG3_TSO5_FW_SBSS_LEN +
4849 TG3_TSO5_FW_BSS_LEN);
4851 info.text_base = TG3_TSO_FW_TEXT_ADDR;
4852 info.text_len = TG3_TSO_FW_TEXT_LEN;
4853 info.text_data = &tg3TsoFwText[0];
4854 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
4855 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
4856 info.rodata_data = &tg3TsoFwRodata[0];
4857 info.data_base = TG3_TSO_FW_DATA_ADDR;
4858 info.data_len = TG3_TSO_FW_DATA_LEN;
4859 info.data_data = &tg3TsoFwData[0];
4860 cpu_base = TX_CPU_BASE;
4861 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
4862 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
4865 err = tg3_load_firmware_cpu(tp, cpu_base,
4866 cpu_scratch_base, cpu_scratch_size,
4871 /* Now startup the cpu. */
4872 tw32(cpu_base + CPU_STATE, 0xffffffff);
4873 tw32_f(cpu_base + CPU_PC, info.text_base);
4875 for (i = 0; i < 5; i++) {
4876 if (tr32(cpu_base + CPU_PC) == info.text_base)
4878 tw32(cpu_base + CPU_STATE, 0xffffffff);
4879 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
4880 tw32_f(cpu_base + CPU_PC, info.text_base);
4884 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
4885 "to set CPU PC, is %08x should be %08x\n",
4886 tp->dev->name, tr32(cpu_base + CPU_PC),
4890 tw32(cpu_base + CPU_STATE, 0xffffffff);
4891 tw32_f(cpu_base + CPU_MODE, 0x00000000);
4895 #endif /* TG3_TSO_SUPPORT != 0 */
4897 /* tp->lock is held. */
4898 static void __tg3_set_mac_addr(struct tg3 *tp)
4900 u32 addr_high, addr_low;
4903 addr_high = ((tp->dev->dev_addr[0] << 8) |
4904 tp->dev->dev_addr[1]);
4905 addr_low = ((tp->dev->dev_addr[2] << 24) |
4906 (tp->dev->dev_addr[3] << 16) |
4907 (tp->dev->dev_addr[4] << 8) |
4908 (tp->dev->dev_addr[5] << 0));
4909 for (i = 0; i < 4; i++) {
4910 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
4911 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
4914 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
4915 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
4916 for (i = 0; i < 12; i++) {
4917 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
4918 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
4922 addr_high = (tp->dev->dev_addr[0] +
4923 tp->dev->dev_addr[1] +
4924 tp->dev->dev_addr[2] +
4925 tp->dev->dev_addr[3] +
4926 tp->dev->dev_addr[4] +
4927 tp->dev->dev_addr[5]) &
4928 TX_BACKOFF_SEED_MASK;
4929 tw32(MAC_TX_BACKOFF_SEED, addr_high);
4932 static int tg3_set_mac_addr(struct net_device *dev, void *p)
4934 struct tg3 *tp = netdev_priv(dev);
4935 struct sockaddr *addr = p;
4937 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4939 spin_lock_irq(&tp->lock);
4940 __tg3_set_mac_addr(tp);
4941 spin_unlock_irq(&tp->lock);
4946 /* tp->lock is held. */
4947 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
4948 dma_addr_t mapping, u32 maxlen_flags,
4952 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
4953 ((u64) mapping >> 32));
4955 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
4956 ((u64) mapping & 0xffffffff));
4958 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
4961 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4963 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
4967 static void __tg3_set_rx_mode(struct net_device *);
4969 /* tp->lock is held. */
4970 static int tg3_reset_hw(struct tg3 *tp)
4972 u32 val, rdmac_mode;
4975 tg3_disable_ints(tp);
4979 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
4981 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
4982 err = tg3_abort_hw(tp);
4987 err = tg3_chip_reset(tp);
4991 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
4993 /* This works around an issue with Athlon chipsets on
4994 * B3 tigon3 silicon. This bit has no effect on any
4995 * other revision. But do not set this on PCI Express
4998 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
4999 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5000 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5002 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5003 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5004 val = tr32(TG3PCI_PCISTATE);
5005 val |= PCISTATE_RETRY_SAME_DMA;
5006 tw32(TG3PCI_PCISTATE, val);
5009 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5010 /* Enable some hw fixes. */
5011 val = tr32(TG3PCI_MSI_DATA);
5012 val |= (1 << 26) | (1 << 28) | (1 << 29);
5013 tw32(TG3PCI_MSI_DATA, val);
5016 /* Descriptor ring init may make accesses to the
5017 * NIC SRAM area to setup the TX descriptors, so we
5018 * can only do this after the hardware has been
5019 * successfully reset.
5023 /* This value is determined during the probe time DMA
5024 * engine test, tg3_test_dma.
5026 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5028 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5029 GRC_MODE_4X_NIC_SEND_RINGS |
5030 GRC_MODE_NO_TX_PHDR_CSUM |
5031 GRC_MODE_NO_RX_PHDR_CSUM);
5032 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5033 if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5034 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5035 if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5036 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5040 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5042 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5043 val = tr32(GRC_MISC_CFG);
5045 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5046 tw32(GRC_MISC_CFG, val);
5048 /* Initialize MBUF/DESC pool. */
5049 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5051 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5052 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5054 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5056 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5057 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5058 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5060 #if TG3_TSO_SUPPORT != 0
5061 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5064 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5065 TG3_TSO5_FW_RODATA_LEN +
5066 TG3_TSO5_FW_DATA_LEN +
5067 TG3_TSO5_FW_SBSS_LEN +
5068 TG3_TSO5_FW_BSS_LEN);
5069 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5070 tw32(BUFMGR_MB_POOL_ADDR,
5071 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5072 tw32(BUFMGR_MB_POOL_SIZE,
5073 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5077 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
5078 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5079 tp->bufmgr_config.mbuf_read_dma_low_water);
5080 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5081 tp->bufmgr_config.mbuf_mac_rx_low_water);
5082 tw32(BUFMGR_MB_HIGH_WATER,
5083 tp->bufmgr_config.mbuf_high_water);
5085 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5086 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5087 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5088 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5089 tw32(BUFMGR_MB_HIGH_WATER,
5090 tp->bufmgr_config.mbuf_high_water_jumbo);
5092 tw32(BUFMGR_DMA_LOW_WATER,
5093 tp->bufmgr_config.dma_low_water);
5094 tw32(BUFMGR_DMA_HIGH_WATER,
5095 tp->bufmgr_config.dma_high_water);
5097 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5098 for (i = 0; i < 2000; i++) {
5099 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5104 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5109 /* Setup replenish threshold. */
5110 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5112 /* Initialize TG3_BDINFO's at:
5113 * RCVDBDI_STD_BD: standard eth size rx ring
5114 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5115 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5118 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5119 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5120 * ring attribute flags
5121 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5123 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5124 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5126 * The size of each ring is fixed in the firmware, but the location is
5129 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5130 ((u64) tp->rx_std_mapping >> 32));
5131 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5132 ((u64) tp->rx_std_mapping & 0xffffffff));
5133 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5134 NIC_SRAM_RX_BUFFER_DESC);
5136 /* Don't even try to program the JUMBO/MINI buffer descriptor
5139 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5140 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5141 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5143 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5144 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5146 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5147 BDINFO_FLAGS_DISABLED);
5149 /* Setup replenish threshold. */
5150 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5152 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
5153 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5154 ((u64) tp->rx_jumbo_mapping >> 32));
5155 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5156 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5157 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5158 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5159 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5160 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5162 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5163 BDINFO_FLAGS_DISABLED);
5168 /* There is only one send ring on 5705/5750, no need to explicitly
5169 * disable the others.
5171 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5172 /* Clear out send RCB ring in SRAM. */
5173 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5174 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5175 BDINFO_FLAGS_DISABLED);
5180 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5181 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5183 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5184 tp->tx_desc_mapping,
5185 (TG3_TX_RING_SIZE <<
5186 BDINFO_FLAGS_MAXLEN_SHIFT),
5187 NIC_SRAM_TX_BUFFER_DESC);
5189 /* There is only one receive return ring on 5705/5750, no need
5190 * to explicitly disable the others.
5192 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5193 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5194 i += TG3_BDINFO_SIZE) {
5195 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5196 BDINFO_FLAGS_DISABLED);
5201 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5203 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5205 (TG3_RX_RCB_RING_SIZE(tp) <<
5206 BDINFO_FLAGS_MAXLEN_SHIFT),
5209 tp->rx_std_ptr = tp->rx_pending;
5210 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5213 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ?
5214 tp->rx_jumbo_pending : 0;
5215 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5218 /* Initialize MAC address and backoff seed. */
5219 __tg3_set_mac_addr(tp);
5221 /* MTU + ethernet header + FCS + optional VLAN tag */
5222 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5224 /* The slot time is changed by tg3_setup_phy if we
5225 * run at gigabit with half duplex.
5227 tw32(MAC_TX_LENGTHS,
5228 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5229 (6 << TX_LENGTHS_IPG_SHIFT) |
5230 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5232 /* Receive rules. */
5233 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5234 tw32(RCVLPC_CONFIG, 0x0181);
5236 /* Calculate RDMAC_MODE setting early, we need it to determine
5237 * the RCVLPC_STATE_ENABLE mask.
5239 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5240 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5241 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5242 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5243 RDMAC_MODE_LNGREAD_ENAB);
5244 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5245 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
5247 /* If statement applies to 5705 and 5750 PCI devices only */
5248 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5249 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5250 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
5251 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5252 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5253 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5254 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5255 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5256 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5257 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5261 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5262 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5264 #if TG3_TSO_SUPPORT != 0
5265 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5266 rdmac_mode |= (1 << 27);
5269 /* Receive/send statistics. */
5270 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5271 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5272 val = tr32(RCVLPC_STATS_ENABLE);
5273 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5274 tw32(RCVLPC_STATS_ENABLE, val);
5276 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5278 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5279 tw32(SNDDATAI_STATSENAB, 0xffffff);
5280 tw32(SNDDATAI_STATSCTRL,
5281 (SNDDATAI_SCTRL_ENABLE |
5282 SNDDATAI_SCTRL_FASTUPD));
5284 /* Setup host coalescing engine. */
5285 tw32(HOSTCC_MODE, 0);
5286 for (i = 0; i < 2000; i++) {
5287 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5292 tw32(HOSTCC_RXCOL_TICKS, 0);
5293 tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
5294 tw32(HOSTCC_RXMAX_FRAMES, 1);
5295 tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
5296 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5297 tw32(HOSTCC_RXCOAL_TICK_INT, 0);
5298 tw32(HOSTCC_TXCOAL_TICK_INT, 0);
5300 tw32(HOSTCC_RXCOAL_MAXF_INT, 1);
5301 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
5303 /* set status block DMA address */
5304 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5305 ((u64) tp->status_mapping >> 32));
5306 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5307 ((u64) tp->status_mapping & 0xffffffff));
5309 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5310 /* Status/statistics block address. See tg3_timer,
5311 * the tg3_periodic_fetch_stats call there, and
5312 * tg3_get_stats to see how this works for 5705/5750 chips.
5314 tw32(HOSTCC_STAT_COAL_TICKS,
5315 DEFAULT_STAT_COAL_TICKS);
5316 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5317 ((u64) tp->stats_mapping >> 32));
5318 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5319 ((u64) tp->stats_mapping & 0xffffffff));
5320 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5321 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5324 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5326 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5327 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5328 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5329 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5331 /* Clear statistics/status block in chip, and status block in ram. */
5332 for (i = NIC_SRAM_STATS_BLK;
5333 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5335 tg3_write_mem(tp, i, 0);
5338 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5340 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5341 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5342 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5345 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5346 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5347 * register to preserve the GPIO settings for LOMs. The GPIOs,
5348 * whether used as inputs or outputs, are set by boot code after
5351 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5354 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5355 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
5357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5358 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5359 GRC_LCLCTRL_GPIO_OUTPUT3;
5361 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5363 /* GPIO1 must be driven high for eeprom write protect */
5364 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5365 GRC_LCLCTRL_GPIO_OUTPUT1);
5367 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5370 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5371 tr32(MAILBOX_INTERRUPT_0);
5373 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5374 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5378 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5379 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5380 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5381 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5382 WDMAC_MODE_LNGREAD_ENAB);
5384 /* If statement applies to 5705 and 5750 PCI devices only */
5385 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5386 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5387 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
5388 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5389 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5390 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5392 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5393 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5394 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5395 val |= WDMAC_MODE_RX_ACCEL;
5399 tw32_f(WDMAC_MODE, val);
5402 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5403 val = tr32(TG3PCI_X_CAPS);
5404 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5405 val &= ~PCIX_CAPS_BURST_MASK;
5406 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5407 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5408 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5409 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5410 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5411 val |= (tp->split_mode_max_reqs <<
5412 PCIX_CAPS_SPLIT_SHIFT);
5414 tw32(TG3PCI_X_CAPS, val);
5417 tw32_f(RDMAC_MODE, rdmac_mode);
5420 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5421 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5422 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5423 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5424 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5425 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5426 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5427 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5428 #if TG3_TSO_SUPPORT != 0
5429 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5430 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5432 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5433 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5435 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5436 err = tg3_load_5701_a0_firmware_fix(tp);
5441 #if TG3_TSO_SUPPORT != 0
5442 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5443 err = tg3_load_tso_firmware(tp);
5449 tp->tx_mode = TX_MODE_ENABLE;
5450 tw32_f(MAC_TX_MODE, tp->tx_mode);
5453 tp->rx_mode = RX_MODE_ENABLE;
5454 tw32_f(MAC_RX_MODE, tp->rx_mode);
5457 if (tp->link_config.phy_is_low_power) {
5458 tp->link_config.phy_is_low_power = 0;
5459 tp->link_config.speed = tp->link_config.orig_speed;
5460 tp->link_config.duplex = tp->link_config.orig_duplex;
5461 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5464 tp->mi_mode = MAC_MI_MODE_BASE;
5465 tw32_f(MAC_MI_MODE, tp->mi_mode);
5468 tw32(MAC_LED_CTRL, tp->led_ctrl);
5470 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5471 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5472 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5475 tw32_f(MAC_RX_MODE, tp->rx_mode);
5478 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5479 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5480 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5481 /* Set drive transmission level to 1.2V */
5482 /* only if the signal pre-emphasis bit is not set */
5483 val = tr32(MAC_SERDES_CFG);
5486 tw32(MAC_SERDES_CFG, val);
5488 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5489 tw32(MAC_SERDES_CFG, 0x616000);
5492 /* Prevent chip from dropping frames when flow control
5495 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5497 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5498 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5499 /* Use hardware link auto-negotiation */
5500 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5503 err = tg3_setup_phy(tp, 1);
5507 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5510 /* Clear CRC stats. */
5511 if (!tg3_readphy(tp, 0x1e, &tmp)) {
5512 tg3_writephy(tp, 0x1e, tmp | 0x8000);
5513 tg3_readphy(tp, 0x14, &tmp);
5517 __tg3_set_rx_mode(tp->dev);
5519 /* Initialize receive rules. */
5520 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
5521 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
5522 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
5523 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5525 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5529 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
5533 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
5535 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
5537 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
5539 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
5541 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
5543 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
5545 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
5547 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
5549 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
5551 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
5553 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
5555 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
5557 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
5559 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
5567 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
5569 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
5570 tg3_enable_ints(tp);
5575 /* Called at device open time to get the chip ready for
5576 * packet processing. Invoked with tp->lock held.
5578 static int tg3_init_hw(struct tg3 *tp)
5582 /* Force the chip into D0. */
5583 err = tg3_set_power_state(tp, 0);
5587 tg3_switch_clocks(tp);
5589 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
5591 err = tg3_reset_hw(tp);
5597 #define TG3_STAT_ADD32(PSTAT, REG) \
5598 do { u32 __val = tr32(REG); \
5599 (PSTAT)->low += __val; \
5600 if ((PSTAT)->low < __val) \
5601 (PSTAT)->high += 1; \
5604 static void tg3_periodic_fetch_stats(struct tg3 *tp)
5606 struct tg3_hw_stats *sp = tp->hw_stats;
5608 if (!netif_carrier_ok(tp->dev))
5611 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
5612 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
5613 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
5614 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
5615 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
5616 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
5617 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
5618 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
5619 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
5620 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
5621 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
5622 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
5623 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
5625 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
5626 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
5627 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
5628 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
5629 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
5630 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
5631 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
5632 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
5633 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
5634 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
5635 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
5636 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
5637 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
5638 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
5641 static void tg3_timer(unsigned long __opaque)
5643 struct tg3 *tp = (struct tg3 *) __opaque;
5644 unsigned long flags;
5646 spin_lock_irqsave(&tp->lock, flags);
5647 spin_lock(&tp->tx_lock);
5649 /* All of this garbage is because when using non-tagged
5650 * IRQ status the mailbox/status_block protocol the chip
5651 * uses with the cpu is race prone.
5653 if (tp->hw_status->status & SD_STATUS_UPDATED) {
5654 tw32(GRC_LOCAL_CTRL,
5655 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
5657 tw32(HOSTCC_MODE, tp->coalesce_mode |
5658 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
5661 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
5662 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
5663 spin_unlock(&tp->tx_lock);
5664 spin_unlock_irqrestore(&tp->lock, flags);
5665 schedule_work(&tp->reset_task);
5669 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5670 tg3_periodic_fetch_stats(tp);
5672 /* This part only runs once per second. */
5673 if (!--tp->timer_counter) {
5674 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
5678 mac_stat = tr32(MAC_STATUS);
5681 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
5682 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
5684 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
5688 tg3_setup_phy(tp, 0);
5689 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
5690 u32 mac_stat = tr32(MAC_STATUS);
5693 if (netif_carrier_ok(tp->dev) &&
5694 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
5697 if (! netif_carrier_ok(tp->dev) &&
5698 (mac_stat & (MAC_STATUS_PCS_SYNCED |
5699 MAC_STATUS_SIGNAL_DET))) {
5705 ~MAC_MODE_PORT_MODE_MASK));
5707 tw32_f(MAC_MODE, tp->mac_mode);
5709 tg3_setup_phy(tp, 0);
5713 tp->timer_counter = tp->timer_multiplier;
5716 /* Heartbeat is only sent once every 120 seconds. */
5717 if (!--tp->asf_counter) {
5718 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5721 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
5722 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
5723 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
5724 val = tr32(GRC_RX_CPU_EVENT);
5726 tw32(GRC_RX_CPU_EVENT, val);
5728 tp->asf_counter = tp->asf_multiplier;
5731 spin_unlock(&tp->tx_lock);
5732 spin_unlock_irqrestore(&tp->lock, flags);
5734 tp->timer.expires = jiffies + tp->timer_offset;
5735 add_timer(&tp->timer);
5738 static int tg3_open(struct net_device *dev)
5740 struct tg3 *tp = netdev_priv(dev);
5743 spin_lock_irq(&tp->lock);
5744 spin_lock(&tp->tx_lock);
5746 tg3_disable_ints(tp);
5747 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
5749 spin_unlock(&tp->tx_lock);
5750 spin_unlock_irq(&tp->lock);
5752 /* The placement of this call is tied
5753 * to the setup and use of Host TX descriptors.
5755 err = tg3_alloc_consistent(tp);
5759 err = request_irq(dev->irq, tg3_interrupt,
5760 SA_SHIRQ, dev->name, dev);
5763 tg3_free_consistent(tp);
5767 spin_lock_irq(&tp->lock);
5768 spin_lock(&tp->tx_lock);
5770 err = tg3_init_hw(tp);
5775 tp->timer_offset = HZ / 10;
5776 tp->timer_counter = tp->timer_multiplier = 10;
5777 tp->asf_counter = tp->asf_multiplier = (10 * 120);
5779 init_timer(&tp->timer);
5780 tp->timer.expires = jiffies + tp->timer_offset;
5781 tp->timer.data = (unsigned long) tp;
5782 tp->timer.function = tg3_timer;
5783 add_timer(&tp->timer);
5785 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
5788 spin_unlock(&tp->tx_lock);
5789 spin_unlock_irq(&tp->lock);
5792 free_irq(dev->irq, dev);
5793 tg3_free_consistent(tp);
5797 spin_lock_irq(&tp->lock);
5798 spin_lock(&tp->tx_lock);
5800 tg3_enable_ints(tp);
5802 spin_unlock(&tp->tx_lock);
5803 spin_unlock_irq(&tp->lock);
5805 netif_start_queue(dev);
5811 /*static*/ void tg3_dump_state(struct tg3 *tp)
5813 u32 val32, val32_2, val32_3, val32_4, val32_5;
5817 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
5818 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
5819 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
5823 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
5824 tr32(MAC_MODE), tr32(MAC_STATUS));
5825 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
5826 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
5827 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
5828 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
5829 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
5830 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
5832 /* Send data initiator control block */
5833 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
5834 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
5835 printk(" SNDDATAI_STATSCTRL[%08x]\n",
5836 tr32(SNDDATAI_STATSCTRL));
5838 /* Send data completion control block */
5839 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
5841 /* Send BD ring selector block */
5842 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
5843 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
5845 /* Send BD initiator control block */
5846 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
5847 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
5849 /* Send BD completion control block */
5850 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
5852 /* Receive list placement control block */
5853 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
5854 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
5855 printk(" RCVLPC_STATSCTRL[%08x]\n",
5856 tr32(RCVLPC_STATSCTRL));
5858 /* Receive data and receive BD initiator control block */
5859 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
5860 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
5862 /* Receive data completion control block */
5863 printk("DEBUG: RCVDCC_MODE[%08x]\n",
5866 /* Receive BD initiator control block */
5867 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
5868 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
5870 /* Receive BD completion control block */
5871 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
5872 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
5874 /* Receive list selector control block */
5875 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
5876 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
5878 /* Mbuf cluster free block */
5879 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
5880 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
5882 /* Host coalescing control block */
5883 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
5884 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
5885 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
5886 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
5887 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
5888 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
5889 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
5890 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
5891 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
5892 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
5893 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
5894 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
5896 /* Memory arbiter control block */
5897 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
5898 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
5900 /* Buffer manager control block */
5901 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
5902 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
5903 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
5904 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
5905 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
5906 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
5907 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
5908 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
5910 /* Read DMA control block */
5911 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
5912 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
5914 /* Write DMA control block */
5915 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
5916 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
5918 /* DMA completion block */
5919 printk("DEBUG: DMAC_MODE[%08x]\n",
5923 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
5924 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
5925 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
5926 tr32(GRC_LOCAL_CTRL));
5929 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
5930 tr32(RCVDBDI_JUMBO_BD + 0x0),
5931 tr32(RCVDBDI_JUMBO_BD + 0x4),
5932 tr32(RCVDBDI_JUMBO_BD + 0x8),
5933 tr32(RCVDBDI_JUMBO_BD + 0xc));
5934 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
5935 tr32(RCVDBDI_STD_BD + 0x0),
5936 tr32(RCVDBDI_STD_BD + 0x4),
5937 tr32(RCVDBDI_STD_BD + 0x8),
5938 tr32(RCVDBDI_STD_BD + 0xc));
5939 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
5940 tr32(RCVDBDI_MINI_BD + 0x0),
5941 tr32(RCVDBDI_MINI_BD + 0x4),
5942 tr32(RCVDBDI_MINI_BD + 0x8),
5943 tr32(RCVDBDI_MINI_BD + 0xc));
5945 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
5946 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
5947 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
5948 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
5949 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
5950 val32, val32_2, val32_3, val32_4);
5952 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
5953 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
5954 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
5955 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
5956 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
5957 val32, val32_2, val32_3, val32_4);
5959 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
5960 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
5961 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
5962 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
5963 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
5964 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
5965 val32, val32_2, val32_3, val32_4, val32_5);
5967 /* SW status block */
5968 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5969 tp->hw_status->status,
5970 tp->hw_status->status_tag,
5971 tp->hw_status->rx_jumbo_consumer,
5972 tp->hw_status->rx_consumer,
5973 tp->hw_status->rx_mini_consumer,
5974 tp->hw_status->idx[0].rx_producer,
5975 tp->hw_status->idx[0].tx_consumer);
5977 /* SW statistics block */
5978 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
5979 ((u32 *)tp->hw_stats)[0],
5980 ((u32 *)tp->hw_stats)[1],
5981 ((u32 *)tp->hw_stats)[2],
5982 ((u32 *)tp->hw_stats)[3]);
5985 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
5986 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
5987 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
5988 tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
5989 tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
5991 /* NIC side send descriptors. */
5992 for (i = 0; i < 6; i++) {
5995 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
5996 + (i * sizeof(struct tg3_tx_buffer_desc));
5997 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
5999 readl(txd + 0x0), readl(txd + 0x4),
6000 readl(txd + 0x8), readl(txd + 0xc));
6003 /* NIC side RX descriptors. */
6004 for (i = 0; i < 6; i++) {
6007 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6008 + (i * sizeof(struct tg3_rx_buffer_desc));
6009 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6011 readl(rxd + 0x0), readl(rxd + 0x4),
6012 readl(rxd + 0x8), readl(rxd + 0xc));
6013 rxd += (4 * sizeof(u32));
6014 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6016 readl(rxd + 0x0), readl(rxd + 0x4),
6017 readl(rxd + 0x8), readl(rxd + 0xc));
6020 for (i = 0; i < 6; i++) {
6023 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6024 + (i * sizeof(struct tg3_rx_buffer_desc));
6025 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6027 readl(rxd + 0x0), readl(rxd + 0x4),
6028 readl(rxd + 0x8), readl(rxd + 0xc));
6029 rxd += (4 * sizeof(u32));
6030 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6032 readl(rxd + 0x0), readl(rxd + 0x4),
6033 readl(rxd + 0x8), readl(rxd + 0xc));
6038 static struct net_device_stats *tg3_get_stats(struct net_device *);
6039 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6041 static int tg3_close(struct net_device *dev)
6043 struct tg3 *tp = netdev_priv(dev);
6045 netif_stop_queue(dev);
6047 del_timer_sync(&tp->timer);
6049 spin_lock_irq(&tp->lock);
6050 spin_lock(&tp->tx_lock);
6055 tg3_disable_ints(tp);
6060 ~(TG3_FLAG_INIT_COMPLETE |
6061 TG3_FLAG_GOT_SERDES_FLOWCTL);
6062 netif_carrier_off(tp->dev);
6064 spin_unlock(&tp->tx_lock);
6065 spin_unlock_irq(&tp->lock);
6067 free_irq(dev->irq, dev);
6069 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6070 sizeof(tp->net_stats_prev));
6071 memcpy(&tp->estats_prev, tg3_get_estats(tp),
6072 sizeof(tp->estats_prev));
6074 tg3_free_consistent(tp);
6079 static inline unsigned long get_stat64(tg3_stat64_t *val)
6083 #if (BITS_PER_LONG == 32)
6086 ret = ((u64)val->high << 32) | ((u64)val->low);
6091 static unsigned long calc_crc_errors(struct tg3 *tp)
6093 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6095 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6096 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6097 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6098 unsigned long flags;
6101 spin_lock_irqsave(&tp->lock, flags);
6102 if (!tg3_readphy(tp, 0x1e, &val)) {
6103 tg3_writephy(tp, 0x1e, val | 0x8000);
6104 tg3_readphy(tp, 0x14, &val);
6107 spin_unlock_irqrestore(&tp->lock, flags);
6109 tp->phy_crc_errors += val;
6111 return tp->phy_crc_errors;
6114 return get_stat64(&hw_stats->rx_fcs_errors);
6117 #define ESTAT_ADD(member) \
6118 estats->member = old_estats->member + \
6119 get_stat64(&hw_stats->member)
6121 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6123 struct tg3_ethtool_stats *estats = &tp->estats;
6124 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6125 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6130 ESTAT_ADD(rx_octets);
6131 ESTAT_ADD(rx_fragments);
6132 ESTAT_ADD(rx_ucast_packets);
6133 ESTAT_ADD(rx_mcast_packets);
6134 ESTAT_ADD(rx_bcast_packets);
6135 ESTAT_ADD(rx_fcs_errors);
6136 ESTAT_ADD(rx_align_errors);
6137 ESTAT_ADD(rx_xon_pause_rcvd);
6138 ESTAT_ADD(rx_xoff_pause_rcvd);
6139 ESTAT_ADD(rx_mac_ctrl_rcvd);
6140 ESTAT_ADD(rx_xoff_entered);
6141 ESTAT_ADD(rx_frame_too_long_errors);
6142 ESTAT_ADD(rx_jabbers);
6143 ESTAT_ADD(rx_undersize_packets);
6144 ESTAT_ADD(rx_in_length_errors);
6145 ESTAT_ADD(rx_out_length_errors);
6146 ESTAT_ADD(rx_64_or_less_octet_packets);
6147 ESTAT_ADD(rx_65_to_127_octet_packets);
6148 ESTAT_ADD(rx_128_to_255_octet_packets);
6149 ESTAT_ADD(rx_256_to_511_octet_packets);
6150 ESTAT_ADD(rx_512_to_1023_octet_packets);
6151 ESTAT_ADD(rx_1024_to_1522_octet_packets);
6152 ESTAT_ADD(rx_1523_to_2047_octet_packets);
6153 ESTAT_ADD(rx_2048_to_4095_octet_packets);
6154 ESTAT_ADD(rx_4096_to_8191_octet_packets);
6155 ESTAT_ADD(rx_8192_to_9022_octet_packets);
6157 ESTAT_ADD(tx_octets);
6158 ESTAT_ADD(tx_collisions);
6159 ESTAT_ADD(tx_xon_sent);
6160 ESTAT_ADD(tx_xoff_sent);
6161 ESTAT_ADD(tx_flow_control);
6162 ESTAT_ADD(tx_mac_errors);
6163 ESTAT_ADD(tx_single_collisions);
6164 ESTAT_ADD(tx_mult_collisions);
6165 ESTAT_ADD(tx_deferred);
6166 ESTAT_ADD(tx_excessive_collisions);
6167 ESTAT_ADD(tx_late_collisions);
6168 ESTAT_ADD(tx_collide_2times);
6169 ESTAT_ADD(tx_collide_3times);
6170 ESTAT_ADD(tx_collide_4times);
6171 ESTAT_ADD(tx_collide_5times);
6172 ESTAT_ADD(tx_collide_6times);
6173 ESTAT_ADD(tx_collide_7times);
6174 ESTAT_ADD(tx_collide_8times);
6175 ESTAT_ADD(tx_collide_9times);
6176 ESTAT_ADD(tx_collide_10times);
6177 ESTAT_ADD(tx_collide_11times);
6178 ESTAT_ADD(tx_collide_12times);
6179 ESTAT_ADD(tx_collide_13times);
6180 ESTAT_ADD(tx_collide_14times);
6181 ESTAT_ADD(tx_collide_15times);
6182 ESTAT_ADD(tx_ucast_packets);
6183 ESTAT_ADD(tx_mcast_packets);
6184 ESTAT_ADD(tx_bcast_packets);
6185 ESTAT_ADD(tx_carrier_sense_errors);
6186 ESTAT_ADD(tx_discards);
6187 ESTAT_ADD(tx_errors);
6189 ESTAT_ADD(dma_writeq_full);
6190 ESTAT_ADD(dma_write_prioq_full);
6191 ESTAT_ADD(rxbds_empty);
6192 ESTAT_ADD(rx_discards);
6193 ESTAT_ADD(rx_errors);
6194 ESTAT_ADD(rx_threshold_hit);
6196 ESTAT_ADD(dma_readq_full);
6197 ESTAT_ADD(dma_read_prioq_full);
6198 ESTAT_ADD(tx_comp_queue_full);
6200 ESTAT_ADD(ring_set_send_prod_index);
6201 ESTAT_ADD(ring_status_update);
6202 ESTAT_ADD(nic_irqs);
6203 ESTAT_ADD(nic_avoided_irqs);
6204 ESTAT_ADD(nic_tx_threshold_hit);
6209 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6211 struct tg3 *tp = netdev_priv(dev);
6212 struct net_device_stats *stats = &tp->net_stats;
6213 struct net_device_stats *old_stats = &tp->net_stats_prev;
6214 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6219 stats->rx_packets = old_stats->rx_packets +
6220 get_stat64(&hw_stats->rx_ucast_packets) +
6221 get_stat64(&hw_stats->rx_mcast_packets) +
6222 get_stat64(&hw_stats->rx_bcast_packets);
6224 stats->tx_packets = old_stats->tx_packets +
6225 get_stat64(&hw_stats->tx_ucast_packets) +
6226 get_stat64(&hw_stats->tx_mcast_packets) +
6227 get_stat64(&hw_stats->tx_bcast_packets);
6229 stats->rx_bytes = old_stats->rx_bytes +
6230 get_stat64(&hw_stats->rx_octets);
6231 stats->tx_bytes = old_stats->tx_bytes +
6232 get_stat64(&hw_stats->tx_octets);
6234 stats->rx_errors = old_stats->rx_errors +
6235 get_stat64(&hw_stats->rx_errors) +
6236 get_stat64(&hw_stats->rx_discards);
6237 stats->tx_errors = old_stats->tx_errors +
6238 get_stat64(&hw_stats->tx_errors) +
6239 get_stat64(&hw_stats->tx_mac_errors) +
6240 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6241 get_stat64(&hw_stats->tx_discards);
6243 stats->multicast = old_stats->multicast +
6244 get_stat64(&hw_stats->rx_mcast_packets);
6245 stats->collisions = old_stats->collisions +
6246 get_stat64(&hw_stats->tx_collisions);
6248 stats->rx_length_errors = old_stats->rx_length_errors +
6249 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6250 get_stat64(&hw_stats->rx_undersize_packets);
6252 stats->rx_over_errors = old_stats->rx_over_errors +
6253 get_stat64(&hw_stats->rxbds_empty);
6254 stats->rx_frame_errors = old_stats->rx_frame_errors +
6255 get_stat64(&hw_stats->rx_align_errors);
6256 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6257 get_stat64(&hw_stats->tx_discards);
6258 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6259 get_stat64(&hw_stats->tx_carrier_sense_errors);
6261 stats->rx_crc_errors = old_stats->rx_crc_errors +
6262 calc_crc_errors(tp);
6267 static inline u32 calc_crc(unsigned char *buf, int len)
6275 for (j = 0; j < len; j++) {
6278 for (k = 0; k < 8; k++) {
6292 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6294 /* accept or reject all multicast frames */
6295 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6296 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6297 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6298 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6301 static void __tg3_set_rx_mode(struct net_device *dev)
6303 struct tg3 *tp = netdev_priv(dev);
6306 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6307 RX_MODE_KEEP_VLAN_TAG);
6309 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6312 #if TG3_VLAN_TAG_USED
6314 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6315 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6317 /* By definition, VLAN is disabled always in this
6320 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6321 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6324 if (dev->flags & IFF_PROMISC) {
6325 /* Promiscuous mode. */
6326 rx_mode |= RX_MODE_PROMISC;
6327 } else if (dev->flags & IFF_ALLMULTI) {
6328 /* Accept all multicast. */
6329 tg3_set_multi (tp, 1);
6330 } else if (dev->mc_count < 1) {
6331 /* Reject all multicast. */
6332 tg3_set_multi (tp, 0);
6334 /* Accept one or more multicast(s). */
6335 struct dev_mc_list *mclist;
6337 u32 mc_filter[4] = { 0, };
6342 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
6343 i++, mclist = mclist->next) {
6345 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
6347 regidx = (bit & 0x60) >> 5;
6349 mc_filter[regidx] |= (1 << bit);
6352 tw32(MAC_HASH_REG_0, mc_filter[0]);
6353 tw32(MAC_HASH_REG_1, mc_filter[1]);
6354 tw32(MAC_HASH_REG_2, mc_filter[2]);
6355 tw32(MAC_HASH_REG_3, mc_filter[3]);
6358 if (rx_mode != tp->rx_mode) {
6359 tp->rx_mode = rx_mode;
6360 tw32_f(MAC_RX_MODE, rx_mode);
6365 static void tg3_set_rx_mode(struct net_device *dev)
6367 struct tg3 *tp = netdev_priv(dev);
6369 spin_lock_irq(&tp->lock);
6370 spin_lock(&tp->tx_lock);
6371 __tg3_set_rx_mode(dev);
6372 spin_unlock(&tp->tx_lock);
6373 spin_unlock_irq(&tp->lock);
6376 #define TG3_REGDUMP_LEN (32 * 1024)
6378 static int tg3_get_regs_len(struct net_device *dev)
6380 return TG3_REGDUMP_LEN;
6383 static void tg3_get_regs(struct net_device *dev,
6384 struct ethtool_regs *regs, void *_p)
6387 struct tg3 *tp = netdev_priv(dev);
6393 memset(p, 0, TG3_REGDUMP_LEN);
6395 spin_lock_irq(&tp->lock);
6396 spin_lock(&tp->tx_lock);
6398 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
6399 #define GET_REG32_LOOP(base,len) \
6400 do { p = (u32 *)(orig_p + (base)); \
6401 for (i = 0; i < len; i += 4) \
6402 __GET_REG32((base) + i); \
6404 #define GET_REG32_1(reg) \
6405 do { p = (u32 *)(orig_p + (reg)); \
6406 __GET_REG32((reg)); \
6409 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
6410 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
6411 GET_REG32_LOOP(MAC_MODE, 0x4f0);
6412 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
6413 GET_REG32_1(SNDDATAC_MODE);
6414 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
6415 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
6416 GET_REG32_1(SNDBDC_MODE);
6417 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
6418 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
6419 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
6420 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
6421 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
6422 GET_REG32_1(RCVDCC_MODE);
6423 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
6424 GET_REG32_LOOP(RCVCC_MODE, 0x14);
6425 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
6426 GET_REG32_1(MBFREE_MODE);
6427 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
6428 GET_REG32_LOOP(MEMARB_MODE, 0x10);
6429 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
6430 GET_REG32_LOOP(RDMAC_MODE, 0x08);
6431 GET_REG32_LOOP(WDMAC_MODE, 0x08);
6432 GET_REG32_LOOP(RX_CPU_BASE, 0x280);
6433 GET_REG32_LOOP(TX_CPU_BASE, 0x280);
6434 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
6435 GET_REG32_LOOP(FTQ_RESET, 0x120);
6436 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
6437 GET_REG32_1(DMAC_MODE);
6438 GET_REG32_LOOP(GRC_MODE, 0x4c);
6439 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6440 GET_REG32_LOOP(NVRAM_CMD, 0x24);
6443 #undef GET_REG32_LOOP
6446 spin_unlock(&tp->tx_lock);
6447 spin_unlock_irq(&tp->lock);
6450 static int tg3_get_eeprom_len(struct net_device *dev)
6452 struct tg3 *tp = netdev_priv(dev);
6454 return tp->nvram_size;
6457 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
6459 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6461 struct tg3 *tp = netdev_priv(dev);
6464 u32 i, offset, len, val, b_offset, b_count;
6466 offset = eeprom->offset;
6470 eeprom->magic = TG3_EEPROM_MAGIC;
6473 /* adjustments to start on required 4 byte boundary */
6474 b_offset = offset & 3;
6475 b_count = 4 - b_offset;
6476 if (b_count > len) {
6477 /* i.e. offset=1 len=2 */
6480 ret = tg3_nvram_read(tp, offset-b_offset, &val);
6483 val = cpu_to_le32(val);
6484 memcpy(data, ((char*)&val) + b_offset, b_count);
6487 eeprom->len += b_count;
6490 /* read bytes upto the last 4 byte boundary */
6491 pd = &data[eeprom->len];
6492 for (i = 0; i < (len - (len & 3)); i += 4) {
6493 ret = tg3_nvram_read(tp, offset + i, &val);
6498 val = cpu_to_le32(val);
6499 memcpy(pd + i, &val, 4);
6504 /* read last bytes not ending on 4 byte boundary */
6505 pd = &data[eeprom->len];
6507 b_offset = offset + len - b_count;
6508 ret = tg3_nvram_read(tp, b_offset, &val);
6511 val = cpu_to_le32(val);
6512 memcpy(pd, ((char*)&val), b_count);
6513 eeprom->len += b_count;
6518 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
6520 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6522 struct tg3 *tp = netdev_priv(dev);
6524 u32 offset, len, b_offset, odd_len, start, end;
6527 if (eeprom->magic != TG3_EEPROM_MAGIC)
6530 offset = eeprom->offset;
6533 if ((b_offset = (offset & 3))) {
6534 /* adjustments to start on required 4 byte boundary */
6535 ret = tg3_nvram_read(tp, offset-b_offset, &start);
6538 start = cpu_to_le32(start);
6544 if ((len & 3) && ((len > 4) || (b_offset == 0))) {
6545 /* adjustments to end on required 4 byte boundary */
6547 len = (len + 3) & ~3;
6548 ret = tg3_nvram_read(tp, offset+len-4, &end);
6551 end = cpu_to_le32(end);
6555 if (b_offset || odd_len) {
6556 buf = kmalloc(len, GFP_KERNEL);
6560 memcpy(buf, &start, 4);
6562 memcpy(buf+len-4, &end, 4);
6563 memcpy(buf + b_offset, data, eeprom->len);
6566 ret = tg3_nvram_write_block(tp, offset, len, buf);
6574 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6576 struct tg3 *tp = netdev_priv(dev);
6578 cmd->supported = (SUPPORTED_Autoneg);
6580 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
6581 cmd->supported |= (SUPPORTED_1000baseT_Half |
6582 SUPPORTED_1000baseT_Full);
6584 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
6585 cmd->supported |= (SUPPORTED_100baseT_Half |
6586 SUPPORTED_100baseT_Full |
6587 SUPPORTED_10baseT_Half |
6588 SUPPORTED_10baseT_Full |
6591 cmd->supported |= SUPPORTED_FIBRE;
6593 cmd->advertising = tp->link_config.advertising;
6594 if (netif_running(dev)) {
6595 cmd->speed = tp->link_config.active_speed;
6596 cmd->duplex = tp->link_config.active_duplex;
6599 cmd->phy_address = PHY_ADDR;
6600 cmd->transceiver = 0;
6601 cmd->autoneg = tp->link_config.autoneg;
6607 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6609 struct tg3 *tp = netdev_priv(dev);
6611 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6612 /* These are the only valid advertisement bits allowed. */
6613 if (cmd->autoneg == AUTONEG_ENABLE &&
6614 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
6615 ADVERTISED_1000baseT_Full |
6616 ADVERTISED_Autoneg |
6621 spin_lock_irq(&tp->lock);
6622 spin_lock(&tp->tx_lock);
6624 tp->link_config.autoneg = cmd->autoneg;
6625 if (cmd->autoneg == AUTONEG_ENABLE) {
6626 tp->link_config.advertising = cmd->advertising;
6627 tp->link_config.speed = SPEED_INVALID;
6628 tp->link_config.duplex = DUPLEX_INVALID;
6630 tp->link_config.advertising = 0;
6631 tp->link_config.speed = cmd->speed;
6632 tp->link_config.duplex = cmd->duplex;
6635 if (netif_running(dev))
6636 tg3_setup_phy(tp, 1);
6638 spin_unlock(&tp->tx_lock);
6639 spin_unlock_irq(&tp->lock);
6644 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6646 struct tg3 *tp = netdev_priv(dev);
6648 strcpy(info->driver, DRV_MODULE_NAME);
6649 strcpy(info->version, DRV_MODULE_VERSION);
6650 strcpy(info->bus_info, pci_name(tp->pdev));
6653 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6655 struct tg3 *tp = netdev_priv(dev);
6657 wol->supported = WAKE_MAGIC;
6659 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
6660 wol->wolopts = WAKE_MAGIC;
6661 memset(&wol->sopass, 0, sizeof(wol->sopass));
6664 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6666 struct tg3 *tp = netdev_priv(dev);
6668 if (wol->wolopts & ~WAKE_MAGIC)
6670 if ((wol->wolopts & WAKE_MAGIC) &&
6671 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
6672 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
6675 spin_lock_irq(&tp->lock);
6676 if (wol->wolopts & WAKE_MAGIC)
6677 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
6679 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
6680 spin_unlock_irq(&tp->lock);
6685 static u32 tg3_get_msglevel(struct net_device *dev)
6687 struct tg3 *tp = netdev_priv(dev);
6688 return tp->msg_enable;
6691 static void tg3_set_msglevel(struct net_device *dev, u32 value)
6693 struct tg3 *tp = netdev_priv(dev);
6694 tp->msg_enable = value;
6697 #if TG3_TSO_SUPPORT != 0
6698 static int tg3_set_tso(struct net_device *dev, u32 value)
6700 struct tg3 *tp = netdev_priv(dev);
6702 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6707 return ethtool_op_set_tso(dev, value);
6711 static int tg3_nway_reset(struct net_device *dev)
6713 struct tg3 *tp = netdev_priv(dev);
6717 if (!netif_running(dev))
6720 spin_lock_irq(&tp->lock);
6722 tg3_readphy(tp, MII_BMCR, &bmcr);
6723 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
6724 (bmcr & BMCR_ANENABLE)) {
6725 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
6728 spin_unlock_irq(&tp->lock);
6733 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6735 struct tg3 *tp = netdev_priv(dev);
6737 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
6738 ering->rx_mini_max_pending = 0;
6739 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
6741 ering->rx_pending = tp->rx_pending;
6742 ering->rx_mini_pending = 0;
6743 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
6744 ering->tx_pending = tp->tx_pending;
6747 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6749 struct tg3 *tp = netdev_priv(dev);
6751 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
6752 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
6753 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
6756 if (netif_running(dev))
6759 spin_lock_irq(&tp->lock);
6760 spin_lock(&tp->tx_lock);
6762 tp->rx_pending = ering->rx_pending;
6764 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
6765 tp->rx_pending > 63)
6766 tp->rx_pending = 63;
6767 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
6768 tp->tx_pending = ering->tx_pending;
6770 if (netif_running(dev)) {
6773 tg3_netif_start(tp);
6776 spin_unlock(&tp->tx_lock);
6777 spin_unlock_irq(&tp->lock);
6782 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6784 struct tg3 *tp = netdev_priv(dev);
6786 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
6787 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
6788 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
6791 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6793 struct tg3 *tp = netdev_priv(dev);
6795 if (netif_running(dev))
6798 spin_lock_irq(&tp->lock);
6799 spin_lock(&tp->tx_lock);
6800 if (epause->autoneg)
6801 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
6803 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
6804 if (epause->rx_pause)
6805 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
6807 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
6808 if (epause->tx_pause)
6809 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
6811 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
6813 if (netif_running(dev)) {
6816 tg3_netif_start(tp);
6818 spin_unlock(&tp->tx_lock);
6819 spin_unlock_irq(&tp->lock);
6824 static u32 tg3_get_rx_csum(struct net_device *dev)
6826 struct tg3 *tp = netdev_priv(dev);
6827 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
6830 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
6832 struct tg3 *tp = netdev_priv(dev);
6834 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
6840 spin_lock_irq(&tp->lock);
6842 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
6844 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
6845 spin_unlock_irq(&tp->lock);
6850 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
6852 struct tg3 *tp = netdev_priv(dev);
6854 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
6861 dev->features |= NETIF_F_IP_CSUM;
6863 dev->features &= ~NETIF_F_IP_CSUM;
6868 static int tg3_get_stats_count (struct net_device *dev)
6870 return TG3_NUM_STATS;
6873 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
6875 switch (stringset) {
6877 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
6880 WARN_ON(1); /* we need a WARN() */
6885 static void tg3_get_ethtool_stats (struct net_device *dev,
6886 struct ethtool_stats *estats, u64 *tmp_stats)
6888 struct tg3 *tp = netdev_priv(dev);
6889 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
6892 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6894 struct mii_ioctl_data *data = if_mii(ifr);
6895 struct tg3 *tp = netdev_priv(dev);
6900 data->phy_id = PHY_ADDR;
6906 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
6907 break; /* We have no PHY */
6909 spin_lock_irq(&tp->lock);
6910 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
6911 spin_unlock_irq(&tp->lock);
6913 data->val_out = mii_regval;
6919 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
6920 break; /* We have no PHY */
6922 if (!capable(CAP_NET_ADMIN))
6925 spin_lock_irq(&tp->lock);
6926 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
6927 spin_unlock_irq(&tp->lock);
6938 #if TG3_VLAN_TAG_USED
6939 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
6941 struct tg3 *tp = netdev_priv(dev);
6943 spin_lock_irq(&tp->lock);
6944 spin_lock(&tp->tx_lock);
6948 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
6949 __tg3_set_rx_mode(dev);
6951 spin_unlock(&tp->tx_lock);
6952 spin_unlock_irq(&tp->lock);
6955 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
6957 struct tg3 *tp = netdev_priv(dev);
6959 spin_lock_irq(&tp->lock);
6960 spin_lock(&tp->tx_lock);
6962 tp->vlgrp->vlan_devices[vid] = NULL;
6963 spin_unlock(&tp->tx_lock);
6964 spin_unlock_irq(&tp->lock);
6968 static struct ethtool_ops tg3_ethtool_ops = {
6969 .get_settings = tg3_get_settings,
6970 .set_settings = tg3_set_settings,
6971 .get_drvinfo = tg3_get_drvinfo,
6972 .get_regs_len = tg3_get_regs_len,
6973 .get_regs = tg3_get_regs,
6974 .get_wol = tg3_get_wol,
6975 .set_wol = tg3_set_wol,
6976 .get_msglevel = tg3_get_msglevel,
6977 .set_msglevel = tg3_set_msglevel,
6978 .nway_reset = tg3_nway_reset,
6979 .get_link = ethtool_op_get_link,
6980 .get_eeprom_len = tg3_get_eeprom_len,
6981 .get_eeprom = tg3_get_eeprom,
6982 .set_eeprom = tg3_set_eeprom,
6983 .get_ringparam = tg3_get_ringparam,
6984 .set_ringparam = tg3_set_ringparam,
6985 .get_pauseparam = tg3_get_pauseparam,
6986 .set_pauseparam = tg3_set_pauseparam,
6987 .get_rx_csum = tg3_get_rx_csum,
6988 .set_rx_csum = tg3_set_rx_csum,
6989 .get_tx_csum = ethtool_op_get_tx_csum,
6990 .set_tx_csum = tg3_set_tx_csum,
6991 .get_sg = ethtool_op_get_sg,
6992 .set_sg = ethtool_op_set_sg,
6993 #if TG3_TSO_SUPPORT != 0
6994 .get_tso = ethtool_op_get_tso,
6995 .set_tso = tg3_set_tso,
6997 .get_strings = tg3_get_strings,
6998 .get_stats_count = tg3_get_stats_count,
6999 .get_ethtool_stats = tg3_get_ethtool_stats,
7002 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
7006 tp->nvram_size = EEPROM_CHIP_SIZE;
7008 if (tg3_nvram_read(tp, 0, &val) != 0)
7011 if (swab32(val) != TG3_EEPROM_MAGIC)
7015 * Size the chip by reading offsets at increasing powers of two.
7016 * When we encounter our validation signature, we know the addressing
7017 * has wrapped around, and thus have our chip size.
7021 while (cursize < tp->nvram_size) {
7022 if (tg3_nvram_read(tp, cursize, &val) != 0)
7025 if (swab32(val) == TG3_EEPROM_MAGIC)
7031 tp->nvram_size = cursize;
7034 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
7038 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
7040 tp->nvram_size = (val >> 16) * 1024;
7044 tp->nvram_size = 0x20000;
7047 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
7051 nvcfg1 = tr32(NVRAM_CFG1);
7052 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
7053 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7056 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7057 tw32(NVRAM_CFG1, nvcfg1);
7060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7061 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
7062 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
7063 tp->nvram_jedecnum = JEDEC_ATMEL;
7064 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7065 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7067 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
7068 tp->nvram_jedecnum = JEDEC_ATMEL;
7069 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
7071 case FLASH_VENDOR_ATMEL_EEPROM:
7072 tp->nvram_jedecnum = JEDEC_ATMEL;
7073 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7074 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7076 case FLASH_VENDOR_ST:
7077 tp->nvram_jedecnum = JEDEC_ST;
7078 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
7079 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7081 case FLASH_VENDOR_SAIFUN:
7082 tp->nvram_jedecnum = JEDEC_SAIFUN;
7083 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
7085 case FLASH_VENDOR_SST_SMALL:
7086 case FLASH_VENDOR_SST_LARGE:
7087 tp->nvram_jedecnum = JEDEC_SST;
7088 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
7093 tp->nvram_jedecnum = JEDEC_ATMEL;
7094 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7095 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7099 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
7100 static void __devinit tg3_nvram_init(struct tg3 *tp)
7104 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
7107 tw32_f(GRC_EEPROM_ADDR,
7108 (EEPROM_ADDR_FSM_RESET |
7109 (EEPROM_DEFAULT_CLOCK_PERIOD <<
7110 EEPROM_ADDR_CLKPERD_SHIFT)));
7112 /* XXX schedule_timeout() ... */
7113 for (j = 0; j < 100; j++)
7116 /* Enable seeprom accesses. */
7117 tw32_f(GRC_LOCAL_CTRL,
7118 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
7121 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
7122 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
7123 tp->tg3_flags |= TG3_FLAG_NVRAM;
7125 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7126 u32 nvaccess = tr32(NVRAM_ACCESS);
7128 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
7131 tg3_get_nvram_info(tp);
7132 tg3_get_nvram_size(tp);
7134 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7135 u32 nvaccess = tr32(NVRAM_ACCESS);
7137 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
7141 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
7143 tg3_get_eeprom_size(tp);
7147 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
7148 u32 offset, u32 *val)
7153 if (offset > EEPROM_ADDR_ADDR_MASK ||
7157 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
7158 EEPROM_ADDR_DEVID_MASK |
7160 tw32(GRC_EEPROM_ADDR,
7162 (0 << EEPROM_ADDR_DEVID_SHIFT) |
7163 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
7164 EEPROM_ADDR_ADDR_MASK) |
7165 EEPROM_ADDR_READ | EEPROM_ADDR_START);
7167 for (i = 0; i < 10000; i++) {
7168 tmp = tr32(GRC_EEPROM_ADDR);
7170 if (tmp & EEPROM_ADDR_COMPLETE)
7174 if (!(tmp & EEPROM_ADDR_COMPLETE))
7177 *val = tr32(GRC_EEPROM_DATA);
7181 #define NVRAM_CMD_TIMEOUT 10000
7183 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
7187 tw32(NVRAM_CMD, nvram_cmd);
7188 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
7190 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
7195 if (i == NVRAM_CMD_TIMEOUT) {
7201 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
7205 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
7206 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
7210 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
7211 return tg3_nvram_read_using_eeprom(tp, offset, val);
7213 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
7214 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
7215 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
7217 offset = ((offset / tp->nvram_pagesize) <<
7218 ATMEL_AT45DB0X1B_PAGE_POS) +
7219 (offset % tp->nvram_pagesize);
7222 if (offset > NVRAM_ADDR_MSK)
7227 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7228 u32 nvaccess = tr32(NVRAM_ACCESS);
7230 tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
7233 tw32(NVRAM_ADDR, offset);
7234 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
7235 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
7238 *val = swab32(tr32(NVRAM_RDDATA));
7240 tg3_nvram_unlock(tp);
7242 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7243 u32 nvaccess = tr32(NVRAM_ACCESS);
7245 tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
7251 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
7252 u32 offset, u32 len, u8 *buf)
7257 for (i = 0; i < len; i += 4) {
7262 memcpy(&data, buf + i, 4);
7264 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
7266 val = tr32(GRC_EEPROM_ADDR);
7267 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
7269 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
7271 tw32(GRC_EEPROM_ADDR, val |
7272 (0 << EEPROM_ADDR_DEVID_SHIFT) |
7273 (addr & EEPROM_ADDR_ADDR_MASK) |
7277 for (j = 0; j < 10000; j++) {
7278 val = tr32(GRC_EEPROM_ADDR);
7280 if (val & EEPROM_ADDR_COMPLETE)
7284 if (!(val & EEPROM_ADDR_COMPLETE)) {
7293 /* offset and length are dword aligned */
7294 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
7298 u32 pagesize = tp->nvram_pagesize;
7299 u32 pagemask = pagesize - 1;
7303 tmp = kmalloc(pagesize, GFP_KERNEL);
7309 u32 phy_addr, page_off, size, nvaccess;
7311 phy_addr = offset & ~pagemask;
7313 for (j = 0; j < pagesize; j += 4) {
7314 if ((ret = tg3_nvram_read(tp, phy_addr + j,
7315 (u32 *) (tmp + j))))
7321 page_off = offset & pagemask;
7328 memcpy(tmp + page_off, buf, size);
7330 offset = offset + (pagesize - page_off);
7332 nvaccess = tr32(NVRAM_ACCESS);
7333 tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
7336 * Before we can erase the flash page, we need
7337 * to issue a special "write enable" command.
7339 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
7341 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
7344 /* Erase the target page */
7345 tw32(NVRAM_ADDR, phy_addr);
7347 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
7348 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
7350 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
7353 /* Issue another write enable to start the write. */
7354 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
7356 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
7359 for (j = 0; j < pagesize; j += 4) {
7362 data = *((u32 *) (tmp + j));
7363 tw32(NVRAM_WRDATA, cpu_to_be32(data));
7365 tw32(NVRAM_ADDR, phy_addr + j);
7367 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
7371 nvram_cmd |= NVRAM_CMD_FIRST;
7372 else if (j == (pagesize - 4))
7373 nvram_cmd |= NVRAM_CMD_LAST;
7375 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
7382 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
7383 tg3_nvram_exec_cmd(tp, nvram_cmd);
7390 /* offset and length are dword aligned */
7391 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
7396 for (i = 0; i < len; i += 4, offset += 4) {
7397 u32 data, page_off, phy_addr, nvram_cmd;
7399 memcpy(&data, buf + i, 4);
7400 tw32(NVRAM_WRDATA, cpu_to_be32(data));
7402 page_off = offset % tp->nvram_pagesize;
7404 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
7405 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
7407 phy_addr = ((offset / tp->nvram_pagesize) <<
7408 ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
7414 tw32(NVRAM_ADDR, phy_addr);
7416 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
7418 if ((page_off == 0) || (i == 0))
7419 nvram_cmd |= NVRAM_CMD_FIRST;
7420 else if (page_off == (tp->nvram_pagesize - 4))
7421 nvram_cmd |= NVRAM_CMD_LAST;
7424 nvram_cmd |= NVRAM_CMD_LAST;
7426 if ((tp->nvram_jedecnum == JEDEC_ST) &&
7427 (nvram_cmd & NVRAM_CMD_FIRST)) {
7429 if ((ret = tg3_nvram_exec_cmd(tp,
7430 NVRAM_CMD_WREN | NVRAM_CMD_GO |
7435 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
7436 /* We always do complete word writes to eeprom. */
7437 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
7440 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
7446 /* offset and length are dword aligned */
7447 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
7451 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
7452 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
7456 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
7457 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
7458 ~GRC_LCLCTRL_GPIO_OUTPUT1);
7462 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
7463 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
7470 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7471 u32 nvaccess = tr32(NVRAM_ACCESS);
7473 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
7475 tw32(NVRAM_WRITE1, 0x406);
7478 grc_mode = tr32(GRC_MODE);
7479 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
7481 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
7482 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
7484 ret = tg3_nvram_write_block_buffered(tp, offset, len,
7488 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
7492 grc_mode = tr32(GRC_MODE);
7493 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
7495 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7496 u32 nvaccess = tr32(NVRAM_ACCESS);
7498 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
7500 tg3_nvram_unlock(tp);
7503 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
7504 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7511 struct subsys_tbl_ent {
7512 u16 subsys_vendor, subsys_devid;
7516 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
7517 /* Broadcom boards. */
7518 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
7519 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
7520 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
7521 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
7522 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
7523 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
7524 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
7525 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
7526 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
7527 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
7528 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
7531 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
7532 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
7533 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
7534 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
7535 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
7538 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
7539 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
7540 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
7541 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
7543 /* Compaq boards. */
7544 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
7545 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
7546 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
7547 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
7548 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
7551 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
7554 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
7558 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
7559 if ((subsys_id_to_phy_id[i].subsys_vendor ==
7560 tp->pdev->subsystem_vendor) &&
7561 (subsys_id_to_phy_id[i].subsys_devid ==
7562 tp->pdev->subsystem_device))
7563 return &subsys_id_to_phy_id[i];
7568 /* Since this function may be called in D3-hot power state during
7569 * tg3_init_one(), only config cycles are allowed.
7571 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
7575 /* Make sure register accesses (indirect or otherwise)
7576 * will function correctly.
7578 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7579 tp->misc_host_ctrl);
7581 tp->phy_id = PHY_ID_INVALID;
7582 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
7584 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7585 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7586 u32 nic_cfg, led_cfg;
7587 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
7588 int eeprom_phy_serdes = 0;
7590 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7591 tp->nic_sram_data_cfg = nic_cfg;
7593 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
7594 ver >>= NIC_SRAM_DATA_VER_SHIFT;
7595 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
7596 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
7597 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
7598 (ver > 0) && (ver < 0x100))
7599 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
7601 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
7602 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
7603 eeprom_phy_serdes = 1;
7605 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
7606 if (nic_phy_id != 0) {
7607 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
7608 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
7610 eeprom_phy_id = (id1 >> 16) << 10;
7611 eeprom_phy_id |= (id2 & 0xfc00) << 16;
7612 eeprom_phy_id |= (id2 & 0x03ff) << 0;
7616 tp->phy_id = eeprom_phy_id;
7617 if (eeprom_phy_serdes)
7618 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
7620 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7621 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
7622 SHASTA_EXT_LED_MODE_MASK);
7624 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
7628 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
7629 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
7632 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
7633 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
7636 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
7637 tp->led_ctrl = LED_CTRL_MODE_MAC;
7640 case SHASTA_EXT_LED_SHARED:
7641 tp->led_ctrl = LED_CTRL_MODE_SHARED;
7642 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7643 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
7644 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
7645 LED_CTRL_MODE_PHY_2);
7648 case SHASTA_EXT_LED_MAC:
7649 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
7652 case SHASTA_EXT_LED_COMBO:
7653 tp->led_ctrl = LED_CTRL_MODE_COMBO;
7654 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
7655 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
7656 LED_CTRL_MODE_PHY_2);
7661 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
7663 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
7664 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
7666 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
7667 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
7668 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
7669 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
7671 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7672 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7673 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7674 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7676 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
7677 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
7679 if (cfg2 & (1 << 17))
7680 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
7682 /* serdes signal pre-emphasis in register 0x590 set by */
7683 /* bootcode if bit 18 is set */
7684 if (cfg2 & (1 << 18))
7685 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
7689 static int __devinit tg3_phy_probe(struct tg3 *tp)
7691 u32 hw_phy_id_1, hw_phy_id_2;
7692 u32 hw_phy_id, hw_phy_id_masked;
7695 /* Reading the PHY ID register can conflict with ASF
7696 * firwmare access to the PHY hardware.
7699 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7700 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
7702 /* Now read the physical PHY_ID from the chip and verify
7703 * that it is sane. If it doesn't look good, we fall back
7704 * to either the hard-coded table based PHY_ID and failing
7705 * that the value found in the eeprom area.
7707 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
7708 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
7710 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
7711 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
7712 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
7714 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
7717 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
7718 tp->phy_id = hw_phy_id;
7719 if (hw_phy_id_masked == PHY_ID_BCM8002)
7720 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
7722 if (tp->phy_id != PHY_ID_INVALID) {
7723 /* Do nothing, phy ID already set up in
7724 * tg3_get_eeprom_hw_cfg().
7727 struct subsys_tbl_ent *p;
7729 /* No eeprom signature? Try the hardcoded
7730 * subsys device table.
7732 p = lookup_by_subsys(tp);
7736 tp->phy_id = p->phy_id;
7738 tp->phy_id == PHY_ID_BCM8002)
7739 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
7743 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7744 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
7745 u32 bmsr, adv_reg, tg3_ctrl;
7747 tg3_readphy(tp, MII_BMSR, &bmsr);
7748 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
7749 (bmsr & BMSR_LSTATUS))
7750 goto skip_phy_reset;
7752 err = tg3_phy_reset(tp);
7756 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
7757 ADVERTISE_100HALF | ADVERTISE_100FULL |
7758 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
7760 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
7761 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
7762 MII_TG3_CTRL_ADV_1000_FULL);
7763 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
7764 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
7765 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
7766 MII_TG3_CTRL_ENABLE_AS_MASTER);
7769 if (!tg3_copper_is_advertising_all(tp)) {
7770 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
7772 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7773 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
7775 tg3_writephy(tp, MII_BMCR,
7776 BMCR_ANENABLE | BMCR_ANRESTART);
7778 tg3_phy_set_wirespeed(tp);
7780 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
7781 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7782 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
7786 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
7787 err = tg3_init_5401phy_dsp(tp);
7792 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
7793 err = tg3_init_5401phy_dsp(tp);
7796 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7797 tp->link_config.advertising =
7798 (ADVERTISED_1000baseT_Half |
7799 ADVERTISED_1000baseT_Full |
7800 ADVERTISED_Autoneg |
7802 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
7803 tp->link_config.advertising &=
7804 ~(ADVERTISED_1000baseT_Half |
7805 ADVERTISED_1000baseT_Full);
7810 static void __devinit tg3_read_partno(struct tg3 *tp)
7812 unsigned char vpd_data[256];
7815 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
7816 /* Sun decided not to put the necessary bits in the
7817 * NVRAM of their onboard tg3 parts :(
7819 strcpy(tp->board_part_number, "Sun 570X");
7823 for (i = 0; i < 256; i += 4) {
7826 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
7829 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
7830 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
7831 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
7832 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
7835 /* Now parse and find the part number. */
7836 for (i = 0; i < 256; ) {
7837 unsigned char val = vpd_data[i];
7840 if (val == 0x82 || val == 0x91) {
7843 (vpd_data[i + 2] << 8)));
7850 block_end = (i + 3 +
7852 (vpd_data[i + 2] << 8)));
7854 while (i < block_end) {
7855 if (vpd_data[i + 0] == 'P' &&
7856 vpd_data[i + 1] == 'N') {
7857 int partno_len = vpd_data[i + 2];
7859 if (partno_len > 24)
7862 memcpy(tp->board_part_number,
7871 /* Part number not found. */
7876 strcpy(tp->board_part_number, "none");
7879 #ifdef CONFIG_SPARC64
7880 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
7882 struct pci_dev *pdev = tp->pdev;
7883 struct pcidev_cookie *pcp = pdev->sysdata;
7886 int node = pcp->prom_node;
7890 err = prom_getproperty(node, "subsystem-vendor-id",
7891 (char *) &venid, sizeof(venid));
7892 if (err == 0 || err == -1)
7894 if (venid == PCI_VENDOR_ID_SUN)
7901 static int __devinit tg3_get_invariants(struct tg3 *tp)
7903 static struct pci_device_id write_reorder_chipsets[] = {
7904 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
7905 PCI_DEVICE_ID_INTEL_82801AA_8) },
7906 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
7907 PCI_DEVICE_ID_INTEL_82801AB_8) },
7908 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
7909 PCI_DEVICE_ID_INTEL_82801BA_11) },
7910 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
7911 PCI_DEVICE_ID_INTEL_82801BA_6) },
7912 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
7913 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
7917 u32 cacheline_sz_reg;
7918 u32 pci_state_reg, grc_misc_cfg;
7923 #ifdef CONFIG_SPARC64
7924 if (tg3_is_sun_570X(tp))
7925 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
7928 /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
7929 * reordering to the mailbox registers done by the host
7930 * controller can cause major troubles. We read back from
7931 * every mailbox register write to force the writes to be
7932 * posted to the chip in order.
7934 if (pci_dev_present(write_reorder_chipsets))
7935 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
7937 /* Force memory write invalidate off. If we leave it on,
7938 * then on 5700_BX chips we have to enable a workaround.
7939 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
7940 * to match the cacheline size. The Broadcom driver have this
7941 * workaround but turns MWI off all the times so never uses
7942 * it. This seems to suggest that the workaround is insufficient.
7944 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7945 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
7946 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7948 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
7949 * has the register indirect write enable bit set before
7950 * we try to access any of the MMIO registers. It is also
7951 * critical that the PCI-X hw workaround situation is decided
7952 * before that as well.
7954 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7957 tp->pci_chip_rev_id = (misc_ctrl_reg >>
7958 MISC_HOST_CTRL_CHIPREV_SHIFT);
7960 /* Wrong chip ID in 5752 A0. This code can be removed later
7961 * as A0 is not in production.
7963 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
7964 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
7966 /* Initialize misc host control in PCI block. */
7967 tp->misc_host_ctrl |= (misc_ctrl_reg &
7968 MISC_HOST_CTRL_CHIPREV);
7969 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7970 tp->misc_host_ctrl);
7972 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
7975 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
7976 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
7977 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
7978 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
7980 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7982 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
7984 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
7985 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
7986 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
7988 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7989 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
7991 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
7992 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
7994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
7995 tp->pci_lat_timer < 64) {
7996 tp->pci_lat_timer = 64;
7998 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
7999 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
8000 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
8001 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
8003 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8007 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8010 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
8011 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
8013 /* If this is a 5700 BX chipset, and we are in PCI-X
8014 * mode, enable register write workaround.
8016 * The workaround is to use indirect register accesses
8017 * for all chip writes not to mailbox registers.
8019 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
8023 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8025 /* The chip can have it's power management PCI config
8026 * space registers clobbered due to this bug.
8027 * So explicitly force the chip into D0 here.
8029 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8031 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
8032 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
8033 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8036 /* Also, force SERR#/PERR# in PCI command. */
8037 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8038 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
8039 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8043 /* Back to back register writes can cause problems on this chip,
8044 * the workaround is to read back all reg writes except those to
8045 * mailbox regs. See tg3_write_indirect_reg32().
8047 * PCI Express 5750_A0 rev chips need this workaround too.
8049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
8050 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
8051 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
8052 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
8054 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
8055 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
8056 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
8057 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
8059 /* Chip-specific fixup from Broadcom driver */
8060 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
8061 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
8062 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
8063 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
8066 /* Get eeprom hw config before calling tg3_set_power_state().
8067 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
8068 * determined before calling tg3_set_power_state() so that
8069 * we know whether or not to switch out of Vaux power.
8070 * When the flag is set, it means that GPIO1 is used for eeprom
8071 * write protect and also implies that it is a LOM where GPIOs
8072 * are not used to switch power.
8074 tg3_get_eeprom_hw_cfg(tp);
8076 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
8077 * GPIO1 driven high will bring 5700's external PHY out of reset.
8078 * It is also used as eeprom write protect on LOMs.
8080 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
8081 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
8082 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
8083 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8084 GRC_LCLCTRL_GPIO_OUTPUT1);
8085 /* Unused GPIO3 must be driven as output on 5752 because there
8086 * are no pull-up resistors on unused GPIO pins.
8088 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8089 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
8091 /* Force the chip into D0. */
8092 err = tg3_set_power_state(tp, 0);
8094 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
8095 pci_name(tp->pdev));
8099 /* 5700 B0 chips do not support checksumming correctly due
8102 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
8103 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
8105 /* Pseudo-header checksum is done by hardware logic and not
8106 * the offload processers, so make the chip do the pseudo-
8107 * header checksums on receive. For transmit it is more
8108 * convenient to do the pseudo-header checksum in software
8109 * as Linux does that on transmit for us in all cases.
8111 tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
8112 tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
8114 /* Derive initial jumbo mode from MTU assigned in
8115 * ether_setup() via the alloc_etherdev() call
8117 if (tp->dev->mtu > ETH_DATA_LEN)
8118 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
8120 /* Determine WakeOnLan speed to use. */
8121 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8122 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8123 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
8124 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
8125 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
8127 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
8130 /* A few boards don't want Ethernet@WireSpeed phy feature */
8131 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
8132 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
8133 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
8134 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
8135 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
8137 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
8138 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
8139 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
8140 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
8141 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
8143 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8144 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
8146 /* Only 5701 and later support tagged irq status mode.
8147 * Also, 5788 chips cannot use tagged irq status.
8149 * However, since we are using NAPI avoid tagged irq status
8150 * because the interrupt condition is more difficult to
8151 * fully clear in that mode.
8153 tp->coalesce_mode = 0;
8155 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
8156 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
8157 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
8159 /* Initialize MAC MI mode, polling disabled. */
8160 tw32_f(MAC_MI_MODE, tp->mi_mode);
8163 /* Initialize data/descriptor byte/word swapping. */
8164 val = tr32(GRC_MODE);
8165 val &= GRC_MODE_HOST_STACKUP;
8166 tw32(GRC_MODE, val | tp->grc_mode);
8168 tg3_switch_clocks(tp);
8170 /* Clear this out for sanity. */
8171 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8173 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8175 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
8176 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
8177 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
8179 if (chiprevid == CHIPREV_ID_5701_A0 ||
8180 chiprevid == CHIPREV_ID_5701_B0 ||
8181 chiprevid == CHIPREV_ID_5701_B2 ||
8182 chiprevid == CHIPREV_ID_5701_B5) {
8183 void __iomem *sram_base;
8185 /* Write some dummy words into the SRAM status block
8186 * area, see if it reads back correctly. If the return
8187 * value is bad, force enable the PCIX workaround.
8189 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
8191 writel(0x00000000, sram_base);
8192 writel(0x00000000, sram_base + 4);
8193 writel(0xffffffff, sram_base + 4);
8194 if (readl(sram_base) != 0x00000000)
8195 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8202 grc_misc_cfg = tr32(GRC_MISC_CFG);
8203 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
8205 /* Broadcom's driver says that CIOBE multisplit has a bug */
8207 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8208 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
8209 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
8210 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
8213 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8214 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
8215 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
8216 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
8218 /* these are limited to 10/100 only */
8219 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8220 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
8221 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8222 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
8223 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
8224 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
8225 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
8226 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
8227 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
8228 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
8229 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
8231 err = tg3_phy_probe(tp);
8233 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
8234 pci_name(tp->pdev), err);
8235 /* ... but do not return immediately ... */
8238 tg3_read_partno(tp);
8240 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8241 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
8243 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
8244 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
8246 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
8249 /* 5700 {AX,BX} chips have a broken status block link
8250 * change bit implementation, so we must use the
8251 * status register in those cases.
8253 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
8254 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
8256 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
8258 /* The led_ctrl is set during tg3_phy_probe, here we might
8259 * have to force the link status polling mechanism based
8260 * upon subsystem IDs.
8262 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
8263 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8264 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
8265 TG3_FLAG_USE_LINKCHG_REG);
8268 /* For all SERDES we poll the MAC status register. */
8269 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8270 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
8272 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
8274 /* 5700 BX chips need to have their TX producer index mailboxes
8275 * written twice to workaround a bug.
8277 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
8278 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
8280 tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
8282 /* It seems all chips can get confused if TX buffers
8283 * straddle the 4GB address boundary in some cases.
8285 tp->dev->hard_start_xmit = tg3_start_xmit;
8288 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
8289 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
8292 /* By default, disable wake-on-lan. User can change this
8293 * using ETHTOOL_SWOL.
8295 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8300 #ifdef CONFIG_SPARC64
8301 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
8303 struct net_device *dev = tp->dev;
8304 struct pci_dev *pdev = tp->pdev;
8305 struct pcidev_cookie *pcp = pdev->sysdata;
8308 int node = pcp->prom_node;
8310 if (prom_getproplen(node, "local-mac-address") == 6) {
8311 prom_getproperty(node, "local-mac-address",
8319 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
8321 struct net_device *dev = tp->dev;
8323 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
8328 static int __devinit tg3_get_device_address(struct tg3 *tp)
8330 struct net_device *dev = tp->dev;
8331 u32 hi, lo, mac_offset;
8333 #ifdef CONFIG_SPARC64
8334 if (!tg3_get_macaddr_sparc(tp))
8339 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8340 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) {
8341 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
8343 if (tg3_nvram_lock(tp))
8344 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
8346 tg3_nvram_unlock(tp);
8349 /* First try to get it from MAC address mailbox. */
8350 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
8351 if ((hi >> 16) == 0x484b) {
8352 dev->dev_addr[0] = (hi >> 8) & 0xff;
8353 dev->dev_addr[1] = (hi >> 0) & 0xff;
8355 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
8356 dev->dev_addr[2] = (lo >> 24) & 0xff;
8357 dev->dev_addr[3] = (lo >> 16) & 0xff;
8358 dev->dev_addr[4] = (lo >> 8) & 0xff;
8359 dev->dev_addr[5] = (lo >> 0) & 0xff;
8361 /* Next, try NVRAM. */
8362 else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
8363 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
8364 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
8365 dev->dev_addr[0] = ((hi >> 16) & 0xff);
8366 dev->dev_addr[1] = ((hi >> 24) & 0xff);
8367 dev->dev_addr[2] = ((lo >> 0) & 0xff);
8368 dev->dev_addr[3] = ((lo >> 8) & 0xff);
8369 dev->dev_addr[4] = ((lo >> 16) & 0xff);
8370 dev->dev_addr[5] = ((lo >> 24) & 0xff);
8372 /* Finally just fetch it out of the MAC control regs. */
8374 hi = tr32(MAC_ADDR_0_HIGH);
8375 lo = tr32(MAC_ADDR_0_LOW);
8377 dev->dev_addr[5] = lo & 0xff;
8378 dev->dev_addr[4] = (lo >> 8) & 0xff;
8379 dev->dev_addr[3] = (lo >> 16) & 0xff;
8380 dev->dev_addr[2] = (lo >> 24) & 0xff;
8381 dev->dev_addr[1] = hi & 0xff;
8382 dev->dev_addr[0] = (hi >> 8) & 0xff;
8385 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
8386 #ifdef CONFIG_SPARC64
8387 if (!tg3_get_default_macaddr_sparc(tp))
8395 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
8397 struct tg3_internal_buffer_desc test_desc;
8401 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
8403 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
8404 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
8405 tw32(RDMAC_STATUS, 0);
8406 tw32(WDMAC_STATUS, 0);
8408 tw32(BUFMGR_MODE, 0);
8411 test_desc.addr_hi = ((u64) buf_dma) >> 32;
8412 test_desc.addr_lo = buf_dma & 0xffffffff;
8413 test_desc.nic_mbuf = 0x00002100;
8414 test_desc.len = size;
8417 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
8418 * the *second* time the tg3 driver was getting loaded after an
8421 * Broadcom tells me:
8422 * ...the DMA engine is connected to the GRC block and a DMA
8423 * reset may affect the GRC block in some unpredictable way...
8424 * The behavior of resets to individual blocks has not been tested.
8426 * Broadcom noted the GRC reset will also reset all sub-components.
8429 test_desc.cqid_sqid = (13 << 8) | 2;
8431 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
8434 test_desc.cqid_sqid = (16 << 8) | 7;
8436 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
8439 test_desc.flags = 0x00000005;
8441 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
8444 val = *(((u32 *)&test_desc) + i);
8445 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
8446 sram_dma_descs + (i * sizeof(u32)));
8447 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
8449 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
8452 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
8454 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
8458 for (i = 0; i < 40; i++) {
8462 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
8464 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
8465 if ((val & 0xffff) == sram_dma_descs) {
8476 #define TEST_BUFFER_SIZE 0x400
8478 static int __devinit tg3_test_dma(struct tg3 *tp)
8484 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
8490 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
8491 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
8497 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
8500 cacheline_size = 1024;
8502 cacheline_size = (int) byte * 4;
8504 switch (cacheline_size) {
8509 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
8510 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8512 DMA_RWCTRL_WRITE_BNDRY_384_PCIX;
8514 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
8516 ~(DMA_RWCTRL_PCI_WRITE_CMD);
8518 DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
8523 if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
8524 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8526 DMA_RWCTRL_WRITE_BNDRY_256;
8527 else if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8529 DMA_RWCTRL_WRITE_BNDRY_256_PCIX;
8534 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
8535 /* DMA read watermark not used on PCIE */
8536 tp->dma_rwctrl |= 0x00180000;
8537 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
8538 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
8539 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
8540 tp->dma_rwctrl |= 0x003f0000;
8542 tp->dma_rwctrl |= 0x003f000f;
8544 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
8545 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8546 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
8548 if (ccval == 0x6 || ccval == 0x7)
8549 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
8551 /* Set bit 23 to renable PCIX hw bug fix */
8552 tp->dma_rwctrl |= 0x009f0000;
8554 tp->dma_rwctrl |= 0x001b000f;
8558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
8559 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8560 tp->dma_rwctrl &= 0xfffffff0;
8562 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8563 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
8564 /* Remove this if it causes problems for some boards. */
8565 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
8567 /* On 5700/5701 chips, we need to set this bit.
8568 * Otherwise the chip will issue cacheline transactions
8569 * to streamable DMA memory with not all the byte
8570 * enables turned on. This is an error on several
8571 * RISC PCI controllers, in particular sparc64.
8573 * On 5703/5704 chips, this bit has been reassigned
8574 * a different meaning. In particular, it is used
8575 * on those chips to enable a PCI-X workaround.
8577 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
8580 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8583 /* Unneeded, already done by tg3_get_invariants. */
8584 tg3_switch_clocks(tp);
8588 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8589 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
8595 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
8598 /* Send the buffer to the chip. */
8599 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
8601 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
8606 /* validate data reached card RAM correctly. */
8607 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
8609 tg3_read_mem(tp, 0x2100 + (i*4), &val);
8610 if (le32_to_cpu(val) != p[i]) {
8611 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
8612 /* ret = -ENODEV here? */
8617 /* Now read it back. */
8618 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
8620 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
8626 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
8630 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) ==
8631 DMA_RWCTRL_WRITE_BNDRY_DISAB) {
8632 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
8633 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8636 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
8642 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
8650 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
8655 static void __devinit tg3_init_link_config(struct tg3 *tp)
8657 tp->link_config.advertising =
8658 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
8659 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
8660 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
8661 ADVERTISED_Autoneg | ADVERTISED_MII);
8662 tp->link_config.speed = SPEED_INVALID;
8663 tp->link_config.duplex = DUPLEX_INVALID;
8664 tp->link_config.autoneg = AUTONEG_ENABLE;
8665 netif_carrier_off(tp->dev);
8666 tp->link_config.active_speed = SPEED_INVALID;
8667 tp->link_config.active_duplex = DUPLEX_INVALID;
8668 tp->link_config.phy_is_low_power = 0;
8669 tp->link_config.orig_speed = SPEED_INVALID;
8670 tp->link_config.orig_duplex = DUPLEX_INVALID;
8671 tp->link_config.orig_autoneg = AUTONEG_INVALID;
8674 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
8676 tp->bufmgr_config.mbuf_read_dma_low_water =
8677 DEFAULT_MB_RDMA_LOW_WATER;
8678 tp->bufmgr_config.mbuf_mac_rx_low_water =
8679 DEFAULT_MB_MACRX_LOW_WATER;
8680 tp->bufmgr_config.mbuf_high_water =
8681 DEFAULT_MB_HIGH_WATER;
8683 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
8684 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
8685 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
8686 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
8687 tp->bufmgr_config.mbuf_high_water_jumbo =
8688 DEFAULT_MB_HIGH_WATER_JUMBO;
8690 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
8691 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
8694 static char * __devinit tg3_phy_string(struct tg3 *tp)
8696 switch (tp->phy_id & PHY_ID_MASK) {
8697 case PHY_ID_BCM5400: return "5400";
8698 case PHY_ID_BCM5401: return "5401";
8699 case PHY_ID_BCM5411: return "5411";
8700 case PHY_ID_BCM5701: return "5701";
8701 case PHY_ID_BCM5703: return "5703";
8702 case PHY_ID_BCM5704: return "5704";
8703 case PHY_ID_BCM5705: return "5705";
8704 case PHY_ID_BCM5750: return "5750";
8705 case PHY_ID_BCM5752: return "5752";
8706 case PHY_ID_BCM8002: return "8002/serdes";
8707 case 0: return "serdes";
8708 default: return "unknown";
8712 static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
8714 struct pci_dev *peer;
8715 unsigned int func, devnr = tp->pdev->devfn & ~7;
8717 for (func = 0; func < 8; func++) {
8718 peer = pci_get_slot(tp->pdev->bus, devnr | func);
8719 if (peer && peer != tp->pdev)
8723 if (!peer || peer == tp->pdev)
8727 * We don't need to keep the refcount elevated; there's no way
8728 * to remove one half of this device without removing the other
8735 static int __devinit tg3_init_one(struct pci_dev *pdev,
8736 const struct pci_device_id *ent)
8738 static int tg3_version_printed = 0;
8739 unsigned long tg3reg_base, tg3reg_len;
8740 struct net_device *dev;
8742 int i, err, pci_using_dac, pm_cap;
8744 if (tg3_version_printed++ == 0)
8745 printk(KERN_INFO "%s", version);
8747 err = pci_enable_device(pdev);
8749 printk(KERN_ERR PFX "Cannot enable PCI device, "
8754 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
8755 printk(KERN_ERR PFX "Cannot find proper PCI device "
8756 "base address, aborting.\n");
8758 goto err_out_disable_pdev;
8761 err = pci_request_regions(pdev, DRV_MODULE_NAME);
8763 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
8765 goto err_out_disable_pdev;
8768 pci_set_master(pdev);
8770 /* Find power-management capability. */
8771 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
8773 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
8776 goto err_out_free_res;
8779 /* Configure DMA attributes. */
8780 err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
8783 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
8785 printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
8786 "for consistent allocations\n");
8787 goto err_out_free_res;
8790 err = pci_set_dma_mask(pdev, 0xffffffffULL);
8792 printk(KERN_ERR PFX "No usable DMA configuration, "
8794 goto err_out_free_res;
8799 tg3reg_base = pci_resource_start(pdev, 0);
8800 tg3reg_len = pci_resource_len(pdev, 0);
8802 dev = alloc_etherdev(sizeof(*tp));
8804 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
8806 goto err_out_free_res;
8809 SET_MODULE_OWNER(dev);
8810 SET_NETDEV_DEV(dev, &pdev->dev);
8813 dev->features |= NETIF_F_HIGHDMA;
8814 dev->features |= NETIF_F_LLTX;
8815 #if TG3_VLAN_TAG_USED
8816 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8817 dev->vlan_rx_register = tg3_vlan_rx_register;
8818 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
8821 tp = netdev_priv(dev);
8824 tp->pm_cap = pm_cap;
8825 tp->mac_mode = TG3_DEF_MAC_MODE;
8826 tp->rx_mode = TG3_DEF_RX_MODE;
8827 tp->tx_mode = TG3_DEF_TX_MODE;
8828 tp->mi_mode = MAC_MI_MODE_BASE;
8830 tp->msg_enable = tg3_debug;
8832 tp->msg_enable = TG3_DEF_MSG_ENABLE;
8834 /* The word/byte swap controls here control register access byte
8835 * swapping. DMA data byte swapping is controlled in the GRC_MODE
8838 tp->misc_host_ctrl =
8839 MISC_HOST_CTRL_MASK_PCI_INT |
8840 MISC_HOST_CTRL_WORD_SWAP |
8841 MISC_HOST_CTRL_INDIR_ACCESS |
8842 MISC_HOST_CTRL_PCISTATE_RW;
8844 /* The NONFRM (non-frame) byte/word swap controls take effect
8845 * on descriptor entries, anything which isn't packet data.
8847 * The StrongARM chips on the board (one for tx, one for rx)
8848 * are running in big-endian mode.
8850 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
8851 GRC_MODE_WSWAP_NONFRM_DATA);
8853 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
8855 spin_lock_init(&tp->lock);
8856 spin_lock_init(&tp->tx_lock);
8857 spin_lock_init(&tp->indirect_lock);
8858 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
8860 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
8861 if (tp->regs == 0UL) {
8862 printk(KERN_ERR PFX "Cannot map device registers, "
8865 goto err_out_free_dev;
8868 tg3_init_link_config(tp);
8870 tg3_init_bufmgr_config(tp);
8872 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
8873 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
8874 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
8876 dev->open = tg3_open;
8877 dev->stop = tg3_close;
8878 dev->get_stats = tg3_get_stats;
8879 dev->set_multicast_list = tg3_set_rx_mode;
8880 dev->set_mac_address = tg3_set_mac_addr;
8881 dev->do_ioctl = tg3_ioctl;
8882 dev->tx_timeout = tg3_tx_timeout;
8883 dev->poll = tg3_poll;
8884 dev->ethtool_ops = &tg3_ethtool_ops;
8886 dev->watchdog_timeo = TG3_TX_TIMEOUT;
8887 dev->change_mtu = tg3_change_mtu;
8888 dev->irq = pdev->irq;
8889 #ifdef CONFIG_NET_POLL_CONTROLLER
8890 dev->poll_controller = tg3_poll_controller;
8893 err = tg3_get_invariants(tp);
8895 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
8897 goto err_out_iounmap;
8900 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8901 tp->bufmgr_config.mbuf_read_dma_low_water =
8902 DEFAULT_MB_RDMA_LOW_WATER_5705;
8903 tp->bufmgr_config.mbuf_mac_rx_low_water =
8904 DEFAULT_MB_MACRX_LOW_WATER_5705;
8905 tp->bufmgr_config.mbuf_high_water =
8906 DEFAULT_MB_HIGH_WATER_5705;
8909 #if TG3_TSO_SUPPORT != 0
8910 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
8911 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8913 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8914 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
8915 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
8916 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
8917 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8919 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8922 /* TSO is off by default, user can enable using ethtool. */
8924 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
8925 dev->features |= NETIF_F_TSO;
8930 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
8931 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8932 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
8933 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
8934 tp->rx_pending = 63;
8937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8938 tp->pdev_peer = tg3_find_5704_peer(tp);
8940 err = tg3_get_device_address(tp);
8942 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
8944 goto err_out_iounmap;
8948 * Reset chip in case UNDI or EFI driver did not shutdown
8949 * DMA self test will enable WDMAC and we'll see (spurious)
8950 * pending DMA on the PCI bus at that point.
8952 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
8953 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8954 pci_save_state(tp->pdev);
8955 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
8959 err = tg3_test_dma(tp);
8961 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
8962 goto err_out_iounmap;
8965 /* Tigon3 can do ipv4 only... and some chips have buggy
8968 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
8969 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
8970 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8972 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8974 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
8975 dev->features &= ~NETIF_F_HIGHDMA;
8977 /* flow control autonegotiation is default behavior */
8978 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8980 err = register_netdev(dev);
8982 printk(KERN_ERR PFX "Cannot register net device, "
8984 goto err_out_iounmap;
8987 pci_set_drvdata(pdev, dev);
8989 /* Now that we have fully setup the chip, save away a snapshot
8990 * of the PCI config space. We need to restore this after
8991 * GRC_MISC_CFG core clock resets and some resume events.
8993 pci_save_state(tp->pdev);
8995 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
8997 tp->board_part_number,
8998 tp->pci_chip_rev_id,
9000 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
9001 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
9002 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
9003 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
9004 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
9005 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
9007 for (i = 0; i < 6; i++)
9008 printk("%2.2x%c", dev->dev_addr[i],
9009 i == 5 ? '\n' : ':');
9011 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
9012 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
9015 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
9016 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
9017 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
9018 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
9019 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
9020 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
9021 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
9032 pci_release_regions(pdev);
9034 err_out_disable_pdev:
9035 pci_disable_device(pdev);
9036 pci_set_drvdata(pdev, NULL);
9040 static void __devexit tg3_remove_one(struct pci_dev *pdev)
9042 struct net_device *dev = pci_get_drvdata(pdev);
9045 struct tg3 *tp = netdev_priv(dev);
9047 unregister_netdev(dev);
9050 pci_release_regions(pdev);
9051 pci_disable_device(pdev);
9052 pci_set_drvdata(pdev, NULL);
9056 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
9058 struct net_device *dev = pci_get_drvdata(pdev);
9059 struct tg3 *tp = netdev_priv(dev);
9062 if (!netif_running(dev))
9067 del_timer_sync(&tp->timer);
9069 spin_lock_irq(&tp->lock);
9070 spin_lock(&tp->tx_lock);
9071 tg3_disable_ints(tp);
9072 spin_unlock(&tp->tx_lock);
9073 spin_unlock_irq(&tp->lock);
9075 netif_device_detach(dev);
9077 spin_lock_irq(&tp->lock);
9078 spin_lock(&tp->tx_lock);
9080 spin_unlock(&tp->tx_lock);
9081 spin_unlock_irq(&tp->lock);
9083 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
9085 spin_lock_irq(&tp->lock);
9086 spin_lock(&tp->tx_lock);
9090 tp->timer.expires = jiffies + tp->timer_offset;
9091 add_timer(&tp->timer);
9093 netif_device_attach(dev);
9094 tg3_netif_start(tp);
9096 spin_unlock(&tp->tx_lock);
9097 spin_unlock_irq(&tp->lock);
9103 static int tg3_resume(struct pci_dev *pdev)
9105 struct net_device *dev = pci_get_drvdata(pdev);
9106 struct tg3 *tp = netdev_priv(dev);
9109 if (!netif_running(dev))
9112 pci_restore_state(tp->pdev);
9114 err = tg3_set_power_state(tp, 0);
9118 netif_device_attach(dev);
9120 spin_lock_irq(&tp->lock);
9121 spin_lock(&tp->tx_lock);
9125 tp->timer.expires = jiffies + tp->timer_offset;
9126 add_timer(&tp->timer);
9128 tg3_enable_ints(tp);
9130 tg3_netif_start(tp);
9132 spin_unlock(&tp->tx_lock);
9133 spin_unlock_irq(&tp->lock);
9138 static struct pci_driver tg3_driver = {
9139 .name = DRV_MODULE_NAME,
9140 .id_table = tg3_pci_tbl,
9141 .probe = tg3_init_one,
9142 .remove = __devexit_p(tg3_remove_one),
9143 .suspend = tg3_suspend,
9144 .resume = tg3_resume
9147 static int __init tg3_init(void)
9149 return pci_module_init(&tg3_driver);
9152 static void __exit tg3_cleanup(void)
9154 pci_unregister_driver(&tg3_driver);
9157 module_init(tg3_init);
9158 module_exit(tg3_cleanup);