2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
4 * Based on skelton.c by Donald Becker.
6 * This driver is a replacement of older and less maintained version.
7 * This is a header of the older version:
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: MontaVista Software, Inc.
11 * ahennessy@mvista.com
12 * Copyright (C) 2000-2001 Toshiba Corporation
13 * static const char *version =
14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
21 * (C) Copyright TOSHIBA CORPORATION 2004-2005
22 * All Rights Reserved.
26 #define DRV_VERSION "1.37-NAPI"
28 #define DRV_VERSION "1.37"
30 static const char *version = "tc35815.c:v" DRV_VERSION "\n";
31 #define MODNAME "tc35815"
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/types.h>
36 #include <linux/fcntl.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/string.h>
42 #include <linux/spinlock.h>
43 #include <linux/errno.h>
44 #include <linux/init.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/delay.h>
49 #include <linux/pci.h>
50 #include <linux/phy.h>
51 #include <linux/workqueue.h>
52 #include <linux/platform_device.h>
54 #include <asm/byteorder.h>
56 /* First, a few definitions that the brave might change. */
58 #define GATHER_TXINT /* On-Demand Tx Interrupt */
59 #define WORKAROUND_LOSTCAR
60 #define WORKAROUND_100HALF_PROMISC
61 /* #define TC35815_USE_PACKEDBUFFER */
63 enum tc35815_chiptype {
69 /* indexed by tc35815_chiptype, above */
72 } chip_info[] __devinitdata = {
73 { "TOSHIBA TC35815CF 10/100BaseTX" },
74 { "TOSHIBA TC35815 with Wake on LAN" },
75 { "TOSHIBA TC35815/TX4939" },
78 static const struct pci_device_id tc35815_pci_tbl[] = {
79 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
80 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
81 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
84 MODULE_DEVICE_TABLE (pci, tc35815_pci_tbl);
86 /* see MODULE_PARM_DESC */
87 static struct tc35815_options {
96 __u32 DMA_Ctl; /* 0x00 */
104 __u32 FDA_Lim; /* 0x20 */
111 __u32 MAC_Ctl; /* 0x40 */
119 __u32 CAM_Adr; /* 0x60 */
132 /* DMA_Ctl bit asign ------------------------------------------------------- */
133 #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
134 #define DMA_RxAlign_1 0x00400000
135 #define DMA_RxAlign_2 0x00800000
136 #define DMA_RxAlign_3 0x00c00000
137 #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
138 #define DMA_IntMask 0x00040000 /* 1:Interupt mask */
139 #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
140 #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
141 #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
142 #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
143 #define DMA_TestMode 0x00002000 /* 1:Test Mode */
144 #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
145 #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
147 /* RxFragSize bit asign ---------------------------------------------------- */
148 #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
149 #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
151 /* MAC_Ctl bit asign ------------------------------------------------------- */
152 #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
153 #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
154 #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
155 #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
156 #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
157 #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
158 #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
159 #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
160 #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
161 #define MAC_Reset 0x00000004 /* 1:Software Reset */
162 #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
163 #define MAC_HaltReq 0x00000001 /* 1:Halt request */
165 /* PROM_Ctl bit asign ------------------------------------------------------ */
166 #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
167 #define PROM_Read 0x00004000 /*10:Read operation */
168 #define PROM_Write 0x00002000 /*01:Write operation */
169 #define PROM_Erase 0x00006000 /*11:Erase operation */
170 /*00:Enable or Disable Writting, */
171 /* as specified in PROM_Addr. */
172 #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
175 /* CAM_Ctl bit asign ------------------------------------------------------- */
176 #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
177 #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
179 #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
180 #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
181 #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
183 /* CAM_Ena bit asign ------------------------------------------------------- */
184 #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
185 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
186 #define CAM_Ena_Bit(index) (1<<(index))
187 #define CAM_ENTRY_DESTINATION 0
188 #define CAM_ENTRY_SOURCE 1
189 #define CAM_ENTRY_MACCTL 20
191 /* Tx_Ctl bit asign -------------------------------------------------------- */
192 #define Tx_En 0x00000001 /* 1:Transmit enable */
193 #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
194 #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
195 #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
196 #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
197 #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
198 #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
199 #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
200 #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
201 #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
202 #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
203 #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
205 /* Tx_Stat bit asign ------------------------------------------------------- */
206 #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
207 #define Tx_ExColl 0x00000010 /* Excessive Collision */
208 #define Tx_TXDefer 0x00000020 /* Transmit Defered */
209 #define Tx_Paused 0x00000040 /* Transmit Paused */
210 #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
211 #define Tx_Under 0x00000100 /* Underrun */
212 #define Tx_Defer 0x00000200 /* Deferral */
213 #define Tx_NCarr 0x00000400 /* No Carrier */
214 #define Tx_10Stat 0x00000800 /* 10Mbps Status */
215 #define Tx_LateColl 0x00001000 /* Late Collision */
216 #define Tx_TxPar 0x00002000 /* Tx Parity Error */
217 #define Tx_Comp 0x00004000 /* Completion */
218 #define Tx_Halted 0x00008000 /* Tx Halted */
219 #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
221 /* Rx_Ctl bit asign -------------------------------------------------------- */
222 #define Rx_EnGood 0x00004000 /* 1:Enable Good */
223 #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
224 #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
225 #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
226 #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
227 #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
228 #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
229 #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
230 #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
231 #define Rx_LongEn 0x00000004 /* 1:Long Enable */
232 #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
233 #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
235 /* Rx_Stat bit asign ------------------------------------------------------- */
236 #define Rx_Halted 0x00008000 /* Rx Halted */
237 #define Rx_Good 0x00004000 /* Rx Good */
238 #define Rx_RxPar 0x00002000 /* Rx Parity Error */
239 /* 0x00001000 not use */
240 #define Rx_LongErr 0x00000800 /* Rx Long Error */
241 #define Rx_Over 0x00000400 /* Rx Overflow */
242 #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
243 #define Rx_Align 0x00000100 /* Rx Alignment Error */
244 #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
245 #define Rx_IntRx 0x00000040 /* Rx Interrupt */
246 #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
248 #define Rx_Stat_Mask 0x0000EFC0 /* Rx All Status Mask */
250 /* Int_En bit asign -------------------------------------------------------- */
251 #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
252 #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Control Complete Enable */
253 #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
254 #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
255 #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
256 #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
257 #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
258 #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
259 #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
260 #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
261 #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
262 #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
263 /* Exhausted Enable */
265 /* Int_Src bit asign ------------------------------------------------------- */
266 #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
267 #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
268 #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
269 #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
270 #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
271 #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
272 #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
273 #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
274 #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
275 #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
276 #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
277 #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
278 #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
279 #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
280 #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
282 /* MD_CA bit asign --------------------------------------------------------- */
283 #define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
284 #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
285 #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
292 /* Frame descripter */
294 volatile __u32 FDNext;
295 volatile __u32 FDSystem;
296 volatile __u32 FDStat;
297 volatile __u32 FDCtl;
300 /* Buffer descripter */
302 volatile __u32 BuffData;
303 volatile __u32 BDCtl;
308 /* Frame Descripter bit asign ---------------------------------------------- */
309 #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
310 #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
311 #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
312 #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
313 #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
314 #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
315 #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
316 #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
317 #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
318 #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
319 #define FD_BDCnt_SHIFT 16
321 /* Buffer Descripter bit asign --------------------------------------------- */
322 #define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
323 #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
324 #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
325 #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
326 #define BD_RxBDID_SHIFT 16
327 #define BD_RxBDSeqN_SHIFT 24
330 /* Some useful constants. */
331 #undef NO_CHECK_CARRIER /* Does not check No-Carrier with TP */
333 #ifdef NO_CHECK_CARRIER
334 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
335 Tx_EnExColl | Tx_EnExDefer | Tx_EnUnder | \
336 Tx_En) /* maybe 0x7b01 */
338 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
339 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
340 Tx_En) /* maybe 0x7b01 */
342 #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
343 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
344 #define INT_EN_CMD (Int_NRAbtEn | \
345 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
346 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
348 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
349 #define DMA_CTL_CMD DMA_BURST_SIZE
350 #define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
352 /* Tuning parameters */
353 #define DMA_BURST_SIZE 32
354 #define TX_THRESHOLD 1024
355 #define TX_THRESHOLD_MAX 1536 /* used threshold with packet max byte for low pci transfer ability.*/
356 #define TX_THRESHOLD_KEEP_LIMIT 10 /* setting threshold max value when overrun error occured this count. */
358 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
359 #ifdef TC35815_USE_PACKEDBUFFER
360 #define FD_PAGE_NUM 2
361 #define RX_BUF_NUM 8 /* >= 2 */
362 #define RX_FD_NUM 250 /* >= 32 */
363 #define TX_FD_NUM 128
364 #define RX_BUF_SIZE PAGE_SIZE
365 #else /* TC35815_USE_PACKEDBUFFER */
366 #define FD_PAGE_NUM 4
367 #define RX_BUF_NUM 128 /* < 256 */
368 #define RX_FD_NUM 256 /* >= 32 */
369 #define TX_FD_NUM 128
370 #if RX_CTL_CMD & Rx_LongEn
371 #define RX_BUF_SIZE PAGE_SIZE
372 #elif RX_CTL_CMD & Rx_StripCRC
373 #define RX_BUF_SIZE ALIGN(ETH_FRAME_LEN + 4 + 2, 32) /* +2: reserve */
375 #define RX_BUF_SIZE ALIGN(ETH_FRAME_LEN + 2, 32) /* +2: reserve */
377 #endif /* TC35815_USE_PACKEDBUFFER */
378 #define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
379 #define NAPI_WEIGHT 16
389 struct BDesc bd[0]; /* variable length */
394 struct BDesc bd[RX_BUF_NUM];
398 #define tc_readl(addr) ioread32(addr)
399 #define tc_writel(d, addr) iowrite32(d, addr)
401 #define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
403 /* Information that need to be kept for each controller. */
404 struct tc35815_local {
405 struct pci_dev *pci_dev;
407 struct net_device *dev;
408 struct napi_struct napi;
418 /* Tx control lock. This protects the transmit buffer ring
419 * state along with the "tx full" state of the driver. This
420 * means all netif_queue flow control actions are protected
421 * by this lock as well.
425 struct mii_bus mii_bus;
426 struct phy_device *phy_dev;
430 struct work_struct restart_work;
433 * Transmitting: Batch Mode.
435 * Receiving: Packing Mode. (TC35815_USE_PACKEDBUFFER)
436 * 1 circular FD for Free Buffer List.
437 * RX_BUF_NUM BD in Free Buffer FD.
438 * One Free Buffer BD has PAGE_SIZE data buffer.
439 * Or Non-Packing Mode.
440 * 1 circular FD for Free Buffer List.
441 * RX_BUF_NUM BD in Free Buffer FD.
442 * One Free Buffer BD has ETH_FRAME_LEN data buffer.
444 void * fd_buf; /* for TxFD, RxFD, FrFD */
445 dma_addr_t fd_buf_dma;
446 struct TxFD *tfd_base;
447 unsigned int tfd_start;
448 unsigned int tfd_end;
449 struct RxFD *rfd_base;
450 struct RxFD *rfd_limit;
451 struct RxFD *rfd_cur;
452 struct FrFD *fbl_ptr;
453 #ifdef TC35815_USE_PACKEDBUFFER
454 unsigned char fbl_curid;
455 void * data_buf[RX_BUF_NUM]; /* packing */
456 dma_addr_t data_buf_dma[RX_BUF_NUM];
460 } tx_skbs[TX_FD_NUM];
462 unsigned int fbl_count;
466 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
469 enum tc35815_chiptype chiptype;
472 static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
474 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
477 static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
479 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
482 #ifdef TC35815_USE_PACKEDBUFFER
483 static inline void *rxbuf_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
486 for (i = 0; i < RX_BUF_NUM; i++) {
487 if (bus >= lp->data_buf_dma[i] &&
488 bus < lp->data_buf_dma[i] + PAGE_SIZE)
489 return (void *)((u8 *)lp->data_buf[i] +
490 (bus - lp->data_buf_dma[i]));
495 #define TC35815_DMA_SYNC_ONDEMAND
496 static void* alloc_rxbuf_page(struct pci_dev *hwdev, dma_addr_t *dma_handle)
498 #ifdef TC35815_DMA_SYNC_ONDEMAND
500 /* pci_map + pci_dma_sync will be more effective than
501 * pci_alloc_consistent on some archs. */
502 if ((buf = (void *)__get_free_page(GFP_ATOMIC)) == NULL)
504 *dma_handle = pci_map_single(hwdev, buf, PAGE_SIZE,
506 if (pci_dma_mapping_error(*dma_handle)) {
507 free_page((unsigned long)buf);
512 return pci_alloc_consistent(hwdev, PAGE_SIZE, dma_handle);
516 static void free_rxbuf_page(struct pci_dev *hwdev, void *buf, dma_addr_t dma_handle)
518 #ifdef TC35815_DMA_SYNC_ONDEMAND
519 pci_unmap_single(hwdev, dma_handle, PAGE_SIZE, PCI_DMA_FROMDEVICE);
520 free_page((unsigned long)buf);
522 pci_free_consistent(hwdev, PAGE_SIZE, buf, dma_handle);
525 #else /* TC35815_USE_PACKEDBUFFER */
526 static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
527 struct pci_dev *hwdev,
528 dma_addr_t *dma_handle)
531 skb = dev_alloc_skb(RX_BUF_SIZE);
534 *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
536 if (pci_dma_mapping_error(*dma_handle)) {
537 dev_kfree_skb_any(skb);
540 skb_reserve(skb, 2); /* make IP header 4byte aligned */
544 static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
546 pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
548 dev_kfree_skb_any(skb);
550 #endif /* TC35815_USE_PACKEDBUFFER */
552 /* Index to functions, as function prototypes. */
554 static int tc35815_open(struct net_device *dev);
555 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
556 static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
558 static int tc35815_rx(struct net_device *dev, int limit);
559 static int tc35815_poll(struct napi_struct *napi, int budget);
561 static void tc35815_rx(struct net_device *dev);
563 static void tc35815_txdone(struct net_device *dev);
564 static int tc35815_close(struct net_device *dev);
565 static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
566 static void tc35815_set_multicast_list(struct net_device *dev);
567 static void tc35815_tx_timeout(struct net_device *dev);
568 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
569 #ifdef CONFIG_NET_POLL_CONTROLLER
570 static void tc35815_poll_controller(struct net_device *dev);
572 static const struct ethtool_ops tc35815_ethtool_ops;
574 /* Example routines you must write ;->. */
575 static void tc35815_chip_reset(struct net_device *dev);
576 static void tc35815_chip_init(struct net_device *dev);
579 static void panic_queues(struct net_device *dev);
582 static void tc35815_restart_work(struct work_struct *work);
584 static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
586 struct net_device *dev = bus->priv;
587 struct tc35815_regs __iomem *tr =
588 (struct tc35815_regs __iomem *)dev->base_addr;
589 unsigned long timeout = jiffies + 10;
591 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
592 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
593 if (time_after(jiffies, timeout))
597 return tc_readl(&tr->MD_Data) & 0xffff;
600 static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
602 struct net_device *dev = bus->priv;
603 struct tc35815_regs __iomem *tr =
604 (struct tc35815_regs __iomem *)dev->base_addr;
605 unsigned long timeout = jiffies + 10;
607 tc_writel(val, &tr->MD_Data);
608 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
610 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
611 if (time_after(jiffies, timeout))
618 static void tc_handle_link_change(struct net_device *dev)
620 struct tc35815_local *lp = netdev_priv(dev);
621 struct phy_device *phydev = lp->phy_dev;
623 int status_change = 0;
625 spin_lock_irqsave(&lp->lock, flags);
627 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
628 struct tc35815_regs __iomem *tr =
629 (struct tc35815_regs __iomem *)dev->base_addr;
632 reg = tc_readl(&tr->MAC_Ctl);
634 tc_writel(reg, &tr->MAC_Ctl);
635 if (phydev->duplex == DUPLEX_FULL)
639 tc_writel(reg, &tr->MAC_Ctl);
641 tc_writel(reg, &tr->MAC_Ctl);
644 * TX4939 PCFG.SPEEDn bit will be changed on
645 * NETDEV_CHANGE event.
648 #if !defined(NO_CHECK_CARRIER) && defined(WORKAROUND_LOSTCAR)
650 * WORKAROUND: enable LostCrS only if half duplex
652 * (TX4939 does not have EnLCarr)
654 if (phydev->duplex == DUPLEX_HALF &&
655 lp->chiptype != TC35815_TX4939)
656 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
660 lp->speed = phydev->speed;
661 lp->duplex = phydev->duplex;
665 if (phydev->link != lp->link) {
667 #ifdef WORKAROUND_100HALF_PROMISC
668 /* delayed promiscuous enabling */
669 if (dev->flags & IFF_PROMISC)
670 tc35815_set_multicast_list(dev);
677 lp->link = phydev->link;
681 spin_unlock_irqrestore(&lp->lock, flags);
683 if (status_change && netif_msg_link(lp)) {
684 phy_print_status(phydev);
687 "%s: MII BMCR %04x BMSR %04x LPA %04x\n",
689 phy_read(phydev, MII_BMCR),
690 phy_read(phydev, MII_BMSR),
691 phy_read(phydev, MII_LPA));
696 static int tc_mii_probe(struct net_device *dev)
698 struct tc35815_local *lp = netdev_priv(dev);
699 struct phy_device *phydev = NULL;
703 /* find the first phy */
704 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
705 if (lp->mii_bus.phy_map[phy_addr]) {
707 printk(KERN_ERR "%s: multiple PHYs found\n",
711 phydev = lp->mii_bus.phy_map[phy_addr];
717 printk(KERN_ERR "%s: no PHY found\n", dev->name);
721 /* attach the mac to the phy */
722 phydev = phy_connect(dev, phydev->dev.bus_id,
723 &tc_handle_link_change, 0,
724 lp->chiptype == TC35815_TX4939 ?
725 PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
726 if (IS_ERR(phydev)) {
727 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
728 return PTR_ERR(phydev);
730 printk(KERN_INFO "%s: attached PHY driver [%s] "
731 "(mii_bus:phy_addr=%s, id=%x)\n",
732 dev->name, phydev->drv->name, phydev->dev.bus_id,
735 /* mask with MAC supported features */
736 phydev->supported &= PHY_BASIC_FEATURES;
738 if (options.speed == 10)
739 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
740 else if (options.speed == 100)
741 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
742 if (options.duplex == 1)
743 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
744 else if (options.duplex == 2)
745 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
746 phydev->supported &= ~dropmask;
747 phydev->advertising = phydev->supported;
752 lp->phy_dev = phydev;
757 static int tc_mii_init(struct net_device *dev)
759 struct tc35815_local *lp = netdev_priv(dev);
763 lp->mii_bus.name = "tc35815_mii_bus";
764 lp->mii_bus.read = tc_mdio_read;
765 lp->mii_bus.write = tc_mdio_write;
766 lp->mii_bus.id = (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn;
767 lp->mii_bus.priv = dev;
768 lp->mii_bus.dev = &lp->pci_dev->dev;
769 lp->mii_bus.irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
770 if (!lp->mii_bus.irq) {
775 for (i = 0; i < PHY_MAX_ADDR; i++)
776 lp->mii_bus.irq[i] = PHY_POLL;
778 err = mdiobus_register(&lp->mii_bus);
780 goto err_out_free_mdio_irq;
781 err = tc_mii_probe(dev);
783 goto err_out_unregister_bus;
786 err_out_unregister_bus:
787 mdiobus_unregister(&lp->mii_bus);
788 err_out_free_mdio_irq:
789 kfree(lp->mii_bus.irq);
794 #ifdef CONFIG_CPU_TX49XX
796 * Find a platform_device providing a MAC address. The platform code
797 * should provide a "tc35815-mac" device with a MAC address in its
800 static int __devinit tc35815_mac_match(struct device *dev, void *data)
802 struct platform_device *plat_dev = to_platform_device(dev);
803 struct pci_dev *pci_dev = data;
804 unsigned int id = pci_dev->irq;
805 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
808 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
810 struct tc35815_local *lp = netdev_priv(dev);
811 struct device *pd = bus_find_device(&platform_bus_type, NULL,
812 lp->pci_dev, tc35815_mac_match);
814 if (pd->platform_data)
815 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
817 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
822 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
828 static int __devinit tc35815_init_dev_addr (struct net_device *dev)
830 struct tc35815_regs __iomem *tr =
831 (struct tc35815_regs __iomem *)dev->base_addr;
834 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
836 for (i = 0; i < 6; i += 2) {
838 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
839 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
841 data = tc_readl(&tr->PROM_Data);
842 dev->dev_addr[i] = data & 0xff;
843 dev->dev_addr[i+1] = data >> 8;
845 if (!is_valid_ether_addr(dev->dev_addr))
846 return tc35815_read_plat_dev_addr(dev);
850 static int __devinit tc35815_init_one (struct pci_dev *pdev,
851 const struct pci_device_id *ent)
853 void __iomem *ioaddr = NULL;
854 struct net_device *dev;
855 struct tc35815_local *lp;
857 DECLARE_MAC_BUF(mac);
859 static int printed_version;
860 if (!printed_version++) {
862 dev_printk(KERN_DEBUG, &pdev->dev,
863 "speed:%d duplex:%d\n",
864 options.speed, options.duplex);
868 dev_warn(&pdev->dev, "no IRQ assigned.\n");
872 /* dev zeroed in alloc_etherdev */
873 dev = alloc_etherdev (sizeof (*lp));
875 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
878 SET_NETDEV_DEV(dev, &pdev->dev);
879 lp = netdev_priv(dev);
882 /* enable device (incl. PCI PM wakeup), and bus-mastering */
883 rc = pcim_enable_device(pdev);
886 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
889 pci_set_master(pdev);
890 ioaddr = pcim_iomap_table(pdev)[1];
892 /* Initialize the device structure. */
893 dev->open = tc35815_open;
894 dev->hard_start_xmit = tc35815_send_packet;
895 dev->stop = tc35815_close;
896 dev->get_stats = tc35815_get_stats;
897 dev->set_multicast_list = tc35815_set_multicast_list;
898 dev->do_ioctl = tc35815_ioctl;
899 dev->ethtool_ops = &tc35815_ethtool_ops;
900 dev->tx_timeout = tc35815_tx_timeout;
901 dev->watchdog_timeo = TC35815_TX_TIMEOUT;
903 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
905 #ifdef CONFIG_NET_POLL_CONTROLLER
906 dev->poll_controller = tc35815_poll_controller;
909 dev->irq = pdev->irq;
910 dev->base_addr = (unsigned long) ioaddr;
912 INIT_WORK(&lp->restart_work, tc35815_restart_work);
913 spin_lock_init(&lp->lock);
915 lp->chiptype = ent->driver_data;
917 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
918 pci_set_drvdata(pdev, dev);
920 /* Soft reset the chip. */
921 tc35815_chip_reset(dev);
923 /* Retrieve the ethernet address. */
924 if (tc35815_init_dev_addr(dev)) {
925 dev_warn(&pdev->dev, "not valid ether addr\n");
926 random_ether_addr(dev->dev_addr);
929 rc = register_netdev (dev);
933 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
934 printk(KERN_INFO "%s: %s at 0x%lx, %s, IRQ %d\n",
936 chip_info[ent->driver_data].name,
938 print_mac(mac, dev->dev_addr),
941 rc = tc_mii_init(dev);
943 goto err_out_unregister;
948 unregister_netdev(dev);
955 static void __devexit tc35815_remove_one (struct pci_dev *pdev)
957 struct net_device *dev = pci_get_drvdata (pdev);
958 struct tc35815_local *lp = netdev_priv(dev);
960 phy_disconnect(lp->phy_dev);
961 mdiobus_unregister(&lp->mii_bus);
962 kfree(lp->mii_bus.irq);
963 unregister_netdev (dev);
966 pci_set_drvdata (pdev, NULL);
970 tc35815_init_queues(struct net_device *dev)
972 struct tc35815_local *lp = netdev_priv(dev);
974 unsigned long fd_addr;
977 BUG_ON(sizeof(struct FDesc) +
978 sizeof(struct BDesc) * RX_BUF_NUM +
979 sizeof(struct FDesc) * RX_FD_NUM +
980 sizeof(struct TxFD) * TX_FD_NUM >
981 PAGE_SIZE * FD_PAGE_NUM);
983 if ((lp->fd_buf = pci_alloc_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM, &lp->fd_buf_dma)) == 0)
985 for (i = 0; i < RX_BUF_NUM; i++) {
986 #ifdef TC35815_USE_PACKEDBUFFER
987 if ((lp->data_buf[i] = alloc_rxbuf_page(lp->pci_dev, &lp->data_buf_dma[i])) == NULL) {
989 free_rxbuf_page(lp->pci_dev,
991 lp->data_buf_dma[i]);
992 lp->data_buf[i] = NULL;
994 pci_free_consistent(lp->pci_dev,
995 PAGE_SIZE * FD_PAGE_NUM,
1002 lp->rx_skbs[i].skb =
1003 alloc_rxbuf_skb(dev, lp->pci_dev,
1004 &lp->rx_skbs[i].skb_dma);
1005 if (!lp->rx_skbs[i].skb) {
1007 free_rxbuf_skb(lp->pci_dev,
1009 lp->rx_skbs[i].skb_dma);
1010 lp->rx_skbs[i].skb = NULL;
1012 pci_free_consistent(lp->pci_dev,
1013 PAGE_SIZE * FD_PAGE_NUM,
1021 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
1022 dev->name, lp->fd_buf);
1023 #ifdef TC35815_USE_PACKEDBUFFER
1025 for (i = 0; i < RX_BUF_NUM; i++)
1026 printk(" %p", lp->data_buf[i]);
1030 for (i = 0; i < FD_PAGE_NUM; i++) {
1031 clear_page((void *)((unsigned long)lp->fd_buf + i * PAGE_SIZE));
1034 fd_addr = (unsigned long)lp->fd_buf;
1036 /* Free Descriptors (for Receive) */
1037 lp->rfd_base = (struct RxFD *)fd_addr;
1038 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
1039 for (i = 0; i < RX_FD_NUM; i++) {
1040 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
1042 lp->rfd_cur = lp->rfd_base;
1043 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
1045 /* Transmit Descriptors */
1046 lp->tfd_base = (struct TxFD *)fd_addr;
1047 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
1048 for (i = 0; i < TX_FD_NUM; i++) {
1049 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
1050 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1051 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
1053 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
1057 /* Buffer List (for Receive) */
1058 lp->fbl_ptr = (struct FrFD *)fd_addr;
1059 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
1060 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
1061 #ifndef TC35815_USE_PACKEDBUFFER
1063 * move all allocated skbs to head of rx_skbs[] array.
1064 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
1065 * tc35815_rx() had failed.
1068 for (i = 0; i < RX_BUF_NUM; i++) {
1069 if (lp->rx_skbs[i].skb) {
1070 if (i != lp->fbl_count) {
1071 lp->rx_skbs[lp->fbl_count].skb =
1073 lp->rx_skbs[lp->fbl_count].skb_dma =
1074 lp->rx_skbs[i].skb_dma;
1080 for (i = 0; i < RX_BUF_NUM; i++) {
1081 #ifdef TC35815_USE_PACKEDBUFFER
1082 lp->fbl_ptr->bd[i].BuffData = cpu_to_le32(lp->data_buf_dma[i]);
1084 if (i >= lp->fbl_count) {
1085 lp->fbl_ptr->bd[i].BuffData = 0;
1086 lp->fbl_ptr->bd[i].BDCtl = 0;
1089 lp->fbl_ptr->bd[i].BuffData =
1090 cpu_to_le32(lp->rx_skbs[i].skb_dma);
1092 /* BDID is index of FrFD.bd[] */
1093 lp->fbl_ptr->bd[i].BDCtl =
1094 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
1097 #ifdef TC35815_USE_PACKEDBUFFER
1101 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
1102 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
1107 tc35815_clear_queues(struct net_device *dev)
1109 struct tc35815_local *lp = netdev_priv(dev);
1112 for (i = 0; i < TX_FD_NUM; i++) {
1113 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1114 struct sk_buff *skb =
1115 fdsystem != 0xffffffff ?
1116 lp->tx_skbs[fdsystem].skb : NULL;
1118 if (lp->tx_skbs[i].skb != skb) {
1119 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1123 BUG_ON(lp->tx_skbs[i].skb != skb);
1126 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1127 lp->tx_skbs[i].skb = NULL;
1128 lp->tx_skbs[i].skb_dma = 0;
1129 dev_kfree_skb_any(skb);
1131 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1134 tc35815_init_queues(dev);
1138 tc35815_free_queues(struct net_device *dev)
1140 struct tc35815_local *lp = netdev_priv(dev);
1144 for (i = 0; i < TX_FD_NUM; i++) {
1145 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1146 struct sk_buff *skb =
1147 fdsystem != 0xffffffff ?
1148 lp->tx_skbs[fdsystem].skb : NULL;
1150 if (lp->tx_skbs[i].skb != skb) {
1151 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1155 BUG_ON(lp->tx_skbs[i].skb != skb);
1159 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1160 lp->tx_skbs[i].skb = NULL;
1161 lp->tx_skbs[i].skb_dma = 0;
1163 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1167 lp->rfd_base = NULL;
1168 lp->rfd_limit = NULL;
1172 for (i = 0; i < RX_BUF_NUM; i++) {
1173 #ifdef TC35815_USE_PACKEDBUFFER
1174 if (lp->data_buf[i]) {
1175 free_rxbuf_page(lp->pci_dev,
1176 lp->data_buf[i], lp->data_buf_dma[i]);
1177 lp->data_buf[i] = NULL;
1180 if (lp->rx_skbs[i].skb) {
1181 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1182 lp->rx_skbs[i].skb_dma);
1183 lp->rx_skbs[i].skb = NULL;
1188 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1189 lp->fd_buf, lp->fd_buf_dma);
1195 dump_txfd(struct TxFD *fd)
1197 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1198 le32_to_cpu(fd->fd.FDNext),
1199 le32_to_cpu(fd->fd.FDSystem),
1200 le32_to_cpu(fd->fd.FDStat),
1201 le32_to_cpu(fd->fd.FDCtl));
1203 printk(" %08x %08x",
1204 le32_to_cpu(fd->bd.BuffData),
1205 le32_to_cpu(fd->bd.BDCtl));
1210 dump_rxfd(struct RxFD *fd)
1212 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1215 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1216 le32_to_cpu(fd->fd.FDNext),
1217 le32_to_cpu(fd->fd.FDSystem),
1218 le32_to_cpu(fd->fd.FDStat),
1219 le32_to_cpu(fd->fd.FDCtl));
1220 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1223 for (i = 0; i < bd_count; i++)
1224 printk(" %08x %08x",
1225 le32_to_cpu(fd->bd[i].BuffData),
1226 le32_to_cpu(fd->bd[i].BDCtl));
1231 #if defined(DEBUG) || defined(TC35815_USE_PACKEDBUFFER)
1233 dump_frfd(struct FrFD *fd)
1236 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1237 le32_to_cpu(fd->fd.FDNext),
1238 le32_to_cpu(fd->fd.FDSystem),
1239 le32_to_cpu(fd->fd.FDStat),
1240 le32_to_cpu(fd->fd.FDCtl));
1242 for (i = 0; i < RX_BUF_NUM; i++)
1243 printk(" %08x %08x",
1244 le32_to_cpu(fd->bd[i].BuffData),
1245 le32_to_cpu(fd->bd[i].BDCtl));
1252 panic_queues(struct net_device *dev)
1254 struct tc35815_local *lp = netdev_priv(dev);
1257 printk("TxFD base %p, start %u, end %u\n",
1258 lp->tfd_base, lp->tfd_start, lp->tfd_end);
1259 printk("RxFD base %p limit %p cur %p\n",
1260 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1261 printk("FrFD %p\n", lp->fbl_ptr);
1262 for (i = 0; i < TX_FD_NUM; i++)
1263 dump_txfd(&lp->tfd_base[i]);
1264 for (i = 0; i < RX_FD_NUM; i++) {
1265 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1266 i += (bd_count + 1) / 2; /* skip BDs */
1268 dump_frfd(lp->fbl_ptr);
1269 panic("%s: Illegal queue state.", dev->name);
1273 static void print_eth(const u8 *add)
1275 DECLARE_MAC_BUF(mac);
1277 printk(KERN_DEBUG "print_eth(%p)\n", add);
1278 printk(KERN_DEBUG " %s =>", print_mac(mac, add + 6));
1279 printk(KERN_CONT " %s : %02x%02x\n",
1280 print_mac(mac, add), add[12], add[13]);
1283 static int tc35815_tx_full(struct net_device *dev)
1285 struct tc35815_local *lp = netdev_priv(dev);
1286 return ((lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end);
1289 static void tc35815_restart(struct net_device *dev)
1291 struct tc35815_local *lp = netdev_priv(dev);
1296 phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET);
1299 if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET))
1304 printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name);
1307 spin_lock_irq(&lp->lock);
1308 tc35815_chip_reset(dev);
1309 tc35815_clear_queues(dev);
1310 tc35815_chip_init(dev);
1311 /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1312 tc35815_set_multicast_list(dev);
1313 spin_unlock_irq(&lp->lock);
1315 netif_wake_queue(dev);
1318 static void tc35815_restart_work(struct work_struct *work)
1320 struct tc35815_local *lp =
1321 container_of(work, struct tc35815_local, restart_work);
1322 struct net_device *dev = lp->dev;
1324 tc35815_restart(dev);
1327 static void tc35815_schedule_restart(struct net_device *dev)
1329 struct tc35815_local *lp = netdev_priv(dev);
1330 struct tc35815_regs __iomem *tr =
1331 (struct tc35815_regs __iomem *)dev->base_addr;
1333 /* disable interrupts */
1334 tc_writel(0, &tr->Int_En);
1335 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1336 schedule_work(&lp->restart_work);
1339 static void tc35815_tx_timeout(struct net_device *dev)
1341 struct tc35815_regs __iomem *tr =
1342 (struct tc35815_regs __iomem *)dev->base_addr;
1344 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1345 dev->name, tc_readl(&tr->Tx_Stat));
1347 /* Try to restart the adaptor. */
1348 tc35815_schedule_restart(dev);
1349 dev->stats.tx_errors++;
1353 * Open/initialize the controller. This is called (in the current kernel)
1354 * sometime after booting when the 'ifconfig' program is run.
1356 * This routine should set everything up anew at each open, even
1357 * registers that "should" only need to be set once at boot, so that
1358 * there is non-reboot way to recover if something goes wrong.
1361 tc35815_open(struct net_device *dev)
1363 struct tc35815_local *lp = netdev_priv(dev);
1366 * This is used if the interrupt line can turned off (shared).
1367 * See 3c503.c for an example of selecting the IRQ at config-time.
1369 if (request_irq(dev->irq, &tc35815_interrupt, IRQF_SHARED, dev->name, dev)) {
1373 tc35815_chip_reset(dev);
1375 if (tc35815_init_queues(dev) != 0) {
1376 free_irq(dev->irq, dev);
1381 napi_enable(&lp->napi);
1384 /* Reset the hardware here. Don't forget to set the station address. */
1385 spin_lock_irq(&lp->lock);
1386 tc35815_chip_init(dev);
1387 spin_unlock_irq(&lp->lock);
1389 /* schedule a link state check */
1390 phy_start(lp->phy_dev);
1392 /* We are now ready to accept transmit requeusts from
1393 * the queueing layer of the networking.
1395 netif_start_queue(dev);
1400 /* This will only be invoked if your driver is _not_ in XOFF state.
1401 * What this means is that you need not check it, and that this
1402 * invariant will hold if you make sure that the netif_*_queue()
1403 * calls are done at the proper times.
1405 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1407 struct tc35815_local *lp = netdev_priv(dev);
1409 unsigned long flags;
1411 /* If some error occurs while trying to transmit this
1412 * packet, you should return '1' from this function.
1413 * In such a case you _may not_ do anything to the
1414 * SKB, it is still owned by the network queueing
1415 * layer when an error is returned. This means you
1416 * may not modify any SKB fields, you may not free
1420 /* This is the most common case for modern hardware.
1421 * The spinlock protects this code from the TX complete
1422 * hardware interrupt handler. Queue flow control is
1423 * thus managed under this lock as well.
1425 spin_lock_irqsave(&lp->lock, flags);
1427 /* failsafe... (handle txdone now if half of FDs are used) */
1428 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1430 tc35815_txdone(dev);
1432 if (netif_msg_pktdata(lp))
1433 print_eth(skb->data);
1435 if (lp->tx_skbs[lp->tfd_start].skb) {
1436 printk("%s: tx_skbs conflict.\n", dev->name);
1440 BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1442 lp->tx_skbs[lp->tfd_start].skb = skb;
1443 lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1446 txfd = &lp->tfd_base[lp->tfd_start];
1447 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1448 txfd->bd.BDCtl = cpu_to_le32(skb->len);
1449 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1450 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1452 if (lp->tfd_start == lp->tfd_end) {
1453 struct tc35815_regs __iomem *tr =
1454 (struct tc35815_regs __iomem *)dev->base_addr;
1455 /* Start DMA Transmitter. */
1456 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1458 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1460 if (netif_msg_tx_queued(lp)) {
1461 printk("%s: starting TxFD.\n", dev->name);
1464 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1466 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1467 if (netif_msg_tx_queued(lp)) {
1468 printk("%s: queueing TxFD.\n", dev->name);
1472 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1474 dev->trans_start = jiffies;
1476 /* If we just used up the very last entry in the
1477 * TX ring on this device, tell the queueing
1478 * layer to send no more.
1480 if (tc35815_tx_full(dev)) {
1481 if (netif_msg_tx_queued(lp))
1482 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1483 netif_stop_queue(dev);
1486 /* When the TX completion hw interrupt arrives, this
1487 * is when the transmit statistics are updated.
1490 spin_unlock_irqrestore(&lp->lock, flags);
1494 #define FATAL_ERROR_INT \
1495 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1496 static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1499 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1501 if (status & Int_IntPCI)
1503 if (status & Int_DmParErr)
1504 printk(" DmParErr");
1505 if (status & Int_IntNRAbt)
1506 printk(" IntNRAbt");
1509 panic("%s: Too many fatal errors.", dev->name);
1510 printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1511 /* Try to restart the adaptor. */
1512 tc35815_schedule_restart(dev);
1516 static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1518 static int tc35815_do_interrupt(struct net_device *dev, u32 status)
1521 struct tc35815_local *lp = netdev_priv(dev);
1522 struct tc35815_regs __iomem *tr =
1523 (struct tc35815_regs __iomem *)dev->base_addr;
1526 /* Fatal errors... */
1527 if (status & FATAL_ERROR_INT) {
1528 tc35815_fatal_error_interrupt(dev, status);
1531 /* recoverable errors */
1532 if (status & Int_IntFDAEx) {
1533 /* disable FDAEx int. (until we make rooms...) */
1534 tc_writel(tc_readl(&tr->Int_En) & ~Int_FDAExEn, &tr->Int_En);
1536 "%s: Free Descriptor Area Exhausted (%#x).\n",
1538 dev->stats.rx_dropped++;
1541 if (status & Int_IntBLEx) {
1542 /* disable BLEx int. (until we make rooms...) */
1543 tc_writel(tc_readl(&tr->Int_En) & ~Int_BLExEn, &tr->Int_En);
1545 "%s: Buffer List Exhausted (%#x).\n",
1547 dev->stats.rx_dropped++;
1550 if (status & Int_IntExBD) {
1552 "%s: Excessive Buffer Descriptiors (%#x).\n",
1554 dev->stats.rx_length_errors++;
1558 /* normal notification */
1559 if (status & Int_IntMacRx) {
1560 /* Got a packet(s). */
1562 ret = tc35815_rx(dev, limit);
1567 lp->lstats.rx_ints++;
1569 if (status & Int_IntMacTx) {
1570 /* Transmit complete. */
1571 lp->lstats.tx_ints++;
1572 tc35815_txdone(dev);
1573 netif_wake_queue(dev);
1580 * The typical workload of the driver:
1581 * Handle the network interface interrupts.
1583 static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1585 struct net_device *dev = dev_id;
1586 struct tc35815_local *lp = netdev_priv(dev);
1587 struct tc35815_regs __iomem *tr =
1588 (struct tc35815_regs __iomem *)dev->base_addr;
1590 u32 dmactl = tc_readl(&tr->DMA_Ctl);
1592 if (!(dmactl & DMA_IntMask)) {
1593 /* disable interrupts */
1594 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1595 if (netif_rx_schedule_prep(dev, &lp->napi))
1596 __netif_rx_schedule(dev, &lp->napi);
1598 printk(KERN_ERR "%s: interrupt taken in poll\n",
1602 (void)tc_readl(&tr->Int_Src); /* flush */
1610 spin_lock(&lp->lock);
1611 status = tc_readl(&tr->Int_Src);
1612 tc_writel(status, &tr->Int_Src); /* write to clear */
1613 handled = tc35815_do_interrupt(dev, status);
1614 (void)tc_readl(&tr->Int_Src); /* flush */
1615 spin_unlock(&lp->lock);
1616 return IRQ_RETVAL(handled >= 0);
1617 #endif /* TC35815_NAPI */
1620 #ifdef CONFIG_NET_POLL_CONTROLLER
1621 static void tc35815_poll_controller(struct net_device *dev)
1623 disable_irq(dev->irq);
1624 tc35815_interrupt(dev->irq, dev);
1625 enable_irq(dev->irq);
1629 /* We have a good packet(s), get it/them out of the buffers. */
1632 tc35815_rx(struct net_device *dev, int limit)
1635 tc35815_rx(struct net_device *dev)
1638 struct tc35815_local *lp = netdev_priv(dev);
1641 int buf_free_count = 0;
1642 int fd_free_count = 0;
1647 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1648 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1649 int pkt_len = fdctl & FD_FDLength_MASK;
1650 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1652 struct RxFD *next_rfd;
1654 #if (RX_CTL_CMD & Rx_StripCRC) == 0
1658 if (netif_msg_rx_status(lp))
1659 dump_rxfd(lp->rfd_cur);
1660 if (status & Rx_Good) {
1661 struct sk_buff *skb;
1662 unsigned char *data;
1664 #ifdef TC35815_USE_PACKEDBUFFER
1672 #ifdef TC35815_USE_PACKEDBUFFER
1673 BUG_ON(bd_count > 2);
1674 skb = dev_alloc_skb(pkt_len + 2); /* +2: for reserve */
1676 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n",
1678 dev->stats.rx_dropped++;
1681 skb_reserve(skb, 2); /* 16 bit alignment */
1683 data = skb_put(skb, pkt_len);
1685 /* copy from receive buffer */
1688 while (offset < pkt_len && cur_bd < bd_count) {
1689 int len = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BDCtl) &
1691 dma_addr_t dma = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BuffData);
1692 void *rxbuf = rxbuf_bus_to_virt(lp, dma);
1693 if (offset + len > pkt_len)
1694 len = pkt_len - offset;
1695 #ifdef TC35815_DMA_SYNC_ONDEMAND
1696 pci_dma_sync_single_for_cpu(lp->pci_dev,
1698 PCI_DMA_FROMDEVICE);
1700 memcpy(data + offset, rxbuf, len);
1701 #ifdef TC35815_DMA_SYNC_ONDEMAND
1702 pci_dma_sync_single_for_device(lp->pci_dev,
1704 PCI_DMA_FROMDEVICE);
1709 #else /* TC35815_USE_PACKEDBUFFER */
1710 BUG_ON(bd_count > 1);
1711 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1712 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1714 if (cur_bd >= RX_BUF_NUM) {
1715 printk("%s: invalid BDID.\n", dev->name);
1718 BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1719 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1720 if (!lp->rx_skbs[cur_bd].skb) {
1721 printk("%s: NULL skb.\n", dev->name);
1725 BUG_ON(cur_bd >= RX_BUF_NUM);
1727 skb = lp->rx_skbs[cur_bd].skb;
1728 prefetch(skb->data);
1729 lp->rx_skbs[cur_bd].skb = NULL;
1731 pci_unmap_single(lp->pci_dev,
1732 lp->rx_skbs[cur_bd].skb_dma,
1733 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1734 if (!HAVE_DMA_RXALIGN(lp))
1735 memmove(skb->data, skb->data - 2, pkt_len);
1736 data = skb_put(skb, pkt_len);
1737 #endif /* TC35815_USE_PACKEDBUFFER */
1738 if (netif_msg_pktdata(lp))
1740 skb->protocol = eth_type_trans(skb, dev);
1742 netif_receive_skb(skb);
1747 dev->last_rx = jiffies;
1748 dev->stats.rx_packets++;
1749 dev->stats.rx_bytes += pkt_len;
1751 dev->stats.rx_errors++;
1752 printk(KERN_DEBUG "%s: Rx error (status %x)\n",
1753 dev->name, status & Rx_Stat_Mask);
1754 /* WORKAROUND: LongErr and CRCErr means Overflow. */
1755 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1756 status &= ~(Rx_LongErr|Rx_CRCErr);
1759 if (status & Rx_LongErr)
1760 dev->stats.rx_length_errors++;
1761 if (status & Rx_Over)
1762 dev->stats.rx_fifo_errors++;
1763 if (status & Rx_CRCErr)
1764 dev->stats.rx_crc_errors++;
1765 if (status & Rx_Align)
1766 dev->stats.rx_frame_errors++;
1770 /* put Free Buffer back to controller */
1771 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1773 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1775 if (id >= RX_BUF_NUM) {
1776 printk("%s: invalid BDID.\n", dev->name);
1780 BUG_ON(id >= RX_BUF_NUM);
1782 /* free old buffers */
1783 #ifdef TC35815_USE_PACKEDBUFFER
1784 while (lp->fbl_curid != id)
1786 while (lp->fbl_count < RX_BUF_NUM)
1789 #ifdef TC35815_USE_PACKEDBUFFER
1790 unsigned char curid = lp->fbl_curid;
1792 unsigned char curid =
1793 (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1795 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1797 bdctl = le32_to_cpu(bd->BDCtl);
1798 if (bdctl & BD_CownsBD) {
1799 printk("%s: Freeing invalid BD.\n",
1804 /* pass BD to controller */
1805 #ifndef TC35815_USE_PACKEDBUFFER
1806 if (!lp->rx_skbs[curid].skb) {
1807 lp->rx_skbs[curid].skb =
1808 alloc_rxbuf_skb(dev,
1810 &lp->rx_skbs[curid].skb_dma);
1811 if (!lp->rx_skbs[curid].skb)
1812 break; /* try on next reception */
1813 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1815 #endif /* TC35815_USE_PACKEDBUFFER */
1816 /* Note: BDLength was modified by chip. */
1817 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1818 (curid << BD_RxBDID_SHIFT) |
1820 #ifdef TC35815_USE_PACKEDBUFFER
1821 lp->fbl_curid = (curid + 1) % RX_BUF_NUM;
1822 if (netif_msg_rx_status(lp)) {
1823 printk("%s: Entering new FBD %d\n",
1824 dev->name, lp->fbl_curid);
1825 dump_frfd(lp->fbl_ptr);
1834 /* put RxFD back to controller */
1836 next_rfd = fd_bus_to_virt(lp,
1837 le32_to_cpu(lp->rfd_cur->fd.FDNext));
1838 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1839 printk("%s: RxFD FDNext invalid.\n", dev->name);
1843 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1844 /* pass FD to controller */
1846 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1848 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1850 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1854 if (lp->rfd_cur > lp->rfd_limit)
1855 lp->rfd_cur = lp->rfd_base;
1857 if (lp->rfd_cur != next_rfd)
1858 printk("rfd_cur = %p, next_rfd %p\n",
1859 lp->rfd_cur, next_rfd);
1863 /* re-enable BL/FDA Exhaust interrupts. */
1864 if (fd_free_count) {
1865 struct tc35815_regs __iomem *tr =
1866 (struct tc35815_regs __iomem *)dev->base_addr;
1867 u32 en, en_old = tc_readl(&tr->Int_En);
1868 en = en_old | Int_FDAExEn;
1872 tc_writel(en, &tr->Int_En);
1880 static int tc35815_poll(struct napi_struct *napi, int budget)
1882 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1883 struct net_device *dev = lp->dev;
1884 struct tc35815_regs __iomem *tr =
1885 (struct tc35815_regs __iomem *)dev->base_addr;
1886 int received = 0, handled;
1889 spin_lock(&lp->lock);
1890 status = tc_readl(&tr->Int_Src);
1892 tc_writel(status, &tr->Int_Src); /* write to clear */
1894 handled = tc35815_do_interrupt(dev, status, limit);
1896 received += handled;
1897 if (received >= budget)
1900 status = tc_readl(&tr->Int_Src);
1902 spin_unlock(&lp->lock);
1904 if (received < budget) {
1905 netif_rx_complete(dev, napi);
1906 /* enable interrupts */
1907 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1913 #ifdef NO_CHECK_CARRIER
1914 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1916 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1920 tc35815_check_tx_stat(struct net_device *dev, int status)
1922 struct tc35815_local *lp = netdev_priv(dev);
1923 const char *msg = NULL;
1925 /* count collisions */
1926 if (status & Tx_ExColl)
1927 dev->stats.collisions += 16;
1928 if (status & Tx_TxColl_MASK)
1929 dev->stats.collisions += status & Tx_TxColl_MASK;
1931 #ifndef NO_CHECK_CARRIER
1932 /* TX4939 does not have NCarr */
1933 if (lp->chiptype == TC35815_TX4939)
1934 status &= ~Tx_NCarr;
1935 #ifdef WORKAROUND_LOSTCAR
1936 /* WORKAROUND: ignore LostCrS in full duplex operation */
1937 if (!lp->link || lp->duplex == DUPLEX_FULL)
1938 status &= ~Tx_NCarr;
1942 if (!(status & TX_STA_ERR)) {
1944 dev->stats.tx_packets++;
1948 dev->stats.tx_errors++;
1949 if (status & Tx_ExColl) {
1950 dev->stats.tx_aborted_errors++;
1951 msg = "Excessive Collision.";
1953 if (status & Tx_Under) {
1954 dev->stats.tx_fifo_errors++;
1955 msg = "Tx FIFO Underrun.";
1956 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1957 lp->lstats.tx_underrun++;
1958 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1959 struct tc35815_regs __iomem *tr =
1960 (struct tc35815_regs __iomem *)dev->base_addr;
1961 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1962 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1966 if (status & Tx_Defer) {
1967 dev->stats.tx_fifo_errors++;
1968 msg = "Excessive Deferral.";
1970 #ifndef NO_CHECK_CARRIER
1971 if (status & Tx_NCarr) {
1972 dev->stats.tx_carrier_errors++;
1973 msg = "Lost Carrier Sense.";
1976 if (status & Tx_LateColl) {
1977 dev->stats.tx_aborted_errors++;
1978 msg = "Late Collision.";
1980 if (status & Tx_TxPar) {
1981 dev->stats.tx_fifo_errors++;
1982 msg = "Transmit Parity Error.";
1984 if (status & Tx_SQErr) {
1985 dev->stats.tx_heartbeat_errors++;
1986 msg = "Signal Quality Error.";
1988 if (msg && netif_msg_tx_err(lp))
1989 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1992 /* This handles TX complete events posted by the device
1996 tc35815_txdone(struct net_device *dev)
1998 struct tc35815_local *lp = netdev_priv(dev);
2002 txfd = &lp->tfd_base[lp->tfd_end];
2003 while (lp->tfd_start != lp->tfd_end &&
2004 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
2005 int status = le32_to_cpu(txfd->fd.FDStat);
2006 struct sk_buff *skb;
2007 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
2008 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
2010 if (netif_msg_tx_done(lp)) {
2011 printk("%s: complete TxFD.\n", dev->name);
2014 tc35815_check_tx_stat(dev, status);
2016 skb = fdsystem != 0xffffffff ?
2017 lp->tx_skbs[fdsystem].skb : NULL;
2019 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
2020 printk("%s: tx_skbs mismatch.\n", dev->name);
2024 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
2027 dev->stats.tx_bytes += skb->len;
2028 pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
2029 lp->tx_skbs[lp->tfd_end].skb = NULL;
2030 lp->tx_skbs[lp->tfd_end].skb_dma = 0;
2032 dev_kfree_skb_any(skb);
2034 dev_kfree_skb_irq(skb);
2037 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
2039 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
2040 txfd = &lp->tfd_base[lp->tfd_end];
2042 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
2043 printk("%s: TxFD FDNext invalid.\n", dev->name);
2047 if (fdnext & FD_Next_EOL) {
2048 /* DMA Transmitter has been stopping... */
2049 if (lp->tfd_end != lp->tfd_start) {
2050 struct tc35815_regs __iomem *tr =
2051 (struct tc35815_regs __iomem *)dev->base_addr;
2052 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
2053 struct TxFD* txhead = &lp->tfd_base[head];
2054 int qlen = (lp->tfd_start + TX_FD_NUM
2055 - lp->tfd_end) % TX_FD_NUM;
2058 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
2059 printk("%s: TxFD FDCtl invalid.\n", dev->name);
2063 /* log max queue length */
2064 if (lp->lstats.max_tx_qlen < qlen)
2065 lp->lstats.max_tx_qlen = qlen;
2068 /* start DMA Transmitter again */
2069 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
2071 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
2073 if (netif_msg_tx_queued(lp)) {
2074 printk("%s: start TxFD on queue.\n",
2078 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
2084 /* If we had stopped the queue due to a "tx full"
2085 * condition, and space has now been made available,
2086 * wake up the queue.
2088 if (netif_queue_stopped(dev) && ! tc35815_tx_full(dev))
2089 netif_wake_queue(dev);
2092 /* The inverse routine to tc35815_open(). */
2094 tc35815_close(struct net_device *dev)
2096 struct tc35815_local *lp = netdev_priv(dev);
2098 netif_stop_queue(dev);
2100 napi_disable(&lp->napi);
2103 phy_stop(lp->phy_dev);
2104 cancel_work_sync(&lp->restart_work);
2106 /* Flush the Tx and disable Rx here. */
2107 tc35815_chip_reset(dev);
2108 free_irq(dev->irq, dev);
2110 tc35815_free_queues(dev);
2117 * Get the current statistics.
2118 * This may be called with the card open or closed.
2120 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
2122 struct tc35815_regs __iomem *tr =
2123 (struct tc35815_regs __iomem *)dev->base_addr;
2124 if (netif_running(dev))
2125 /* Update the statistics from the device registers. */
2126 dev->stats.rx_missed_errors = tc_readl(&tr->Miss_Cnt);
2131 static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
2133 struct tc35815_local *lp = netdev_priv(dev);
2134 struct tc35815_regs __iomem *tr =
2135 (struct tc35815_regs __iomem *)dev->base_addr;
2136 int cam_index = index * 6;
2139 DECLARE_MAC_BUF(mac);
2141 saved_addr = tc_readl(&tr->CAM_Adr);
2143 if (netif_msg_hw(lp))
2144 printk(KERN_DEBUG "%s: CAM %d: %s\n",
2145 dev->name, index, print_mac(mac, addr));
2147 /* read modify write */
2148 tc_writel(cam_index - 2, &tr->CAM_Adr);
2149 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
2150 cam_data |= addr[0] << 8 | addr[1];
2151 tc_writel(cam_data, &tr->CAM_Data);
2152 /* write whole word */
2153 tc_writel(cam_index + 2, &tr->CAM_Adr);
2154 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
2155 tc_writel(cam_data, &tr->CAM_Data);
2157 /* write whole word */
2158 tc_writel(cam_index, &tr->CAM_Adr);
2159 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
2160 tc_writel(cam_data, &tr->CAM_Data);
2161 /* read modify write */
2162 tc_writel(cam_index + 4, &tr->CAM_Adr);
2163 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
2164 cam_data |= addr[4] << 24 | (addr[5] << 16);
2165 tc_writel(cam_data, &tr->CAM_Data);
2168 tc_writel(saved_addr, &tr->CAM_Adr);
2173 * Set or clear the multicast filter for this adaptor.
2174 * num_addrs == -1 Promiscuous mode, receive all packets
2175 * num_addrs == 0 Normal mode, clear multicast list
2176 * num_addrs > 0 Multicast mode, receive normal and MC packets,
2177 * and do best-effort filtering.
2180 tc35815_set_multicast_list(struct net_device *dev)
2182 struct tc35815_regs __iomem *tr =
2183 (struct tc35815_regs __iomem *)dev->base_addr;
2185 if (dev->flags&IFF_PROMISC)
2187 #ifdef WORKAROUND_100HALF_PROMISC
2188 /* With some (all?) 100MHalf HUB, controller will hang
2189 * if we enabled promiscuous mode before linkup... */
2190 struct tc35815_local *lp = netdev_priv(dev);
2195 /* Enable promiscuous mode */
2196 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
2198 else if((dev->flags&IFF_ALLMULTI) || dev->mc_count > CAM_ENTRY_MAX - 3)
2200 /* CAM 0, 1, 20 are reserved. */
2201 /* Disable promiscuous mode, use normal mode. */
2202 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
2204 else if(dev->mc_count)
2206 struct dev_mc_list* cur_addr = dev->mc_list;
2208 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
2210 tc_writel(0, &tr->CAM_Ctl);
2211 /* Walk the address list, and load the filter */
2212 for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
2215 /* entry 0,1 is reserved. */
2216 tc35815_set_cam_entry(dev, i + 2, cur_addr->dmi_addr);
2217 ena_bits |= CAM_Ena_Bit(i + 2);
2219 tc_writel(ena_bits, &tr->CAM_Ena);
2220 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2223 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2224 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2228 static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2230 struct tc35815_local *lp = netdev_priv(dev);
2231 strcpy(info->driver, MODNAME);
2232 strcpy(info->version, DRV_VERSION);
2233 strcpy(info->bus_info, pci_name(lp->pci_dev));
2236 static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2238 struct tc35815_local *lp = netdev_priv(dev);
2242 return phy_ethtool_gset(lp->phy_dev, cmd);
2245 static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2247 struct tc35815_local *lp = netdev_priv(dev);
2251 return phy_ethtool_sset(lp->phy_dev, cmd);
2254 static u32 tc35815_get_msglevel(struct net_device *dev)
2256 struct tc35815_local *lp = netdev_priv(dev);
2257 return lp->msg_enable;
2260 static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
2262 struct tc35815_local *lp = netdev_priv(dev);
2263 lp->msg_enable = datum;
2266 static int tc35815_get_sset_count(struct net_device *dev, int sset)
2268 struct tc35815_local *lp = netdev_priv(dev);
2272 return sizeof(lp->lstats) / sizeof(int);
2278 static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2280 struct tc35815_local *lp = netdev_priv(dev);
2281 data[0] = lp->lstats.max_tx_qlen;
2282 data[1] = lp->lstats.tx_ints;
2283 data[2] = lp->lstats.rx_ints;
2284 data[3] = lp->lstats.tx_underrun;
2288 const char str[ETH_GSTRING_LEN];
2289 } ethtool_stats_keys[] = {
2296 static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2298 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2301 static const struct ethtool_ops tc35815_ethtool_ops = {
2302 .get_drvinfo = tc35815_get_drvinfo,
2303 .get_settings = tc35815_get_settings,
2304 .set_settings = tc35815_set_settings,
2305 .get_link = ethtool_op_get_link,
2306 .get_msglevel = tc35815_get_msglevel,
2307 .set_msglevel = tc35815_set_msglevel,
2308 .get_strings = tc35815_get_strings,
2309 .get_sset_count = tc35815_get_sset_count,
2310 .get_ethtool_stats = tc35815_get_ethtool_stats,
2313 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2315 struct tc35815_local *lp = netdev_priv(dev);
2317 if (!netif_running(dev))
2321 return phy_mii_ioctl(lp->phy_dev, if_mii(rq), cmd);
2324 static void tc35815_chip_reset(struct net_device *dev)
2326 struct tc35815_regs __iomem *tr =
2327 (struct tc35815_regs __iomem *)dev->base_addr;
2329 /* reset the controller */
2330 tc_writel(MAC_Reset, &tr->MAC_Ctl);
2331 udelay(4); /* 3200ns */
2333 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2335 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2340 tc_writel(0, &tr->MAC_Ctl);
2342 /* initialize registers to default value */
2343 tc_writel(0, &tr->DMA_Ctl);
2344 tc_writel(0, &tr->TxThrsh);
2345 tc_writel(0, &tr->TxPollCtr);
2346 tc_writel(0, &tr->RxFragSize);
2347 tc_writel(0, &tr->Int_En);
2348 tc_writel(0, &tr->FDA_Bas);
2349 tc_writel(0, &tr->FDA_Lim);
2350 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
2351 tc_writel(0, &tr->CAM_Ctl);
2352 tc_writel(0, &tr->Tx_Ctl);
2353 tc_writel(0, &tr->Rx_Ctl);
2354 tc_writel(0, &tr->CAM_Ena);
2355 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
2357 /* initialize internal SRAM */
2358 tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2359 for (i = 0; i < 0x1000; i += 4) {
2360 tc_writel(i, &tr->CAM_Adr);
2361 tc_writel(0, &tr->CAM_Data);
2363 tc_writel(0, &tr->DMA_Ctl);
2366 static void tc35815_chip_init(struct net_device *dev)
2368 struct tc35815_local *lp = netdev_priv(dev);
2369 struct tc35815_regs __iomem *tr =
2370 (struct tc35815_regs __iomem *)dev->base_addr;
2371 unsigned long txctl = TX_CTL_CMD;
2373 /* load station address to CAM */
2374 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2376 /* Enable CAM (broadcast and unicast) */
2377 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2378 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2380 /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2381 if (HAVE_DMA_RXALIGN(lp))
2382 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2384 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2385 #ifdef TC35815_USE_PACKEDBUFFER
2386 tc_writel(RxFrag_EnPack | ETH_ZLEN, &tr->RxFragSize); /* Packing */
2388 tc_writel(ETH_ZLEN, &tr->RxFragSize);
2390 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
2391 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2392 tc_writel(INT_EN_CMD, &tr->Int_En);
2395 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2396 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2399 * Activation method:
2400 * First, enable the MAC Transmitter and the DMA Receive circuits.
2401 * Then enable the DMA Transmitter and the MAC Receive circuits.
2403 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
2404 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
2406 /* start MAC transmitter */
2407 #ifndef NO_CHECK_CARRIER
2408 /* TX4939 does not have EnLCarr */
2409 if (lp->chiptype == TC35815_TX4939)
2410 txctl &= ~Tx_EnLCarr;
2411 #ifdef WORKAROUND_LOSTCAR
2412 /* WORKAROUND: ignore LostCrS in full duplex operation */
2413 if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
2414 txctl &= ~Tx_EnLCarr;
2416 #endif /* !NO_CHECK_CARRIER */
2418 txctl &= ~Tx_EnComp; /* disable global tx completion int. */
2420 tc_writel(txctl, &tr->Tx_Ctl);
2424 static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2426 struct net_device *dev = pci_get_drvdata(pdev);
2427 struct tc35815_local *lp = netdev_priv(dev);
2428 unsigned long flags;
2430 pci_save_state(pdev);
2431 if (!netif_running(dev))
2433 netif_device_detach(dev);
2435 phy_stop(lp->phy_dev);
2436 spin_lock_irqsave(&lp->lock, flags);
2437 tc35815_chip_reset(dev);
2438 spin_unlock_irqrestore(&lp->lock, flags);
2439 pci_set_power_state(pdev, PCI_D3hot);
2443 static int tc35815_resume(struct pci_dev *pdev)
2445 struct net_device *dev = pci_get_drvdata(pdev);
2446 struct tc35815_local *lp = netdev_priv(dev);
2448 pci_restore_state(pdev);
2449 if (!netif_running(dev))
2451 pci_set_power_state(pdev, PCI_D0);
2452 tc35815_restart(dev);
2454 phy_start(lp->phy_dev);
2455 netif_device_attach(dev);
2458 #endif /* CONFIG_PM */
2460 static struct pci_driver tc35815_pci_driver = {
2462 .id_table = tc35815_pci_tbl,
2463 .probe = tc35815_init_one,
2464 .remove = __devexit_p(tc35815_remove_one),
2466 .suspend = tc35815_suspend,
2467 .resume = tc35815_resume,
2471 module_param_named(speed, options.speed, int, 0);
2472 MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2473 module_param_named(duplex, options.duplex, int, 0);
2474 MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2476 static int __init tc35815_init_module(void)
2478 return pci_register_driver(&tc35815_pci_driver);
2481 static void __exit tc35815_cleanup_module(void)
2483 pci_unregister_driver(&tc35815_pci_driver);
2486 module_init(tc35815_init_module);
2487 module_exit(tc35815_cleanup_module);
2489 MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2490 MODULE_LICENSE("GPL");