1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
33 ---------------------------------------------------------------------------*/
39 * Define your architecture specific bus configuration parameters here.
42 #if defined(CONFIG_ARCH_LUBBOCK)
44 /* We can only do 16-bit reads and writes in the static memory space. */
45 #define SMC_CAN_USE_8BIT 0
46 #define SMC_CAN_USE_16BIT 1
47 #define SMC_CAN_USE_32BIT 0
50 /* The first two address lines aren't connected... */
51 #define SMC_IO_SHIFT 2
53 #define SMC_inw(a, r) readw((a) + (r))
54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
58 #elif defined(CONFIG_BFIN)
60 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
61 #define RPC_LSA_DEFAULT RPC_LED_100_10
62 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
64 # if defined (CONFIG_BFIN561_EZKIT)
65 #define SMC_CAN_USE_8BIT 0
66 #define SMC_CAN_USE_16BIT 1
67 #define SMC_CAN_USE_32BIT 1
68 #define SMC_IO_SHIFT 0
70 #define SMC_USE_BFIN_DMA 0
73 #define SMC_inw(a, r) readw((a) + (r))
74 #define SMC_outw(v, a, r) writew(v, (a) + (r))
75 #define SMC_inl(a, r) readl((a) + (r))
76 #define SMC_outl(v, a, r) writel(v, (a) + (r))
77 #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
78 #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
80 #define SMC_CAN_USE_8BIT 0
81 #define SMC_CAN_USE_16BIT 1
82 #define SMC_CAN_USE_32BIT 0
83 #define SMC_IO_SHIFT 0
85 #define SMC_USE_BFIN_DMA 0
88 #define SMC_inw(a, r) readw((a) + (r))
89 #define SMC_outw(v, a, r) writew(v, (a) + (r))
90 #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
91 #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
93 /* check if the mac in reg is valid */
94 #define SMC_GET_MAC_ADDR(addr) \
97 __v = SMC_inw(ioaddr, ADDR0_REG); \
98 addr[0] = __v; addr[1] = __v >> 8; \
99 __v = SMC_inw(ioaddr, ADDR1_REG); \
100 addr[2] = __v; addr[3] = __v >> 8; \
101 __v = SMC_inw(ioaddr, ADDR2_REG); \
102 addr[4] = __v; addr[5] = __v >> 8; \
103 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
104 random_ether_addr(addr); \
107 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
109 /* We can only do 16-bit reads and writes in the static memory space. */
110 #define SMC_CAN_USE_8BIT 0
111 #define SMC_CAN_USE_16BIT 1
112 #define SMC_CAN_USE_32BIT 0
115 #define SMC_IO_SHIFT 0
117 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
118 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
119 #define SMC_insw(a, r, p, l) \
121 unsigned long __port = (a) + (r); \
122 u16 *__p = (u16 *)(p); \
124 insw(__port, __p, __l); \
126 *__p = swab16(*__p); \
131 #define SMC_outsw(a, r, p, l) \
133 unsigned long __port = (a) + (r); \
134 u16 *__p = (u16 *)(p); \
137 /* Believe it or not, the swab isn't needed. */ \
138 outw( /* swab16 */ (*__p++), __port); \
142 #define SMC_IRQ_FLAGS (0)
144 #elif defined(CONFIG_SA1100_PLEB)
145 /* We can only do 16-bit reads and writes in the static memory space. */
146 #define SMC_CAN_USE_8BIT 1
147 #define SMC_CAN_USE_16BIT 1
148 #define SMC_CAN_USE_32BIT 0
149 #define SMC_IO_SHIFT 0
152 #define SMC_inb(a, r) readb((a) + (r))
153 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
154 #define SMC_inw(a, r) readw((a) + (r))
155 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
156 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
157 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
158 #define SMC_outw(v, a, r) writew(v, (a) + (r))
159 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
161 #define SMC_IRQ_FLAGS (0)
163 #elif defined(CONFIG_SA1100_ASSABET)
165 #include <asm/arch/neponset.h>
167 /* We can only do 8-bit reads and writes in the static memory space. */
168 #define SMC_CAN_USE_8BIT 1
169 #define SMC_CAN_USE_16BIT 0
170 #define SMC_CAN_USE_32BIT 0
173 /* The first two address lines aren't connected... */
174 #define SMC_IO_SHIFT 2
176 #define SMC_inb(a, r) readb((a) + (r))
177 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
178 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
179 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
181 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
183 #define SMC_CAN_USE_8BIT 0
184 #define SMC_CAN_USE_16BIT 1
185 #define SMC_CAN_USE_32BIT 0
186 #define SMC_IO_SHIFT 0
189 #define SMC_inw(a, r) readw((a) + (r))
190 #define SMC_outw(v, a, r) writew(v, (a) + (r))
191 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
192 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
194 #elif defined(CONFIG_ARCH_INNOKOM) || \
195 defined(CONFIG_MACH_MAINSTONE) || \
196 defined(CONFIG_ARCH_PXA_IDP) || \
197 defined(CONFIG_ARCH_RAMSES)
199 #define SMC_CAN_USE_8BIT 1
200 #define SMC_CAN_USE_16BIT 1
201 #define SMC_CAN_USE_32BIT 1
202 #define SMC_IO_SHIFT 0
204 #define SMC_USE_PXA_DMA 1
206 #define SMC_inb(a, r) readb((a) + (r))
207 #define SMC_inw(a, r) readw((a) + (r))
208 #define SMC_inl(a, r) readl((a) + (r))
209 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
210 #define SMC_outl(v, a, r) writel(v, (a) + (r))
211 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
212 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
214 /* We actually can't write halfwords properly if not word aligned */
216 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
219 unsigned int v = val << 16;
220 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
221 writel(v, ioaddr + (reg & ~2));
223 writew(val, ioaddr + reg);
227 #elif defined(CONFIG_MACH_ZYLONITE)
229 #define SMC_CAN_USE_8BIT 1
230 #define SMC_CAN_USE_16BIT 1
231 #define SMC_CAN_USE_32BIT 0
232 #define SMC_IO_SHIFT 0
234 #define SMC_USE_PXA_DMA 1
235 #define SMC_inb(a, r) readb((a) + (r))
236 #define SMC_inw(a, r) readw((a) + (r))
237 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
238 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
239 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
240 #define SMC_outw(v, a, r) writew(v, (a) + (r))
242 #elif defined(CONFIG_ARCH_OMAP)
244 /* We can only do 16-bit reads and writes in the static memory space. */
245 #define SMC_CAN_USE_8BIT 0
246 #define SMC_CAN_USE_16BIT 1
247 #define SMC_CAN_USE_32BIT 0
248 #define SMC_IO_SHIFT 0
251 #define SMC_inw(a, r) readw((a) + (r))
252 #define SMC_outw(v, a, r) writew(v, (a) + (r))
253 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
254 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
256 #include <asm/mach-types.h>
257 #include <asm/arch/cpu.h>
259 #ifdef CONFIG_ARCH_OMAP1
260 #define SMC_IRQ_FLAGS ((machine_is_omap_innovator() || \
261 machine_is_omap_osk()) \
262 ? IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING)
264 #define SMC_IRQ_FLAGS (machine_is_omap_apollon() \
265 ? IRQF_TRIGGER_RISING : IRQF_TRIGGER_LOW)
268 #elif defined(CONFIG_SH_SH4202_MICRODEV)
270 #define SMC_CAN_USE_8BIT 0
271 #define SMC_CAN_USE_16BIT 1
272 #define SMC_CAN_USE_32BIT 0
274 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
275 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
276 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
277 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
278 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
279 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
280 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
281 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
282 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
283 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
285 #define SMC_IRQ_FLAGS (0)
287 #elif defined(CONFIG_ISA)
289 #define SMC_CAN_USE_8BIT 1
290 #define SMC_CAN_USE_16BIT 1
291 #define SMC_CAN_USE_32BIT 0
293 #define SMC_inb(a, r) inb((a) + (r))
294 #define SMC_inw(a, r) inw((a) + (r))
295 #define SMC_outb(v, a, r) outb(v, (a) + (r))
296 #define SMC_outw(v, a, r) outw(v, (a) + (r))
297 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
298 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
300 #elif defined(CONFIG_SUPERH)
302 #ifdef CONFIG_SOLUTION_ENGINE
303 #define SMC_IRQ_FLAGS (0)
304 #define SMC_CAN_USE_8BIT 0
305 #define SMC_CAN_USE_16BIT 1
306 #define SMC_CAN_USE_32BIT 0
307 #define SMC_IO_SHIFT 0
310 #define SMC_inw(a, r) inw((a) + (r))
311 #define SMC_outw(v, a, r) outw(v, (a) + (r))
312 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
313 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
317 #define SMC_CAN_USE_8BIT 1
318 #define SMC_CAN_USE_16BIT 1
319 #define SMC_CAN_USE_32BIT 0
321 #define SMC_inb(a, r) inb((a) + (r))
322 #define SMC_inw(a, r) inw((a) + (r))
323 #define SMC_outb(v, a, r) outb(v, (a) + (r))
324 #define SMC_outw(v, a, r) outw(v, (a) + (r))
325 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
326 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
330 #elif defined(CONFIG_M32R)
332 #define SMC_CAN_USE_8BIT 0
333 #define SMC_CAN_USE_16BIT 1
334 #define SMC_CAN_USE_32BIT 0
336 #define SMC_inb(a, r) inb(((u32)a) + (r))
337 #define SMC_inw(a, r) inw(((u32)a) + (r))
338 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
339 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
340 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
341 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
343 #define SMC_IRQ_FLAGS (0)
345 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
346 #define RPC_LSB_DEFAULT RPC_LED_100_10
348 #elif defined(CONFIG_MACH_LPD79520) \
349 || defined(CONFIG_MACH_LPD7A400) \
350 || defined(CONFIG_MACH_LPD7A404)
352 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
353 * way that the CPU handles chip selects and the way that the SMC chip
354 * expects the chip select to operate. Refer to
355 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
356 * IOBARRIER is a byte, in order that we read the least-common
357 * denominator. It would be wasteful to read 32 bits from an 8-bit
360 * There is no explicit protection against interrupts intervening
361 * between the writew and the IOBARRIER. In SMC ISR there is a
362 * preamble that performs an IOBARRIER in the extremely unlikely event
363 * that the driver interrupts itself between a writew to the chip an
364 * the IOBARRIER that follows *and* the cache is large enough that the
365 * first off-chip access while handing the interrupt is to the SMC
366 * chip. Other devices in the same address space as the SMC chip must
367 * be aware of the potential for trouble and perform a similar
368 * IOBARRIER on entry to their ISR.
371 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
373 #define SMC_CAN_USE_8BIT 0
374 #define SMC_CAN_USE_16BIT 1
375 #define SMC_CAN_USE_32BIT 0
377 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
379 #define SMC_inw(a,r)\
380 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
381 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
383 #define SMC_insw LPD7_SMC_insw
384 static inline void LPD7_SMC_insw (unsigned char* a, int r,
385 unsigned char* p, int l)
387 unsigned short* ps = (unsigned short*) p;
389 *ps++ = readw (a + r);
394 #define SMC_outsw LPD7_SMC_outsw
395 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
396 unsigned char* p, int l)
398 unsigned short* ps = (unsigned short*) p;
400 writew (*ps++, a + r);
405 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
407 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
408 #define RPC_LSB_DEFAULT RPC_LED_100_10
410 #elif defined(CONFIG_SOC_AU1X00)
414 /* We can only do 16-bit reads and writes in the static memory space. */
415 #define SMC_CAN_USE_8BIT 0
416 #define SMC_CAN_USE_16BIT 1
417 #define SMC_CAN_USE_32BIT 0
418 #define SMC_IO_SHIFT 0
421 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
422 #define SMC_insw(a, r, p, l) \
424 unsigned long _a = (unsigned long)((a) + (r)); \
426 u16 *_p = (u16 *)(p); \
428 *_p++ = au_readw(_a); \
430 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
431 #define SMC_outsw(a, r, p, l) \
433 unsigned long _a = (unsigned long)((a) + (r)); \
435 const u16 *_p = (const u16 *)(p); \
437 au_writew(*_p++ , _a); \
440 #define SMC_IRQ_FLAGS (0)
442 #elif defined(CONFIG_ARCH_VERSATILE)
444 #define SMC_CAN_USE_8BIT 1
445 #define SMC_CAN_USE_16BIT 1
446 #define SMC_CAN_USE_32BIT 1
449 #define SMC_inb(a, r) readb((a) + (r))
450 #define SMC_inw(a, r) readw((a) + (r))
451 #define SMC_inl(a, r) readl((a) + (r))
452 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
453 #define SMC_outw(v, a, r) writew(v, (a) + (r))
454 #define SMC_outl(v, a, r) writel(v, (a) + (r))
455 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
456 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
458 #define SMC_IRQ_FLAGS (0)
462 #define SMC_CAN_USE_8BIT 1
463 #define SMC_CAN_USE_16BIT 1
464 #define SMC_CAN_USE_32BIT 1
467 #define SMC_inb(a, r) readb((a) + (r))
468 #define SMC_inw(a, r) readw((a) + (r))
469 #define SMC_inl(a, r) readl((a) + (r))
470 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
471 #define SMC_outw(v, a, r) writew(v, (a) + (r))
472 #define SMC_outl(v, a, r) writel(v, (a) + (r))
473 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
474 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
476 #define RPC_LSA_DEFAULT RPC_LED_100_10
477 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
482 /* store this information for the driver.. */
485 * If I have to wait until memory is available to send a
486 * packet, I will store the skbuff here, until I get the
487 * desired memory. Then, I'll send it out and free it.
489 struct sk_buff *pending_tx_skb;
490 struct tasklet_struct tx_task;
492 /* version/revision of the SMC91x chip */
495 /* Contains the current active transmission mode */
498 /* Contains the current active receive mode */
501 /* Contains the current active receive/phy mode */
508 struct mii_if_info mii;
511 struct work_struct phy_configure;
512 struct net_device *dev;
517 #ifdef SMC_USE_PXA_DMA
518 /* DMA needs the physical address of the chip */
520 struct device *device;
523 void __iomem *datacs;
527 #ifdef SMC_USE_PXA_DMA
529 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
530 * always happening in irq context so no need to worry about races. TX is
531 * different and probably not worth it for that reason, and not as critical
532 * as RX which can overrun memory and lose packets.
534 #include <linux/dma-mapping.h>
536 #include <asm/arch/pxa-regs.h>
540 #define SMC_insl(a, r, p, l) \
541 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
543 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
544 u_char *buf, int len)
546 u_long physaddr = lp->physaddr;
549 /* fallback if no DMA available */
550 if (dma == (unsigned char)-1) {
551 readsl(ioaddr + reg, buf, len);
555 /* 64 bit alignment is required for memory to memory DMA */
557 *((u32 *)buf) = SMC_inl(ioaddr, reg);
563 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
564 DCSR(dma) = DCSR_NODESC;
566 DSADR(dma) = physaddr + reg;
567 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
568 DCMD_WIDTH4 | (DCMD_LENGTH & len));
569 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
570 while (!(DCSR(dma) & DCSR_STOPSTATE))
573 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
579 #define SMC_insw(a, r, p, l) \
580 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
582 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
583 u_char *buf, int len)
585 u_long physaddr = lp->physaddr;
588 /* fallback if no DMA available */
589 if (dma == (unsigned char)-1) {
590 readsw(ioaddr + reg, buf, len);
594 /* 64 bit alignment is required for memory to memory DMA */
595 while ((long)buf & 6) {
596 *((u16 *)buf) = SMC_inw(ioaddr, reg);
602 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
603 DCSR(dma) = DCSR_NODESC;
605 DSADR(dma) = physaddr + reg;
606 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
607 DCMD_WIDTH2 | (DCMD_LENGTH & len));
608 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
609 while (!(DCSR(dma) & DCSR_STOPSTATE))
612 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
617 smc_pxa_dma_irq(int dma, void *dummy)
621 #endif /* SMC_USE_PXA_DMA */
625 * Everything a particular hardware setup needs should have been defined
626 * at this point. Add stubs for the undefined cases, mainly to avoid
627 * compilation warnings since they'll be optimized away, or to prevent buggy
631 #if ! SMC_CAN_USE_32BIT
632 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
633 #define SMC_outl(x, ioaddr, reg) BUG()
634 #define SMC_insl(a, r, p, l) BUG()
635 #define SMC_outsl(a, r, p, l) BUG()
638 #if !defined(SMC_insl) || !defined(SMC_outsl)
639 #define SMC_insl(a, r, p, l) BUG()
640 #define SMC_outsl(a, r, p, l) BUG()
643 #if ! SMC_CAN_USE_16BIT
646 * Any 16-bit access is performed with two 8-bit accesses if the hardware
647 * can't do it directly. Most registers are 16-bit so those are mandatory.
649 #define SMC_outw(x, ioaddr, reg) \
651 unsigned int __val16 = (x); \
652 SMC_outb( __val16, ioaddr, reg ); \
653 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
655 #define SMC_inw(ioaddr, reg) \
657 unsigned int __val16; \
658 __val16 = SMC_inb( ioaddr, reg ); \
659 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
663 #define SMC_insw(a, r, p, l) BUG()
664 #define SMC_outsw(a, r, p, l) BUG()
668 #if !defined(SMC_insw) || !defined(SMC_outsw)
669 #define SMC_insw(a, r, p, l) BUG()
670 #define SMC_outsw(a, r, p, l) BUG()
673 #if ! SMC_CAN_USE_8BIT
674 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
675 #define SMC_outb(x, ioaddr, reg) BUG()
676 #define SMC_insb(a, r, p, l) BUG()
677 #define SMC_outsb(a, r, p, l) BUG()
680 #if !defined(SMC_insb) || !defined(SMC_outsb)
681 #define SMC_insb(a, r, p, l) BUG()
682 #define SMC_outsb(a, r, p, l) BUG()
685 #ifndef SMC_CAN_USE_DATACS
686 #define SMC_CAN_USE_DATACS 0
690 #define SMC_IO_SHIFT 0
693 #ifndef SMC_IRQ_FLAGS
694 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
697 #ifndef SMC_INTERRUPT_PREAMBLE
698 #define SMC_INTERRUPT_PREAMBLE
702 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
703 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
704 #define SMC_DATA_EXTENT (4)
707 . Bank Select Register:
709 . yyyy yyyy 0000 00xx
711 . yyyy yyyy = 0x33, for identification purposes.
713 #define BANK_SELECT (14 << SMC_IO_SHIFT)
716 // Transmit Control Register
718 #define TCR_REG SMC_REG(0x0000, 0)
719 #define TCR_ENABLE 0x0001 // When 1 we can transmit
720 #define TCR_LOOP 0x0002 // Controls output pin LBK
721 #define TCR_FORCOL 0x0004 // When 1 will force a collision
722 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
723 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
724 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
725 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
726 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
727 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
728 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
730 #define TCR_CLEAR 0 /* do NOTHING */
731 /* the default settings for the TCR register : */
732 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
735 // EPH Status Register
737 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
738 #define ES_TX_SUC 0x0001 // Last TX was successful
739 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
740 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
741 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
742 #define ES_16COL 0x0010 // 16 Collisions Reached
743 #define ES_SQET 0x0020 // Signal Quality Error Test
744 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
745 #define ES_TXDEFR 0x0080 // Transmit Deferred
746 #define ES_LATCOL 0x0200 // Late collision detected on last tx
747 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
748 #define ES_EXC_DEF 0x0800 // Excessive Deferral
749 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
750 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
751 #define ES_TXUNRN 0x8000 // Tx Underrun
754 // Receive Control Register
756 #define RCR_REG SMC_REG(0x0004, 0)
757 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
758 #define RCR_PRMS 0x0002 // Enable promiscuous mode
759 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
760 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
761 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
762 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
763 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
764 #define RCR_SOFTRST 0x8000 // resets the chip
766 /* the normal settings for the RCR register : */
767 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
768 #define RCR_CLEAR 0x0 // set it to a base state
773 #define COUNTER_REG SMC_REG(0x0006, 0)
776 // Memory Information Register
778 #define MIR_REG SMC_REG(0x0008, 0)
781 // Receive/Phy Control Register
783 #define RPC_REG SMC_REG(0x000A, 0)
784 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
785 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
786 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
787 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
788 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
789 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
790 #define RPC_LED_RES (0x01) // LED = Reserved
791 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
792 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
793 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
794 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
795 #define RPC_LED_TX (0x06) // LED = TX packet occurred
796 #define RPC_LED_RX (0x07) // LED = RX packet occurred
798 #ifndef RPC_LSA_DEFAULT
799 #define RPC_LSA_DEFAULT RPC_LED_100
801 #ifndef RPC_LSB_DEFAULT
802 #define RPC_LSB_DEFAULT RPC_LED_FD
805 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
808 /* Bank 0 0x0C is reserved */
810 // Bank Select Register
812 #define BSR_REG 0x000E
817 #define CONFIG_REG SMC_REG(0x0000, 1)
818 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
819 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
820 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
821 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
823 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
824 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
827 // Base Address Register
829 #define BASE_REG SMC_REG(0x0002, 1)
832 // Individual Address Registers
834 #define ADDR0_REG SMC_REG(0x0004, 1)
835 #define ADDR1_REG SMC_REG(0x0006, 1)
836 #define ADDR2_REG SMC_REG(0x0008, 1)
839 // General Purpose Register
841 #define GP_REG SMC_REG(0x000A, 1)
846 #define CTL_REG SMC_REG(0x000C, 1)
847 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
848 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
849 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
850 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
851 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
852 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
853 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
854 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
857 // MMU Command Register
859 #define MMU_CMD_REG SMC_REG(0x0000, 2)
860 #define MC_BUSY 1 // When 1 the last release has not completed
861 #define MC_NOP (0<<5) // No Op
862 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
863 #define MC_RESET (2<<5) // Reset MMU to initial state
864 #define MC_REMOVE (3<<5) // Remove the current rx packet
865 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
866 #define MC_FREEPKT (5<<5) // Release packet in PNR register
867 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
868 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
871 // Packet Number Register
873 #define PN_REG SMC_REG(0x0002, 2)
876 // Allocation Result Register
878 #define AR_REG SMC_REG(0x0003, 2)
879 #define AR_FAILED 0x80 // Alocation Failed
882 // TX FIFO Ports Register
884 #define TXFIFO_REG SMC_REG(0x0004, 2)
885 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
887 // RX FIFO Ports Register
889 #define RXFIFO_REG SMC_REG(0x0005, 2)
890 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
892 #define FIFO_REG SMC_REG(0x0004, 2)
896 #define PTR_REG SMC_REG(0x0006, 2)
897 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
898 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
899 #define PTR_READ 0x2000 // When 1 the operation is a read
904 #define DATA_REG SMC_REG(0x0008, 2)
907 // Interrupt Status/Acknowledge Register
909 #define INT_REG SMC_REG(0x000C, 2)
912 // Interrupt Mask Register
914 #define IM_REG SMC_REG(0x000D, 2)
915 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
916 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
917 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
918 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
919 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
920 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
921 #define IM_TX_INT 0x02 // Transmit Interrupt
922 #define IM_RCV_INT 0x01 // Receive Interrupt
925 // Multicast Table Registers
927 #define MCAST_REG1 SMC_REG(0x0000, 3)
928 #define MCAST_REG2 SMC_REG(0x0002, 3)
929 #define MCAST_REG3 SMC_REG(0x0004, 3)
930 #define MCAST_REG4 SMC_REG(0x0006, 3)
933 // Management Interface Register (MII)
935 #define MII_REG SMC_REG(0x0008, 3)
936 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
937 #define MII_MDOE 0x0008 // MII Output Enable
938 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
939 #define MII_MDI 0x0002 // MII Input, pin MDI
940 #define MII_MDO 0x0001 // MII Output, pin MDO
945 /* ( hi: chip id low: rev # ) */
946 #define REV_REG SMC_REG(0x000A, 3)
949 // Early RCV Register
951 /* this is NOT on SMC9192 */
952 #define ERCV_REG SMC_REG(0x000C, 3)
953 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
954 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
959 #define EXT_REG SMC_REG(0x0000, 7)
967 #define CHIP_91100FD 8
968 #define CHIP_91111FD 9
970 static const char * chip_ids[ 16 ] = {
972 /* 3 */ "SMC91C90/91C92",
977 /* 8 */ "SMC91C100FD",
978 /* 9 */ "SMC91C11xFD",
984 . Receive status bits
986 #define RS_ALGNERR 0x8000
987 #define RS_BRODCAST 0x4000
988 #define RS_BADCRC 0x2000
989 #define RS_ODDFRAME 0x1000
990 #define RS_TOOLONG 0x0800
991 #define RS_TOOSHORT 0x0400
992 #define RS_MULTICAST 0x0001
993 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
998 * LAN83C183 == LAN91C111 Internal PHY
1000 #define PHY_LAN83C183 0x0016f840
1001 #define PHY_LAN83C180 0x02821c50
1004 * PHY Register Addresses (LAN91C111 Internal PHY)
1006 * Generic PHY registers can be found in <linux/mii.h>
1008 * These phy registers are specific to our on-board phy.
1011 // PHY Configuration Register 1
1012 #define PHY_CFG1_REG 0x10
1013 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
1014 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
1015 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
1016 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
1017 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
1018 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
1019 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
1020 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
1021 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
1022 #define PHY_CFG1_TLVL_MASK 0x003C
1023 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
1026 // PHY Configuration Register 2
1027 #define PHY_CFG2_REG 0x11
1028 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
1029 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
1030 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
1031 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
1033 // PHY Status Output (and Interrupt status) Register
1034 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
1035 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
1036 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
1037 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
1038 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
1039 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
1040 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
1041 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
1042 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
1043 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
1044 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
1046 // PHY Interrupt/Status Mask Register
1047 #define PHY_MASK_REG 0x13 // Interrupt Mask
1048 // Uses the same bit definitions as PHY_INT_REG
1052 * SMC91C96 ethernet config and status registers.
1053 * These are in the "attribute" space.
1056 #define ECOR_RESET 0x80
1057 #define ECOR_LEVEL_IRQ 0x40
1058 #define ECOR_WR_ATTRIB 0x04
1059 #define ECOR_ENABLE 0x01
1062 #define ECSR_IOIS8 0x20
1063 #define ECSR_PWRDWN 0x04
1064 #define ECSR_INT 0x02
1066 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1070 * Macros to abstract register access according to the data bus
1071 * capabilities. Please use those and not the in/out primitives.
1072 * Note: the following macros do *not* select the bank -- this must
1073 * be done separately as needed in the main code. The SMC_REG() macro
1074 * only uses the bank argument for debugging purposes (when enabled).
1076 * Note: despite inline functions being safer, everything leading to this
1077 * should preferably be macros to let BUG() display the line number in
1078 * the core source code since we're interested in the top call site
1079 * not in any inline function location.
1083 #define SMC_REG(reg, bank) \
1085 int __b = SMC_CURRENT_BANK(); \
1086 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1087 printk( "%s: bank reg screwed (0x%04x)\n", \
1091 reg<<SMC_IO_SHIFT; \
1094 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
1098 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1099 * aligned to a 32 bit boundary. I tell you that does exist!
1100 * Fortunately the affected register accesses can be easily worked around
1101 * since we can write zeroes to the preceeding 16 bits without adverse
1102 * effects and use a 32-bit access.
1104 * Enforce it on any 32-bit capable setup for now.
1106 #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
1108 #define SMC_GET_PN() \
1109 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
1110 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
1112 #define SMC_SET_PN(x) \
1114 if (SMC_MUST_ALIGN_WRITE) \
1115 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
1116 else if (SMC_CAN_USE_8BIT) \
1117 SMC_outb(x, ioaddr, PN_REG); \
1119 SMC_outw(x, ioaddr, PN_REG); \
1122 #define SMC_GET_AR() \
1123 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
1124 : (SMC_inw(ioaddr, PN_REG) >> 8) )
1126 #define SMC_GET_TXFIFO() \
1127 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
1128 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
1130 #define SMC_GET_RXFIFO() \
1131 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
1132 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
1134 #define SMC_GET_INT() \
1135 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
1136 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
1138 #define SMC_ACK_INT(x) \
1140 if (SMC_CAN_USE_8BIT) \
1141 SMC_outb(x, ioaddr, INT_REG); \
1143 unsigned long __flags; \
1145 local_irq_save(__flags); \
1146 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1147 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1148 local_irq_restore(__flags); \
1152 #define SMC_GET_INT_MASK() \
1153 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1154 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1156 #define SMC_SET_INT_MASK(x) \
1158 if (SMC_CAN_USE_8BIT) \
1159 SMC_outb(x, ioaddr, IM_REG); \
1161 SMC_outw((x) << 8, ioaddr, INT_REG); \
1164 #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1166 #define SMC_SELECT_BANK(x) \
1168 if (SMC_MUST_ALIGN_WRITE) \
1169 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1171 SMC_outw(x, ioaddr, BANK_SELECT); \
1174 #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1176 #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1178 #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1180 #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1182 #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1184 #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1186 #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1188 #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1190 #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1192 #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1194 #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1196 #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1198 #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1200 #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1202 #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1204 #define SMC_SET_PTR(x) \
1206 if (SMC_MUST_ALIGN_WRITE) \
1207 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1209 SMC_outw(x, ioaddr, PTR_REG); \
1212 #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1214 #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1216 #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1218 #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1220 #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1222 #define SMC_SET_RPC(x) \
1224 if (SMC_MUST_ALIGN_WRITE) \
1225 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1227 SMC_outw(x, ioaddr, RPC_REG); \
1230 #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1232 #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1234 #ifndef SMC_GET_MAC_ADDR
1235 #define SMC_GET_MAC_ADDR(addr) \
1238 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1239 addr[0] = __v; addr[1] = __v >> 8; \
1240 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1241 addr[2] = __v; addr[3] = __v >> 8; \
1242 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1243 addr[4] = __v; addr[5] = __v >> 8; \
1247 #define SMC_SET_MAC_ADDR(addr) \
1249 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1250 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1251 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1254 #define SMC_SET_MCAST(x) \
1256 const unsigned char *mt = (x); \
1257 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1258 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1259 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1260 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1263 #define SMC_PUT_PKT_HDR(status, length) \
1265 if (SMC_CAN_USE_32BIT) \
1266 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1268 SMC_outw(status, ioaddr, DATA_REG); \
1269 SMC_outw(length, ioaddr, DATA_REG); \
1273 #define SMC_GET_PKT_HDR(status, length) \
1275 if (SMC_CAN_USE_32BIT) { \
1276 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1277 (status) = __val & 0xffff; \
1278 (length) = __val >> 16; \
1280 (status) = SMC_inw(ioaddr, DATA_REG); \
1281 (length) = SMC_inw(ioaddr, DATA_REG); \
1285 #define SMC_PUSH_DATA(p, l) \
1287 if (SMC_CAN_USE_32BIT) { \
1288 void *__ptr = (p); \
1290 void __iomem *__ioaddr = ioaddr; \
1291 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1293 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1296 if (SMC_CAN_USE_DATACS && lp->datacs) \
1297 __ioaddr = lp->datacs; \
1298 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1300 __ptr += (__len & ~3); \
1301 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1303 } else if (SMC_CAN_USE_16BIT) \
1304 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1305 else if (SMC_CAN_USE_8BIT) \
1306 SMC_outsb(ioaddr, DATA_REG, p, l); \
1309 #define SMC_PULL_DATA(p, l) \
1311 if (SMC_CAN_USE_32BIT) { \
1312 void *__ptr = (p); \
1314 void __iomem *__ioaddr = ioaddr; \
1315 if ((unsigned long)__ptr & 2) { \
1317 * We want 32bit alignment here. \
1318 * Since some buses perform a full \
1319 * 32bit fetch even for 16bit data \
1320 * we can't use SMC_inw() here. \
1321 * Back both source (on-chip) and \
1322 * destination pointers of 2 bytes. \
1323 * This is possible since the call to \
1324 * SMC_GET_PKT_HDR() already advanced \
1325 * the source pointer of 4 bytes, and \
1326 * the skb_reserve(skb, 2) advanced \
1327 * the destination pointer of 2 bytes. \
1331 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1333 if (SMC_CAN_USE_DATACS && lp->datacs) \
1334 __ioaddr = lp->datacs; \
1336 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1337 } else if (SMC_CAN_USE_16BIT) \
1338 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1339 else if (SMC_CAN_USE_8BIT) \
1340 SMC_insb(ioaddr, DATA_REG, p, l); \
1343 #endif /* _SMC91X_H_ */