1 /*------------------------------------------------------------------------
2 . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
4 . Copyright (C) 2005 Sensoria Corp.
5 . Derived from the unified SMC91x driver by Nicolas Pitre
7 . This program is free software; you can redistribute it and/or modify
8 . it under the terms of the GNU General Public License as published by
9 . the Free Software Foundation; either version 2 of the License, or
10 . (at your option) any later version.
12 . This program is distributed in the hope that it will be useful,
13 . but WITHOUT ANY WARRANTY; without even the implied warranty of
14 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 . GNU General Public License for more details.
17 . You should have received a copy of the GNU General Public License
18 . along with this program; if not, write to the Free Software
19 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 . Information contained in this file was obtained from the LAN9118
22 . manual from SMC. To get a copy, if you really want one, you can find
23 . information under www.smsc.com.
26 . Dustin McIntire <dustin@sensoria.com>
28 ---------------------------------------------------------------------------*/
33 * Use the DMA feature on PXA chips
35 #ifdef CONFIG_ARCH_PXA
36 #define SMC_USE_PXA_DMA 1
37 #define SMC_USE_16BIT 0
38 #define SMC_USE_32BIT 1
39 #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
40 #elif defined(CONFIG_SH_MAGIC_PANEL_R2)
41 #define SMC_USE_SH_DMA 0
42 #define SMC_USE_16BIT 0
43 #define SMC_USE_32BIT 1
44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
49 * Define the bus width specific IO macros
53 #define SMC_inl(a, r) (readw((a) + (r)) & 0xFFFF) + (readw((a) + (r) + 2) << 16))
54 #define SMC_outl(v, a, r) \
56 writew(v & 0xFFFF, (a) + (r)); \
57 writew(v >> 16, (a) + (r) + 2); \
59 #define SMC_insl(a, r, p, l) readsw((short*)((a) + (r)), p, l*2)
60 #define SMC_outsl(a, r, p, l) writesw((short*)((a) + (r)), p, l*2)
63 #define SMC_inl(a, r) readl((a) + (r))
64 #define SMC_outl(v, a, r) writel(v, (a) + (r))
65 #define SMC_insl(a, r, p, l) readsl((int*)((a) + (r)), p, l)
66 #define SMC_outsl(a, r, p, l) writesl((int*)((a) + (r)), p, l)
68 #endif /* SMC_USE_16BIT */
72 #ifdef SMC_USE_PXA_DMA
76 * Define the request and free functions
77 * These are unfortunately architecture specific as no generic allocation
80 #define SMC_DMA_REQUEST(dev, handler) \
81 pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
83 #define SMC_DMA_FREE(dev, dma) \
86 #define SMC_DMA_ACK_IRQ(dev, dma) \
88 if (DCSR(dma) & DCSR_BUSERR) { \
89 printk("%s: DMA %d bus error!\n", dev->name, dma); \
91 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; \
95 * Use a DMA for RX and TX packets.
97 #include <linux/dma-mapping.h>
99 #include <asm/arch/pxa-regs.h>
101 static dma_addr_t rx_dmabuf, tx_dmabuf;
102 static int rx_dmalen, tx_dmalen;
106 #define SMC_insl(a, r, p, l) \
107 smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
110 smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
111 int reg, int dma, u_char *buf, int len)
113 /* 64 bit alignment is required for memory to memory DMA */
115 *((u32 *)buf) = SMC_inl(ioaddr, reg);
121 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
123 DCSR(dma) = DCSR_NODESC;
124 DTADR(dma) = rx_dmabuf;
125 DSADR(dma) = physaddr + reg;
126 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
127 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
128 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
134 #define SMC_outsl(a, r, p, l) \
135 smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
138 smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr,
139 int reg, int dma, u_char *buf, int len)
141 /* 64 bit alignment is required for memory to memory DMA */
143 SMC_outl(*((u32 *)buf), ioaddr, reg);
149 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
151 DCSR(dma) = DCSR_NODESC;
152 DSADR(dma) = tx_dmabuf;
153 DTADR(dma) = physaddr + reg;
154 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
155 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
156 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
159 #endif /* SMC_USE_PXA_DMA */
162 /* Chip Parameters and Register Definitions */
164 #define SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2)
166 #define SMC911X_IO_EXTENT 0x100
168 #define SMC911X_EEPROM_LEN 7
170 /* Below are the register offsets and bit definitions
171 * of the Lan911x memory space
173 #define RX_DATA_FIFO (0x00)
175 #define TX_DATA_FIFO (0x20)
176 #define TX_CMD_A_INT_ON_COMP_ (0x80000000)
177 #define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000)
178 #define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000)
179 #define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000)
180 #define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000)
181 #define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000)
182 #define TX_CMD_A_INT_FIRST_SEG_ (0x00002000)
183 #define TX_CMD_A_INT_LAST_SEG_ (0x00001000)
184 #define TX_CMD_A_BUF_SIZE_ (0x000007FF)
185 #define TX_CMD_B_PKT_TAG_ (0xFFFF0000)
186 #define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000)
187 #define TX_CMD_B_DISABLE_PADDING_ (0x00001000)
188 #define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF)
190 #define RX_STATUS_FIFO (0x40)
191 #define RX_STS_PKT_LEN_ (0x3FFF0000)
192 #define RX_STS_ES_ (0x00008000)
193 #define RX_STS_BCST_ (0x00002000)
194 #define RX_STS_LEN_ERR_ (0x00001000)
195 #define RX_STS_RUNT_ERR_ (0x00000800)
196 #define RX_STS_MCAST_ (0x00000400)
197 #define RX_STS_TOO_LONG_ (0x00000080)
198 #define RX_STS_COLL_ (0x00000040)
199 #define RX_STS_ETH_TYPE_ (0x00000020)
200 #define RX_STS_WDOG_TMT_ (0x00000010)
201 #define RX_STS_MII_ERR_ (0x00000008)
202 #define RX_STS_DRIBBLING_ (0x00000004)
203 #define RX_STS_CRC_ERR_ (0x00000002)
204 #define RX_STATUS_FIFO_PEEK (0x44)
205 #define TX_STATUS_FIFO (0x48)
206 #define TX_STS_TAG_ (0xFFFF0000)
207 #define TX_STS_ES_ (0x00008000)
208 #define TX_STS_LOC_ (0x00000800)
209 #define TX_STS_NO_CARR_ (0x00000400)
210 #define TX_STS_LATE_COLL_ (0x00000200)
211 #define TX_STS_MANY_COLL_ (0x00000100)
212 #define TX_STS_COLL_CNT_ (0x00000078)
213 #define TX_STS_MANY_DEFER_ (0x00000004)
214 #define TX_STS_UNDERRUN_ (0x00000002)
215 #define TX_STS_DEFERRED_ (0x00000001)
216 #define TX_STATUS_FIFO_PEEK (0x4C)
217 #define ID_REV (0x50)
218 #define ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */
219 #define ID_REV_REV_ID_ (0x0000FFFF) /* RO */
221 #define INT_CFG (0x54)
222 #define INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */
223 #define INT_CFG_INT_DEAS_CLR_ (0x00004000)
224 #define INT_CFG_INT_DEAS_STS_ (0x00002000)
225 #define INT_CFG_IRQ_INT_ (0x00001000) /* RO */
226 #define INT_CFG_IRQ_EN_ (0x00000100) /* R/W */
227 #define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */
228 #define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */
230 #define INT_STS (0x58)
231 #define INT_STS_SW_INT_ (0x80000000) /* R/WC */
232 #define INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */
233 #define INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */
234 #define INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */
235 #define INT_STS_RXDF_INT_ (0x00400000) /* R/WC */
236 #define INT_STS_TX_IOC_ (0x00200000) /* R/WC */
237 #define INT_STS_RXD_INT_ (0x00100000) /* R/WC */
238 #define INT_STS_GPT_INT_ (0x00080000) /* R/WC */
239 #define INT_STS_PHY_INT_ (0x00040000) /* RO */
240 #define INT_STS_PME_INT_ (0x00020000) /* R/WC */
241 #define INT_STS_TXSO_ (0x00010000) /* R/WC */
242 #define INT_STS_RWT_ (0x00008000) /* R/WC */
243 #define INT_STS_RXE_ (0x00004000) /* R/WC */
244 #define INT_STS_TXE_ (0x00002000) /* R/WC */
245 //#define INT_STS_ERX_ (0x00001000) /* R/WC */
246 #define INT_STS_TDFU_ (0x00000800) /* R/WC */
247 #define INT_STS_TDFO_ (0x00000400) /* R/WC */
248 #define INT_STS_TDFA_ (0x00000200) /* R/WC */
249 #define INT_STS_TSFF_ (0x00000100) /* R/WC */
250 #define INT_STS_TSFL_ (0x00000080) /* R/WC */
251 //#define INT_STS_RXDF_ (0x00000040) /* R/WC */
252 #define INT_STS_RDFO_ (0x00000040) /* R/WC */
253 #define INT_STS_RDFL_ (0x00000020) /* R/WC */
254 #define INT_STS_RSFF_ (0x00000010) /* R/WC */
255 #define INT_STS_RSFL_ (0x00000008) /* R/WC */
256 #define INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */
257 #define INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */
258 #define INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */
260 #define INT_EN (0x5C)
261 #define INT_EN_SW_INT_EN_ (0x80000000) /* R/W */
262 #define INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */
263 #define INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */
264 #define INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */
265 //#define INT_EN_RXDF_INT_EN_ (0x00400000) /* R/W */
266 #define INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */
267 #define INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */
268 #define INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */
269 #define INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */
270 #define INT_EN_PME_INT_EN_ (0x00020000) /* R/W */
271 #define INT_EN_TXSO_EN_ (0x00010000) /* R/W */
272 #define INT_EN_RWT_EN_ (0x00008000) /* R/W */
273 #define INT_EN_RXE_EN_ (0x00004000) /* R/W */
274 #define INT_EN_TXE_EN_ (0x00002000) /* R/W */
275 //#define INT_EN_ERX_EN_ (0x00001000) /* R/W */
276 #define INT_EN_TDFU_EN_ (0x00000800) /* R/W */
277 #define INT_EN_TDFO_EN_ (0x00000400) /* R/W */
278 #define INT_EN_TDFA_EN_ (0x00000200) /* R/W */
279 #define INT_EN_TSFF_EN_ (0x00000100) /* R/W */
280 #define INT_EN_TSFL_EN_ (0x00000080) /* R/W */
281 //#define INT_EN_RXDF_EN_ (0x00000040) /* R/W */
282 #define INT_EN_RDFO_EN_ (0x00000040) /* R/W */
283 #define INT_EN_RDFL_EN_ (0x00000020) /* R/W */
284 #define INT_EN_RSFF_EN_ (0x00000010) /* R/W */
285 #define INT_EN_RSFL_EN_ (0x00000008) /* R/W */
286 #define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */
287 #define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */
288 #define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */
290 #define BYTE_TEST (0x64)
291 #define FIFO_INT (0x68)
292 #define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */
293 #define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */
294 #define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */
295 #define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */
297 #define RX_CFG (0x6C)
298 #define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */
299 #define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */
300 #define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */
301 #define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */
302 #define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */
303 #define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */
304 #define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */
305 //#define RX_CFG_RXBAD_ (0x00000001) /* R/W */
307 #define TX_CFG (0x70)
308 //#define TX_CFG_TX_DMA_LVL_ (0xE0000000) /* R/W */
309 //#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000) /* R/W Self Clearing */
310 #define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */
311 #define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */
312 #define TX_CFG_TXSAO_ (0x00000004) /* R/W */
313 #define TX_CFG_TX_ON_ (0x00000002) /* R/W */
314 #define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */
316 #define HW_CFG (0x74)
317 #define HW_CFG_TTM_ (0x00200000) /* R/W */
318 #define HW_CFG_SF_ (0x00100000) /* R/W */
319 #define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */
320 #define HW_CFG_TR_ (0x00003000) /* R/W */
321 #define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */
322 #define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */
323 #define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */
324 #define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */
325 #define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */
326 #define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */
327 #define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */
328 #define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */
329 #define HW_CFG_SRST_TO_ (0x00000002) /* RO */
330 #define HW_CFG_SRST_ (0x00000001) /* Self Clearing */
332 #define RX_DP_CTRL (0x78)
333 #define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */
334 #define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */
336 #define RX_FIFO_INF (0x7C)
337 #define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */
338 #define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */
340 #define TX_FIFO_INF (0x80)
341 #define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */
342 #define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */
344 #define PMT_CTRL (0x84)
345 #define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */
346 #define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */
347 #define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */
348 #define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */
349 #define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
350 #define PMT_CTRL_WUPS_ (0x00000030) /* R/WC */
351 #define PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */
352 #define PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */
353 #define PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */
354 #define PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */
355 #define PMT_CTRL_PME_IND_ (0x00000008) /* R/W */
356 #define PMT_CTRL_PME_POL_ (0x00000004) /* R/W */
357 #define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
358 #define PMT_CTRL_READY_ (0x00000001) /* RO */
360 #define GPIO_CFG (0x88)
361 #define GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */
362 #define GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */
363 #define GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */
364 #define GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */
365 #define GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */
366 #define GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */
367 #define GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */
368 #define GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */
369 #define GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */
370 #define GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */
371 #define GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */
372 #define GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */
373 #define GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */
374 #define GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */
375 #define GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */
376 #define GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */
377 #define GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */
378 #define GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */
380 #define GPT_CFG (0x8C)
381 #define GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */
382 #define GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */
384 #define GPT_CNT (0x90)
385 #define GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */
387 #define ENDIAN (0x98)
388 #define FREE_RUN (0x9C)
389 #define RX_DROP (0xA0)
390 #define MAC_CSR_CMD (0xA4)
391 #define MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */
392 #define MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */
393 #define MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */
395 #define MAC_CSR_DATA (0xA8)
396 #define AFC_CFG (0xAC)
397 #define AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */
398 #define AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */
399 #define AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */
400 #define AFC_CFG_FCMULT_ (0x00000008) /* R/W */
401 #define AFC_CFG_FCBRD_ (0x00000004) /* R/W */
402 #define AFC_CFG_FCADD_ (0x00000002) /* R/W */
403 #define AFC_CFG_FCANY_ (0x00000001) /* R/W */
405 #define E2P_CMD (0xB0)
406 #define E2P_CMD_EPC_BUSY_ (0x80000000) /* Self Clearing */
407 #define E2P_CMD_EPC_CMD_ (0x70000000) /* R/W */
408 #define E2P_CMD_EPC_CMD_READ_ (0x00000000) /* R/W */
409 #define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) /* R/W */
410 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) /* R/W */
411 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) /* R/W */
412 #define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) /* R/W */
413 #define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) /* R/W */
414 #define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) /* R/W */
415 #define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) /* R/W */
416 #define E2P_CMD_EPC_TIMEOUT_ (0x00000200) /* RO */
417 #define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) /* RO */
418 #define E2P_CMD_EPC_ADDR_ (0x000000FF) /* R/W */
420 #define E2P_DATA (0xB4)
421 #define E2P_DATA_EEPROM_DATA_ (0x000000FF) /* R/W */
422 /* end of LAN register offsets and bit definitions */
425 ****************************************************************************
426 ****************************************************************************
427 * MAC Control and Status Register (Indirect Address)
428 * Offset (through the MAC_CSR CMD and DATA port)
429 ****************************************************************************
430 ****************************************************************************
433 #define MAC_CR (0x01) /* R/W */
435 /* MAC_CR - MAC Control Register */
436 #define MAC_CR_RXALL_ (0x80000000)
437 // TODO: delete this bit? It is not described in the data sheet.
438 #define MAC_CR_HBDIS_ (0x10000000)
439 #define MAC_CR_RCVOWN_ (0x00800000)
440 #define MAC_CR_LOOPBK_ (0x00200000)
441 #define MAC_CR_FDPX_ (0x00100000)
442 #define MAC_CR_MCPAS_ (0x00080000)
443 #define MAC_CR_PRMS_ (0x00040000)
444 #define MAC_CR_INVFILT_ (0x00020000)
445 #define MAC_CR_PASSBAD_ (0x00010000)
446 #define MAC_CR_HFILT_ (0x00008000)
447 #define MAC_CR_HPFILT_ (0x00002000)
448 #define MAC_CR_LCOLL_ (0x00001000)
449 #define MAC_CR_BCAST_ (0x00000800)
450 #define MAC_CR_DISRTY_ (0x00000400)
451 #define MAC_CR_PADSTR_ (0x00000100)
452 #define MAC_CR_BOLMT_MASK_ (0x000000C0)
453 #define MAC_CR_DFCHK_ (0x00000020)
454 #define MAC_CR_TXEN_ (0x00000008)
455 #define MAC_CR_RXEN_ (0x00000004)
457 #define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
458 #define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
459 #define HASHH (0x04) /* R/W */
460 #define HASHL (0x05) /* R/W */
462 #define MII_ACC (0x06) /* R/W */
463 #define MII_ACC_PHY_ADDR_ (0x0000F800)
464 #define MII_ACC_MIIRINDA_ (0x000007C0)
465 #define MII_ACC_MII_WRITE_ (0x00000002)
466 #define MII_ACC_MII_BUSY_ (0x00000001)
468 #define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
470 #define FLOW (0x08) /* R/W */
471 #define FLOW_FCPT_ (0xFFFF0000)
472 #define FLOW_FCPASS_ (0x00000004)
473 #define FLOW_FCEN_ (0x00000002)
474 #define FLOW_FCBSY_ (0x00000001)
476 #define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
477 #define VLAN1_VTI1_ (0x0000ffff)
479 #define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
480 #define VLAN2_VTI2_ (0x0000ffff)
482 #define WUFF (0x0B) /* WO */
484 #define WUCSR (0x0C) /* R/W */
485 #define WUCSR_GUE_ (0x00000200)
486 #define WUCSR_WUFR_ (0x00000040)
487 #define WUCSR_MPR_ (0x00000020)
488 #define WUCSR_WAKE_EN_ (0x00000004)
489 #define WUCSR_MPEN_ (0x00000002)
492 ****************************************************************************
493 * Chip Specific MII Defines
494 ****************************************************************************
496 * Phy register offsets and bit definitions
500 #define PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register */
501 //#define MODE_CTRL_STS_FASTRIP_ ((u16)0x4000)
502 #define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)
503 //#define MODE_CTRL_STS_LOWSQEN_ ((u16)0x0800)
504 //#define MODE_CTRL_STS_MDPREBP_ ((u16)0x0400)
505 //#define MODE_CTRL_STS_FARLOOPBACK_ ((u16)0x0200)
506 //#define MODE_CTRL_STS_FASTEST_ ((u16)0x0100)
507 //#define MODE_CTRL_STS_REFCLKEN_ ((u16)0x0010)
508 //#define MODE_CTRL_STS_PHYADBP_ ((u16)0x0008)
509 //#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
510 #define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)
512 #define PHY_INT_SRC ((u32)29)
513 #define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)
514 #define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)
515 #define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)
516 #define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)
517 #define PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008)
518 #define PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004)
519 #define PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002)
521 #define PHY_INT_MASK ((u32)30)
522 #define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)
523 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
524 #define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)
525 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
526 #define PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008)
527 #define PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004)
528 #define PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002)
530 #define PHY_SPECIAL ((u32)31)
531 #define PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000)
532 #define PHY_SPECIAL_RES_ ((u16)0x0040)
533 #define PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1)
534 #define PHY_SPECIAL_SPD_ ((u16)0x001C)
535 #define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)
536 #define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)
537 #define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)
538 #define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)
540 #define LAN911X_INTERNAL_PHY_ID (0x0007C000)
543 #define CHIP_9115 0x115
544 #define CHIP_9116 0x116
545 #define CHIP_9117 0x117
546 #define CHIP_9118 0x118
553 static const struct chip_id chip_ids[] = {
554 { CHIP_9115, "LAN9115" },
555 { CHIP_9116, "LAN9116" },
556 { CHIP_9117, "LAN9117" },
557 { CHIP_9118, "LAN9118" },
561 #define IS_REV_A(x) ((x & 0xFFFF)==0)
564 * Macros to abstract register access according to the data bus
565 * capabilities. Please use those and not the in/out primitives.
567 /* FIFO read/write macros */
568 #define SMC_PUSH_DATA(p, l) SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 )
569 #define SMC_PULL_DATA(p, l) SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 )
570 #define SMC_SET_TX_FIFO(x) SMC_outl( x, ioaddr, TX_DATA_FIFO )
571 #define SMC_GET_RX_FIFO() SMC_inl( ioaddr, RX_DATA_FIFO )
574 /* I/O mapped register read/write macros */
575 #define SMC_GET_TX_STS_FIFO() SMC_inl( ioaddr, TX_STATUS_FIFO )
576 #define SMC_GET_RX_STS_FIFO() SMC_inl( ioaddr, RX_STATUS_FIFO )
577 #define SMC_GET_RX_STS_FIFO_PEEK() SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK )
578 #define SMC_GET_PN() (SMC_inl( ioaddr, ID_REV ) >> 16)
579 #define SMC_GET_REV() (SMC_inl( ioaddr, ID_REV ) & 0xFFFF)
580 #define SMC_GET_IRQ_CFG() SMC_inl( ioaddr, INT_CFG )
581 #define SMC_SET_IRQ_CFG(x) SMC_outl( x, ioaddr, INT_CFG )
582 #define SMC_GET_INT() SMC_inl( ioaddr, INT_STS )
583 #define SMC_ACK_INT(x) SMC_outl( x, ioaddr, INT_STS )
584 #define SMC_GET_INT_EN() SMC_inl( ioaddr, INT_EN )
585 #define SMC_SET_INT_EN(x) SMC_outl( x, ioaddr, INT_EN )
586 #define SMC_GET_BYTE_TEST() SMC_inl( ioaddr, BYTE_TEST )
587 #define SMC_SET_BYTE_TEST(x) SMC_outl( x, ioaddr, BYTE_TEST )
588 #define SMC_GET_FIFO_INT() SMC_inl( ioaddr, FIFO_INT )
589 #define SMC_SET_FIFO_INT(x) SMC_outl( x, ioaddr, FIFO_INT )
590 #define SMC_SET_FIFO_TDA(x) \
592 unsigned long __flags; \
594 local_irq_save(__flags); \
595 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24); \
596 SMC_SET_FIFO_INT( __mask | (x)<<24 ); \
597 local_irq_restore(__flags); \
599 #define SMC_SET_FIFO_TSL(x) \
601 unsigned long __flags; \
603 local_irq_save(__flags); \
604 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16); \
605 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \
606 local_irq_restore(__flags); \
608 #define SMC_SET_FIFO_RSA(x) \
610 unsigned long __flags; \
612 local_irq_save(__flags); \
613 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8); \
614 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8)); \
615 local_irq_restore(__flags); \
617 #define SMC_SET_FIFO_RSL(x) \
619 unsigned long __flags; \
621 local_irq_save(__flags); \
622 __mask = SMC_GET_FIFO_INT() & ~0xFF; \
623 SMC_SET_FIFO_INT( __mask | ((x) & 0xFF)); \
624 local_irq_restore(__flags); \
626 #define SMC_GET_RX_CFG() SMC_inl( ioaddr, RX_CFG )
627 #define SMC_SET_RX_CFG(x) SMC_outl( x, ioaddr, RX_CFG )
628 #define SMC_GET_TX_CFG() SMC_inl( ioaddr, TX_CFG )
629 #define SMC_SET_TX_CFG(x) SMC_outl( x, ioaddr, TX_CFG )
630 #define SMC_GET_HW_CFG() SMC_inl( ioaddr, HW_CFG )
631 #define SMC_SET_HW_CFG(x) SMC_outl( x, ioaddr, HW_CFG )
632 #define SMC_GET_RX_DP_CTRL() SMC_inl( ioaddr, RX_DP_CTRL )
633 #define SMC_SET_RX_DP_CTRL(x) SMC_outl( x, ioaddr, RX_DP_CTRL )
634 #define SMC_GET_PMT_CTRL() SMC_inl( ioaddr, PMT_CTRL )
635 #define SMC_SET_PMT_CTRL(x) SMC_outl( x, ioaddr, PMT_CTRL )
636 #define SMC_GET_GPIO_CFG() SMC_inl( ioaddr, GPIO_CFG )
637 #define SMC_SET_GPIO_CFG(x) SMC_outl( x, ioaddr, GPIO_CFG )
638 #define SMC_GET_RX_FIFO_INF() SMC_inl( ioaddr, RX_FIFO_INF )
639 #define SMC_SET_RX_FIFO_INF(x) SMC_outl( x, ioaddr, RX_FIFO_INF )
640 #define SMC_GET_TX_FIFO_INF() SMC_inl( ioaddr, TX_FIFO_INF )
641 #define SMC_SET_TX_FIFO_INF(x) SMC_outl( x, ioaddr, TX_FIFO_INF )
642 #define SMC_GET_GPT_CFG() SMC_inl( ioaddr, GPT_CFG )
643 #define SMC_SET_GPT_CFG(x) SMC_outl( x, ioaddr, GPT_CFG )
644 #define SMC_GET_RX_DROP() SMC_inl( ioaddr, RX_DROP )
645 #define SMC_SET_RX_DROP(x) SMC_outl( x, ioaddr, RX_DROP )
646 #define SMC_GET_MAC_CMD() SMC_inl( ioaddr, MAC_CSR_CMD )
647 #define SMC_SET_MAC_CMD(x) SMC_outl( x, ioaddr, MAC_CSR_CMD )
648 #define SMC_GET_MAC_DATA() SMC_inl( ioaddr, MAC_CSR_DATA )
649 #define SMC_SET_MAC_DATA(x) SMC_outl( x, ioaddr, MAC_CSR_DATA )
650 #define SMC_GET_AFC_CFG() SMC_inl( ioaddr, AFC_CFG )
651 #define SMC_SET_AFC_CFG(x) SMC_outl( x, ioaddr, AFC_CFG )
652 #define SMC_GET_E2P_CMD() SMC_inl( ioaddr, E2P_CMD )
653 #define SMC_SET_E2P_CMD(x) SMC_outl( x, ioaddr, E2P_CMD )
654 #define SMC_GET_E2P_DATA() SMC_inl( ioaddr, E2P_DATA )
655 #define SMC_SET_E2P_DATA(x) SMC_outl( x, ioaddr, E2P_DATA )
657 /* MAC register read/write macros */
658 #define SMC_GET_MAC_CSR(a,v) \
660 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
661 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | \
662 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
663 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
664 v = SMC_GET_MAC_DATA(); \
666 #define SMC_SET_MAC_CSR(a,v) \
668 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
669 SMC_SET_MAC_DATA(v); \
670 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
671 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
673 #define SMC_GET_MAC_CR(x) SMC_GET_MAC_CSR( MAC_CR, x )
674 #define SMC_SET_MAC_CR(x) SMC_SET_MAC_CSR( MAC_CR, x )
675 #define SMC_GET_ADDRH(x) SMC_GET_MAC_CSR( ADDRH, x )
676 #define SMC_SET_ADDRH(x) SMC_SET_MAC_CSR( ADDRH, x )
677 #define SMC_GET_ADDRL(x) SMC_GET_MAC_CSR( ADDRL, x )
678 #define SMC_SET_ADDRL(x) SMC_SET_MAC_CSR( ADDRL, x )
679 #define SMC_GET_HASHH(x) SMC_GET_MAC_CSR( HASHH, x )
680 #define SMC_SET_HASHH(x) SMC_SET_MAC_CSR( HASHH, x )
681 #define SMC_GET_HASHL(x) SMC_GET_MAC_CSR( HASHL, x )
682 #define SMC_SET_HASHL(x) SMC_SET_MAC_CSR( HASHL, x )
683 #define SMC_GET_MII_ACC(x) SMC_GET_MAC_CSR( MII_ACC, x )
684 #define SMC_SET_MII_ACC(x) SMC_SET_MAC_CSR( MII_ACC, x )
685 #define SMC_GET_MII_DATA(x) SMC_GET_MAC_CSR( MII_DATA, x )
686 #define SMC_SET_MII_DATA(x) SMC_SET_MAC_CSR( MII_DATA, x )
687 #define SMC_GET_FLOW(x) SMC_GET_MAC_CSR( FLOW, x )
688 #define SMC_SET_FLOW(x) SMC_SET_MAC_CSR( FLOW, x )
689 #define SMC_GET_VLAN1(x) SMC_GET_MAC_CSR( VLAN1, x )
690 #define SMC_SET_VLAN1(x) SMC_SET_MAC_CSR( VLAN1, x )
691 #define SMC_GET_VLAN2(x) SMC_GET_MAC_CSR( VLAN2, x )
692 #define SMC_SET_VLAN2(x) SMC_SET_MAC_CSR( VLAN2, x )
693 #define SMC_SET_WUFF(x) SMC_SET_MAC_CSR( WUFF, x )
694 #define SMC_GET_WUCSR(x) SMC_GET_MAC_CSR( WUCSR, x )
695 #define SMC_SET_WUCSR(x) SMC_SET_MAC_CSR( WUCSR, x )
697 /* PHY register read/write macros */
698 #define SMC_GET_MII(a,phy,v) \
702 SMC_GET_MII_ACC(__v); \
703 } while ( __v & MII_ACC_MII_BUSY_ ); \
704 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \
705 MII_ACC_MII_BUSY_); \
707 SMC_GET_MII_ACC(__v); \
708 } while ( __v & MII_ACC_MII_BUSY_ ); \
709 SMC_GET_MII_DATA(v); \
711 #define SMC_SET_MII(a,phy,v) \
715 SMC_GET_MII_ACC(__v); \
716 } while ( __v & MII_ACC_MII_BUSY_ ); \
717 SMC_SET_MII_DATA(v); \
718 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \
719 MII_ACC_MII_BUSY_ | \
720 MII_ACC_MII_WRITE_ ); \
722 SMC_GET_MII_ACC(__v); \
723 } while ( __v & MII_ACC_MII_BUSY_ ); \
725 #define SMC_GET_PHY_BMCR(phy,x) SMC_GET_MII( MII_BMCR, phy, x )
726 #define SMC_SET_PHY_BMCR(phy,x) SMC_SET_MII( MII_BMCR, phy, x )
727 #define SMC_GET_PHY_BMSR(phy,x) SMC_GET_MII( MII_BMSR, phy, x )
728 #define SMC_GET_PHY_ID1(phy,x) SMC_GET_MII( MII_PHYSID1, phy, x )
729 #define SMC_GET_PHY_ID2(phy,x) SMC_GET_MII( MII_PHYSID2, phy, x )
730 #define SMC_GET_PHY_MII_ADV(phy,x) SMC_GET_MII( MII_ADVERTISE, phy, x )
731 #define SMC_SET_PHY_MII_ADV(phy,x) SMC_SET_MII( MII_ADVERTISE, phy, x )
732 #define SMC_GET_PHY_MII_LPA(phy,x) SMC_GET_MII( MII_LPA, phy, x )
733 #define SMC_SET_PHY_MII_LPA(phy,x) SMC_SET_MII( MII_LPA, phy, x )
734 #define SMC_GET_PHY_CTRL_STS(phy,x) SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x )
735 #define SMC_SET_PHY_CTRL_STS(phy,x) SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x )
736 #define SMC_GET_PHY_INT_SRC(phy,x) SMC_GET_MII( PHY_INT_SRC, phy, x )
737 #define SMC_SET_PHY_INT_SRC(phy,x) SMC_SET_MII( PHY_INT_SRC, phy, x )
738 #define SMC_GET_PHY_INT_MASK(phy,x) SMC_GET_MII( PHY_INT_MASK, phy, x )
739 #define SMC_SET_PHY_INT_MASK(phy,x) SMC_SET_MII( PHY_INT_MASK, phy, x )
740 #define SMC_GET_PHY_SPECIAL(phy,x) SMC_GET_MII( PHY_SPECIAL, phy, x )
744 /* Misc read/write macros */
746 #ifndef SMC_GET_MAC_ADDR
747 #define SMC_GET_MAC_ADDR(addr) \
751 SMC_GET_MAC_CSR(ADDRL, __v); \
752 addr[0] = __v; addr[1] = __v >> 8; \
753 addr[2] = __v >> 16; addr[3] = __v >> 24; \
754 SMC_GET_MAC_CSR(ADDRH, __v); \
755 addr[4] = __v; addr[5] = __v >> 8; \
759 #define SMC_SET_MAC_ADDR(addr) \
761 SMC_SET_MAC_CSR(ADDRL, \
766 SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\
770 #define SMC_WRITE_EEPROM_CMD(cmd, addr) \
772 while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
773 SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a ); \
774 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
777 #endif /* _SMC911X_H_ */