drivers/net/smc911x.h

   1 /*------------------------------------------------------------------------
   2  . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
   3  .
   4  . Copyright (C) 2005 Sensoria Corp.
   5  . Derived from the unified SMC91x driver by Nicolas Pitre
   6  .
   7  . This program is free software; you can redistribute it and/or modify
   8  . it under the terms of the GNU General Public License as published by
   9  . the Free Software Foundation; either version 2 of the License, or
  10  . (at your option) any later version.
  11  .
  12  . This program is distributed in the hope that it will be useful,
  13  . but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  . GNU General Public License for more details.
  16  .
  17  . You should have received a copy of the GNU General Public License
  18  . along with this program; if not, write to the Free Software
  19  . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  .
  21  . Information contained in this file was obtained from the LAN9118
  22  . manual from SMC.  To get a copy, if you really want one, you can find
  23  . information under www.smsc.com.
  24  .
  25  . Authors
  26  .       Dustin McIntire                 <dustin@sensoria.com>
  27  .
  28  ---------------------------------------------------------------------------*/
  29 #ifndef _SMC911X_H_
  30 #define _SMC911X_H_
  31
  32 /*
  33  * Use the DMA feature on PXA chips
  34  */
  35 #ifdef CONFIG_ARCH_PXA
  36   #define SMC_USE_PXA_DMA       1
  37   #define SMC_USE_16BIT         0
  38   #define SMC_USE_32BIT         1
  39   #define SMC_IRQ_SENSE         IRQF_TRIGGER_FALLING
  40 #elif defined(CONFIG_SH_MAGIC_PANEL_R2)
  41   #define SMC_USE_SH_DMA        0
  42   #define SMC_USE_16BIT         0
  43   #define SMC_USE_32BIT         1
  44   #define SMC_IRQ_SENSE         IRQF_TRIGGER_LOW
  45 #endif
  46
  47 /* store this information for the driver.. */
  48 struct smc911x_local {
  49         /*
  50          * If I have to wait until the DMA is finished and ready to reload a
  51          * packet, I will store the skbuff here. Then, the DMA will send it
  52          * out and free it.
  53          */
  54         struct sk_buff *pending_tx_skb;
  55
  56         /* version/revision of the SMC911x chip */
  57         u16 version;
  58         u16 revision;
  59
  60         /* FIFO sizes */
  61         int tx_fifo_kb;
  62         int tx_fifo_size;
  63         int rx_fifo_size;
  64         int afc_cfg;
  65
  66         /* Contains the current active receive/phy mode */
  67         int ctl_rfduplx;
  68         int ctl_rspeed;
  69
  70         u32 msg_enable;
  71         u32 phy_type;
  72         struct mii_if_info mii;
  73
  74         /* work queue */
  75         struct work_struct phy_configure;
  76         int work_pending;
  77
  78         int tx_throttle;
  79         spinlock_t lock;
  80
  81         struct net_device *netdev;
  82
  83 #ifdef SMC_USE_DMA
  84         /* DMA needs the physical address of the chip */
  85         u_long physaddr;
  86         int rxdma;
  87         int txdma;
  88         int rxdma_active;
  89         int txdma_active;
  90         struct sk_buff *current_rx_skb;
  91         struct sk_buff *current_tx_skb;
  92         struct device *dev;
  93 #endif
  94         void __iomem *base;
  95 };
  96
  97 /*
  98  * Define the bus width specific IO macros
  99  */
 100
 101 #if     SMC_USE_16BIT
 102 #define SMC_inl(lp, r)           ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
 103 #define SMC_outl(v, lp, r)                       \
 104         do{                                      \
 105                  writew(v & 0xFFFF, (lp)->base + (r));   \
 106                  writew(v >> 16, (lp)->base + (r) + 2); \
 107          } while (0)
 108 #define SMC_insl(lp, r, p, l)    readsw((short*)((lp)->base + (r)), p, l*2)
 109 #define SMC_outsl(lp, r, p, l)   writesw((short*)((lp)->base + (r)), p, l*2)
 110
 111 #elif   SMC_USE_32BIT
 112 #define SMC_inl(lp, r)           readl((lp)->base + (r))
 113 #define SMC_outl(v, lp, r)       writel(v, (lp)->base + (r))
 114 #define SMC_insl(lp, r, p, l)    readsl((int*)((lp)->base + (r)), p, l)
 115 #define SMC_outsl(lp, r, p, l)   writesl((int*)((lp)->base + (r)), p, l)
 116
 117 #endif /* SMC_USE_16BIT */
 118
 119 #ifdef SMC_USE_PXA_DMA
 120 #define SMC_USE_DMA
 121
 122 /*
 123  * Define the request and free functions
 124  * These are unfortunately architecture specific as no generic allocation
 125  * mechanism exits
 126  */
 127 #define SMC_DMA_REQUEST(dev, handler) \
 128          pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
 129
 130 #define SMC_DMA_FREE(dev, dma) \
 131          pxa_free_dma(dma)
 132
 133 #define SMC_DMA_ACK_IRQ(dev, dma)                                       \
 134 {                                                                       \
 135         if (DCSR(dma) & DCSR_BUSERR) {                                  \
 136                 printk("%s: DMA %d bus error!\n", dev->name, dma);      \
 137         }                                                               \
 138         DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;            \
 139 }
 140
 141 /*
 142  * Use a DMA for RX and TX packets.
 143  */
 144 #include <linux/dma-mapping.h>
 145 #include <asm/dma.h>
 146 #include <asm/arch/pxa-regs.h>
 147
 148 static dma_addr_t rx_dmabuf, tx_dmabuf;
 149 static int rx_dmalen, tx_dmalen;
 150
 151 #ifdef SMC_insl
 152 #undef SMC_insl
 153 #define SMC_insl(lp, r, p, l) \
 154         smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
 155
 156 static inline void
 157 smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
 158                 int reg, int dma, u_char *buf, int len)
 159 {
 160         /* 64 bit alignment is required for memory to memory DMA */
 161         if ((long)buf & 4) {
 162                 *((u32 *)buf) = SMC_inl(lp, reg);
 163                 buf += 4;
 164                 len--;
 165         }
 166
 167         len *= 4;
 168         rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
 169         rx_dmalen = len;
 170         DCSR(dma) = DCSR_NODESC;
 171         DTADR(dma) = rx_dmabuf;
 172         DSADR(dma) = physaddr + reg;
 173         DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
 174                 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
 175         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 176 }
 177 #endif
 178
 179 #ifdef SMC_outsl
 180 #undef SMC_outsl
 181 #define SMC_outsl(lp, r, p, l) \
 182          smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
 183
 184 static inline void
 185 smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
 186                 int reg, int dma, u_char *buf, int len)
 187 {
 188         /* 64 bit alignment is required for memory to memory DMA */
 189         if ((long)buf & 4) {
 190                 SMC_outl(*((u32 *)buf), lp, reg);
 191                 buf += 4;
 192                 len--;
 193         }
 194
 195         len *= 4;
 196         tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
 197         tx_dmalen = len;
 198         DCSR(dma) = DCSR_NODESC;
 199         DSADR(dma) = tx_dmabuf;
 200         DTADR(dma) = physaddr + reg;
 201         DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
 202                 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
 203         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 204 }
 205 #endif
 206 #endif   /* SMC_USE_PXA_DMA */
 207
 208
 209 /* Chip Parameters and Register Definitions */
 210
 211 #define SMC911X_TX_FIFO_LOW_THRESHOLD   (1536*2)
 212
 213 #define SMC911X_IO_EXTENT        0x100
 214
 215 #define SMC911X_EEPROM_LEN       7
 216
 217 /* Below are the register offsets and bit definitions
 218  * of the Lan911x memory space
 219  */
 220 #define RX_DATA_FIFO             (0x00)
 221
 222 #define TX_DATA_FIFO             (0x20)
 223 #define TX_CMD_A_INT_ON_COMP_           (0x80000000)
 224 #define TX_CMD_A_INT_BUF_END_ALGN_      (0x03000000)
 225 #define TX_CMD_A_INT_4_BYTE_ALGN_       (0x00000000)
 226 #define TX_CMD_A_INT_16_BYTE_ALGN_      (0x01000000)
 227 #define TX_CMD_A_INT_32_BYTE_ALGN_      (0x02000000)
 228 #define TX_CMD_A_INT_DATA_OFFSET_       (0x001F0000)
 229 #define TX_CMD_A_INT_FIRST_SEG_         (0x00002000)
 230 #define TX_CMD_A_INT_LAST_SEG_          (0x00001000)
 231 #define TX_CMD_A_BUF_SIZE_              (0x000007FF)
 232 #define TX_CMD_B_PKT_TAG_               (0xFFFF0000)
 233 #define TX_CMD_B_ADD_CRC_DISABLE_       (0x00002000)
 234 #define TX_CMD_B_DISABLE_PADDING_       (0x00001000)
 235 #define TX_CMD_B_PKT_BYTE_LENGTH_       (0x000007FF)
 236
 237 #define RX_STATUS_FIFO          (0x40)
 238 #define RX_STS_PKT_LEN_                 (0x3FFF0000)
 239 #define RX_STS_ES_                      (0x00008000)
 240 #define RX_STS_BCST_                    (0x00002000)
 241 #define RX_STS_LEN_ERR_                 (0x00001000)
 242 #define RX_STS_RUNT_ERR_                (0x00000800)
 243 #define RX_STS_MCAST_                   (0x00000400)
 244 #define RX_STS_TOO_LONG_                (0x00000080)
 245 #define RX_STS_COLL_                    (0x00000040)
 246 #define RX_STS_ETH_TYPE_                (0x00000020)
 247 #define RX_STS_WDOG_TMT_                (0x00000010)
 248 #define RX_STS_MII_ERR_                 (0x00000008)
 249 #define RX_STS_DRIBBLING_               (0x00000004)
 250 #define RX_STS_CRC_ERR_                 (0x00000002)
 251 #define RX_STATUS_FIFO_PEEK     (0x44)
 252 #define TX_STATUS_FIFO          (0x48)
 253 #define TX_STS_TAG_                     (0xFFFF0000)
 254 #define TX_STS_ES_                      (0x00008000)
 255 #define TX_STS_LOC_                     (0x00000800)
 256 #define TX_STS_NO_CARR_                 (0x00000400)
 257 #define TX_STS_LATE_COLL_               (0x00000200)
 258 #define TX_STS_MANY_COLL_               (0x00000100)
 259 #define TX_STS_COLL_CNT_                (0x00000078)
 260 #define TX_STS_MANY_DEFER_              (0x00000004)
 261 #define TX_STS_UNDERRUN_                (0x00000002)
 262 #define TX_STS_DEFERRED_                (0x00000001)
 263 #define TX_STATUS_FIFO_PEEK     (0x4C)
 264 #define ID_REV                  (0x50)
 265 #define ID_REV_CHIP_ID_                 (0xFFFF0000)  /* RO */
 266 #define ID_REV_REV_ID_                  (0x0000FFFF)  /* RO */
 267
 268 #define INT_CFG                 (0x54)
 269 #define INT_CFG_INT_DEAS_               (0xFF000000)  /* R/W */
 270 #define INT_CFG_INT_DEAS_CLR_           (0x00004000)
 271 #define INT_CFG_INT_DEAS_STS_           (0x00002000)
 272 #define INT_CFG_IRQ_INT_                (0x00001000)  /* RO */
 273 #define INT_CFG_IRQ_EN_                 (0x00000100)  /* R/W */
 274 #define INT_CFG_IRQ_POL_                (0x00000010)  /* R/W Not Affected by SW Reset */
 275 #define INT_CFG_IRQ_TYPE_               (0x00000001)  /* R/W Not Affected by SW Reset */
 276
 277 #define INT_STS                 (0x58)
 278 #define INT_STS_SW_INT_                 (0x80000000)  /* R/WC */
 279 #define INT_STS_TXSTOP_INT_             (0x02000000)  /* R/WC */
 280 #define INT_STS_RXSTOP_INT_             (0x01000000)  /* R/WC */
 281 #define INT_STS_RXDFH_INT_              (0x00800000)  /* R/WC */
 282 #define INT_STS_RXDF_INT_               (0x00400000)  /* R/WC */
 283 #define INT_STS_TX_IOC_                 (0x00200000)  /* R/WC */
 284 #define INT_STS_RXD_INT_                (0x00100000)  /* R/WC */
 285 #define INT_STS_GPT_INT_                (0x00080000)  /* R/WC */
 286 #define INT_STS_PHY_INT_                (0x00040000)  /* RO */
 287 #define INT_STS_PME_INT_                (0x00020000)  /* R/WC */
 288 #define INT_STS_TXSO_                   (0x00010000)  /* R/WC */
 289 #define INT_STS_RWT_                    (0x00008000)  /* R/WC */
 290 #define INT_STS_RXE_                    (0x00004000)  /* R/WC */
 291 #define INT_STS_TXE_                    (0x00002000)  /* R/WC */
 292 //#define       INT_STS_ERX_            (0x00001000)  /* R/WC */
 293 #define INT_STS_TDFU_                   (0x00000800)  /* R/WC */
 294 #define INT_STS_TDFO_                   (0x00000400)  /* R/WC */
 295 #define INT_STS_TDFA_                   (0x00000200)  /* R/WC */
 296 #define INT_STS_TSFF_                   (0x00000100)  /* R/WC */
 297 #define INT_STS_TSFL_                   (0x00000080)  /* R/WC */
 298 //#define       INT_STS_RXDF_           (0x00000040)  /* R/WC */
 299 #define INT_STS_RDFO_                   (0x00000040)  /* R/WC */
 300 #define INT_STS_RDFL_                   (0x00000020)  /* R/WC */
 301 #define INT_STS_RSFF_                   (0x00000010)  /* R/WC */
 302 #define INT_STS_RSFL_                   (0x00000008)  /* R/WC */
 303 #define INT_STS_GPIO2_INT_              (0x00000004)  /* R/WC */
 304 #define INT_STS_GPIO1_INT_              (0x00000002)  /* R/WC */
 305 #define INT_STS_GPIO0_INT_              (0x00000001)  /* R/WC */
 306
 307 #define INT_EN                  (0x5C)
 308 #define INT_EN_SW_INT_EN_               (0x80000000)  /* R/W */
 309 #define INT_EN_TXSTOP_INT_EN_           (0x02000000)  /* R/W */
 310 #define INT_EN_RXSTOP_INT_EN_           (0x01000000)  /* R/W */
 311 #define INT_EN_RXDFH_INT_EN_            (0x00800000)  /* R/W */
 312 //#define       INT_EN_RXDF_INT_EN_             (0x00400000)  /* R/W */
 313 #define INT_EN_TIOC_INT_EN_             (0x00200000)  /* R/W */
 314 #define INT_EN_RXD_INT_EN_              (0x00100000)  /* R/W */
 315 #define INT_EN_GPT_INT_EN_              (0x00080000)  /* R/W */
 316 #define INT_EN_PHY_INT_EN_              (0x00040000)  /* R/W */
 317 #define INT_EN_PME_INT_EN_              (0x00020000)  /* R/W */
 318 #define INT_EN_TXSO_EN_                 (0x00010000)  /* R/W */
 319 #define INT_EN_RWT_EN_                  (0x00008000)  /* R/W */
 320 #define INT_EN_RXE_EN_                  (0x00004000)  /* R/W */
 321 #define INT_EN_TXE_EN_                  (0x00002000)  /* R/W */
 322 //#define       INT_EN_ERX_EN_                  (0x00001000)  /* R/W */
 323 #define INT_EN_TDFU_EN_                 (0x00000800)  /* R/W */
 324 #define INT_EN_TDFO_EN_                 (0x00000400)  /* R/W */
 325 #define INT_EN_TDFA_EN_                 (0x00000200)  /* R/W */
 326 #define INT_EN_TSFF_EN_                 (0x00000100)  /* R/W */
 327 #define INT_EN_TSFL_EN_                 (0x00000080)  /* R/W */
 328 //#define       INT_EN_RXDF_EN_                 (0x00000040)  /* R/W */
 329 #define INT_EN_RDFO_EN_                 (0x00000040)  /* R/W */
 330 #define INT_EN_RDFL_EN_                 (0x00000020)  /* R/W */
 331 #define INT_EN_RSFF_EN_                 (0x00000010)  /* R/W */
 332 #define INT_EN_RSFL_EN_                 (0x00000008)  /* R/W */
 333 #define INT_EN_GPIO2_INT_               (0x00000004)  /* R/W */
 334 #define INT_EN_GPIO1_INT_               (0x00000002)  /* R/W */
 335 #define INT_EN_GPIO0_INT_               (0x00000001)  /* R/W */
 336
 337 #define BYTE_TEST               (0x64)
 338 #define FIFO_INT                (0x68)
 339 #define FIFO_INT_TX_AVAIL_LEVEL_        (0xFF000000)  /* R/W */
 340 #define FIFO_INT_TX_STS_LEVEL_          (0x00FF0000)  /* R/W */
 341 #define FIFO_INT_RX_AVAIL_LEVEL_        (0x0000FF00)  /* R/W */
 342 #define FIFO_INT_RX_STS_LEVEL_          (0x000000FF)  /* R/W */
 343
 344 #define RX_CFG                  (0x6C)
 345 #define RX_CFG_RX_END_ALGN_             (0xC0000000)  /* R/W */
 346 #define         RX_CFG_RX_END_ALGN4_            (0x00000000)  /* R/W */
 347 #define         RX_CFG_RX_END_ALGN16_           (0x40000000)  /* R/W */
 348 #define         RX_CFG_RX_END_ALGN32_           (0x80000000)  /* R/W */
 349 #define RX_CFG_RX_DMA_CNT_              (0x0FFF0000)  /* R/W */
 350 #define RX_CFG_RX_DUMP_                 (0x00008000)  /* R/W */
 351 #define RX_CFG_RXDOFF_                  (0x00001F00)  /* R/W */
 352 //#define       RX_CFG_RXBAD_                   (0x00000001)  /* R/W */
 353
 354 #define TX_CFG                  (0x70)
 355 //#define       TX_CFG_TX_DMA_LVL_              (0xE0000000)     /* R/W */
 356 //#define       TX_CFG_TX_DMA_CNT_              (0x0FFF0000)     /* R/W Self Clearing */
 357 #define TX_CFG_TXS_DUMP_                (0x00008000)  /* Self Clearing */
 358 #define TX_CFG_TXD_DUMP_                (0x00004000)  /* Self Clearing */
 359 #define TX_CFG_TXSAO_                   (0x00000004)  /* R/W */
 360 #define TX_CFG_TX_ON_                   (0x00000002)  /* R/W */
 361 #define TX_CFG_STOP_TX_                 (0x00000001)  /* Self Clearing */
 362
 363 #define HW_CFG                  (0x74)
 364 #define HW_CFG_TTM_                     (0x00200000)  /* R/W */
 365 #define HW_CFG_SF_                      (0x00100000)  /* R/W */
 366 #define HW_CFG_TX_FIF_SZ_               (0x000F0000)  /* R/W */
 367 #define HW_CFG_TR_                      (0x00003000)  /* R/W */
 368 #define HW_CFG_PHY_CLK_SEL_             (0x00000060)  /* R/W */
 369 #define          HW_CFG_PHY_CLK_SEL_INT_PHY_    (0x00000000) /* R/W */
 370 #define          HW_CFG_PHY_CLK_SEL_EXT_PHY_    (0x00000020) /* R/W */
 371 #define          HW_CFG_PHY_CLK_SEL_CLK_DIS_    (0x00000040) /* R/W */
 372 #define HW_CFG_SMI_SEL_                 (0x00000010)  /* R/W */
 373 #define HW_CFG_EXT_PHY_DET_             (0x00000008)  /* RO */
 374 #define HW_CFG_EXT_PHY_EN_              (0x00000004)  /* R/W */
 375 #define HW_CFG_32_16_BIT_MODE_          (0x00000004)  /* RO */
 376 #define HW_CFG_SRST_TO_                 (0x00000002)  /* RO */
 377 #define HW_CFG_SRST_                    (0x00000001)  /* Self Clearing */
 378
 379 #define RX_DP_CTRL              (0x78)
 380 #define RX_DP_CTRL_RX_FFWD_             (0x80000000)  /* R/W */
 381 #define RX_DP_CTRL_FFWD_BUSY_           (0x80000000)  /* RO */
 382
 383 #define RX_FIFO_INF             (0x7C)
 384 #define  RX_FIFO_INF_RXSUSED_           (0x00FF0000)  /* RO */
 385 #define  RX_FIFO_INF_RXDUSED_           (0x0000FFFF)  /* RO */
 386
 387 #define TX_FIFO_INF             (0x80)
 388 #define TX_FIFO_INF_TSUSED_             (0x00FF0000)  /* RO */
 389 #define TX_FIFO_INF_TDFREE_             (0x0000FFFF)  /* RO */
 390
 391 #define PMT_CTRL                (0x84)
 392 #define PMT_CTRL_PM_MODE_               (0x00003000)  /* Self Clearing */
 393 #define PMT_CTRL_PHY_RST_               (0x00000400)  /* Self Clearing */
 394 #define PMT_CTRL_WOL_EN_                (0x00000200)  /* R/W */
 395 #define PMT_CTRL_ED_EN_                 (0x00000100)  /* R/W */
 396 #define PMT_CTRL_PME_TYPE_              (0x00000040)  /* R/W Not Affected by SW Reset */
 397 #define PMT_CTRL_WUPS_                  (0x00000030)  /* R/WC */
 398 #define         PMT_CTRL_WUPS_NOWAKE_           (0x00000000)  /* R/WC */
 399 #define         PMT_CTRL_WUPS_ED_               (0x00000010)  /* R/WC */
 400 #define         PMT_CTRL_WUPS_WOL_              (0x00000020)  /* R/WC */
 401 #define         PMT_CTRL_WUPS_MULTI_            (0x00000030)  /* R/WC */
 402 #define PMT_CTRL_PME_IND_               (0x00000008)  /* R/W */
 403 #define PMT_CTRL_PME_POL_               (0x00000004)  /* R/W */
 404 #define PMT_CTRL_PME_EN_                (0x00000002)  /* R/W Not Affected by SW Reset */
 405 #define PMT_CTRL_READY_                 (0x00000001)  /* RO */
 406
 407 #define GPIO_CFG                (0x88)
 408 #define GPIO_CFG_LED3_EN_               (0x40000000)  /* R/W */
 409 #define GPIO_CFG_LED2_EN_               (0x20000000)  /* R/W */
 410 #define GPIO_CFG_LED1_EN_               (0x10000000)  /* R/W */
 411 #define GPIO_CFG_GPIO2_INT_POL_         (0x04000000)  /* R/W */
 412 #define GPIO_CFG_GPIO1_INT_POL_         (0x02000000)  /* R/W */
 413 #define GPIO_CFG_GPIO0_INT_POL_         (0x01000000)  /* R/W */
 414 #define GPIO_CFG_EEPR_EN_               (0x00700000)  /* R/W */
 415 #define GPIO_CFG_GPIOBUF2_              (0x00040000)  /* R/W */
 416 #define GPIO_CFG_GPIOBUF1_              (0x00020000)  /* R/W */
 417 #define GPIO_CFG_GPIOBUF0_              (0x00010000)  /* R/W */
 418 #define GPIO_CFG_GPIODIR2_              (0x00000400)  /* R/W */
 419 #define GPIO_CFG_GPIODIR1_              (0x00000200)  /* R/W */
 420 #define GPIO_CFG_GPIODIR0_              (0x00000100)  /* R/W */
 421 #define GPIO_CFG_GPIOD4_                (0x00000010)  /* R/W */
 422 #define GPIO_CFG_GPIOD3_                (0x00000008)  /* R/W */
 423 #define GPIO_CFG_GPIOD2_                (0x00000004)  /* R/W */
 424 #define GPIO_CFG_GPIOD1_                (0x00000002)  /* R/W */
 425 #define GPIO_CFG_GPIOD0_                (0x00000001)  /* R/W */
 426
 427 #define GPT_CFG                 (0x8C)
 428 #define GPT_CFG_TIMER_EN_               (0x20000000)  /* R/W */
 429 #define GPT_CFG_GPT_LOAD_               (0x0000FFFF)  /* R/W */
 430
 431 #define GPT_CNT                 (0x90)
 432 #define GPT_CNT_GPT_CNT_                (0x0000FFFF)  /* RO */
 433
 434 #define ENDIAN                  (0x98)
 435 #define FREE_RUN                (0x9C)
 436 #define RX_DROP                 (0xA0)
 437 #define MAC_CSR_CMD             (0xA4)
 438 #define  MAC_CSR_CMD_CSR_BUSY_          (0x80000000)  /* Self Clearing */
 439 #define  MAC_CSR_CMD_R_NOT_W_           (0x40000000)  /* R/W */
 440 #define  MAC_CSR_CMD_CSR_ADDR_          (0x000000FF)  /* R/W */
 441
 442 #define MAC_CSR_DATA            (0xA8)
 443 #define AFC_CFG                 (0xAC)
 444 #define         AFC_CFG_AFC_HI_                 (0x00FF0000)  /* R/W */
 445 #define         AFC_CFG_AFC_LO_                 (0x0000FF00)  /* R/W */
 446 #define         AFC_CFG_BACK_DUR_               (0x000000F0)  /* R/W */
 447 #define         AFC_CFG_FCMULT_                 (0x00000008)  /* R/W */
 448 #define         AFC_CFG_FCBRD_                  (0x00000004)  /* R/W */
 449 #define         AFC_CFG_FCADD_                  (0x00000002)  /* R/W */
 450 #define         AFC_CFG_FCANY_                  (0x00000001)  /* R/W */
 451
 452 #define E2P_CMD                 (0xB0)
 453 #define E2P_CMD_EPC_BUSY_               (0x80000000)  /* Self Clearing */
 454 #define E2P_CMD_EPC_CMD_                        (0x70000000)  /* R/W */
 455 #define         E2P_CMD_EPC_CMD_READ_           (0x00000000)  /* R/W */
 456 #define         E2P_CMD_EPC_CMD_EWDS_           (0x10000000)  /* R/W */
 457 #define         E2P_CMD_EPC_CMD_EWEN_           (0x20000000)  /* R/W */
 458 #define         E2P_CMD_EPC_CMD_WRITE_          (0x30000000)  /* R/W */
 459 #define         E2P_CMD_EPC_CMD_WRAL_           (0x40000000)  /* R/W */
 460 #define         E2P_CMD_EPC_CMD_ERASE_          (0x50000000)  /* R/W */
 461 #define         E2P_CMD_EPC_CMD_ERAL_           (0x60000000)  /* R/W */
 462 #define         E2P_CMD_EPC_CMD_RELOAD_         (0x70000000)  /* R/W */
 463 #define E2P_CMD_EPC_TIMEOUT_            (0x00000200)  /* RO */
 464 #define E2P_CMD_MAC_ADDR_LOADED_        (0x00000100)  /* RO */
 465 #define E2P_CMD_EPC_ADDR_               (0x000000FF)  /* R/W */
 466
 467 #define E2P_DATA                (0xB4)
 468 #define E2P_DATA_EEPROM_DATA_           (0x000000FF)  /* R/W */
 469 /* end of LAN register offsets and bit definitions */
 470
 471 /*
 472  ****************************************************************************
 473  ****************************************************************************
 474  * MAC Control and Status Register (Indirect Address)
 475  * Offset (through the MAC_CSR CMD and DATA port)
 476  ****************************************************************************
 477  ****************************************************************************
 478  *
 479  */
 480 #define MAC_CR                  (0x01)  /* R/W */
 481
 482 /* MAC_CR - MAC Control Register */
 483 #define MAC_CR_RXALL_                   (0x80000000)
 484 // TODO: delete this bit? It is not described in the data sheet.
 485 #define MAC_CR_HBDIS_                   (0x10000000)
 486 #define MAC_CR_RCVOWN_                  (0x00800000)
 487 #define MAC_CR_LOOPBK_                  (0x00200000)
 488 #define MAC_CR_FDPX_                    (0x00100000)
 489 #define MAC_CR_MCPAS_                   (0x00080000)
 490 #define MAC_CR_PRMS_                    (0x00040000)
 491 #define MAC_CR_INVFILT_                 (0x00020000)
 492 #define MAC_CR_PASSBAD_                 (0x00010000)
 493 #define MAC_CR_HFILT_                   (0x00008000)
 494 #define MAC_CR_HPFILT_                  (0x00002000)
 495 #define MAC_CR_LCOLL_                   (0x00001000)
 496 #define MAC_CR_BCAST_                   (0x00000800)
 497 #define MAC_CR_DISRTY_                  (0x00000400)
 498 #define MAC_CR_PADSTR_                  (0x00000100)
 499 #define MAC_CR_BOLMT_MASK_              (0x000000C0)
 500 #define MAC_CR_DFCHK_                   (0x00000020)
 501 #define MAC_CR_TXEN_                    (0x00000008)
 502 #define MAC_CR_RXEN_                    (0x00000004)
 503
 504 #define ADDRH                   (0x02)    /* R/W mask 0x0000FFFFUL */
 505 #define ADDRL                   (0x03)    /* R/W mask 0xFFFFFFFFUL */
 506 #define HASHH                   (0x04)    /* R/W */
 507 #define HASHL                   (0x05)    /* R/W */
 508
 509 #define MII_ACC                 (0x06)    /* R/W */
 510 #define MII_ACC_PHY_ADDR_               (0x0000F800)
 511 #define MII_ACC_MIIRINDA_               (0x000007C0)
 512 #define MII_ACC_MII_WRITE_              (0x00000002)
 513 #define MII_ACC_MII_BUSY_               (0x00000001)
 514
 515 #define MII_DATA                (0x07)    /* R/W mask 0x0000FFFFUL */
 516
 517 #define FLOW                    (0x08)    /* R/W */
 518 #define FLOW_FCPT_                      (0xFFFF0000)
 519 #define FLOW_FCPASS_                    (0x00000004)
 520 #define FLOW_FCEN_                      (0x00000002)
 521 #define FLOW_FCBSY_                     (0x00000001)
 522
 523 #define VLAN1                   (0x09)    /* R/W mask 0x0000FFFFUL */
 524 #define VLAN1_VTI1_                     (0x0000ffff)
 525
 526 #define VLAN2                   (0x0A)    /* R/W mask 0x0000FFFFUL */
 527 #define VLAN2_VTI2_                     (0x0000ffff)
 528
 529 #define WUFF                    (0x0B)    /* WO */
 530
 531 #define WUCSR                   (0x0C)    /* R/W */
 532 #define WUCSR_GUE_                      (0x00000200)
 533 #define WUCSR_WUFR_                     (0x00000040)
 534 #define WUCSR_MPR_                      (0x00000020)
 535 #define WUCSR_WAKE_EN_                  (0x00000004)
 536 #define WUCSR_MPEN_                     (0x00000002)
 537
 538 /*
 539  ****************************************************************************
 540  * Chip Specific MII Defines
 541  ****************************************************************************
 542  *
 543  * Phy register offsets and bit definitions
 544  *
 545  */
 546
 547 #define PHY_MODE_CTRL_STS       ((u32)17)       /* Mode Control/Status Register */
 548 //#define MODE_CTRL_STS_FASTRIP_          ((u16)0x4000)
 549 #define MODE_CTRL_STS_EDPWRDOWN_         ((u16)0x2000)
 550 //#define MODE_CTRL_STS_LOWSQEN_           ((u16)0x0800)
 551 //#define MODE_CTRL_STS_MDPREBP_           ((u16)0x0400)
 552 //#define MODE_CTRL_STS_FARLOOPBACK_  ((u16)0x0200)
 553 //#define MODE_CTRL_STS_FASTEST_           ((u16)0x0100)
 554 //#define MODE_CTRL_STS_REFCLKEN_          ((u16)0x0010)
 555 //#define MODE_CTRL_STS_PHYADBP_           ((u16)0x0008)
 556 //#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
 557 #define MODE_CTRL_STS_ENERGYON_         ((u16)0x0002)
 558
 559 #define PHY_INT_SRC                     ((u32)29)
 560 #define PHY_INT_SRC_ENERGY_ON_                  ((u16)0x0080)
 561 #define PHY_INT_SRC_ANEG_COMP_                  ((u16)0x0040)
 562 #define PHY_INT_SRC_REMOTE_FAULT_               ((u16)0x0020)
 563 #define PHY_INT_SRC_LINK_DOWN_                  ((u16)0x0010)
 564 #define PHY_INT_SRC_ANEG_LP_ACK_                ((u16)0x0008)
 565 #define PHY_INT_SRC_PAR_DET_FAULT_              ((u16)0x0004)
 566 #define PHY_INT_SRC_ANEG_PGRX_                  ((u16)0x0002)
 567
 568 #define PHY_INT_MASK                    ((u32)30)
 569 #define PHY_INT_MASK_ENERGY_ON_                 ((u16)0x0080)
 570 #define PHY_INT_MASK_ANEG_COMP_                 ((u16)0x0040)
 571 #define PHY_INT_MASK_REMOTE_FAULT_              ((u16)0x0020)
 572 #define PHY_INT_MASK_LINK_DOWN_                 ((u16)0x0010)
 573 #define PHY_INT_MASK_ANEG_LP_ACK_               ((u16)0x0008)
 574 #define PHY_INT_MASK_PAR_DET_FAULT_             ((u16)0x0004)
 575 #define PHY_INT_MASK_ANEG_PGRX_                 ((u16)0x0002)
 576
 577 #define PHY_SPECIAL                     ((u32)31)
 578 #define PHY_SPECIAL_ANEG_DONE_                  ((u16)0x1000)
 579 #define PHY_SPECIAL_RES_                        ((u16)0x0040)
 580 #define PHY_SPECIAL_RES_MASK_                   ((u16)0x0FE1)
 581 #define PHY_SPECIAL_SPD_                        ((u16)0x001C)
 582 #define PHY_SPECIAL_SPD_10HALF_                 ((u16)0x0004)
 583 #define PHY_SPECIAL_SPD_10FULL_                 ((u16)0x0014)
 584 #define PHY_SPECIAL_SPD_100HALF_                ((u16)0x0008)
 585 #define PHY_SPECIAL_SPD_100FULL_                ((u16)0x0018)
 586
 587 #define LAN911X_INTERNAL_PHY_ID         (0x0007C000)
 588
 589 /* Chip ID values */
 590 #define CHIP_9115       0x115
 591 #define CHIP_9116       0x116
 592 #define CHIP_9117       0x117
 593 #define CHIP_9118       0x118
 594
 595 struct chip_id {
 596         u16 id;
 597         char *name;
 598 };
 599
 600 static const struct chip_id chip_ids[] =  {
 601         { CHIP_9115, "LAN9115" },
 602         { CHIP_9116, "LAN9116" },
 603         { CHIP_9117, "LAN9117" },
 604         { CHIP_9118, "LAN9118" },
 605         { 0, NULL },
 606 };
 607
 608 #define IS_REV_A(x)     ((x & 0xFFFF)==0)
 609
 610 /*
 611  * Macros to abstract register access according to the data bus
 612  * capabilities.  Please use those and not the in/out primitives.
 613  */
 614 /* FIFO read/write macros */
 615 #define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
 616 #define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
 617 #define SMC_SET_TX_FIFO(lp, x)  SMC_outl( x, lp, TX_DATA_FIFO )
 618 #define SMC_GET_RX_FIFO(lp)     SMC_inl( lp, RX_DATA_FIFO )
 619
 620
 621 /* I/O mapped register read/write macros */
 622 #define SMC_GET_TX_STS_FIFO(lp)         SMC_inl( lp, TX_STATUS_FIFO )
 623 #define SMC_GET_RX_STS_FIFO(lp)         SMC_inl( lp, RX_STATUS_FIFO )
 624 #define SMC_GET_RX_STS_FIFO_PEEK(lp)    SMC_inl( lp, RX_STATUS_FIFO_PEEK )
 625 #define SMC_GET_PN(lp)                  (SMC_inl( lp, ID_REV ) >> 16)
 626 #define SMC_GET_REV(lp)                 (SMC_inl( lp, ID_REV ) & 0xFFFF)
 627 #define SMC_GET_IRQ_CFG(lp)             SMC_inl( lp, INT_CFG )
 628 #define SMC_SET_IRQ_CFG(lp, x)          SMC_outl( x, lp, INT_CFG )
 629 #define SMC_GET_INT(lp)                 SMC_inl( lp, INT_STS )
 630 #define SMC_ACK_INT(lp, x)                      SMC_outl( x, lp, INT_STS )
 631 #define SMC_GET_INT_EN(lp)              SMC_inl( lp, INT_EN )
 632 #define SMC_SET_INT_EN(lp, x)           SMC_outl( x, lp, INT_EN )
 633 #define SMC_GET_BYTE_TEST(lp)           SMC_inl( lp, BYTE_TEST )
 634 #define SMC_SET_BYTE_TEST(lp, x)                SMC_outl( x, lp, BYTE_TEST )
 635 #define SMC_GET_FIFO_INT(lp)            SMC_inl( lp, FIFO_INT )
 636 #define SMC_SET_FIFO_INT(lp, x)         SMC_outl( x, lp, FIFO_INT )
 637 #define SMC_SET_FIFO_TDA(lp, x)                                 \
 638         do {                                                    \
 639                 unsigned long __flags;                          \
 640                 int __mask;                                     \
 641                 local_irq_save(__flags);                        \
 642                 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24);  \
 643                 SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 );     \
 644                 local_irq_restore(__flags);                     \
 645         } while (0)
 646 #define SMC_SET_FIFO_TSL(lp, x)                                 \
 647         do {                                                    \
 648                 unsigned long __flags;                          \
 649                 int __mask;                                     \
 650                 local_irq_save(__flags);                        \
 651                 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16);  \
 652                 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16));   \
 653                 local_irq_restore(__flags);                     \
 654         } while (0)
 655 #define SMC_SET_FIFO_RSA(lp, x)                                 \
 656         do {                                                    \
 657                 unsigned long __flags;                          \
 658                 int __mask;                                     \
 659                 local_irq_save(__flags);                        \
 660                 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8);   \
 661                 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8));    \
 662                 local_irq_restore(__flags);                     \
 663         } while (0)
 664 #define SMC_SET_FIFO_RSL(lp, x)                                 \
 665         do {                                                    \
 666                 unsigned long __flags;                          \
 667                 int __mask;                                     \
 668                 local_irq_save(__flags);                        \
 669                 __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF;        \
 670                 SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF));  \
 671                 local_irq_restore(__flags);                     \
 672         } while (0)
 673 #define SMC_GET_RX_CFG(lp)              SMC_inl( lp, RX_CFG )
 674 #define SMC_SET_RX_CFG(lp, x)           SMC_outl( x, lp, RX_CFG )
 675 #define SMC_GET_TX_CFG(lp)              SMC_inl( lp, TX_CFG )
 676 #define SMC_SET_TX_CFG(lp, x)           SMC_outl( x, lp, TX_CFG )
 677 #define SMC_GET_HW_CFG(lp)              SMC_inl( lp, HW_CFG )
 678 #define SMC_SET_HW_CFG(lp, x)           SMC_outl( x, lp, HW_CFG )
 679 #define SMC_GET_RX_DP_CTRL(lp)          SMC_inl( lp, RX_DP_CTRL )
 680 #define SMC_SET_RX_DP_CTRL(lp, x)               SMC_outl( x, lp, RX_DP_CTRL )
 681 #define SMC_GET_PMT_CTRL(lp)            SMC_inl( lp, PMT_CTRL )
 682 #define SMC_SET_PMT_CTRL(lp, x)         SMC_outl( x, lp, PMT_CTRL )
 683 #define SMC_GET_GPIO_CFG(lp)            SMC_inl( lp, GPIO_CFG )
 684 #define SMC_SET_GPIO_CFG(lp, x)         SMC_outl( x, lp, GPIO_CFG )
 685 #define SMC_GET_RX_FIFO_INF(lp)         SMC_inl( lp, RX_FIFO_INF )
 686 #define SMC_SET_RX_FIFO_INF(lp, x)              SMC_outl( x, lp, RX_FIFO_INF )
 687 #define SMC_GET_TX_FIFO_INF(lp)         SMC_inl( lp, TX_FIFO_INF )
 688 #define SMC_SET_TX_FIFO_INF(lp, x)              SMC_outl( x, lp, TX_FIFO_INF )
 689 #define SMC_GET_GPT_CFG(lp)             SMC_inl( lp, GPT_CFG )
 690 #define SMC_SET_GPT_CFG(lp, x)          SMC_outl( x, lp, GPT_CFG )
 691 #define SMC_GET_RX_DROP(lp)             SMC_inl( lp, RX_DROP )
 692 #define SMC_SET_RX_DROP(lp, x)          SMC_outl( x, lp, RX_DROP )
 693 #define SMC_GET_MAC_CMD(lp)             SMC_inl( lp, MAC_CSR_CMD )
 694 #define SMC_SET_MAC_CMD(lp, x)          SMC_outl( x, lp, MAC_CSR_CMD )
 695 #define SMC_GET_MAC_DATA(lp)            SMC_inl( lp, MAC_CSR_DATA )
 696 #define SMC_SET_MAC_DATA(lp, x)         SMC_outl( x, lp, MAC_CSR_DATA )
 697 #define SMC_GET_AFC_CFG(lp)             SMC_inl( lp, AFC_CFG )
 698 #define SMC_SET_AFC_CFG(lp, x)          SMC_outl( x, lp, AFC_CFG )
 699 #define SMC_GET_E2P_CMD(lp)             SMC_inl( lp, E2P_CMD )
 700 #define SMC_SET_E2P_CMD(lp, x)          SMC_outl( x, lp, E2P_CMD )
 701 #define SMC_GET_E2P_DATA(lp)            SMC_inl( lp, E2P_DATA )
 702 #define SMC_SET_E2P_DATA(lp, x)         SMC_outl( x, lp, E2P_DATA )
 703
 704 /* MAC register read/write macros */
 705 #define SMC_GET_MAC_CSR(lp,a,v)                                         \
 706         do {                                                            \
 707                 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 708                 SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ |            \
 709                         MAC_CSR_CMD_R_NOT_W_ | (a) );                   \
 710                 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 711                 v = SMC_GET_MAC_DATA((lp));                             \
 712         } while (0)
 713 #define SMC_SET_MAC_CSR(lp,a,v)                                         \
 714         do {                                                            \
 715                 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 716                 SMC_SET_MAC_DATA((lp), v);                              \
 717                 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) );    \
 718                 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 719         } while (0)
 720 #define SMC_GET_MAC_CR(lp, x)   SMC_GET_MAC_CSR( (lp), MAC_CR, x )
 721 #define SMC_SET_MAC_CR(lp, x)   SMC_SET_MAC_CSR( (lp), MAC_CR, x )
 722 #define SMC_GET_ADDRH(lp, x)    SMC_GET_MAC_CSR( (lp), ADDRH, x )
 723 #define SMC_SET_ADDRH(lp, x)    SMC_SET_MAC_CSR( (lp), ADDRH, x )
 724 #define SMC_GET_ADDRL(lp, x)    SMC_GET_MAC_CSR( (lp), ADDRL, x )
 725 #define SMC_SET_ADDRL(lp, x)    SMC_SET_MAC_CSR( (lp), ADDRL, x )
 726 #define SMC_GET_HASHH(lp, x)    SMC_GET_MAC_CSR( (lp), HASHH, x )
 727 #define SMC_SET_HASHH(lp, x)    SMC_SET_MAC_CSR( (lp), HASHH, x )
 728 #define SMC_GET_HASHL(lp, x)    SMC_GET_MAC_CSR( (lp), HASHL, x )
 729 #define SMC_SET_HASHL(lp, x)    SMC_SET_MAC_CSR( (lp), HASHL, x )
 730 #define SMC_GET_MII_ACC(lp, x)  SMC_GET_MAC_CSR( (lp), MII_ACC, x )
 731 #define SMC_SET_MII_ACC(lp, x)  SMC_SET_MAC_CSR( (lp), MII_ACC, x )
 732 #define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
 733 #define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
 734 #define SMC_GET_FLOW(lp, x)             SMC_GET_MAC_CSR( (lp), FLOW, x )
 735 #define SMC_SET_FLOW(lp, x)             SMC_SET_MAC_CSR( (lp), FLOW, x )
 736 #define SMC_GET_VLAN1(lp, x)    SMC_GET_MAC_CSR( (lp), VLAN1, x )
 737 #define SMC_SET_VLAN1(lp, x)    SMC_SET_MAC_CSR( (lp), VLAN1, x )
 738 #define SMC_GET_VLAN2(lp, x)    SMC_GET_MAC_CSR( (lp), VLAN2, x )
 739 #define SMC_SET_VLAN2(lp, x)    SMC_SET_MAC_CSR( (lp), VLAN2, x )
 740 #define SMC_SET_WUFF(lp, x)             SMC_SET_MAC_CSR( (lp), WUFF, x )
 741 #define SMC_GET_WUCSR(lp, x)    SMC_GET_MAC_CSR( (lp), WUCSR, x )
 742 #define SMC_SET_WUCSR(lp, x)    SMC_SET_MAC_CSR( (lp), WUCSR, x )
 743
 744 /* PHY register read/write macros */
 745 #define SMC_GET_MII(lp,a,phy,v)                                 \
 746         do {                                                    \
 747                 u32 __v;                                        \
 748                 do {                                            \
 749                         SMC_GET_MII_ACC((lp), __v);                     \
 750                 } while ( __v & MII_ACC_MII_BUSY_ );            \
 751                 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
 752                         MII_ACC_MII_BUSY_);                     \
 753                 do {                                            \
 754                         SMC_GET_MII_ACC( (lp), __v);                    \
 755                 } while ( __v & MII_ACC_MII_BUSY_ );            \
 756                 SMC_GET_MII_DATA((lp), v);                              \
 757         } while (0)
 758 #define SMC_SET_MII(lp,a,phy,v)                                 \
 759         do {                                                    \
 760                 u32 __v;                                        \
 761                 do {                                            \
 762                         SMC_GET_MII_ACC((lp), __v);                     \
 763                 } while ( __v & MII_ACC_MII_BUSY_ );            \
 764                 SMC_SET_MII_DATA((lp), v);                              \
 765                 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
 766                         MII_ACC_MII_BUSY_        |              \
 767                         MII_ACC_MII_WRITE_  );                  \
 768                 do {                                            \
 769                         SMC_GET_MII_ACC((lp), __v);                     \
 770                 } while ( __v & MII_ACC_MII_BUSY_ );            \
 771         } while (0)
 772 #define SMC_GET_PHY_BMCR(lp,phy,x)              SMC_GET_MII( (lp), MII_BMCR, phy, x )
 773 #define SMC_SET_PHY_BMCR(lp,phy,x)              SMC_SET_MII( (lp), MII_BMCR, phy, x )
 774 #define SMC_GET_PHY_BMSR(lp,phy,x)              SMC_GET_MII( (lp), MII_BMSR, phy, x )
 775 #define SMC_GET_PHY_ID1(lp,phy,x)               SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
 776 #define SMC_GET_PHY_ID2(lp,phy,x)               SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
 777 #define SMC_GET_PHY_MII_ADV(lp,phy,x)   SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
 778 #define SMC_SET_PHY_MII_ADV(lp,phy,x)   SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
 779 #define SMC_GET_PHY_MII_LPA(lp,phy,x)   SMC_GET_MII( (lp), MII_LPA, phy, x )
 780 #define SMC_SET_PHY_MII_LPA(lp,phy,x)   SMC_SET_MII( (lp), MII_LPA, phy, x )
 781 #define SMC_GET_PHY_CTRL_STS(lp,phy,x)  SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
 782 #define SMC_SET_PHY_CTRL_STS(lp,phy,x)  SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
 783 #define SMC_GET_PHY_INT_SRC(lp,phy,x)   SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
 784 #define SMC_SET_PHY_INT_SRC(lp,phy,x)   SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
 785 #define SMC_GET_PHY_INT_MASK(lp,phy,x)  SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
 786 #define SMC_SET_PHY_INT_MASK(lp,phy,x)  SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
 787 #define SMC_GET_PHY_SPECIAL(lp,phy,x)   SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
 788
 789
 790
 791 /* Misc read/write macros */
 792
 793 #ifndef SMC_GET_MAC_ADDR
 794 #define SMC_GET_MAC_ADDR(lp, addr)                              \
 795         do {                                                    \
 796                 unsigned int __v;                               \
 797                                                                 \
 798                 SMC_GET_MAC_CSR((lp), ADDRL, __v);                      \
 799                 addr[0] = __v; addr[1] = __v >> 8;              \
 800                 addr[2] = __v >> 16; addr[3] = __v >> 24;       \
 801                 SMC_GET_MAC_CSR((lp), ADDRH, __v);                      \
 802                 addr[4] = __v; addr[5] = __v >> 8;              \
 803         } while (0)
 804 #endif
 805
 806 #define SMC_SET_MAC_ADDR(lp, addr)                              \
 807         do {                                                    \
 808                  SMC_SET_MAC_CSR((lp), ADDRL,                           \
 809                                  addr[0] |                      \
 810                                 (addr[1] << 8) |                \
 811                                 (addr[2] << 16) |               \
 812                                 (addr[3] << 24));               \
 813                  SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
 814         } while (0)
 815
 816
 817 #define SMC_WRITE_EEPROM_CMD(lp, cmd, addr)                             \
 818         do {                                                            \
 819                 while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 820                 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a );               \
 821                 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_);  \
 822         } while (0)
 823
 824 #endif   /* _SMC911X_H_ */