2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.17"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 MODULE_DEVICE_TABLE(pci, sky2_id_table);
141 /* Avoid conditionals by using array */
142 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
143 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
144 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
146 /* This driver supports yukon2 chipset only */
147 static const char *yukon2_name[] = {
149 "EC Ultra", /* 0xb4 */
150 "Extreme", /* 0xb5 */
156 static void sky2_set_multicast(struct net_device *dev);
158 /* Access to external PHY */
159 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
163 gma_write16(hw, port, GM_SMI_DATA, val);
164 gma_write16(hw, port, GM_SMI_CTRL,
165 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
167 for (i = 0; i < PHY_RETRIES; i++) {
168 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
173 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
177 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
181 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
182 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
184 for (i = 0; i < PHY_RETRIES; i++) {
185 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
186 *val = gma_read16(hw, port, GM_SMI_DATA);
196 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
200 if (__gm_phy_read(hw, port, reg, &v) != 0)
201 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
206 static void sky2_power_on(struct sky2_hw *hw)
208 /* switch power to VCC (WA for VAUX problem) */
209 sky2_write8(hw, B0_POWER_CTRL,
210 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212 /* disable Core Clock Division, */
213 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
216 /* enable bits are inverted */
217 sky2_write8(hw, B2_Y2_CLK_GATE,
218 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
219 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
220 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
227 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
229 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
230 /* set all bits to 0 except bits 15..12 and 8 */
231 reg &= P_ASPM_CONTROL_MSK;
232 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
234 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
235 /* set all bits to 0 except bits 28 & 27 */
236 reg &= P_CTL_TIM_VMAIN_AV_MSK;
237 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
239 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
241 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
242 reg = sky2_read32(hw, B2_GP_IO);
243 reg |= GLB_GPIO_STAT_RACE_DIS;
244 sky2_write32(hw, B2_GP_IO, reg);
246 sky2_read32(hw, B2_GP_IO);
250 static void sky2_power_aux(struct sky2_hw *hw)
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
255 /* enable bits are inverted */
256 sky2_write8(hw, B2_Y2_CLK_GATE,
257 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
258 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
259 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
261 /* switch power to VAUX */
262 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
263 sky2_write8(hw, B0_POWER_CTRL,
264 (PC_VAUX_ENA | PC_VCC_ENA |
265 PC_VAUX_ON | PC_VCC_OFF));
268 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
287 /* flow control to advertise bits */
288 static const u16 copper_fc_adv[] = {
290 [FC_TX] = PHY_M_AN_ASP,
291 [FC_RX] = PHY_M_AN_PC,
292 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
295 /* flow control to advertise bits when using 1000BaseX */
296 static const u16 fiber_fc_adv[] = {
297 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
298 [FC_TX] = PHY_M_P_ASYM_MD_X,
299 [FC_RX] = PHY_M_P_SYM_MD_X,
300 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
303 /* flow control to GMA disable bits */
304 static const u16 gm_fc_disable[] = {
305 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
306 [FC_TX] = GM_GPCR_FC_RX_DIS,
307 [FC_RX] = GM_GPCR_FC_TX_DIS,
312 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
314 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
315 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
317 if (sky2->autoneg == AUTONEG_ENABLE &&
318 !(hw->flags & SKY2_HW_NEWER_PHY)) {
319 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
321 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
323 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
325 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
326 if (hw->chip_id == CHIP_ID_YUKON_EC)
327 /* set downshift counter to 3x and enable downshift */
328 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
330 /* set master & slave downshift counter to 1x */
331 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
333 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
336 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
337 if (sky2_is_copper(hw)) {
338 if (!(hw->flags & SKY2_HW_GIGABIT)) {
339 /* enable automatic crossover */
340 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
342 /* disable energy detect */
343 ctrl &= ~PHY_M_PC_EN_DET_MSK;
345 /* enable automatic crossover */
346 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
348 /* downshift on PHY 88E1112 and 88E1149 is changed */
349 if (sky2->autoneg == AUTONEG_ENABLE
350 && (hw->flags & SKY2_HW_NEWER_PHY)) {
351 /* set downshift counter to 3x and enable downshift */
352 ctrl &= ~PHY_M_PC_DSC_MSK;
353 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
357 /* workaround for deviation #4.88 (CRC errors) */
358 /* disable Automatic Crossover */
360 ctrl &= ~PHY_M_PC_MDIX_MSK;
363 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
365 /* special setup for PHY 88E1112 Fiber */
366 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
367 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
369 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
370 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
371 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
372 ctrl &= ~PHY_M_MAC_MD_MSK;
373 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
374 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
376 if (hw->pmd_type == 'P') {
377 /* select page 1 to access Fiber registers */
378 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
380 /* for SFP-module set SIGDET polarity to low */
381 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
382 ctrl |= PHY_M_FIB_SIGD_POL;
383 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
386 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
394 if (sky2->autoneg == AUTONEG_ENABLE) {
395 if (sky2_is_copper(hw)) {
396 if (sky2->advertising & ADVERTISED_1000baseT_Full)
397 ct1000 |= PHY_M_1000C_AFD;
398 if (sky2->advertising & ADVERTISED_1000baseT_Half)
399 ct1000 |= PHY_M_1000C_AHD;
400 if (sky2->advertising & ADVERTISED_100baseT_Full)
401 adv |= PHY_M_AN_100_FD;
402 if (sky2->advertising & ADVERTISED_100baseT_Half)
403 adv |= PHY_M_AN_100_HD;
404 if (sky2->advertising & ADVERTISED_10baseT_Full)
405 adv |= PHY_M_AN_10_FD;
406 if (sky2->advertising & ADVERTISED_10baseT_Half)
407 adv |= PHY_M_AN_10_HD;
409 adv |= copper_fc_adv[sky2->flow_mode];
410 } else { /* special defines for FIBER (88E1040S only) */
411 if (sky2->advertising & ADVERTISED_1000baseT_Full)
412 adv |= PHY_M_AN_1000X_AFD;
413 if (sky2->advertising & ADVERTISED_1000baseT_Half)
414 adv |= PHY_M_AN_1000X_AHD;
416 adv |= fiber_fc_adv[sky2->flow_mode];
419 /* Restart Auto-negotiation */
420 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
422 /* forced speed/duplex settings */
423 ct1000 = PHY_M_1000C_MSE;
425 /* Disable auto update for duplex flow control and speed */
426 reg |= GM_GPCR_AU_ALL_DIS;
428 switch (sky2->speed) {
430 ctrl |= PHY_CT_SP1000;
431 reg |= GM_GPCR_SPEED_1000;
434 ctrl |= PHY_CT_SP100;
435 reg |= GM_GPCR_SPEED_100;
439 if (sky2->duplex == DUPLEX_FULL) {
440 reg |= GM_GPCR_DUP_FULL;
441 ctrl |= PHY_CT_DUP_MD;
442 } else if (sky2->speed < SPEED_1000)
443 sky2->flow_mode = FC_NONE;
446 reg |= gm_fc_disable[sky2->flow_mode];
448 /* Forward pause packets to GMAC? */
449 if (sky2->flow_mode & FC_RX)
450 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
452 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
455 gma_write16(hw, port, GM_GP_CTRL, reg);
457 if (hw->flags & SKY2_HW_GIGABIT)
458 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
460 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
461 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
463 /* Setup Phy LED's */
464 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
467 switch (hw->chip_id) {
468 case CHIP_ID_YUKON_FE:
469 /* on 88E3082 these bits are at 11..9 (shifted left) */
470 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
472 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
474 /* delete ACT LED control bits */
475 ctrl &= ~PHY_M_FELP_LED1_MSK;
476 /* change ACT LED control to blink mode */
477 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
478 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
481 case CHIP_ID_YUKON_FE_P:
482 /* Enable Link Partner Next Page */
483 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
484 ctrl |= PHY_M_PC_ENA_LIP_NP;
486 /* disable Energy Detect and enable scrambler */
487 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
488 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
490 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
491 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
492 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
493 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
498 case CHIP_ID_YUKON_XL:
499 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
501 /* select page 3 to access LED control register */
502 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
504 /* set LED Function Control register */
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
506 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
507 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
508 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
509 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
511 /* set Polarity Control register */
512 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
513 (PHY_M_POLC_LS1_P_MIX(4) |
514 PHY_M_POLC_IS0_P_MIX(4) |
515 PHY_M_POLC_LOS_CTRL(2) |
516 PHY_M_POLC_INIT_CTRL(2) |
517 PHY_M_POLC_STA1_CTRL(2) |
518 PHY_M_POLC_STA0_CTRL(2)));
520 /* restore page register */
521 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
524 case CHIP_ID_YUKON_EC_U:
525 case CHIP_ID_YUKON_EX:
526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
528 /* select page 3 to access LED control register */
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
531 /* set LED Function Control register */
532 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
533 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
534 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
535 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
536 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
538 /* set Blink Rate in LED Timer Control Register */
539 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
540 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
541 /* restore page register */
542 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
546 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
547 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
548 /* turn off the Rx LED (LED_RX) */
549 ledover &= ~PHY_M_LED_MO_RX;
552 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
553 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
554 /* apply fixes in PHY AFE */
555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
557 /* increase differential signal amplitude in 10BASE-T */
558 gm_phy_write(hw, port, 0x18, 0xaa99);
559 gm_phy_write(hw, port, 0x17, 0x2011);
561 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
562 gm_phy_write(hw, port, 0x18, 0xa204);
563 gm_phy_write(hw, port, 0x17, 0x2002);
565 /* set page register to 0 */
566 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
567 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
568 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
569 /* apply workaround for integrated resistors calibration */
570 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
571 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
572 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
573 /* no effect on Yukon-XL */
574 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
576 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
577 /* turn on 100 Mbps LED (LED_LINK100) */
578 ledover |= PHY_M_LED_MO_100;
582 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
586 /* Enable phy interrupt on auto-negotiation complete (or link up) */
587 if (sky2->autoneg == AUTONEG_ENABLE)
588 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
590 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
593 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
596 static const u32 phy_power[]
597 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
599 /* looks like this XL is back asswards .. */
600 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
603 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
604 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
606 /* Turn off phy power saving */
607 reg1 &= ~phy_power[port];
609 reg1 |= phy_power[port];
611 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
612 sky2_pci_read32(hw, PCI_DEV_REG1);
613 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
617 /* Force a renegotiation */
618 static void sky2_phy_reinit(struct sky2_port *sky2)
620 spin_lock_bh(&sky2->phy_lock);
621 sky2_phy_init(sky2->hw, sky2->port);
622 spin_unlock_bh(&sky2->phy_lock);
625 /* Put device in state to listen for Wake On Lan */
626 static void sky2_wol_init(struct sky2_port *sky2)
628 struct sky2_hw *hw = sky2->hw;
629 unsigned port = sky2->port;
630 enum flow_control save_mode;
634 /* Bring hardware out of reset */
635 sky2_write16(hw, B0_CTST, CS_RST_CLR);
636 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
638 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
639 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
642 * sky2_reset will re-enable on resume
644 save_mode = sky2->flow_mode;
645 ctrl = sky2->advertising;
647 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
648 sky2->flow_mode = FC_NONE;
649 sky2_phy_power(hw, port, 1);
650 sky2_phy_reinit(sky2);
652 sky2->flow_mode = save_mode;
653 sky2->advertising = ctrl;
655 /* Set GMAC to no flow control and auto update for speed/duplex */
656 gma_write16(hw, port, GM_GP_CTRL,
657 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
658 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
660 /* Set WOL address */
661 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
662 sky2->netdev->dev_addr, ETH_ALEN);
664 /* Turn on appropriate WOL control bits */
665 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
667 if (sky2->wol & WAKE_PHY)
668 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
670 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
672 if (sky2->wol & WAKE_MAGIC)
673 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
675 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
677 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
678 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
680 /* Turn on legacy PCI-Express PME mode */
681 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
682 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
683 reg1 |= PCI_Y2_PME_LEGACY;
684 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
685 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
688 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
692 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
694 struct net_device *dev = hw->dev[port];
696 if (dev->mtu <= ETH_DATA_LEN)
697 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
698 TX_JUMBO_DIS | TX_STFW_ENA);
700 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
701 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
702 TX_STFW_ENA | TX_JUMBO_ENA);
704 /* set Tx GMAC FIFO Almost Empty Threshold */
705 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
706 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
708 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
709 TX_JUMBO_ENA | TX_STFW_DIS);
711 /* Can't do offload because of lack of store/forward */
712 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
716 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
718 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
722 const u8 *addr = hw->dev[port]->dev_addr;
724 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
725 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
727 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
729 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
730 /* WA DEV_472 -- looks like crossed wires on port 2 */
731 /* clear GMAC 1 Control reset */
732 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
734 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
735 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
736 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
737 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
738 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
741 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
743 /* Enable Transmit FIFO Underrun */
744 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
746 spin_lock_bh(&sky2->phy_lock);
747 sky2_phy_init(hw, port);
748 spin_unlock_bh(&sky2->phy_lock);
751 reg = gma_read16(hw, port, GM_PHY_ADDR);
752 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
754 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
755 gma_read16(hw, port, i);
756 gma_write16(hw, port, GM_PHY_ADDR, reg);
758 /* transmit control */
759 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
761 /* receive control reg: unicast + multicast + no FCS */
762 gma_write16(hw, port, GM_RX_CTRL,
763 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
765 /* transmit flow control */
766 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
768 /* transmit parameter */
769 gma_write16(hw, port, GM_TX_PARAM,
770 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
771 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
772 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
773 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
775 /* serial mode register */
776 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
777 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
779 if (hw->dev[port]->mtu > ETH_DATA_LEN)
780 reg |= GM_SMOD_JUMBO_ENA;
782 gma_write16(hw, port, GM_SERIAL_MODE, reg);
784 /* virtual address for data */
785 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
787 /* physical address: used for pause frames */
788 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
790 /* ignore counter overflows */
791 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
792 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
793 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
795 /* Configure Rx MAC FIFO */
796 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
797 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
798 if (hw->chip_id == CHIP_ID_YUKON_EX ||
799 hw->chip_id == CHIP_ID_YUKON_FE_P)
800 rx_reg |= GMF_RX_OVER_ON;
802 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
804 /* Flush Rx MAC FIFO on any flow control or error */
805 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
807 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
808 reg = RX_GMF_FL_THR_DEF + 1;
809 /* Another magic mystery workaround from sk98lin */
810 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
811 hw->chip_rev == CHIP_REV_YU_FE2_A0)
813 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
815 /* Configure Tx MAC FIFO */
816 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
817 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
819 if (!(hw->flags & SKY2_HW_RAMBUFFER)) {
820 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
821 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
823 sky2_set_tx_stfwd(hw, port);
828 /* Assign Ram Buffer allocation to queue */
829 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
833 /* convert from K bytes to qwords used for hw register */
836 end = start + space - 1;
838 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
839 sky2_write32(hw, RB_ADDR(q, RB_START), start);
840 sky2_write32(hw, RB_ADDR(q, RB_END), end);
841 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
842 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
844 if (q == Q_R1 || q == Q_R2) {
845 u32 tp = space - space/4;
847 /* On receive queue's set the thresholds
848 * give receiver priority when > 3/4 full
849 * send pause when down to 2K
851 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
852 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
855 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
856 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
858 /* Enable store & forward on Tx queue's because
859 * Tx FIFO is only 1K on Yukon
861 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
864 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
865 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
868 /* Setup Bus Memory Interface */
869 static void sky2_qset(struct sky2_hw *hw, u16 q)
871 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
872 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
873 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
874 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
877 /* Setup prefetch unit registers. This is the interface between
878 * hardware and driver list elements
880 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
883 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
884 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
885 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
886 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
887 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
888 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
890 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
893 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
895 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
897 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
902 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
903 struct sky2_tx_le *le)
905 return sky2->tx_ring + (le - sky2->tx_le);
908 /* Update chip's next pointer */
909 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
911 /* Make sure write' to descriptors are complete before we tell hardware */
913 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
915 /* Synchronize I/O on since next processor may write to tail */
920 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
922 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
923 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
928 /* Build description to hardware for one receive segment */
929 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
930 dma_addr_t map, unsigned len)
932 struct sky2_rx_le *le;
933 u32 hi = upper_32_bits(map);
935 if (sky2->rx_addr64 != hi) {
936 le = sky2_next_rx(sky2);
937 le->addr = cpu_to_le32(hi);
938 le->opcode = OP_ADDR64 | HW_OWNER;
939 sky2->rx_addr64 = upper_32_bits(map + len);
942 le = sky2_next_rx(sky2);
943 le->addr = cpu_to_le32((u32) map);
944 le->length = cpu_to_le16(len);
945 le->opcode = op | HW_OWNER;
948 /* Build description to hardware for one possibly fragmented skb */
949 static void sky2_rx_submit(struct sky2_port *sky2,
950 const struct rx_ring_info *re)
954 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
956 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
957 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
961 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
964 struct sk_buff *skb = re->skb;
967 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
968 pci_unmap_len_set(re, data_size, size);
970 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
971 re->frag_addr[i] = pci_map_page(pdev,
972 skb_shinfo(skb)->frags[i].page,
973 skb_shinfo(skb)->frags[i].page_offset,
974 skb_shinfo(skb)->frags[i].size,
978 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
980 struct sk_buff *skb = re->skb;
983 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
986 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
987 pci_unmap_page(pdev, re->frag_addr[i],
988 skb_shinfo(skb)->frags[i].size,
992 /* Tell chip where to start receive checksum.
993 * Actually has two checksums, but set both same to avoid possible byte
996 static void rx_set_checksum(struct sky2_port *sky2)
998 struct sky2_rx_le *le = sky2_next_rx(sky2);
1000 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1002 le->opcode = OP_TCPSTART | HW_OWNER;
1004 sky2_write32(sky2->hw,
1005 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1006 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1010 * The RX Stop command will not work for Yukon-2 if the BMU does not
1011 * reach the end of packet and since we can't make sure that we have
1012 * incoming data, we must reset the BMU while it is not doing a DMA
1013 * transfer. Since it is possible that the RX path is still active,
1014 * the RX RAM buffer will be stopped first, so any possible incoming
1015 * data will not trigger a DMA. After the RAM buffer is stopped, the
1016 * BMU is polled until any DMA in progress is ended and only then it
1019 static void sky2_rx_stop(struct sky2_port *sky2)
1021 struct sky2_hw *hw = sky2->hw;
1022 unsigned rxq = rxqaddr[sky2->port];
1025 /* disable the RAM Buffer receive queue */
1026 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1028 for (i = 0; i < 0xffff; i++)
1029 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1030 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1033 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1034 sky2->netdev->name);
1036 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1038 /* reset the Rx prefetch unit */
1039 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1043 /* Clean out receive buffer area, assumes receiver hardware stopped */
1044 static void sky2_rx_clean(struct sky2_port *sky2)
1048 memset(sky2->rx_le, 0, RX_LE_BYTES);
1049 for (i = 0; i < sky2->rx_pending; i++) {
1050 struct rx_ring_info *re = sky2->rx_ring + i;
1053 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1060 /* Basic MII support */
1061 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1063 struct mii_ioctl_data *data = if_mii(ifr);
1064 struct sky2_port *sky2 = netdev_priv(dev);
1065 struct sky2_hw *hw = sky2->hw;
1066 int err = -EOPNOTSUPP;
1068 if (!netif_running(dev))
1069 return -ENODEV; /* Phy still in reset */
1073 data->phy_id = PHY_ADDR_MARV;
1079 spin_lock_bh(&sky2->phy_lock);
1080 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1081 spin_unlock_bh(&sky2->phy_lock);
1083 data->val_out = val;
1088 if (!capable(CAP_NET_ADMIN))
1091 spin_lock_bh(&sky2->phy_lock);
1092 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1094 spin_unlock_bh(&sky2->phy_lock);
1100 #ifdef SKY2_VLAN_TAG_USED
1101 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1103 struct sky2_port *sky2 = netdev_priv(dev);
1104 struct sky2_hw *hw = sky2->hw;
1105 u16 port = sky2->port;
1107 netif_tx_lock_bh(dev);
1108 netif_poll_disable(sky2->hw->dev[0]);
1112 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1114 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1117 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1119 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1123 netif_poll_enable(sky2->hw->dev[0]);
1124 netif_tx_unlock_bh(dev);
1129 * Allocate an skb for receiving. If the MTU is large enough
1130 * make the skb non-linear with a fragment list of pages.
1132 * It appears the hardware has a bug in the FIFO logic that
1133 * cause it to hang if the FIFO gets overrun and the receive buffer
1134 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1135 * aligned except if slab debugging is enabled.
1137 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1139 struct sk_buff *skb;
1143 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1147 p = (unsigned long) skb->data;
1148 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1150 for (i = 0; i < sky2->rx_nfrags; i++) {
1151 struct page *page = alloc_page(GFP_ATOMIC);
1155 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1165 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1167 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1171 * Allocate and setup receiver buffer pool.
1172 * Normal case this ends up creating one list element for skb
1173 * in the receive ring. Worst case if using large MTU and each
1174 * allocation falls on a different 64 bit region, that results
1175 * in 6 list elements per ring entry.
1176 * One element is used for checksum enable/disable, and one
1177 * extra to avoid wrap.
1179 static int sky2_rx_start(struct sky2_port *sky2)
1181 struct sky2_hw *hw = sky2->hw;
1182 struct rx_ring_info *re;
1183 unsigned rxq = rxqaddr[sky2->port];
1184 unsigned i, size, space, thresh;
1186 sky2->rx_put = sky2->rx_next = 0;
1189 /* On PCI express lowering the watermark gives better performance */
1190 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1191 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1193 /* These chips have no ram buffer?
1194 * MAC Rx RAM Read is controlled by hardware */
1195 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1196 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1197 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1198 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1200 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1202 if (!(hw->flags & SKY2_HW_NEW_LE))
1203 rx_set_checksum(sky2);
1205 /* Space needed for frame data + headers rounded up */
1206 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1208 /* Stopping point for hardware truncation */
1209 thresh = (size - 8) / sizeof(u32);
1211 /* Account for overhead of skb - to avoid order > 0 allocation */
1212 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1213 + sizeof(struct skb_shared_info);
1215 sky2->rx_nfrags = space >> PAGE_SHIFT;
1216 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1218 if (sky2->rx_nfrags != 0) {
1219 /* Compute residue after pages */
1220 space = sky2->rx_nfrags << PAGE_SHIFT;
1227 /* Optimize to handle small packets and headers */
1228 if (size < copybreak)
1230 if (size < ETH_HLEN)
1233 sky2->rx_data_size = size;
1236 for (i = 0; i < sky2->rx_pending; i++) {
1237 re = sky2->rx_ring + i;
1239 re->skb = sky2_rx_alloc(sky2);
1243 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1244 sky2_rx_submit(sky2, re);
1248 * The receiver hangs if it receives frames larger than the
1249 * packet buffer. As a workaround, truncate oversize frames, but
1250 * the register is limited to 9 bits, so if you do frames > 2052
1251 * you better get the MTU right!
1254 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1256 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1257 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1260 /* Tell chip about available buffers */
1261 sky2_rx_update(sky2, rxq);
1264 sky2_rx_clean(sky2);
1268 /* Bring up network interface. */
1269 static int sky2_up(struct net_device *dev)
1271 struct sky2_port *sky2 = netdev_priv(dev);
1272 struct sky2_hw *hw = sky2->hw;
1273 unsigned port = sky2->port;
1275 int cap, err = -ENOMEM;
1276 struct net_device *otherdev = hw->dev[sky2->port^1];
1279 * On dual port PCI-X card, there is an problem where status
1280 * can be received out of order due to split transactions
1282 if (otherdev && netif_running(otherdev) &&
1283 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1284 struct sky2_port *osky2 = netdev_priv(otherdev);
1287 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1288 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1289 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1295 if (netif_msg_ifup(sky2))
1296 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1298 netif_carrier_off(dev);
1300 /* must be power of 2 */
1301 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1303 sizeof(struct sky2_tx_le),
1308 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1312 sky2->tx_prod = sky2->tx_cons = 0;
1314 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1318 memset(sky2->rx_le, 0, RX_LE_BYTES);
1320 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1325 sky2_phy_power(hw, port, 1);
1327 sky2_mac_init(hw, port);
1329 if (hw->flags & SKY2_HW_RAMBUFFER) {
1330 /* Register is number of 4K blocks on internal RAM buffer. */
1331 u32 ramsize = sky2_read8(hw, B2_E_0) * 4;
1334 printk(KERN_DEBUG PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1337 rxspace = ramsize / 2;
1339 rxspace = 8 + (2*(ramsize - 16))/3;
1341 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1342 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1344 /* Make sure SyncQ is disabled */
1345 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1349 sky2_qset(hw, txqaddr[port]);
1351 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1352 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1353 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1355 /* Set almost empty threshold */
1356 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1357 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1358 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1360 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1363 err = sky2_rx_start(sky2);
1367 /* Enable interrupts from phy/mac for port */
1368 imask = sky2_read32(hw, B0_IMSK);
1369 imask |= portirq_msk[port];
1370 sky2_write32(hw, B0_IMSK, imask);
1376 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1377 sky2->rx_le, sky2->rx_le_map);
1381 pci_free_consistent(hw->pdev,
1382 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1383 sky2->tx_le, sky2->tx_le_map);
1386 kfree(sky2->tx_ring);
1387 kfree(sky2->rx_ring);
1389 sky2->tx_ring = NULL;
1390 sky2->rx_ring = NULL;
1394 /* Modular subtraction in ring */
1395 static inline int tx_dist(unsigned tail, unsigned head)
1397 return (head - tail) & (TX_RING_SIZE - 1);
1400 /* Number of list elements available for next tx */
1401 static inline int tx_avail(const struct sky2_port *sky2)
1403 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1406 /* Estimate of number of transmit list elements required */
1407 static unsigned tx_le_req(const struct sk_buff *skb)
1411 count = sizeof(dma_addr_t) / sizeof(u32);
1412 count += skb_shinfo(skb)->nr_frags * count;
1414 if (skb_is_gso(skb))
1417 if (skb->ip_summed == CHECKSUM_PARTIAL)
1424 * Put one packet in ring for transmit.
1425 * A single packet can generate multiple list elements, and
1426 * the number of ring elements will probably be less than the number
1427 * of list elements used.
1429 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1431 struct sky2_port *sky2 = netdev_priv(dev);
1432 struct sky2_hw *hw = sky2->hw;
1433 struct sky2_tx_le *le = NULL;
1434 struct tx_ring_info *re;
1441 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1442 return NETDEV_TX_BUSY;
1444 if (unlikely(netif_msg_tx_queued(sky2)))
1445 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1446 dev->name, sky2->tx_prod, skb->len);
1448 len = skb_headlen(skb);
1449 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1450 addr64 = upper_32_bits(mapping);
1452 /* Send high bits if changed or crosses boundary */
1453 if (addr64 != sky2->tx_addr64 ||
1454 upper_32_bits(mapping + len) != sky2->tx_addr64) {
1455 le = get_tx_le(sky2);
1456 le->addr = cpu_to_le32(addr64);
1457 le->opcode = OP_ADDR64 | HW_OWNER;
1458 sky2->tx_addr64 = upper_32_bits(mapping + len);
1461 /* Check for TCP Segmentation Offload */
1462 mss = skb_shinfo(skb)->gso_size;
1465 if (!(hw->flags & SKY2_HW_NEW_LE))
1466 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1468 if (mss != sky2->tx_last_mss) {
1469 le = get_tx_le(sky2);
1470 le->addr = cpu_to_le32(mss);
1472 if (hw->flags & SKY2_HW_NEW_LE)
1473 le->opcode = OP_MSS | HW_OWNER;
1475 le->opcode = OP_LRGLEN | HW_OWNER;
1476 sky2->tx_last_mss = mss;
1481 #ifdef SKY2_VLAN_TAG_USED
1482 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1483 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1485 le = get_tx_le(sky2);
1487 le->opcode = OP_VLAN|HW_OWNER;
1489 le->opcode |= OP_VLAN;
1490 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1495 /* Handle TCP checksum offload */
1496 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1497 /* On Yukon EX (some versions) encoding change. */
1498 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1499 ctrl |= CALSUM; /* auto checksum */
1501 const unsigned offset = skb_transport_offset(skb);
1504 tcpsum = offset << 16; /* sum start */
1505 tcpsum |= offset + skb->csum_offset; /* sum write */
1507 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1508 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1511 if (tcpsum != sky2->tx_tcpsum) {
1512 sky2->tx_tcpsum = tcpsum;
1514 le = get_tx_le(sky2);
1515 le->addr = cpu_to_le32(tcpsum);
1516 le->length = 0; /* initial checksum value */
1517 le->ctrl = 1; /* one packet */
1518 le->opcode = OP_TCPLISW | HW_OWNER;
1523 le = get_tx_le(sky2);
1524 le->addr = cpu_to_le32((u32) mapping);
1525 le->length = cpu_to_le16(len);
1527 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1529 re = tx_le_re(sky2, le);
1531 pci_unmap_addr_set(re, mapaddr, mapping);
1532 pci_unmap_len_set(re, maplen, len);
1534 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1535 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1537 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1538 frag->size, PCI_DMA_TODEVICE);
1539 addr64 = upper_32_bits(mapping);
1540 if (addr64 != sky2->tx_addr64) {
1541 le = get_tx_le(sky2);
1542 le->addr = cpu_to_le32(addr64);
1544 le->opcode = OP_ADDR64 | HW_OWNER;
1545 sky2->tx_addr64 = addr64;
1548 le = get_tx_le(sky2);
1549 le->addr = cpu_to_le32((u32) mapping);
1550 le->length = cpu_to_le16(frag->size);
1552 le->opcode = OP_BUFFER | HW_OWNER;
1554 re = tx_le_re(sky2, le);
1556 pci_unmap_addr_set(re, mapaddr, mapping);
1557 pci_unmap_len_set(re, maplen, frag->size);
1562 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1563 netif_stop_queue(dev);
1565 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1567 dev->trans_start = jiffies;
1568 return NETDEV_TX_OK;
1572 * Free ring elements from starting at tx_cons until "done"
1574 * NB: the hardware will tell us about partial completion of multi-part
1575 * buffers so make sure not to free skb to early.
1577 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1579 struct net_device *dev = sky2->netdev;
1580 struct pci_dev *pdev = sky2->hw->pdev;
1583 BUG_ON(done >= TX_RING_SIZE);
1585 for (idx = sky2->tx_cons; idx != done;
1586 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1587 struct sky2_tx_le *le = sky2->tx_le + idx;
1588 struct tx_ring_info *re = sky2->tx_ring + idx;
1590 switch(le->opcode & ~HW_OWNER) {
1593 pci_unmap_single(pdev,
1594 pci_unmap_addr(re, mapaddr),
1595 pci_unmap_len(re, maplen),
1599 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1600 pci_unmap_len(re, maplen),
1605 if (le->ctrl & EOP) {
1606 if (unlikely(netif_msg_tx_done(sky2)))
1607 printk(KERN_DEBUG "%s: tx done %u\n",
1610 sky2->net_stats.tx_packets++;
1611 sky2->net_stats.tx_bytes += re->skb->len;
1613 dev_kfree_skb_any(re->skb);
1614 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1618 sky2->tx_cons = idx;
1621 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1622 netif_wake_queue(dev);
1625 /* Cleanup all untransmitted buffers, assume transmitter not running */
1626 static void sky2_tx_clean(struct net_device *dev)
1628 struct sky2_port *sky2 = netdev_priv(dev);
1630 netif_tx_lock_bh(dev);
1631 sky2_tx_complete(sky2, sky2->tx_prod);
1632 netif_tx_unlock_bh(dev);
1635 /* Network shutdown */
1636 static int sky2_down(struct net_device *dev)
1638 struct sky2_port *sky2 = netdev_priv(dev);
1639 struct sky2_hw *hw = sky2->hw;
1640 unsigned port = sky2->port;
1644 /* Never really got started! */
1648 if (netif_msg_ifdown(sky2))
1649 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1651 if (netif_carrier_ok(dev) && --hw->active == 0)
1652 del_timer(&hw->watchdog_timer);
1654 /* Stop more packets from being queued */
1655 netif_stop_queue(dev);
1657 /* Disable port IRQ */
1658 imask = sky2_read32(hw, B0_IMSK);
1659 imask &= ~portirq_msk[port];
1660 sky2_write32(hw, B0_IMSK, imask);
1662 sky2_gmac_reset(hw, port);
1664 /* Stop transmitter */
1665 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1666 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1668 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1669 RB_RST_SET | RB_DIS_OP_MD);
1671 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1672 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1673 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1675 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1677 /* Workaround shared GMAC reset */
1678 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1679 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1680 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1682 /* Disable Force Sync bit and Enable Alloc bit */
1683 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1684 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1686 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1687 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1688 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1690 /* Reset the PCI FIFO of the async Tx queue */
1691 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1692 BMU_RST_SET | BMU_FIFO_RST);
1694 /* Reset the Tx prefetch units */
1695 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1698 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1702 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1703 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1705 sky2_phy_power(hw, port, 0);
1707 netif_carrier_off(dev);
1709 /* turn off LED's */
1710 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1712 synchronize_irq(hw->pdev->irq);
1715 sky2_rx_clean(sky2);
1717 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1718 sky2->rx_le, sky2->rx_le_map);
1719 kfree(sky2->rx_ring);
1721 pci_free_consistent(hw->pdev,
1722 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1723 sky2->tx_le, sky2->tx_le_map);
1724 kfree(sky2->tx_ring);
1729 sky2->rx_ring = NULL;
1730 sky2->tx_ring = NULL;
1735 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1737 if (hw->flags & SKY2_HW_FIBRE_PHY)
1740 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1741 if (aux & PHY_M_PS_SPEED_100)
1747 switch (aux & PHY_M_PS_SPEED_MSK) {
1748 case PHY_M_PS_SPEED_1000:
1750 case PHY_M_PS_SPEED_100:
1757 static void sky2_link_up(struct sky2_port *sky2)
1759 struct sky2_hw *hw = sky2->hw;
1760 unsigned port = sky2->port;
1762 static const char *fc_name[] = {
1770 reg = gma_read16(hw, port, GM_GP_CTRL);
1771 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1772 gma_write16(hw, port, GM_GP_CTRL, reg);
1774 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1776 netif_carrier_on(sky2->netdev);
1778 if (hw->active++ == 0)
1779 mod_timer(&hw->watchdog_timer, jiffies + 1);
1782 /* Turn on link LED */
1783 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1784 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1786 if (hw->flags & SKY2_HW_NEWER_PHY) {
1787 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1788 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1790 switch(sky2->speed) {
1792 led |= PHY_M_LEDC_INIT_CTRL(7);
1796 led |= PHY_M_LEDC_STA1_CTRL(7);
1800 led |= PHY_M_LEDC_STA0_CTRL(7);
1804 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1805 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1806 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1809 if (netif_msg_link(sky2))
1810 printk(KERN_INFO PFX
1811 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1812 sky2->netdev->name, sky2->speed,
1813 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1814 fc_name[sky2->flow_status]);
1817 static void sky2_link_down(struct sky2_port *sky2)
1819 struct sky2_hw *hw = sky2->hw;
1820 unsigned port = sky2->port;
1823 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1825 reg = gma_read16(hw, port, GM_GP_CTRL);
1826 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1827 gma_write16(hw, port, GM_GP_CTRL, reg);
1829 netif_carrier_off(sky2->netdev);
1831 /* Stop watchdog if both ports are not active */
1832 if (--hw->active == 0)
1833 del_timer(&hw->watchdog_timer);
1836 /* Turn on link LED */
1837 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1839 if (netif_msg_link(sky2))
1840 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1842 sky2_phy_init(hw, port);
1845 static enum flow_control sky2_flow(int rx, int tx)
1848 return tx ? FC_BOTH : FC_RX;
1850 return tx ? FC_TX : FC_NONE;
1853 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1855 struct sky2_hw *hw = sky2->hw;
1856 unsigned port = sky2->port;
1859 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1860 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1861 if (lpa & PHY_M_AN_RF) {
1862 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1866 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1867 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1868 sky2->netdev->name);
1872 sky2->speed = sky2_phy_speed(hw, aux);
1873 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1875 /* Since the pause result bits seem to in different positions on
1876 * different chips. look at registers.
1878 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1879 /* Shift for bits in fiber PHY */
1880 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1881 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1883 if (advert & ADVERTISE_1000XPAUSE)
1884 advert |= ADVERTISE_PAUSE_CAP;
1885 if (advert & ADVERTISE_1000XPSE_ASYM)
1886 advert |= ADVERTISE_PAUSE_ASYM;
1887 if (lpa & LPA_1000XPAUSE)
1888 lpa |= LPA_PAUSE_CAP;
1889 if (lpa & LPA_1000XPAUSE_ASYM)
1890 lpa |= LPA_PAUSE_ASYM;
1893 sky2->flow_status = FC_NONE;
1894 if (advert & ADVERTISE_PAUSE_CAP) {
1895 if (lpa & LPA_PAUSE_CAP)
1896 sky2->flow_status = FC_BOTH;
1897 else if (advert & ADVERTISE_PAUSE_ASYM)
1898 sky2->flow_status = FC_RX;
1899 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1900 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1901 sky2->flow_status = FC_TX;
1904 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1905 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1906 sky2->flow_status = FC_NONE;
1908 if (sky2->flow_status & FC_TX)
1909 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1911 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1916 /* Interrupt from PHY */
1917 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1919 struct net_device *dev = hw->dev[port];
1920 struct sky2_port *sky2 = netdev_priv(dev);
1921 u16 istatus, phystat;
1923 if (!netif_running(dev))
1926 spin_lock(&sky2->phy_lock);
1927 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1928 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1930 if (netif_msg_intr(sky2))
1931 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1932 sky2->netdev->name, istatus, phystat);
1934 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1935 if (sky2_autoneg_done(sky2, phystat) == 0)
1940 if (istatus & PHY_M_IS_LSP_CHANGE)
1941 sky2->speed = sky2_phy_speed(hw, phystat);
1943 if (istatus & PHY_M_IS_DUP_CHANGE)
1945 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1947 if (istatus & PHY_M_IS_LST_CHANGE) {
1948 if (phystat & PHY_M_PS_LINK_UP)
1951 sky2_link_down(sky2);
1954 spin_unlock(&sky2->phy_lock);
1957 /* Transmit timeout is only called if we are running, carrier is up
1958 * and tx queue is full (stopped).
1960 static void sky2_tx_timeout(struct net_device *dev)
1962 struct sky2_port *sky2 = netdev_priv(dev);
1963 struct sky2_hw *hw = sky2->hw;
1965 if (netif_msg_timer(sky2))
1966 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1968 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1969 dev->name, sky2->tx_cons, sky2->tx_prod,
1970 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1971 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1973 /* can't restart safely under softirq */
1974 schedule_work(&hw->restart_work);
1977 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1979 struct sky2_port *sky2 = netdev_priv(dev);
1980 struct sky2_hw *hw = sky2->hw;
1981 unsigned port = sky2->port;
1986 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1989 if (new_mtu > ETH_DATA_LEN &&
1990 (hw->chip_id == CHIP_ID_YUKON_FE ||
1991 hw->chip_id == CHIP_ID_YUKON_FE_P))
1994 if (!netif_running(dev)) {
1999 imask = sky2_read32(hw, B0_IMSK);
2000 sky2_write32(hw, B0_IMSK, 0);
2002 dev->trans_start = jiffies; /* prevent tx timeout */
2003 netif_stop_queue(dev);
2004 netif_poll_disable(hw->dev[0]);
2006 synchronize_irq(hw->pdev->irq);
2008 if (!(hw->flags & SKY2_HW_RAMBUFFER))
2009 sky2_set_tx_stfwd(hw, port);
2011 ctl = gma_read16(hw, port, GM_GP_CTRL);
2012 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2014 sky2_rx_clean(sky2);
2018 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2019 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2021 if (dev->mtu > ETH_DATA_LEN)
2022 mode |= GM_SMOD_JUMBO_ENA;
2024 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2026 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2028 err = sky2_rx_start(sky2);
2029 sky2_write32(hw, B0_IMSK, imask);
2034 gma_write16(hw, port, GM_GP_CTRL, ctl);
2036 netif_poll_enable(hw->dev[0]);
2037 netif_wake_queue(dev);
2043 /* For small just reuse existing skb for next receive */
2044 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2045 const struct rx_ring_info *re,
2048 struct sk_buff *skb;
2050 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2052 skb_reserve(skb, 2);
2053 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2054 length, PCI_DMA_FROMDEVICE);
2055 skb_copy_from_linear_data(re->skb, skb->data, length);
2056 skb->ip_summed = re->skb->ip_summed;
2057 skb->csum = re->skb->csum;
2058 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2059 length, PCI_DMA_FROMDEVICE);
2060 re->skb->ip_summed = CHECKSUM_NONE;
2061 skb_put(skb, length);
2066 /* Adjust length of skb with fragments to match received data */
2067 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2068 unsigned int length)
2073 /* put header into skb */
2074 size = min(length, hdr_space);
2079 num_frags = skb_shinfo(skb)->nr_frags;
2080 for (i = 0; i < num_frags; i++) {
2081 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2084 /* don't need this page */
2085 __free_page(frag->page);
2086 --skb_shinfo(skb)->nr_frags;
2088 size = min(length, (unsigned) PAGE_SIZE);
2091 skb->data_len += size;
2092 skb->truesize += size;
2099 /* Normal packet - take skb from ring element and put in a new one */
2100 static struct sk_buff *receive_new(struct sky2_port *sky2,
2101 struct rx_ring_info *re,
2102 unsigned int length)
2104 struct sk_buff *skb, *nskb;
2105 unsigned hdr_space = sky2->rx_data_size;
2107 /* Don't be tricky about reusing pages (yet) */
2108 nskb = sky2_rx_alloc(sky2);
2109 if (unlikely(!nskb))
2113 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2115 prefetch(skb->data);
2117 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2119 if (skb_shinfo(skb)->nr_frags)
2120 skb_put_frags(skb, hdr_space, length);
2122 skb_put(skb, length);
2127 * Receive one packet.
2128 * For larger packets, get new buffer.
2130 static struct sk_buff *sky2_receive(struct net_device *dev,
2131 u16 length, u32 status)
2133 struct sky2_port *sky2 = netdev_priv(dev);
2134 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2135 struct sk_buff *skb = NULL;
2136 u16 count = (status & GMR_FS_LEN) >> 16;
2138 #ifdef SKY2_VLAN_TAG_USED
2139 /* Account for vlan tag */
2140 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2144 if (unlikely(netif_msg_rx_status(sky2)))
2145 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2146 dev->name, sky2->rx_next, status, length);
2148 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2149 prefetch(sky2->rx_ring + sky2->rx_next);
2151 if (status & GMR_FS_ANY_ERR)
2154 if (!(status & GMR_FS_RX_OK))
2157 /* if length reported by DMA does not match PHY, packet was truncated */
2158 if (length != count)
2161 if (length < copybreak)
2162 skb = receive_copy(sky2, re, length);
2164 skb = receive_new(sky2, re, length);
2166 sky2_rx_submit(sky2, re);
2171 /* Truncation of overlength packets
2172 causes PHY length to not match MAC length */
2173 ++sky2->net_stats.rx_length_errors;
2174 if (netif_msg_rx_err(sky2) && net_ratelimit())
2175 pr_info(PFX "%s: rx length mismatch: length %d status %#x\n",
2176 dev->name, length, status);
2180 ++sky2->net_stats.rx_errors;
2181 if (status & GMR_FS_RX_FF_OV) {
2182 sky2->net_stats.rx_over_errors++;
2186 if (netif_msg_rx_err(sky2) && net_ratelimit())
2187 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2188 dev->name, status, length);
2190 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2191 sky2->net_stats.rx_length_errors++;
2192 if (status & GMR_FS_FRAGMENT)
2193 sky2->net_stats.rx_frame_errors++;
2194 if (status & GMR_FS_CRC_ERR)
2195 sky2->net_stats.rx_crc_errors++;
2200 /* Transmit complete */
2201 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2203 struct sky2_port *sky2 = netdev_priv(dev);
2205 if (netif_running(dev)) {
2207 sky2_tx_complete(sky2, last);
2208 netif_tx_unlock(dev);
2212 /* Process status response ring */
2213 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2216 unsigned rx[2] = { 0, 0 };
2217 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2221 while (hw->st_idx != hwidx) {
2222 struct sky2_port *sky2;
2223 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2224 unsigned port = le->css & CSS_LINK_BIT;
2225 struct net_device *dev;
2226 struct sk_buff *skb;
2230 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2232 dev = hw->dev[port];
2233 sky2 = netdev_priv(dev);
2234 length = le16_to_cpu(le->length);
2235 status = le32_to_cpu(le->status);
2237 switch (le->opcode & ~HW_OWNER) {
2240 skb = sky2_receive(dev, length, status);
2241 if (unlikely(!skb)) {
2242 sky2->net_stats.rx_dropped++;
2246 /* This chip reports checksum status differently */
2247 if (hw->flags & SKY2_HW_NEW_LE) {
2248 if (sky2->rx_csum &&
2249 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2250 (le->css & CSS_TCPUDPCSOK))
2251 skb->ip_summed = CHECKSUM_UNNECESSARY;
2253 skb->ip_summed = CHECKSUM_NONE;
2256 skb->protocol = eth_type_trans(skb, dev);
2257 sky2->net_stats.rx_packets++;
2258 sky2->net_stats.rx_bytes += skb->len;
2259 dev->last_rx = jiffies;
2261 #ifdef SKY2_VLAN_TAG_USED
2262 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2263 vlan_hwaccel_receive_skb(skb,
2265 be16_to_cpu(sky2->rx_tag));
2268 netif_receive_skb(skb);
2270 /* Stop after net poll weight */
2271 if (++work_done >= to_do)
2275 #ifdef SKY2_VLAN_TAG_USED
2277 sky2->rx_tag = length;
2281 sky2->rx_tag = length;
2288 /* If this happens then driver assuming wrong format */
2289 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2290 if (net_ratelimit())
2291 printk(KERN_NOTICE "%s: unexpected"
2292 " checksum status\n",
2297 /* Both checksum counters are programmed to start at
2298 * the same offset, so unless there is a problem they
2299 * should match. This failure is an early indication that
2300 * hardware receive checksumming won't work.
2302 if (likely(status >> 16 == (status & 0xffff))) {
2303 skb = sky2->rx_ring[sky2->rx_next].skb;
2304 skb->ip_summed = CHECKSUM_COMPLETE;
2305 skb->csum = status & 0xffff;
2307 printk(KERN_NOTICE PFX "%s: hardware receive "
2308 "checksum problem (status = %#x)\n",
2311 sky2_write32(sky2->hw,
2312 Q_ADDR(rxqaddr[port], Q_CSR),
2318 /* TX index reports status for both ports */
2319 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2320 sky2_tx_done(hw->dev[0], status & 0xfff);
2322 sky2_tx_done(hw->dev[1],
2323 ((status >> 24) & 0xff)
2324 | (u16)(length & 0xf) << 8);
2328 if (net_ratelimit())
2329 printk(KERN_WARNING PFX
2330 "unknown status opcode 0x%x\n", le->opcode);
2334 /* Fully processed status ring so clear irq */
2335 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2339 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2342 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2347 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2349 struct net_device *dev = hw->dev[port];
2351 if (net_ratelimit())
2352 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2355 if (status & Y2_IS_PAR_RD1) {
2356 if (net_ratelimit())
2357 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2360 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2363 if (status & Y2_IS_PAR_WR1) {
2364 if (net_ratelimit())
2365 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2368 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2371 if (status & Y2_IS_PAR_MAC1) {
2372 if (net_ratelimit())
2373 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2374 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2377 if (status & Y2_IS_PAR_RX1) {
2378 if (net_ratelimit())
2379 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2380 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2383 if (status & Y2_IS_TCP_TXA1) {
2384 if (net_ratelimit())
2385 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2387 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2391 static void sky2_hw_intr(struct sky2_hw *hw)
2393 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2395 if (status & Y2_IS_TIST_OV)
2396 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2398 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2401 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2402 if (net_ratelimit())
2403 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2406 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2407 sky2_pci_write16(hw, PCI_STATUS,
2408 pci_err | PCI_STATUS_ERROR_BITS);
2409 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2412 if (status & Y2_IS_PCI_EXP) {
2413 /* PCI-Express uncorrectable Error occurred */
2416 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2418 if (net_ratelimit())
2419 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2422 /* clear the interrupt */
2423 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2424 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2426 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2428 if (pex_err & PEX_FATAL_ERRORS) {
2429 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2430 hwmsk &= ~Y2_IS_PCI_EXP;
2431 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2435 if (status & Y2_HWE_L1_MASK)
2436 sky2_hw_error(hw, 0, status);
2438 if (status & Y2_HWE_L1_MASK)
2439 sky2_hw_error(hw, 1, status);
2442 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2444 struct net_device *dev = hw->dev[port];
2445 struct sky2_port *sky2 = netdev_priv(dev);
2446 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2448 if (netif_msg_intr(sky2))
2449 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2452 if (status & GM_IS_RX_CO_OV)
2453 gma_read16(hw, port, GM_RX_IRQ_SRC);
2455 if (status & GM_IS_TX_CO_OV)
2456 gma_read16(hw, port, GM_TX_IRQ_SRC);
2458 if (status & GM_IS_RX_FF_OR) {
2459 ++sky2->net_stats.rx_fifo_errors;
2460 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2463 if (status & GM_IS_TX_FF_UR) {
2464 ++sky2->net_stats.tx_fifo_errors;
2465 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2469 /* This should never happen it is a bug. */
2470 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2471 u16 q, unsigned ring_size)
2473 struct net_device *dev = hw->dev[port];
2474 struct sky2_port *sky2 = netdev_priv(dev);
2476 const u64 *le = (q == Q_R1 || q == Q_R2)
2477 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2479 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2480 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2481 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2482 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2484 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2487 /* Check for lost IRQ once a second */
2488 static void sky2_watchdog(unsigned long arg)
2490 struct sky2_hw *hw = (struct sky2_hw *) arg;
2492 if (sky2_read32(hw, B0_ISRC)) {
2493 struct net_device *dev = hw->dev[0];
2495 if (__netif_rx_schedule_prep(dev))
2496 __netif_rx_schedule(dev);
2500 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2503 /* Hardware/software error handling */
2504 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2506 if (net_ratelimit())
2507 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2509 if (status & Y2_IS_HW_ERR)
2512 if (status & Y2_IS_IRQ_MAC1)
2513 sky2_mac_intr(hw, 0);
2515 if (status & Y2_IS_IRQ_MAC2)
2516 sky2_mac_intr(hw, 1);
2518 if (status & Y2_IS_CHK_RX1)
2519 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2521 if (status & Y2_IS_CHK_RX2)
2522 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2524 if (status & Y2_IS_CHK_TXA1)
2525 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2527 if (status & Y2_IS_CHK_TXA2)
2528 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2531 static int sky2_poll(struct net_device *dev0, int *budget)
2533 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2535 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2537 if (unlikely(status & Y2_IS_ERROR))
2538 sky2_err_intr(hw, status);
2540 if (status & Y2_IS_IRQ_PHY1)
2541 sky2_phy_intr(hw, 0);
2543 if (status & Y2_IS_IRQ_PHY2)
2544 sky2_phy_intr(hw, 1);
2546 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2547 *budget -= work_done;
2548 dev0->quota -= work_done;
2551 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
2554 /* Bug/Errata workaround?
2555 * Need to kick the TX irq moderation timer.
2557 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2558 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2559 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2561 netif_rx_complete(dev0);
2563 sky2_read32(hw, B0_Y2_SP_LISR);
2567 static irqreturn_t sky2_intr(int irq, void *dev_id)
2569 struct sky2_hw *hw = dev_id;
2570 struct net_device *dev0 = hw->dev[0];
2573 /* Reading this mask interrupts as side effect */
2574 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2575 if (status == 0 || status == ~0)
2578 prefetch(&hw->st_le[hw->st_idx]);
2579 if (likely(__netif_rx_schedule_prep(dev0)))
2580 __netif_rx_schedule(dev0);
2585 #ifdef CONFIG_NET_POLL_CONTROLLER
2586 static void sky2_netpoll(struct net_device *dev)
2588 struct sky2_port *sky2 = netdev_priv(dev);
2589 struct net_device *dev0 = sky2->hw->dev[0];
2591 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2592 __netif_rx_schedule(dev0);
2596 /* Chip internal frequency for clock calculations */
2597 static u32 sky2_mhz(const struct sky2_hw *hw)
2599 switch (hw->chip_id) {
2600 case CHIP_ID_YUKON_EC:
2601 case CHIP_ID_YUKON_EC_U:
2602 case CHIP_ID_YUKON_EX:
2605 case CHIP_ID_YUKON_FE:
2608 case CHIP_ID_YUKON_FE_P:
2611 case CHIP_ID_YUKON_XL:
2619 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2621 return sky2_mhz(hw) * us;
2624 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2626 return clk / sky2_mhz(hw);
2630 static int __devinit sky2_init(struct sky2_hw *hw)
2634 /* Enable all clocks */
2635 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2637 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2639 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2640 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2642 switch(hw->chip_id) {
2643 case CHIP_ID_YUKON_XL:
2644 hw->flags = SKY2_HW_GIGABIT
2646 | SKY2_HW_RAMBUFFER;
2649 case CHIP_ID_YUKON_EC_U:
2650 hw->flags = SKY2_HW_GIGABIT
2652 | SKY2_HW_ADV_POWER_CTL;
2655 case CHIP_ID_YUKON_EX:
2656 hw->flags = SKY2_HW_GIGABIT
2659 | SKY2_HW_ADV_POWER_CTL;
2661 /* New transmit checksum */
2662 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2663 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2666 case CHIP_ID_YUKON_EC:
2667 /* This rev is really old, and requires untested workarounds */
2668 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2669 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2672 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RAMBUFFER;
2675 case CHIP_ID_YUKON_FE:
2676 hw->flags = SKY2_HW_RAMBUFFER;
2679 case CHIP_ID_YUKON_FE_P:
2680 hw->flags = SKY2_HW_NEWER_PHY
2682 | SKY2_HW_AUTO_TX_SUM
2683 | SKY2_HW_ADV_POWER_CTL;
2686 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2691 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2692 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2693 hw->flags |= SKY2_HW_FIBRE_PHY;
2697 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2698 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2699 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2706 static void sky2_reset(struct sky2_hw *hw)
2712 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2713 status = sky2_read16(hw, HCU_CCSR);
2714 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2715 HCU_CCSR_UC_STATE_MSK);
2716 sky2_write16(hw, HCU_CCSR, status);
2718 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2719 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2722 sky2_write8(hw, B0_CTST, CS_RST_SET);
2723 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2725 /* clear PCI errors, if any */
2726 status = sky2_pci_read16(hw, PCI_STATUS);
2728 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2729 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2732 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2734 /* clear any PEX errors */
2735 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2736 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2741 for (i = 0; i < hw->ports; i++) {
2742 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2743 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2745 if (hw->chip_id == CHIP_ID_YUKON_EX)
2746 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2747 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2751 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2753 /* Clear I2C IRQ noise */
2754 sky2_write32(hw, B2_I2C_IRQ, 1);
2756 /* turn off hardware timer (unused) */
2757 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2758 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2760 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2762 /* Turn off descriptor polling */
2763 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2765 /* Turn off receive timestamp */
2766 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2767 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2769 /* enable the Tx Arbiters */
2770 for (i = 0; i < hw->ports; i++)
2771 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2773 /* Initialize ram interface */
2774 for (i = 0; i < hw->ports; i++) {
2775 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2777 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2778 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2779 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2780 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2781 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2782 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2783 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2784 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2785 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2786 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2787 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2788 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2791 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2793 for (i = 0; i < hw->ports; i++)
2794 sky2_gmac_reset(hw, i);
2796 memset(hw->st_le, 0, STATUS_LE_BYTES);
2799 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2800 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2802 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2803 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2805 /* Set the list last index */
2806 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2808 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2809 sky2_write8(hw, STAT_FIFO_WM, 16);
2811 /* set Status-FIFO ISR watermark */
2812 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2813 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2815 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2817 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2818 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2819 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2821 /* enable status unit */
2822 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2824 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2825 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2826 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2829 static void sky2_restart(struct work_struct *work)
2831 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2832 struct net_device *dev;
2836 sky2_write32(hw, B0_IMSK, 0);
2837 sky2_read32(hw, B0_IMSK);
2839 netif_poll_disable(hw->dev[0]);
2841 for (i = 0; i < hw->ports; i++) {
2843 if (netif_running(dev))
2848 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2849 netif_poll_enable(hw->dev[0]);
2851 for (i = 0; i < hw->ports; i++) {
2853 if (netif_running(dev)) {
2856 printk(KERN_INFO PFX "%s: could not restart %d\n",
2866 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2868 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2871 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2873 const struct sky2_port *sky2 = netdev_priv(dev);
2875 wol->supported = sky2_wol_supported(sky2->hw);
2876 wol->wolopts = sky2->wol;
2879 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2881 struct sky2_port *sky2 = netdev_priv(dev);
2882 struct sky2_hw *hw = sky2->hw;
2884 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2887 sky2->wol = wol->wolopts;
2889 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2890 hw->chip_id == CHIP_ID_YUKON_EX ||
2891 hw->chip_id == CHIP_ID_YUKON_FE_P)
2892 sky2_write32(hw, B0_CTST, sky2->wol
2893 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2895 if (!netif_running(dev))
2896 sky2_wol_init(sky2);
2900 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2902 if (sky2_is_copper(hw)) {
2903 u32 modes = SUPPORTED_10baseT_Half
2904 | SUPPORTED_10baseT_Full
2905 | SUPPORTED_100baseT_Half
2906 | SUPPORTED_100baseT_Full
2907 | SUPPORTED_Autoneg | SUPPORTED_TP;
2909 if (hw->flags & SKY2_HW_GIGABIT)
2910 modes |= SUPPORTED_1000baseT_Half
2911 | SUPPORTED_1000baseT_Full;
2914 return SUPPORTED_1000baseT_Half
2915 | SUPPORTED_1000baseT_Full
2920 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2922 struct sky2_port *sky2 = netdev_priv(dev);
2923 struct sky2_hw *hw = sky2->hw;
2925 ecmd->transceiver = XCVR_INTERNAL;
2926 ecmd->supported = sky2_supported_modes(hw);
2927 ecmd->phy_address = PHY_ADDR_MARV;
2928 if (sky2_is_copper(hw)) {
2929 ecmd->port = PORT_TP;
2930 ecmd->speed = sky2->speed;
2932 ecmd->speed = SPEED_1000;
2933 ecmd->port = PORT_FIBRE;
2936 ecmd->advertising = sky2->advertising;
2937 ecmd->autoneg = sky2->autoneg;
2938 ecmd->duplex = sky2->duplex;
2942 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2944 struct sky2_port *sky2 = netdev_priv(dev);
2945 const struct sky2_hw *hw = sky2->hw;
2946 u32 supported = sky2_supported_modes(hw);
2948 if (ecmd->autoneg == AUTONEG_ENABLE) {
2949 ecmd->advertising = supported;
2955 switch (ecmd->speed) {
2957 if (ecmd->duplex == DUPLEX_FULL)
2958 setting = SUPPORTED_1000baseT_Full;
2959 else if (ecmd->duplex == DUPLEX_HALF)
2960 setting = SUPPORTED_1000baseT_Half;
2965 if (ecmd->duplex == DUPLEX_FULL)
2966 setting = SUPPORTED_100baseT_Full;
2967 else if (ecmd->duplex == DUPLEX_HALF)
2968 setting = SUPPORTED_100baseT_Half;
2974 if (ecmd->duplex == DUPLEX_FULL)
2975 setting = SUPPORTED_10baseT_Full;
2976 else if (ecmd->duplex == DUPLEX_HALF)
2977 setting = SUPPORTED_10baseT_Half;
2985 if ((setting & supported) == 0)
2988 sky2->speed = ecmd->speed;
2989 sky2->duplex = ecmd->duplex;
2992 sky2->autoneg = ecmd->autoneg;
2993 sky2->advertising = ecmd->advertising;
2995 if (netif_running(dev)) {
2996 sky2_phy_reinit(sky2);
2997 sky2_set_multicast(dev);
3003 static void sky2_get_drvinfo(struct net_device *dev,
3004 struct ethtool_drvinfo *info)
3006 struct sky2_port *sky2 = netdev_priv(dev);
3008 strcpy(info->driver, DRV_NAME);
3009 strcpy(info->version, DRV_VERSION);
3010 strcpy(info->fw_version, "N/A");
3011 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3014 static const struct sky2_stat {
3015 char name[ETH_GSTRING_LEN];
3018 { "tx_bytes", GM_TXO_OK_HI },
3019 { "rx_bytes", GM_RXO_OK_HI },
3020 { "tx_broadcast", GM_TXF_BC_OK },
3021 { "rx_broadcast", GM_RXF_BC_OK },
3022 { "tx_multicast", GM_TXF_MC_OK },
3023 { "rx_multicast", GM_RXF_MC_OK },
3024 { "tx_unicast", GM_TXF_UC_OK },
3025 { "rx_unicast", GM_RXF_UC_OK },
3026 { "tx_mac_pause", GM_TXF_MPAUSE },
3027 { "rx_mac_pause", GM_RXF_MPAUSE },
3028 { "collisions", GM_TXF_COL },
3029 { "late_collision",GM_TXF_LAT_COL },
3030 { "aborted", GM_TXF_ABO_COL },
3031 { "single_collisions", GM_TXF_SNG_COL },
3032 { "multi_collisions", GM_TXF_MUL_COL },
3034 { "rx_short", GM_RXF_SHT },
3035 { "rx_runt", GM_RXE_FRAG },
3036 { "rx_64_byte_packets", GM_RXF_64B },
3037 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3038 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3039 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3040 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3041 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3042 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3043 { "rx_too_long", GM_RXF_LNG_ERR },
3044 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3045 { "rx_jabber", GM_RXF_JAB_PKT },
3046 { "rx_fcs_error", GM_RXF_FCS_ERR },
3048 { "tx_64_byte_packets", GM_TXF_64B },
3049 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3050 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3051 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3052 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3053 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3054 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3055 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3058 static u32 sky2_get_rx_csum(struct net_device *dev)
3060 struct sky2_port *sky2 = netdev_priv(dev);
3062 return sky2->rx_csum;
3065 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3067 struct sky2_port *sky2 = netdev_priv(dev);
3069 sky2->rx_csum = data;
3071 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3072 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3077 static u32 sky2_get_msglevel(struct net_device *netdev)
3079 struct sky2_port *sky2 = netdev_priv(netdev);
3080 return sky2->msg_enable;
3083 static int sky2_nway_reset(struct net_device *dev)
3085 struct sky2_port *sky2 = netdev_priv(dev);
3087 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3090 sky2_phy_reinit(sky2);
3091 sky2_set_multicast(dev);
3096 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3098 struct sky2_hw *hw = sky2->hw;
3099 unsigned port = sky2->port;
3102 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3103 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3104 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3105 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3107 for (i = 2; i < count; i++)
3108 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3111 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3113 struct sky2_port *sky2 = netdev_priv(netdev);
3114 sky2->msg_enable = value;
3117 static int sky2_get_stats_count(struct net_device *dev)
3119 return ARRAY_SIZE(sky2_stats);
3122 static void sky2_get_ethtool_stats(struct net_device *dev,
3123 struct ethtool_stats *stats, u64 * data)
3125 struct sky2_port *sky2 = netdev_priv(dev);
3127 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3130 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3134 switch (stringset) {
3136 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3137 memcpy(data + i * ETH_GSTRING_LEN,
3138 sky2_stats[i].name, ETH_GSTRING_LEN);
3143 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3145 struct sky2_port *sky2 = netdev_priv(dev);
3146 return &sky2->net_stats;
3149 static int sky2_set_mac_address(struct net_device *dev, void *p)
3151 struct sky2_port *sky2 = netdev_priv(dev);
3152 struct sky2_hw *hw = sky2->hw;
3153 unsigned port = sky2->port;
3154 const struct sockaddr *addr = p;
3156 if (!is_valid_ether_addr(addr->sa_data))
3157 return -EADDRNOTAVAIL;
3159 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3160 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3161 dev->dev_addr, ETH_ALEN);
3162 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3163 dev->dev_addr, ETH_ALEN);
3165 /* virtual address for data */
3166 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3168 /* physical address: used for pause frames */
3169 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3174 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3178 bit = ether_crc(ETH_ALEN, addr) & 63;
3179 filter[bit >> 3] |= 1 << (bit & 7);
3182 static void sky2_set_multicast(struct net_device *dev)
3184 struct sky2_port *sky2 = netdev_priv(dev);
3185 struct sky2_hw *hw = sky2->hw;
3186 unsigned port = sky2->port;
3187 struct dev_mc_list *list = dev->mc_list;
3191 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3193 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3194 memset(filter, 0, sizeof(filter));
3196 reg = gma_read16(hw, port, GM_RX_CTRL);
3197 reg |= GM_RXCR_UCF_ENA;
3199 if (dev->flags & IFF_PROMISC) /* promiscuous */
3200 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3201 else if (dev->flags & IFF_ALLMULTI)
3202 memset(filter, 0xff, sizeof(filter));
3203 else if (dev->mc_count == 0 && !rx_pause)
3204 reg &= ~GM_RXCR_MCF_ENA;
3207 reg |= GM_RXCR_MCF_ENA;
3210 sky2_add_filter(filter, pause_mc_addr);
3212 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3213 sky2_add_filter(filter, list->dmi_addr);
3216 gma_write16(hw, port, GM_MC_ADDR_H1,
3217 (u16) filter[0] | ((u16) filter[1] << 8));
3218 gma_write16(hw, port, GM_MC_ADDR_H2,
3219 (u16) filter[2] | ((u16) filter[3] << 8));
3220 gma_write16(hw, port, GM_MC_ADDR_H3,
3221 (u16) filter[4] | ((u16) filter[5] << 8));
3222 gma_write16(hw, port, GM_MC_ADDR_H4,
3223 (u16) filter[6] | ((u16) filter[7] << 8));
3225 gma_write16(hw, port, GM_RX_CTRL, reg);
3228 /* Can have one global because blinking is controlled by
3229 * ethtool and that is always under RTNL mutex
3231 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3235 switch (hw->chip_id) {
3236 case CHIP_ID_YUKON_XL:
3237 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3238 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3239 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3240 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3241 PHY_M_LEDC_INIT_CTRL(7) |
3242 PHY_M_LEDC_STA1_CTRL(7) |
3243 PHY_M_LEDC_STA0_CTRL(7))
3246 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3250 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3251 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3252 on ? PHY_M_LED_ALL : 0);
3256 /* blink LED's for finding board */
3257 static int sky2_phys_id(struct net_device *dev, u32 data)
3259 struct sky2_port *sky2 = netdev_priv(dev);
3260 struct sky2_hw *hw = sky2->hw;
3261 unsigned port = sky2->port;
3262 u16 ledctrl, ledover = 0;
3267 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3268 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3272 /* save initial values */
3273 spin_lock_bh(&sky2->phy_lock);
3274 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3275 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3276 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3277 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3278 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3280 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3281 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3285 while (!interrupted && ms > 0) {
3286 sky2_led(hw, port, onoff);
3289 spin_unlock_bh(&sky2->phy_lock);
3290 interrupted = msleep_interruptible(250);
3291 spin_lock_bh(&sky2->phy_lock);
3296 /* resume regularly scheduled programming */
3297 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3298 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3299 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3300 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3301 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3303 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3304 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3306 spin_unlock_bh(&sky2->phy_lock);
3311 static void sky2_get_pauseparam(struct net_device *dev,
3312 struct ethtool_pauseparam *ecmd)
3314 struct sky2_port *sky2 = netdev_priv(dev);
3316 switch (sky2->flow_mode) {
3318 ecmd->tx_pause = ecmd->rx_pause = 0;
3321 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3324 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3327 ecmd->tx_pause = ecmd->rx_pause = 1;
3330 ecmd->autoneg = sky2->autoneg;
3333 static int sky2_set_pauseparam(struct net_device *dev,
3334 struct ethtool_pauseparam *ecmd)
3336 struct sky2_port *sky2 = netdev_priv(dev);
3338 sky2->autoneg = ecmd->autoneg;
3339 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3341 if (netif_running(dev))
3342 sky2_phy_reinit(sky2);
3347 static int sky2_get_coalesce(struct net_device *dev,
3348 struct ethtool_coalesce *ecmd)
3350 struct sky2_port *sky2 = netdev_priv(dev);
3351 struct sky2_hw *hw = sky2->hw;
3353 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3354 ecmd->tx_coalesce_usecs = 0;
3356 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3357 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3359 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3361 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3362 ecmd->rx_coalesce_usecs = 0;
3364 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3365 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3367 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3369 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3370 ecmd->rx_coalesce_usecs_irq = 0;
3372 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3373 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3376 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3381 /* Note: this affect both ports */
3382 static int sky2_set_coalesce(struct net_device *dev,
3383 struct ethtool_coalesce *ecmd)
3385 struct sky2_port *sky2 = netdev_priv(dev);
3386 struct sky2_hw *hw = sky2->hw;
3387 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3389 if (ecmd->tx_coalesce_usecs > tmax ||
3390 ecmd->rx_coalesce_usecs > tmax ||
3391 ecmd->rx_coalesce_usecs_irq > tmax)
3394 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3396 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3398 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3401 if (ecmd->tx_coalesce_usecs == 0)
3402 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3404 sky2_write32(hw, STAT_TX_TIMER_INI,
3405 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3406 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3408 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3410 if (ecmd->rx_coalesce_usecs == 0)
3411 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3413 sky2_write32(hw, STAT_LEV_TIMER_INI,
3414 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3415 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3417 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3419 if (ecmd->rx_coalesce_usecs_irq == 0)
3420 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3422 sky2_write32(hw, STAT_ISR_TIMER_INI,
3423 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3424 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3426 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3430 static void sky2_get_ringparam(struct net_device *dev,
3431 struct ethtool_ringparam *ering)
3433 struct sky2_port *sky2 = netdev_priv(dev);
3435 ering->rx_max_pending = RX_MAX_PENDING;
3436 ering->rx_mini_max_pending = 0;
3437 ering->rx_jumbo_max_pending = 0;
3438 ering->tx_max_pending = TX_RING_SIZE - 1;
3440 ering->rx_pending = sky2->rx_pending;
3441 ering->rx_mini_pending = 0;
3442 ering->rx_jumbo_pending = 0;
3443 ering->tx_pending = sky2->tx_pending;
3446 static int sky2_set_ringparam(struct net_device *dev,
3447 struct ethtool_ringparam *ering)
3449 struct sky2_port *sky2 = netdev_priv(dev);
3452 if (ering->rx_pending > RX_MAX_PENDING ||
3453 ering->rx_pending < 8 ||
3454 ering->tx_pending < MAX_SKB_TX_LE ||
3455 ering->tx_pending > TX_RING_SIZE - 1)
3458 if (netif_running(dev))
3461 sky2->rx_pending = ering->rx_pending;
3462 sky2->tx_pending = ering->tx_pending;
3464 if (netif_running(dev)) {
3469 sky2_set_multicast(dev);
3475 static int sky2_get_regs_len(struct net_device *dev)
3481 * Returns copy of control register region
3482 * Note: ethtool_get_regs always provides full size (16k) buffer
3484 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3487 const struct sky2_port *sky2 = netdev_priv(dev);
3488 const void __iomem *io = sky2->hw->regs;
3491 memset(p, 0, regs->len);
3493 memcpy_fromio(p, io, B3_RAM_ADDR);
3495 /* skip diagnostic ram region */
3496 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3498 /* copy GMAC registers */
3499 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3500 if (sky2->hw->ports > 1)
3501 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3505 /* In order to do Jumbo packets on these chips, need to turn off the
3506 * transmit store/forward. Therefore checksum offload won't work.
3508 static int no_tx_offload(struct net_device *dev)
3510 const struct sky2_port *sky2 = netdev_priv(dev);
3511 const struct sky2_hw *hw = sky2->hw;
3513 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3516 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3518 if (data && no_tx_offload(dev))
3521 return ethtool_op_set_tx_csum(dev, data);
3525 static int sky2_set_tso(struct net_device *dev, u32 data)
3527 if (data && no_tx_offload(dev))
3530 return ethtool_op_set_tso(dev, data);
3533 static int sky2_get_eeprom_len(struct net_device *dev)
3535 struct sky2_port *sky2 = netdev_priv(dev);
3538 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3539 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3542 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3544 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3546 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3548 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3551 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3553 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3554 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3557 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3560 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3563 struct sky2_port *sky2 = netdev_priv(dev);
3564 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3565 int length = eeprom->len;
3566 u16 offset = eeprom->offset;
3571 eeprom->magic = SKY2_EEPROM_MAGIC;
3573 while (length > 0) {
3574 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3575 int n = min_t(int, length, sizeof(val));
3577 memcpy(data, &val, n);
3585 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3588 struct sky2_port *sky2 = netdev_priv(dev);
3589 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3590 int length = eeprom->len;
3591 u16 offset = eeprom->offset;
3596 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3599 while (length > 0) {
3601 int n = min_t(int, length, sizeof(val));
3603 if (n < sizeof(val))
3604 val = sky2_vpd_read(sky2->hw, cap, offset);
3605 memcpy(&val, data, n);
3607 sky2_vpd_write(sky2->hw, cap, offset, val);
3617 static const struct ethtool_ops sky2_ethtool_ops = {
3618 .get_settings = sky2_get_settings,
3619 .set_settings = sky2_set_settings,
3620 .get_drvinfo = sky2_get_drvinfo,
3621 .get_wol = sky2_get_wol,
3622 .set_wol = sky2_set_wol,
3623 .get_msglevel = sky2_get_msglevel,
3624 .set_msglevel = sky2_set_msglevel,
3625 .nway_reset = sky2_nway_reset,
3626 .get_regs_len = sky2_get_regs_len,
3627 .get_regs = sky2_get_regs,
3628 .get_link = ethtool_op_get_link,
3629 .get_eeprom_len = sky2_get_eeprom_len,
3630 .get_eeprom = sky2_get_eeprom,
3631 .set_eeprom = sky2_set_eeprom,
3632 .get_sg = ethtool_op_get_sg,
3633 .set_sg = ethtool_op_set_sg,
3634 .get_tx_csum = ethtool_op_get_tx_csum,
3635 .set_tx_csum = sky2_set_tx_csum,
3636 .get_tso = ethtool_op_get_tso,
3637 .set_tso = sky2_set_tso,
3638 .get_rx_csum = sky2_get_rx_csum,
3639 .set_rx_csum = sky2_set_rx_csum,
3640 .get_strings = sky2_get_strings,
3641 .get_coalesce = sky2_get_coalesce,
3642 .set_coalesce = sky2_set_coalesce,
3643 .get_ringparam = sky2_get_ringparam,
3644 .set_ringparam = sky2_set_ringparam,
3645 .get_pauseparam = sky2_get_pauseparam,
3646 .set_pauseparam = sky2_set_pauseparam,
3647 .phys_id = sky2_phys_id,
3648 .get_stats_count = sky2_get_stats_count,
3649 .get_ethtool_stats = sky2_get_ethtool_stats,
3652 #ifdef CONFIG_SKY2_DEBUG
3654 static struct dentry *sky2_debug;
3656 static int sky2_debug_show(struct seq_file *seq, void *v)
3658 struct net_device *dev = seq->private;
3659 const struct sky2_port *sky2 = netdev_priv(dev);
3660 const struct sky2_hw *hw = sky2->hw;
3661 unsigned port = sky2->port;
3665 if (!netif_running(dev))
3668 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3669 sky2_read32(hw, B0_ISRC),
3670 sky2_read32(hw, B0_IMSK),
3671 sky2_read32(hw, B0_Y2_SP_ICR));
3673 netif_poll_disable(hw->dev[0]);
3674 last = sky2_read16(hw, STAT_PUT_IDX);
3676 if (hw->st_idx == last)
3677 seq_puts(seq, "Status ring (empty)\n");
3679 seq_puts(seq, "Status ring\n");
3680 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3681 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3682 const struct sky2_status_le *le = hw->st_le + idx;
3683 seq_printf(seq, "[%d] %#x %d %#x\n",
3684 idx, le->opcode, le->length, le->status);
3686 seq_puts(seq, "\n");
3689 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3690 sky2->tx_cons, sky2->tx_prod,
3691 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3692 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3694 /* Dump contents of tx ring */
3696 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3697 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3698 const struct sky2_tx_le *le = sky2->tx_le + idx;
3699 u32 a = le32_to_cpu(le->addr);
3702 seq_printf(seq, "%u:", idx);
3705 switch(le->opcode & ~HW_OWNER) {
3707 seq_printf(seq, " %#x:", a);
3710 seq_printf(seq, " mtu=%d", a);
3713 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3716 seq_printf(seq, " csum=%#x", a);
3719 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3722 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3725 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3728 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3729 a, le16_to_cpu(le->length));
3732 if (le->ctrl & EOP) {
3733 seq_putc(seq, '\n');
3738 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3739 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3740 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3741 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3743 netif_poll_enable(hw->dev[0]);
3747 static int sky2_debug_open(struct inode *inode, struct file *file)
3749 return single_open(file, sky2_debug_show, inode->i_private);
3752 static const struct file_operations sky2_debug_fops = {
3753 .owner = THIS_MODULE,
3754 .open = sky2_debug_open,
3756 .llseek = seq_lseek,
3757 .release = single_release,
3761 * Use network device events to create/remove/rename
3762 * debugfs file entries
3764 static int sky2_device_event(struct notifier_block *unused,
3765 unsigned long event, void *ptr)
3767 struct net_device *dev = ptr;
3769 if (dev->open == sky2_up) {
3770 struct sky2_port *sky2 = netdev_priv(dev);
3773 case NETDEV_CHANGENAME:
3774 if (!netif_running(dev))
3778 case NETDEV_GOING_DOWN:
3779 if (sky2->debugfs) {
3780 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3782 debugfs_remove(sky2->debugfs);
3783 sky2->debugfs = NULL;
3786 if (event != NETDEV_CHANGENAME)
3788 /* fallthrough for changename */
3792 d = debugfs_create_file(dev->name, S_IRUGO,
3795 if (d == NULL || IS_ERR(d))
3796 printk(KERN_INFO PFX
3797 "%s: debugfs create failed\n",
3809 static struct notifier_block sky2_notifier = {
3810 .notifier_call = sky2_device_event,
3814 static __init void sky2_debug_init(void)
3818 ent = debugfs_create_dir("sky2", NULL);
3819 if (!ent || IS_ERR(ent))
3823 register_netdevice_notifier(&sky2_notifier);
3826 static __exit void sky2_debug_cleanup(void)
3829 unregister_netdevice_notifier(&sky2_notifier);
3830 debugfs_remove(sky2_debug);
3836 #define sky2_debug_init()
3837 #define sky2_debug_cleanup()
3841 /* Initialize network device */
3842 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3844 int highmem, int wol)
3846 struct sky2_port *sky2;
3847 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3850 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3854 SET_MODULE_OWNER(dev);
3855 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3856 dev->irq = hw->pdev->irq;
3857 dev->open = sky2_up;
3858 dev->stop = sky2_down;
3859 dev->do_ioctl = sky2_ioctl;
3860 dev->hard_start_xmit = sky2_xmit_frame;
3861 dev->get_stats = sky2_get_stats;
3862 dev->set_multicast_list = sky2_set_multicast;
3863 dev->set_mac_address = sky2_set_mac_address;
3864 dev->change_mtu = sky2_change_mtu;
3865 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3866 dev->tx_timeout = sky2_tx_timeout;
3867 dev->watchdog_timeo = TX_WATCHDOG;
3869 dev->poll = sky2_poll;
3870 dev->weight = NAPI_WEIGHT;
3871 #ifdef CONFIG_NET_POLL_CONTROLLER
3872 /* Network console (only works on port 0)
3873 * because netpoll makes assumptions about NAPI
3876 dev->poll_controller = sky2_netpoll;
3879 sky2 = netdev_priv(dev);
3882 sky2->msg_enable = netif_msg_init(debug, default_msg);
3884 /* This chip has hardware problems that generates
3885 * bogus PHY receive status so by default shut up the message.
3887 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
3888 hw->chip_rev == CHIP_REV_YU_FE2_A0)
3889 sky2->msg_enable &= ~NETIF_MSG_RX_ERR;
3891 /* Auto speed and flow control */
3892 sky2->autoneg = AUTONEG_ENABLE;
3893 sky2->flow_mode = FC_BOTH;
3897 sky2->advertising = sky2_supported_modes(hw);
3901 spin_lock_init(&sky2->phy_lock);
3902 sky2->tx_pending = TX_DEF_PENDING;
3903 sky2->rx_pending = RX_DEF_PENDING;
3905 hw->dev[port] = dev;
3909 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3911 dev->features |= NETIF_F_HIGHDMA;
3913 #ifdef SKY2_VLAN_TAG_USED
3914 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3915 dev->vlan_rx_register = sky2_vlan_rx_register;
3918 /* read the mac address */
3919 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3920 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3925 static void __devinit sky2_show_addr(struct net_device *dev)
3927 const struct sky2_port *sky2 = netdev_priv(dev);
3929 if (netif_msg_probe(sky2))
3930 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3932 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3933 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3936 /* Handle software interrupt used during MSI test */
3937 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3939 struct sky2_hw *hw = dev_id;
3940 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3945 if (status & Y2_IS_IRQ_SW) {
3946 hw->flags |= SKY2_HW_USE_MSI;
3947 wake_up(&hw->msi_wait);
3948 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3950 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3955 /* Test interrupt path by forcing a a software IRQ */
3956 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3958 struct pci_dev *pdev = hw->pdev;
3961 init_waitqueue_head (&hw->msi_wait);
3963 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3965 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3967 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3971 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3972 sky2_read8(hw, B0_CTST);
3974 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
3976 if (!(hw->flags & SKY2_HW_USE_MSI)) {
3977 /* MSI test failed, go back to INTx mode */
3978 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3979 "switching to INTx mode.\n");
3982 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3985 sky2_write32(hw, B0_IMSK, 0);
3986 sky2_read32(hw, B0_IMSK);
3988 free_irq(pdev->irq, hw);
3993 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3995 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4000 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4002 return value & PCI_PM_CTRL_PME_ENABLE;
4005 static int __devinit sky2_probe(struct pci_dev *pdev,
4006 const struct pci_device_id *ent)
4008 struct net_device *dev;
4010 int err, using_dac = 0, wol_default;
4012 err = pci_enable_device(pdev);
4014 dev_err(&pdev->dev, "cannot enable PCI device\n");
4018 err = pci_request_regions(pdev, DRV_NAME);
4020 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4021 goto err_out_disable;
4024 pci_set_master(pdev);
4026 if (sizeof(dma_addr_t) > sizeof(u32) &&
4027 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4029 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4031 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4032 "for consistent allocations\n");
4033 goto err_out_free_regions;
4036 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4038 dev_err(&pdev->dev, "no usable DMA configuration\n");
4039 goto err_out_free_regions;
4043 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4046 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4048 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4049 goto err_out_free_regions;
4054 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4056 dev_err(&pdev->dev, "cannot map device registers\n");
4057 goto err_out_free_hw;
4061 /* The sk98lin vendor driver uses hardware byte swapping but
4062 * this driver uses software swapping.
4066 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4067 reg &= ~PCI_REV_DESC;
4068 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4072 /* ring for status responses */
4073 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
4076 goto err_out_iounmap;
4078 err = sky2_init(hw);
4080 goto err_out_iounmap;
4082 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4083 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4084 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4085 hw->chip_id, hw->chip_rev);
4089 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4092 goto err_out_free_pci;
4095 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4096 err = sky2_test_msi(hw);
4097 if (err == -EOPNOTSUPP)
4098 pci_disable_msi(pdev);
4100 goto err_out_free_netdev;
4103 err = register_netdev(dev);
4105 dev_err(&pdev->dev, "cannot register net device\n");
4106 goto err_out_free_netdev;
4109 err = request_irq(pdev->irq, sky2_intr,
4110 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4113 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4114 goto err_out_unregister;
4116 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4118 sky2_show_addr(dev);
4120 if (hw->ports > 1) {
4121 struct net_device *dev1;
4123 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4125 dev_warn(&pdev->dev, "allocation for second device failed\n");
4126 else if ((err = register_netdev(dev1))) {
4127 dev_warn(&pdev->dev,
4128 "register of second port failed (%d)\n", err);
4132 sky2_show_addr(dev1);
4135 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4136 INIT_WORK(&hw->restart_work, sky2_restart);
4138 pci_set_drvdata(pdev, hw);
4143 if (hw->flags & SKY2_HW_USE_MSI)
4144 pci_disable_msi(pdev);
4145 unregister_netdev(dev);
4146 err_out_free_netdev:
4149 sky2_write8(hw, B0_CTST, CS_RST_SET);
4150 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4155 err_out_free_regions:
4156 pci_release_regions(pdev);
4158 pci_disable_device(pdev);
4160 pci_set_drvdata(pdev, NULL);
4164 static void __devexit sky2_remove(struct pci_dev *pdev)
4166 struct sky2_hw *hw = pci_get_drvdata(pdev);
4167 struct net_device *dev0, *dev1;
4172 del_timer_sync(&hw->watchdog_timer);
4174 flush_scheduled_work();
4176 sky2_write32(hw, B0_IMSK, 0);
4177 synchronize_irq(hw->pdev->irq);
4182 unregister_netdev(dev1);
4183 unregister_netdev(dev0);
4187 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4188 sky2_write8(hw, B0_CTST, CS_RST_SET);
4189 sky2_read8(hw, B0_CTST);
4191 free_irq(pdev->irq, hw);
4192 if (hw->flags & SKY2_HW_USE_MSI)
4193 pci_disable_msi(pdev);
4194 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4195 pci_release_regions(pdev);
4196 pci_disable_device(pdev);
4204 pci_set_drvdata(pdev, NULL);
4208 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4210 struct sky2_hw *hw = pci_get_drvdata(pdev);
4216 netif_poll_disable(hw->dev[0]);
4218 for (i = 0; i < hw->ports; i++) {
4219 struct net_device *dev = hw->dev[i];
4220 struct sky2_port *sky2 = netdev_priv(dev);
4222 if (netif_running(dev))
4226 sky2_wol_init(sky2);
4231 sky2_write32(hw, B0_IMSK, 0);
4234 pci_save_state(pdev);
4235 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4236 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4241 static int sky2_resume(struct pci_dev *pdev)
4243 struct sky2_hw *hw = pci_get_drvdata(pdev);
4249 err = pci_set_power_state(pdev, PCI_D0);
4253 err = pci_restore_state(pdev);
4257 pci_enable_wake(pdev, PCI_D0, 0);
4259 /* Re-enable all clocks */
4260 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4261 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4262 hw->chip_id == CHIP_ID_YUKON_FE_P)
4263 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4267 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4269 for (i = 0; i < hw->ports; i++) {
4270 struct net_device *dev = hw->dev[i];
4271 if (netif_running(dev)) {
4274 printk(KERN_ERR PFX "%s: could not up: %d\n",
4280 sky2_set_multicast(dev);
4284 netif_poll_enable(hw->dev[0]);
4288 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4289 pci_disable_device(pdev);
4294 static void sky2_shutdown(struct pci_dev *pdev)
4296 struct sky2_hw *hw = pci_get_drvdata(pdev);
4302 netif_poll_disable(hw->dev[0]);
4304 for (i = 0; i < hw->ports; i++) {
4305 struct net_device *dev = hw->dev[i];
4306 struct sky2_port *sky2 = netdev_priv(dev);
4310 sky2_wol_init(sky2);
4317 pci_enable_wake(pdev, PCI_D3hot, wol);
4318 pci_enable_wake(pdev, PCI_D3cold, wol);
4320 pci_disable_device(pdev);
4321 pci_set_power_state(pdev, PCI_D3hot);
4325 static struct pci_driver sky2_driver = {
4327 .id_table = sky2_id_table,
4328 .probe = sky2_probe,
4329 .remove = __devexit_p(sky2_remove),
4331 .suspend = sky2_suspend,
4332 .resume = sky2_resume,
4334 .shutdown = sky2_shutdown,
4337 static int __init sky2_init_module(void)
4340 return pci_register_driver(&sky2_driver);
4343 static void __exit sky2_cleanup_module(void)
4345 pci_unregister_driver(&sky2_driver);
4346 sky2_debug_cleanup();
4349 module_init(sky2_init_module);
4350 module_exit(sky2_cleanup_module);
4352 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4353 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4354 MODULE_LICENSE("GPL");
4355 MODULE_VERSION(DRV_VERSION);